CN101114619A - Thin-film transistor and method for producing display element using the same - Google Patents
Thin-film transistor and method for producing display element using the same Download PDFInfo
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- CN101114619A CN101114619A CNA2007101425812A CN200710142581A CN101114619A CN 101114619 A CN101114619 A CN 101114619A CN A2007101425812 A CNA2007101425812 A CN A2007101425812A CN 200710142581 A CN200710142581 A CN 200710142581A CN 101114619 A CN101114619 A CN 101114619A
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Abstract
The invention discloses the manufacturing method for a thin film transistor, including the following steps: forming a first patterned conducting layer with a grid on a base plate; sequentially forming a dielectric layer, a semiconductor layer, a second conducting layer and a photo-resist layer on the first patterned conducting layer, providing a photo-mask with different light penetrations, and X-ray exposing of the photo-resist layer, and ensuring that the patterned photo-resist layer has at least three different thickness; removing a photo-resist corresponding to a channel area, etching the second conducting layer and part of source electrode and drain electrode of the semiconductor layer and the related surrounding, exposing a pixel junction area and a data linking area; heating rest of the photo-resist in order to have the photo-resist after re-flowing cover the channel; taking the photo-resist t after re-flowing and the second patterned conducting layer as the mask, removing the exposed semiconductor layer; forming a patterned transparent electrode which can partly cover the pixel junction area of the exposed source electrode and drain electrode.
Description
Technical field
The present invention relates to the manufacture method of the display element of a kind of thin-film transistor and application thereof, and relate in particular to a kind of photomask with four kinds of penetrations of not sharing the same light that utilizes, to reduce the manufacture method that photomask in the fabrication schedule uses the display element of the thin-film transistor of number and application thereof.
Background technology
Traditional tft liquid crystal display element (TFT-LCD) uses five roads or four road photomask technologies on technology, comprise forming grid (the first metal layer), dielectric layer, semiconductor layer, source electrode and drain electrode (second metal level), protective layer and transparency electrode (for example ITO) etc.Yet in order to simplify processing step and to save manufacturing cost, those skilled in the art still expect to reach with number of optical mask still less the same usefulness of thin-film transistor.
Summary of the invention
Technical problem to be solved by this invention is to provide the manufacture method of the display element of a kind of thin-film transistor and application thereof, can reduce photomask and use number, to reduce manufacturing cost.
According to purpose of the present invention, a kind of thin-film transistor (Thin Film Transistor is proposed, TFT) manufacture method, wherein a channel region of thin-film transistor is between an one source pole district and a drain region, this method comprises: form a patterning first conductive layer on a substrate, this patterning first conductive layer comprises a grid; On this patterning first conductive layer, form a dielectric layer, semi-conductor layer, one second conductive layer and a photoresist layer in regular turn; Provide one to have the photomask of the penetration of not sharing the same light and this photoresist layer is carried out exposure imaging, photoresist layer has at least three kinds of thickness behind the patterning that is produced, wherein grid connection pad district does not have photoresist formation, wherein corresponding to this channel region, the photoresist that capacitive region and pixel region etc. are located has one first thickness, has one second thickness corresponding to the pixel bonding pad of the periphery of this source area/this drain region and the photoresist in data connection pad district, photoresist corresponding to this source area and this drain region then has one the 3rd thickness, and the 3rd thickness greater than this second thickness greater than this first thickness; Remove the photoresist that has this first thickness corresponding to this channel region place, and etching be positioned at this channel region place this second conductive layer and and this semiconductor layer (being the n+ amorphous silicon layer) partly, with a passage, one source pole and a drain electrode that forms this thin-film transistor; Remove photoresist, and expose this source electrode and this drain electrode this pixel bonding pad wherein with this second thickness; Heating is corresponding to this source area and this drain region and peripheral residue photoresist thereof, makes the photoresist after flow again (reflow) cover this passage; With this photoresist after flowing again and this second conductive layer behind the patterning is mask, removes this semiconductor layer that exposes; And forming a patterned transparent electrode, part is covered in this source electrode of exposing maybe on this drain electrode this pixel bonding pad wherein.
And, for achieving the above object, reintroduce a kind of manufacture method of display element, wherein display element has a plurality of holding wires (Scan Line) and a plurality of data signal lines (Data Line) of scanning and intersects vertically with the form of array, and those scan holding wire and those data signal lines define a plurality of pixel regions, each pixel region a pair ofly scans holding wire and adjacent a pair of data signal line is defined by adjacent, each scan signal line extends a grid connection pad that is connected a grid connection pad (Gate-pad) district, each data signal line extends a data connection pad that is connected a data connection pad (Data-pad) district, this manufacture method comprises: form a patterning first conductive layer on a substrate, this patterning first conductive layer comprises each signal line, at a grid of the thin film transistor region (TFT region) of each pixel region and a capacitance electrode of a capacitive region (Cst region), and this grid connection pad in each grid connection pad district; On this substrate, form a dielectric layer, semi-conductor layer, one second conductive layer and a photoresist layer in regular turn, this substrate of whole covering; Provide one to have the photomask of four kinds of penetrations of not sharing the same light and this photoresist layer is carried out exposure imaging, photoresist layer comprises behind the patterning that is produced: (a) at the channel region corresponding to this thin film transistor region, the photoresist that capacitive region and pixel region etc. are located has one first thickness, has one second thickness corresponding to the pixel bonding pad of the periphery of one source pole district/drain region and the photoresist in data connection pad district, photoresist corresponding to this source area and this drain region then has one the 3rd thickness, and the 3rd thickness greater than this second thickness greater than this first thickness, (b) remove fully at photoresist, then have this first thickness corresponding to the photoresist of the periphery at this grid connection pad place corresponding to this grid connection pad place in this grid connection pad district; Remove this second conductive layer, this semiconductor layer and this dielectric layer in this grid connection pad district in regular turn,, remove this photoresist layer with this first thickness, this second conductive layer of exposed portions serve simultaneously to expose this grid connection pad; This photoresist layer with this second and the 3rd thickness is a mask, remove this second conductive layer that exposes and reach partly semiconductor layer (being the non-silicon layer of n+), with a passage, one source pole and a drain electrode that forms this thin film transistor region, and each this data signal line and each this data connection pad; Remove photoresist layer, and expose this source electrode and this drain electrode pixel bonding pad and data connection pad district wherein corresponding to this source area and this drain region and this second thickness of peripheral tool thereof; Heating is corresponding to this source area and this drain region and peripheral residue photoresist thereof, makes the photoresist after flow again (reflow) cover this passage; With this photoresist after flowing again and this second conductive layer behind the patterning is mask, removes this semiconductor layer that exposes; And forming a patterned transparent electrode, part is covered in this source electrode of exposing maybe on this drain electrode pixel bonding pad wherein.
Adopt the present invention; utilize a photomask with four kinds of penetrations of not sharing the same light; to form the photoresist figure of three kinds of different-thickness; then can be used as protective layer in the display element through the photoresist after flow being shaped again; and then the step of having exempted follow-up formation protective layer, reach and reduce the purpose that photomask uses number and reduces manufacturing cost.
Description of drawings
Figure 1A to Fig. 1 J is the manufacture method according to the display element of a preferred embodiment of the present invention.
Wherein, Reference numeral:
9: substrate 11: grid connection pad district
111: connection pad 13: thin film transistor region
131: grid 15,153,153 ', 159: photoresist layer
T1: first thickness T 2 of photoresist layer: second thickness of photoresist layer
T3: the 3rd thickness 154 of photoresist layer: the photoresist after flowing again
17: capacitive region 171: capacitance electrode
19: data connection pad district 197: data connection pad
101: silicon nitride layer 103,103 ': amorphous silicon layer
105,105 ': 107: the second metal levels of n+ amorphous silicon layer
127: pixel bonding pad 20: photomask
21a, 21b, 21c and 21d: first transparent area 22a and the 22b: second transparent area
23a, 23b, 23c and 23d: the 3rd transparent area 24a: the 4th transparent area
33: passage 41,43,49: transparency electrode
Embodiment
The present invention proposes a kind of manufacture method (three road technology) that photomask uses number that reduces, utilize a photomask with four kinds of penetrations of not sharing the same light, to form the photoresist figure of three kinds of different-thickness, and the heat-resisting organic photoresist of use sensitization, reach the purpose that reduces number of optical mask, and then reduce manufacturing cost.The method can be applicable to have the display element of the thin-film transistor of different structure, for example carries on the back the thin-film transistor that passage etching formula structure (Back-Channel Etching (BCE) Type TFT) and etching stop formula structure (Etch Stop TypeTFT); Or being applied in display element with Cst on gate or Cst on Com structure, the present invention is not particularly limited these.
Below propose a preferred embodiment as explanation of the present invention, wherein the thin-film transistor in the display element of embodiment is back of the body passage etching formula (BCE) structure; And the display element that embodiment the proposed usefulness for illustrating only can't be done limit to the scope of desire protection of the present invention.In addition, the accompanying drawing among the embodiment also omits unnecessary element, in order to clear demonstration technical characterstic of the present invention.
Please refer to Figure 1A to Fig. 1 J, it is the manufacture method according to the display element of a preferred embodiment of the present invention.Wherein display element has a plurality of holding wire (not shown) and a plurality of data signal line (not shown)s of scanning and intersects vertically with the form of array, and scan holding wire and data signal line and define a plurality of pixels, each pixel a pair ofly scans holding wire and adjacent a pair of data signal line is defined by adjacent.And in this embodiment, each pixel is to have the explanation of a grid connection pad district 11, a thin film transistor region 13, a capacitive region (Cstregion) 17 and a data connection pad district (data-pad region) 19 these embodiment manufacture methods of work.The first road technology
At first, forming one first conductive layer on a substrate 9 for example is the first metal layer (not shown), again to after first conductive layer patternization (as etching), in grid connection pad district 11, thin film transistor region 13 and the capacitive region 17 of each pixel, form a grid connection pad (gate pad) 111, one grid 131 and a capacitance electrode 171 respectively, shown in Figure 1A.
The second road technology
Then, shown in Figure 1B, on substrate 9, form a dielectric layer such as silicon nitride (SiNx) layer 101 in regular turn, semi-conductor layer comprises amorphous silicon layer (a-Si Layer) 103 and n+ amorphous silicon layer (n+a-Si) 105; On n+ amorphous silicon layer 105, form for example second metal level 107 of one second conductive layer again.Wherein, silicon nitride layer 101 covers grid connection pad 111, grid 131 and the capacitance electrode 171 on the substrate 9.
Afterwards, form a photoresist layer on second metal level 107, and provide one to have the photomask 20 of four kinds of penetrations of not sharing the same light so that this photoresist layer is carried out exposure imaging.In each pixel, the photomask 20 of this embodiment has a plurality of first transparent area 21a, 21b, 21c and 21d, second transparent area 22a and the 22b, the 3rd transparent area 23a, 23b, 23c and 23d and the 4th transparent area 24a.Wherein the printing opacity degree is arranged to maximum by minimum, is respectively the first, second, third and the 4th transparent area.Photoresist layer 15 is an eurymeric photoresist layer in addition, is made of an organic material, and has the characteristic that can flow again under etch resistant and the high temperature.
And photoresist layer 15 has three kinds of different-thickness behind the patterning that the back of developing is produced, and asks simultaneously with reference to Fig. 1 C:
(a) has first thickness T 1 at photoresist corresponding to a channel region place of thin film transistor region 13, photoresist corresponding to the pixel bonding pad (being the zone of label 127 among Fig. 1 G) of the periphery of source/drain region has second thickness T 2, photoresist corresponding to source/drain region then has the 3rd thickness T 3, and the 3rd thickness T 3 greater than second thickness T, 2, the second thickness T 2 greater than this first thickness T 1;
(b) remove fully at photoresist, then have first thickness T 1 corresponding to the photoresists at grid connection pad 111 peripheral places corresponding to grid connection pad 111 places in grid connection pad district 11;
(c) has first thickness T 1 at photoresist corresponding to capacitive region 17.
(d) has second thickness T 2 at photoresist corresponding to 19 places, data connection pad district.
Afterwards, shown in Fig. 1 D, utilize dry-etching to remove second metal level 107, n+ amorphous silicon layer 105, amorphous silicon layer 103 and the silicon nitride layer 101 in grid connection pad district 11 in regular turn, to expose grid connection pad 111.
Then, photoresist layer 15 is carried out the thinning step.Utilize the mode of dry-etching (Dry etching) or ashing (Ashing), deduct the thickness of photoresist layer 15, the photoresist figure after the thinning comprises shown in Fig. 1 E:
(1) photoresist corresponding to the channel region place removes fully in the thin film transistor region 13, then carries out attenuate corresponding to the photoresist of source/drain region, shown in photoresist 153;
(2) remove the photoresist at grid connection pad district 11 and capacitive region 17 places fully;
(3) photoresist corresponding to 19 places, data connection pad district then carries out attenuate, shown in photoresist 159.
Then, shown in Fig. 1 F, photoresist 153 according in the thin film transistor region 13 carries out etching (for example Wet-type etching) to second metal level 107 and the n+ amorphous silicon layer 105 that is positioned at the channel region place, to form a passage 33, one source pole S and a drain D of thin film transistor region 13.When carrying out this step, also can be etched with second metal level 107 and the n+ amorphous silicon layer 105 that Remove All grid connection pad district 11 and capacitive region 17 places simultaneously.19 places, data connection pad district then form a data connection pad 197, and data connection pad 197 tops have a photoresist pattern 159.
Then, shown in Fig. 1 G, the photoresist 153 in the thin film transistor region 13 is carried out attenuate once more, particularly can suitably expose source S/drain D pixel bonding pad 127 wherein after the thinning corresponding to source/drain region and peripheral photoresist 153 ' thereof.The thinning mode for example is etching or ashing (ashing).And in thinning photoresist 153, also remove the photoresist pattern 159 at 19 places, data connection pad district, to expose data connection pad 197.
Then, heating makes its flow (reflow) to cover passage 33 corresponding to source area and drain region and peripheral residue photoresist 153 ' thereof again.Shown in Fig. 1 H, the photoresist 154 after flowing again covers passages 33 and protects source S/drain D (patterning second metal level 107 and form).In addition, before heating the step of photoresist, more can preferably comprise: passage 33 is carried out the step that an electricity slurry is handled (Plasma Treatment), to promote the electrical of thin-film transistor.
Then, shown in Fig. 1 I, with photoresist 154 after flowing again and second conductive layer (i.e. second metal level 107) behind the patterning is mask, other semiconductor layer that exposes (comprising n+ amorphous silicon layer 105 and amorphous silicon layer 103) is removed fully, the only surplus silicon nitride layer 101 in this moment grid connection pad district 11 and capacitive region 17 places, 19 places, data connection pad district then form a storehouse body that comprises data connection pad 197, n+ amorphous silicon layer 105 ' and amorphous silicon layer 103 '.And Fig. 1 I also is resulting structure after finishing according to the second road photomask technology of preferred embodiment of the present invention.
The 3rd road technology
At last, form a transparency conducting layer (for example being indium tin oxide layer-ITO layer) on silicon nitride layer 101, through behind the patterning, form a transparency electrode 43 on the pixel bonding pad 127 of the source S/drain D that exposes, a transparency electrode 41 on the grid connection pad 111 in grid connection pad district 11 and a transparency electrode 49 on the data connection pad 197 at 19 places, data connection pad district, shown in Fig. 1 J.Wherein, the transparency electrode 49 in data connection pad district 19 coats the storehouse body of being made up of data connection pad 197, n+ amorphous silicon layer 105 ' and amorphous silicon layer 103 '.
According to the foregoing description; utilize a photomask with four kinds of penetrations of not sharing the same light; to form the photoresist figure of three kinds of different-thickness; then can be used as protective layer in the display element through the photoresist 154 after flow being shaped again; and then the step of having exempted follow-up formation protective layer, reach and reduce the purpose that photomask uses number and reduces manufacturing cost.
Certainly; the present invention also can have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof; being familiar with those of ordinary skill in the art ought can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection range of the appended claim of the present invention.
Claims (25)
1. method of manufacturing thin film transistor, a channel region of this thin-film transistor is characterized in that between an one source pole district and a drain region this method comprises:
Form a patterning first conductive layer on a substrate, this patterning first conductive layer comprises a grid;
On this patterning first conductive layer, form a dielectric layer, semi-conductor layer, one second conductive layer and a photoresist layer in regular turn;
Provide one to have the photomask of the penetration of not sharing the same light and this photoresist layer is carried out exposure imaging, photoresist layer has at least three kinds of thickness behind the patterning that is produced, photoresist corresponding to this channel region place has one first thickness, photoresist corresponding to a pixel bonding pad of this source area/this periphery, drain region has one second thickness, photoresist corresponding to this source area and this drain region then has one the 3rd thickness, and the 3rd thickness greater than this second thickness greater than this first thickness;
Remove the photoresist that has this first thickness corresponding to this channel region place, and etching is positioned at this second conductive layer at this channel region place and this semiconductor layer partly, with a passage, one source pole and a drain electrode that forms this thin-film transistor;
Remove photoresist, and expose this source electrode and this drain electrode this pixel bonding pad wherein with this second thickness;
Heating makes the photoresist after flowing again cover this passage corresponding to this source area and this drain region and peripheral residue photoresist thereof;
With this photoresist after flowing again and this second conductive layer behind the patterning is mask, removes this semiconductor layer that exposes; And
Form a patterned transparent electrode, part is covered in this source electrode of exposing maybe on this drain electrode this pixel bonding pad wherein.
2. manufacture method according to claim 1 is characterized in that, the step that forms this grid comprises:
Form a first metal layer on this substrate; With
This first metal layer of patterning is to form this grid.
3. manufacture method according to claim 1 is characterized in that this semiconductor layer comprises an amorphous silicon layer.
4. manufacture method according to claim 3 is characterized in that, also is included in and forms a n+ amorphous silicon layer on this amorphous silicon layer.
5. manufacture method according to claim 1, it is characterized in that, comprise that the mode of utilizing dry-etching or ashing has the photoresist of this first thickness to remove corresponding to this channel region place, and utilize the mode of Wet-type etching to remove this second conductive layer that is positioned at this channel region place.
6. manufacture method according to claim 1 is characterized in that, comprises that the mode of utilizing etching or ashing is to remove corresponding to this source area and this drain region and peripheral photoresist thereof.
7. manufacture method according to claim 1 is characterized in that, before heating the step of photoresist, also comprises: this passage is carried out an electricity slurry handle.
8. manufacture method according to claim 1 is characterized in that this photoresist layer comprises an organic material.
9. manufacture method according to claim 1 is characterized in that this dielectric layer comprises a silicon nitride layer, and this transparency electrode comprises an indium tin oxide layer.
10. the manufacture method of a display element, this display element has a plurality of holding wire and a plurality of data signal lines of scanning and intersects vertically with the form of array, and those scan holding wire and those data signal lines define a plurality of pixel regions, each pixel region a pair ofly scans holding wire and adjacent a pair of data signal line is defined by adjacent, each scan signal line extends a grid connection pad that is connected a grid connection pad district, each data signal line extends a data connection pad that is connected a data connection pad district, it is characterized in that this manufacture method comprises:
On a substrate, form a patterning first conductive layer, this patterning first conductive layer comprises each signal line, at a grid of a thin film transistor region of each pixel region and a capacitance electrode of a capacitive region, and this grid connection pad in each grid connection pad district;
On this substrate, form a dielectric layer, semi-conductor layer, one second conductive layer and a photoresist layer in regular turn, this substrate of whole covering;
Provide one to have the photomask of four kinds of penetrations of not sharing the same light and this photoresist layer is carried out exposure imaging, photoresist layer comprises behind the patterning that is produced: (a) have one first thickness at the photoresist corresponding to a channel region place of this thin film transistor region, photoresist corresponding to a pixel bonding pad of the periphery of one source pole district/drain region has one second thickness, photoresist corresponding to this source area and this drain region then has one the 3rd thickness, and the 3rd thickness greater than this second thickness greater than this first thickness, (b) remove fully at photoresist, then have this first thickness corresponding to the photoresist of the periphery at this grid connection pad place corresponding to this grid connection pad place in this grid connection pad district;
Remove this second conductive layer, this semiconductor layer and this dielectric layer in this grid connection pad district in regular turn,, remove this photoresist layer with this first thickness, this second conductive layer of exposed portions serve simultaneously to expose this grid connection pad;
This photoresist layer with this second and the 3rd thickness is a mask, removes this second conductive layer and this semiconductor layer of part of exposing, with a passage, one source pole and a drain electrode that forms this thin film transistor region, and each this data signal line and each this data connection pad;
Remove photoresist layer, and expose this source electrode and this drain electrode this pixel bonding pad wherein corresponding to this source area and this drain region and this second thickness of peripheral tool thereof;
Heating makes the photoresist after flowing again cover this passage corresponding to this source area and this drain region and peripheral residue photoresist thereof;
With this photoresist after flowing again and this second conductive layer behind the patterning is mask, removes this semiconductor layer that exposes; And
Form a patterned transparent electrode, part is covered in this source electrode of exposing maybe on this drain electrode this pixel bonding pad wherein.
11. manufacture method according to claim 10 is characterized in that, forms a first metal layer on this substrate, and this first metal layer of patterning is to form this grid, this capacitance electrode and this grid connection pad.
12. manufacture method according to claim 10 is characterized in that, this semiconductor layer comprises an amorphous silicon layer.
13. manufacture method according to claim 12 is characterized in that, also is included in and forms a n+ amorphous silicon layer on this amorphous silicon layer.
14. manufacture method according to claim 13 is characterized in that, when this second conductive layer at this channel region place is with this n+ amorphous silicon layer in this thin film transistor region of etching, also comprises step:
Be etched with this second conductive layer and this n+ amorphous silicon layer of Removing All this grid connection pad district and this capacitive region place simultaneously.
15. manufacture method according to claim 10 is characterized in that, this photoresist layer is being carried out in the step of exposure imaging, photoresist layer also comprises behind this patterning that is produced:
(c) photoresist at this capacitive region place has this first thickness.
16. manufacture method according to claim 10, it is characterized in that, comprise the mode of utilizing dry-etching or ashing removing in this thin film transistor region photoresist, and utilize the mode of Wet-type etching to remove this second conductive layer that is positioned at this channel region place corresponding to this channel region place.
17. manufacture method according to claim 10 is characterized in that, after exposing this grid connection pad in this grid connection pad district, also comprises:
The mode of utilizing dry-etching or ashing to this patterning after photoresist layer handle, to remove the photoresist at this grid connection pad district and this capacitive region place fully.
18. manufacture method according to claim 10 is characterized in that, comprise the mode of utilizing etching or ashing with in this thin film transistor region of thinning corresponding to this source area and this drain region and peripheral photoresist thereof.
19. manufacture method according to claim 10 is characterized in that, before heating the step of photoresist, also comprises: this passage to this thin film transistor region carries out an electricity slurry processing.
20. manufacture method according to claim 10 is characterized in that, is forming this patterned transparent electrode in this source electrode that exposes maybe during the step in this drain electrode, this patterned transparent electrode also is covered on this grid connection pad in this grid connection pad district simultaneously.
21. manufacture method according to claim 10 is characterized in that, data connection pad district is carrying out this photoresist layer in the step of exposure imaging, and photoresist layer also comprises behind this patterning that is produced:
(d) photoresist at this place, data connection pad district has this second thickness.
22. manufacture method according to claim 21 is characterized in that, when removing corresponding to this source area and this drain region and peripheral photoresist thereof, this photoresist pattern that also removes this place, data connection pad district simultaneously is to expose this data connection pad.
23. manufacture method according to claim 22 is characterized in that, is forming this patterned transparent electrode in this source electrode that exposes maybe during the step in this drain electrode, this patterned transparent electrode also is covered on this data connection pad of locating in this data connection pad district simultaneously.
24. manufacture method according to claim 10 is characterized in that, this photoresist layer comprises an organic material.
25. manufacture method according to claim 10 is characterized in that, this dielectric layer comprises a silicon nitride layer, and this transparency electrode comprises an indium tin oxide layer.
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Also Published As
| Publication number | Publication date |
|---|---|
| CN100511653C (en) | 2009-07-08 |
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