CN101110446A

CN101110446A - Channel structure of high voltage NMOS field transistor in EEPROM peripheral circuit and manufacturing method thereof

Info

Publication number: CN101110446A
Application number: CNA2006100292490A
Authority: CN
Inventors: 钱文生
Original assignee: Shanghai Hua Hong NEC Electronics Co Ltd
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2006-07-21
Filing date: 2006-07-21
Publication date: 2008-01-23

Abstract

The present invention discloses a trench structure for medium and high voltage NMOS field transistor of EEPROM peripheral circuit, which is filled with boron ions. Production technique of the trench structure lies in that in current technical flows, a trench area is opened through photo-etching. In synchronization with light dope/boron implantation into high-voltage PMOS transistor, boron ions are implanted into the trench. The present invention ensures more effective field isolation, reduces unit area and improves chip integration.

Description

The channel structure and the manufacture method of EEPROM peripheral circuit mesohigh NMOS field transistor

Technical field

The present invention relates to the channel structure of a kind of EEPROM peripheral circuit mesohigh NMOS (N type metal oxide semiconductor) field transistor (Field Transistor); The invention still further relates to a kind of process for making of this channel structure.

Background technology

Growing along with semiconductor fabrication, the competition of integrated circuit (IC) design is growing more intense, and especially at the design aspect of memory cell, in order to enhance competitiveness, need as much as possible dwindle cellar area, simplifies manufacture craft.In memory cell, it is the isolation that is used between the unit that very big area is arranged, and as shortening the isolation spacing between the unit, will effectively reduce cellar area.

In EEPROM (electrically erasable programmable ROM) unit, the size of unit was originally more little, therefore isolated size and also required very little.Because the doping content of the N trap of memory cell is not high, for dwindling the isolation size, under field oxide, to remake the primary field ion usually and inject, so just need to increase a photoetching, also increased the technology cost simultaneously.

Summary of the invention

The technical problem to be solved in the present invention provides a kind of channel structure of EEPROM peripheral circuit mesohigh NMOS field transistor, and it can more effectively bring into play an isolation effect, can reduce cellar area again, improves the integrated level of chip; For this reason, the present invention also will provide a kind of process for making of this channel structure.

For solving the problems of the technologies described above, the channel structure of EEPROM peripheral circuit mesohigh NMOS field transistor of the present invention is to adopt following technical scheme to realize, injects the boron ion in described raceway groove.

The process for making of above-mentioned raceway groove is: in the existing processes flow process, open channel region by photoetching, when carrying out high voltage PMOS transistor lightly-doped source/leakage (LDD) boron ion injection, with the boron implanted channel.

After adopting the present invention, increase the raceway groove concentration of N type field transistor, stoped the mutual break-through of (two unit pipes lightly-doped sources leak between N-) between the unit, also increased threshold voltage vt 2 simultaneously, played the good isolation effect.Can dwindle the isolation size effectively, can save a photoetching again, save the technology cost.

Description of drawings

The present invention is further detailed explanation below in conjunction with the drawings and specific embodiments:

Fig. 1 is the channel structure schematic diagram of EEPROM peripheral circuit mesohigh NMOS field transistor of the present invention;

Fig. 2 to Fig. 5 is the high pressure NMOS field transistor manufacture craft flow chart with channel structure shown in Figure 1.

Embodiment

Because the transistor channel doping content of EEPROM unit is all lower usually, therefore the isolation ratio between the unit is difficult, require the interval between the unit enough big on the one hand, prevent the mutual break-through between Unit two, also will satisfy field transistor on the other hand has sufficiently high threshold voltage vt 2.

The channel structure of EEPROM peripheral circuit mesohigh NMOS field transistor of the present invention as shown in Figure 1, on high pressure P trap (HV PWell), form two unit pipes lightly-doped sources and leak N type N-district, inject the boron ion in the raceway groove between the N-district, simultaneously, N-district and raceway groove adopt selective oxidation silicon to isolate (LOCOS).Form the structure of embedded injection zone of fieldistor channel.

The manufacture craft flow process that realizes the high pressure NMOS field transistor of above-mentioned channel structure is:

On P type substrate (P-Sub) with LOCOS isolation, carry out HV Pwell ion and inject, form HV Pwell (referring to Fig. 2).

On silicon chip, apply photoresist, open high pressure NMOS field transistor mid portion channel region and high voltage PMOS LDD zone by photoetching, the LDD boron atom that carries out high voltage PMOS transistor then injects, and makes high pressure NMOS field transistor intermediate channel zone inject the boron ion.(referring to Fig. 3).

Remove photoresist, and apply photoresist again, utilize photoetching to open high pressure NMOS lightly-doped source drain region, carry out phosphonium ion and inject, form two unit pipes N type lightly-doped sources and leak the N-district.(referring to Fig. 4).

Remove photoresist, and the deposit polysilicon gate, etch polysilicon grid then form the grid of high pressure NMOS field transistor.(referring to Fig. 5).

The present invention need not to increase special photolithography plate for the isolation that improves between the EEPROM unit, only need in the photolithography plate of high voltage PMOS LDD, the channel region of high pressure NMOS field transistor is opened, the high-energy boron ion of high voltage PMOS LDD is injected in the field transistor raceway groove simultaneously; Inject to replace extra field ion.Under the situation that does not increase the photoetching number of times, increased the impurity concentration of field transistor raceway groove, effectively reduced the isolation size between the unit, improve the threshold voltage of field transistor, improved isolation effect.So both can play the good isolation effect, and can dwindle the isolation size effectively, and can save a photoetching again, simplify technology, save the technology cost.

Claims

1. the channel structure of an EEPROM peripheral circuit mesohigh NMOS field transistor is characterized in that, injects the boron ion in described raceway groove.

2. the process for making of a channel structure as claimed in claim 1, it is characterized in that, in the existing processes flow process, open channel region by photoetching, when carrying out high voltage PMOS transistor lightly-doped source/leakage boron ion injection, with the boron implanted channel.