CN101093518A - 优化电路设计中的流水线结构布置的方法和系统 - Google Patents
优化电路设计中的流水线结构布置的方法和系统 Download PDFInfo
- Publication number
- CN101093518A CN101093518A CNA2007101010852A CN200710101085A CN101093518A CN 101093518 A CN101093518 A CN 101093518A CN A2007101010852 A CNA2007101010852 A CN A2007101010852A CN 200710101085 A CN200710101085 A CN 200710101085A CN 101093518 A CN101093518 A CN 101093518A
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- CN
- China
- Prior art keywords
- layout
- circuit design
- latch
- pipeline organization
- design
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
Abstract
Description
Claims (14)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/425,721 | 2006-06-22 | ||
US11/425,721 US7496866B2 (en) | 2006-06-22 | 2006-06-22 | Method for optimizing of pipeline structure placement |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101093518A true CN101093518A (zh) | 2007-12-26 |
CN101093518B CN101093518B (zh) | 2010-04-14 |
Family
ID=38874884
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2007101010852A Expired - Fee Related CN101093518B (zh) | 2006-06-22 | 2007-04-26 | 优化电路设计中的流水线逻辑结构布置的方法和系统 |
Country Status (2)
Country | Link |
---|---|
US (2) | US7496866B2 (zh) |
CN (1) | CN101093518B (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110192192A (zh) * | 2017-01-17 | 2019-08-30 | 赛灵思公司 | 用于电路设计的基于神经网络的物理综合 |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8918748B1 (en) * | 2012-08-24 | 2014-12-23 | Altera Corporation | M/A for performing automatic latency optimization on system designs for implementation on programmable hardware |
US10572618B2 (en) | 2017-11-28 | 2020-02-25 | International Business Machines Corporation | Enabling automatic staging for nets or net groups with VHDL attributes |
US10558775B2 (en) | 2017-12-20 | 2020-02-11 | International Business Machines Corporation | Memory element graph-based placement in integrated circuit design |
US11113176B2 (en) | 2019-01-14 | 2021-09-07 | Microsoft Technology Licensing, Llc | Generating a debugging network for a synchronous digital circuit during compilation of program source code |
US11093682B2 (en) * | 2019-01-14 | 2021-08-17 | Microsoft Technology Licensing, Llc | Language and compiler that generate synchronous digital circuits that maintain thread execution order |
US11275568B2 (en) | 2019-01-14 | 2022-03-15 | Microsoft Technology Licensing, Llc | Generating a synchronous digital circuit from a source code construct defining a function call |
US10810343B2 (en) | 2019-01-14 | 2020-10-20 | Microsoft Technology Licensing, Llc | Mapping software constructs to synchronous digital circuits that do not deadlock |
US11106437B2 (en) | 2019-01-14 | 2021-08-31 | Microsoft Technology Licensing, Llc | Lookup table optimization for programming languages that target synchronous digital circuits |
US11144286B2 (en) | 2019-01-14 | 2021-10-12 | Microsoft Technology Licensing, Llc | Generating synchronous digital circuits from source code constructs that map to circuit implementations |
US11030367B2 (en) | 2019-09-11 | 2021-06-08 | International Business Machines Corporation | Out-of-context feedback hierarchical large block synthesis (HLBS) optimization |
CN111046513B (zh) * | 2019-11-25 | 2020-08-11 | 河海大学 | 智能综合能源系统供热管网布局优化设计方法 |
JP7449780B2 (ja) * | 2020-06-05 | 2024-03-14 | 株式会社日立製作所 | 管路更新支援装置、及び管路更新支援方法 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07319938A (ja) | 1994-05-20 | 1995-12-08 | Hitachi Ltd | 論理設計支援方法 |
US5659716A (en) * | 1994-11-23 | 1997-08-19 | Virtual Machine Works, Inc. | Pipe-lined static router and scheduler for configurable logic system performing simultaneous communications and computation |
US6594814B1 (en) * | 1999-12-29 | 2003-07-15 | National Science Council | Dynamic pipelining approach for high performance circuit design |
JP3759860B2 (ja) * | 2000-06-08 | 2006-03-29 | シャープ株式会社 | 自己同期型のパイプライン制御を採用したデータ駆動型情報処理装置の設計方法 |
US6684373B1 (en) * | 2000-07-20 | 2004-01-27 | Silicon Graphics, Inc. | Optimize global net timing with repeater buffers |
US6588001B1 (en) * | 2000-08-31 | 2003-07-01 | Micron Technology, Inc. | Method for inserting repeater cells in a deep sub-micron design |
JP2003006253A (ja) * | 2001-06-20 | 2003-01-10 | Mitsubishi Electric Corp | ロジック回路設計方法およびその方法をコンピュータに実行させるプログラム |
US7207024B2 (en) * | 2002-09-13 | 2007-04-17 | Cadence Design Sytems, Inc. | Automatic insertion of clocked elements into an electronic design to improve system performance |
US6834378B2 (en) * | 2002-10-03 | 2004-12-21 | International Business Machines Corporation | System on a chip bus with automatic pipeline stage insertion for timing closure |
CN1266592C (zh) * | 2003-11-26 | 2006-07-26 | 中国人民解放军国防科学技术大学 | 依据确定延迟的动态vliw指令调度方法 |
CN1267853C (zh) * | 2004-04-07 | 2006-08-02 | 西安交通大学 | 同步流水算术编码器的vlsi实现方法 |
US7426704B2 (en) * | 2004-05-10 | 2008-09-16 | International Business Machines Corporation | Design verification of highly optimized synchronous pipelines via random simulation driven by critical resource scheduling |
EP1907957A4 (en) * | 2005-06-29 | 2013-03-20 | Otrsotech Ltd Liability Company | INVESTMENT METHODS AND SYSTEMS |
-
2006
- 2006-06-22 US US11/425,721 patent/US7496866B2/en not_active Expired - Fee Related
-
2007
- 2007-04-26 CN CN2007101010852A patent/CN101093518B/zh not_active Expired - Fee Related
-
2009
- 2009-01-05 US US12/348,380 patent/US8141019B2/en not_active Expired - Fee Related
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110192192A (zh) * | 2017-01-17 | 2019-08-30 | 赛灵思公司 | 用于电路设计的基于神经网络的物理综合 |
CN110192192B (zh) * | 2017-01-17 | 2023-03-17 | 赛灵思公司 | 用于电路设计的基于神经网络的物理综合 |
Also Published As
Publication number | Publication date |
---|---|
CN101093518B (zh) | 2010-04-14 |
US8141019B2 (en) | 2012-03-20 |
US7496866B2 (en) | 2009-02-24 |
US20090106711A1 (en) | 2009-04-23 |
US20070300192A1 (en) | 2007-12-27 |
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C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
TR01 | Transfer of patent right | ||
TR01 | Transfer of patent right |
Effective date of registration: 20171127 Address after: Grand Cayman, Cayman Islands Patentee after: GLOBALFOUNDRIES INC. Address before: American New York Patentee before: Core USA second LLC Effective date of registration: 20171127 Address after: American New York Patentee after: Core USA second LLC Address before: American New York Patentee before: International Business Machines Corp. |
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CF01 | Termination of patent right due to non-payment of annual fee | ||
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Granted publication date: 20100414 Termination date: 20190426 |