CN101089994A - Non-volatile memory device and method thereof - Google Patents
Non-volatile memory device and method thereof Download PDFInfo
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- CN101089994A CN101089994A CNA2007101090185A CN200710109018A CN101089994A CN 101089994 A CN101089994 A CN 101089994A CN A2007101090185 A CNA2007101090185 A CN A2007101090185A CN 200710109018 A CN200710109018 A CN 200710109018A CN 101089994 A CN101089994 A CN 101089994A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/10—Decoders
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5628—Programming or writing circuits; Data input circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
- G11C16/3427—Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
- G11C2211/564—Miscellaneous aspects
- G11C2211/5646—Multilevel memory with flag bits, e.g. for showing that a "first page" of a word line is programmed but not a "second page"
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Abstract
A non-volatile memory device and method thereof are provided. The example non-volatile memory device may include a plurality of main cells, each of the plurality of main cells arranged at first intersection regions between one of a plurality of word lines and one of a plurality of main bit line pairs and a plurality of flag cells, each of the plurality of flag cells arranged at second intersection regions between one of the plurality of word lines and a plurality of flag bit line pairs, each of the plurality of flag cells configured to store page information in a manner such that page information associated with main cells corresponding to one of the main bit line pairs is stored in flag cells corresponding to more than one of the flag bit line pairs.
Description
Technical field
In general example embodiment of the present invention relates to nonvolatile memory device and method thereof.
Background technology
Memory device as volatile memory and nonvolatile memory, can be included in traditional mobile device (as MP3 player, portable electronic device (PMP), mobile phone, notebook, PDA(Personal Digital Assistant) etc.).Traditional mobile device can comprise high relatively memory capacity, so that higher functional (functionality) (for example, videograph, picture etc.) is provided.Traditional many bit memory equipment of storing 2 Bit datas or multi-bit certificate in the single memory unit can allow each memory cell to obtain more high storage density.
If 1 Bit data is stored in the single memory unit, then described memory cell can have the threshold voltage that belongs to one of two threshold voltage distribution.That is, 1 bit memory cell can have two threshold voltage ranges, distribution or " state ", corresponding to first logic level (for example, high logic level or logical one) or second logic level (for example, low logic level or logical zero).In another example, if 2 Bit datas are stored in the single memory unit, then memory cell can comprise and corresponding 4 the voltages distributions that separate of 4 corresponding states (for example, " 00 ", " 01 ", " 10 ", " 11 ").
Fig. 1 illustrates the logic state of 2 traditional bit memory cell.With reference to Fig. 1, threshold voltage distribution can Be Controlled, so that corresponding to the threshold voltage distribution of 4 states, be determined in the preset threshold voltage window respectively.Increase progressively step pulse programming (ISPP) technology (process) and can be used to control threshold voltage distribution.
In traditional ISPP scheme, threshold voltage can be adjusted with fixing program voltage increment in iterative program cycle period.Therefore, the low relatively fixed increment of program voltage is set allows threshold voltage distribution to be controlled more accurately, make that the abundant surplus between different threshold voltage distribution can be kept.Yet,, can require the more time to carry out ISPP technology if the fixed increment of program voltage is lower.Therefore, the increment of program voltage can be determined based on threshold voltage distribution control and the compromise between the execution time.
Even used the ISPP scheme, it is wideer that the threshold voltage distribution of each state can become, and this and the window ratio of hope are because any one of many factors, can reduce equally adjacent voltage between distributing surplus and increase the possibility (for example, during read operation) of memory error.
Fig. 2 illustrates the field coupled/F-Poly coupling that takes place between traditional memory cell.
With reference to Fig. 2, threshold voltage distribution may increase because of the coupling between neighbor memory cell.Described coupling can be called " field coupled " or " F-poly coupling ".For example, in Fig. 2, can suppose that memory cell MCA can be any one unit that is programmed to have in 4 states, and memory cell MCB is programmed to have any one unit in 4 states.Under such hypothesis, when memory cell MCB was programmed, electric charge can be accumulated in floating grid (floatinggate) FG.Then, the electromotive force of the floating grid FG of neighbor memory cell MCA can increase owing to the floating grid FG coupling with memory cell MCB.The threshold voltage of Zeng Jiaing in this way, even after programming operation, can be kept because of the coupling between the floating grid.Memory cell MCB can comprise the memory cell in word-line direction and/or bit line direction placement with respect to memory cell MCA.Coupling between the floating grid of each memory cell can cause that the threshold voltage of the memory cell MCA that programmed increases, and described threshold voltage distribution may similarly increase, as by shown in the dotted line of Fig. 2.
Traditional flash memory device can comprise the unit (being referred to as hereinafter, " tag unit ") that is used for the storage information (hereinafter, be referred to as " flag information ") relevant with row (or page or leaf).Flag information can with belong to mutually go together/the identical condition of the condition of master unit of page or leaf under, be programmed in the tag unit.
Fig. 3 illustrates the programming process of traditional tag unit.With reference to Fig. 3, in an example, can suppose that each row comprises two pages.If programming (for example belongs to given row, the memory cell of even-numbered page or leaf WL0) 1. (for example, be positioned at BLe and WL0 infall), then 1. the corresponding tag unit in the tag unit zone (for example, is positioned at FBLe and WL0 infall) and can be optionally programmed.And, (for example, the memory cell of odd-numbered page or leaf WL0) 2. (for example, is positioned at BLo and WL0 infall) if programming belongs to given row, then 2. the corresponding tag unit in the tag unit zone (for example, is positioned at FBLo and WL0 infall) and can be optionally programmed.Equally, (for example, the memory cell of even-numbered page or leaf WL1) 3. (for example, is positioned at BLe and WL1 infall) if programming belongs to next line, then 3. the corresponding tag unit in the tag unit zone (for example, is positioned at FBLe and WL1 infall) and can be optionally programmed.And, (for example, the memory cell of odd-numbered page or leaf WL1) 4. (for example, is positioned at BLo and WL1 infall) if programming belongs to described row, then 4. the corresponding tag unit in the tag unit zone (for example, is positioned at FBLo and WL1 infall) and can be optionally programmed.
With reference to Fig. 3, arrow can be indicated: if given unit is programmed, and the F-poly coupling that then previous programmed cells can receive.For example, if 2. tag unit is programmed, then tag unit 1. can be owing to 2. tag unit receives the F-poly coupling.
In traditional multi-bit flash storage component part, tag unit can be configured to have and the threshold voltage of going up most or high threshold voltage distributes and is associated.Because tag unit can be programmed to have the threshold voltage that is associated with the threshold voltage distribution that goes up most, so if adjacent cells is programmed, then formerly the threshold voltage of programmed unit can increase owing to the F-poly coupling.For example, with reference to Fig. 3,1. tag unit can may cause that tag unit that tag unit threshold voltage 1. increases 2., during each the programming operation 3. and 4., receive the F-poly coupling.Similarly, 2. and 3. tag unit also can receive F-poly coupling, and this tag unit 2. and threshold voltage 3. also can increase.The increase of the threshold voltage of tag unit can be reduced in the electric current on the unit that flows through a string tag unit during the read operation, and this may increase the generation of read error.
Summary of the invention
One exemplary embodiment of the present invention is directed to a kind of nonvolatile memory device, and it comprises: a plurality of master units, each in these a plurality of master units be arranged on one of a plurality of word lines and a plurality of main bit line to one of between first intersecting area; And a plurality of tag unit, each of these a plurality of tag unit be arranged on a plurality of sign bit lines to and a plurality of word line in one between second intersecting area, each of these a plurality of tag unit is configured to memory page information in such a way, make with corresponding to main bit line to one of the page information that is associated of master unit, be stored in and more than a described sign bit line in corresponding each tag unit.
Another one exemplary embodiment of the present invention is directed to a kind of method of operating nonvolatile memory device, comprising: one of a plurality of word lines and a plurality of main bit line to one of between first intersecting area, arrange each in a plurality of master units; And page information is stored at least one of described a plurality of tag unit, each of these a plurality of tag unit be arranged on a plurality of sign bit lines to and a plurality of word line in one between second intersecting area, described page information is stored in such a way, make with corresponding to main bit line to one of the page information that is associated of master unit, be stored in and more than a described sign bit line in corresponding each tag unit.
Another one exemplary embodiment of the present invention is directed to a kind of multi-bit flash memory device and programmed method thereof, and it can reduce the F-poly coupling that (for example, minimizing) occurs between the tag unit that is used for memory page information.
Description of drawings
Accompanying drawing is comprised provides further understanding of the invention, and is merged and constituted the part of this instructions.Accompanying drawing has been set forth example embodiment of the present invention with describing, and is used to explain principle of the present invention.
Fig. 1 illustrates the logic state of 2 traditional bit memory cell.
Fig. 2 illustrates the field coupled/F-poly coupling that occurs between traditional memory cell.
Fig. 3 illustrates the programming process of traditional tag unit.
Fig. 4 is the block diagram of diagram according to the flash memory device of example embodiment of the present invention.
Fig. 5 is the circuit diagram of diagram according to the memory cell array part of flash memory device example embodiment of the present invention, Fig. 4.
Fig. 6 to Fig. 8 illustrates the tag unit programming process according to flash memory device 1000 example embodiment of the present invention, Fig. 4.
Embodiment
Detailed n-lustrative example embodiment of the present invention is disclosed at this.Yet concrete structure disclosed herein and function detail only are exemplary, are used to describe the purpose of example embodiment of the present invention.Yet example embodiment of the present invention can realize with many alternative forms, and the embodiment that should not be construed as limited in this proposition.
Therefore, although example embodiment of the present invention allows various modifications and replacement form, its specific embodiment illustrates by the example in the accompanying drawing, and will describe in detail at this.Yet, should be appreciated that not having restriction example embodiment of the present invention is the intention of disclosed particular form, and opposite, example embodiment of the present invention will cover whole modifications, the equivalence that falls in the spirit and scope of the present invention and replace.The description that identical label spreads all over accompanying drawing can refer to components identical.
Will be understood that although first, second grade of term can be used to describe various elements at this, these elements should not limited by these terms yet.These terms only are used to distinguish an element and another element.For example, first element can be known as second element, and similarly, second element can be known as first element, and does not depart from scope of the present invention.As used herein, term " and/or " comprise one or more any and whole combination of the project that is listed that is associated.
Will be understood that when element is called when being " connected " or " coupled " another element, it can be connected directly or be coupled to another element, perhaps can have Jie's element therebetween.On the contrary, " when being directly connected " or " directly coupled " to another element, the element that does not have to be situated between therebetween exists when element is called.Other words that are used to describe each interelement relation should explain with similar fashion (for example, " and ... between " with respect to " and directly exist ... between ", " adjacent " is with respect to " direct neighbor " etc.).
Term only is used to describe the purpose of specific embodiment as used herein, and intention does not lie in restriction example embodiment of the present invention.As used herein, singulative " (a) ", " one (an) " and " being somebody's turn to do " intention are also to comprise plural form, unless context clearly refers else.Will be further understood that, term " comprises (comprise) ", " comprising (comprising) ", " comprising (include) " and/or " comprising (including) ", when when this uses, limit the existence of described feature, integral body (integer), step, operation, element and/or assembly, but do not get rid of one or more other the existence or interpolations of feature, integer, step, operation, element, assembly and/or its set.
Unless different definition is arranged, as used herein all terms (term that comprises technology and science) have with the present invention under the field in the identical implication of implication of those of ordinary skill common sense.Will be further understood that some term as those terms that define, should be interpreted as and has the implication consistent with the environment of association area in common dictionary, and by with idealized or too regular meaning interpretation, unless in this clearly so definition.
Fig. 4 is the block diagram of diagram according to the flash memory device 1000 of example embodiment of the present invention.
In the example embodiment of Fig. 4, flash memory device 1000 can comprise and is used to store the memory cell array 100 that multi-bit it is believed that breath.A plurality of bit lines to (BLe0, BLo0)-(BLei BLoi) can be arranged on the memory cell array 100.String (string) 101 can be connected to every pair bit line (for example, being referred to as main bit line).The string 101 of every row can constitute memory block.
Fig. 5 is the circuit diagram of diagram according to the part of memory cell array 100 example embodiment of the present invention, Fig. 4.
In the example embodiment of Fig. 5, each string of memory block 101 can comprise: string select transistor SST, select transistor GST and memory cell MC31-MC0.In an example, each memory cell can be configured to the floating grid transistor.String select transistor SST can be controlled by string selection wire SSL, and can comprise the drain electrode that is connected to corresponding bit line.Ground selects transistor GST to be controlled by ground selection wire GSL, and can comprise the source electrode that is connected to common source polar curve CSL.Memory cell MC31-MC0 can be connected in series in source electrode and the ground of string select transistor SST and select between the drain electrode of transistor GST, and can be respectively by corresponding word line WL31-WL0 control.A plurality of bit lines to (BLe0, BLo0)-(BLei BLoi) can be arranged and intersects with word line WL31-WL0.Reading/programming operation during, a bit lines of each bit line pairs can be selected by the page or leaf buffer stopper 300 of Fig. 4.
Get back to the example embodiment of Fig. 4, memory cell array 100 can also comprise a plurality of sign bit lines to (FBLej, FBLoj).For example, memory cell array 100 can be provided with at least two pairs of sign bit lines.As mentioned above, the string 101 can be connected to each the sign bit line (FBLej, FBLoj).In an example, (FBLej, FBLoj) string 101 of Lian Jieing can dispose as shown in the example embodiment of Fig. 5 with the sign bit line.Form with the sign bit line (FBLej, FBLoj) the selection transistor and the memory cell of each string of Lian Jieing, can with belong to the string of going together mutually together, the selection circuit 200 of go is controlled.For example, (BLe0, (FBLej, each memory cell FBLoj) can be connected to each word line to bit line for each memory cell BLo0) and sign bit line.In an example, with sign bit line (FBLej, the memory cell of each row that FBLoj) connects, can store colleague's page information mutually, and can be programmed or be converted to " going up most " state ST4 (for example, ceiling voltage distributes, as shown in the ST4 among Fig. 1 like that).With reference to flash memory device 1000, (FBLej, the FBLoj) memory cell of Lian Jieing can be programmed with the mode different with traditional field, as describing in more detail hereinafter with the sign bit line.
In the example embodiment of Fig. 4, page or leaf buffer stopper 300 can be by steering logic piece 800 control, and can comprise with a plurality of bit lines to (BLe0, BLo0)-(BLei, BLoi) page buffer 301 of Lian Jieing.Each page buffer 301 can be operating as write driver or detecting amplifier based on operator scheme.Page or leaf buffer stopper 300 can also comprise respectively with the sign bit line to (FBLej, FBLoj) page buffer 302 of Lian Jieing.Page buffer 302 each can be during programming operation, by 800 pairs of programming data settings of steering logic piece.During programming operation, the information of the word line of selecting (for example, the page or leaf of selecting) can be under the control of steering logic piece 800, be stored in the memory cell of the sign bit line FBLej that is connected with selected word line or FBLoj, as general's description in more detail hereinafter.During read operation, the page information that is read by page buffer 302 can be provided for steering logic piece 800.Steering logic piece 800 can be configured to produce during read operation selects signal SEL.For example, in order to export the data that read by page buffer 301, steering logic piece 800 can change (for example, activating) and select signal SEL to first logic level (for example, high logic level or logical one).Therefore, in this example, steering logic piece 800 can use incoming page information, controls follow-up operation.In the example that substitutes, in order to export the page information that is read by page buffer 302, steering logic piece 800 can change (for example, deactivation) and select signal SEL to second logic level (for example, low logic level or logical zero).In this example, steering logic piece 800 can be exported incoming page information to selecting circuit 600.
In the example embodiment of Fig. 4, every row/word line can comprise at least two pages (for example, pages or leaves of even number and odd-numbered).Therefore, at least two bit line BLe and BLo can be electrically connected to a page buffer.In an example, one page (for example, the page or leaf of even-numbered) can be selected by the page buffer corresponding to bit line BLe, and this bit line BLe is corresponding to the page or leaf of even-numbered.Equally, another page or leaf (for example, the page or leaf of odd-numbered) can be selected with the corresponding page buffer of bit line BLo, and this bit line BLo is corresponding with the page or leaf of odd-numbered.
In the example embodiment of Fig. 4, flash memory device 1000 can also comprise: redundant array 400 and redundant page or leaf buffer stopper 410.Redundant array 400 can comprise: redundant bit line is right, be used for substituting a sign bit line to (BLej, BLoj); And/or a plurality of redundant bit lines are right, be used for respectively substituting many to the sign bit line (BLej, BLoj).The information that substitutes of sign bit line may be programmed in the steering logic piece 800.In the example that substitutes, the information that is used for the surrogate markers bit line may be programmed into fusing (fuse) box (not shown).Yet, will recognize that other one exemplary embodiment can be stored the information of relevant surrogate markers bit line with any known way.And although do not illustrate clearly in Fig. 4, each string also can be connected to redundancy or alternative bit line.A redundant page or leaf buffer stopper 410 can comprise and is connected to the right redundant page buffer of at least one redundant bit line.
In the example embodiment of Fig. 4, column select circuit 500 can be controlled by steering logic 800, and can select the page buffer 301 of page or leaf buffer stopper 300 by given unit (for example, * 8, * 16, * 32 etc.).The data bit of the page buffer of selecting 301 can be output to selects circuit 600.Select circuit 600 to select the output of column select circuit 500, and/or can select in response to selecting signal SEL from the page information of steering logic piece 800 outputs.For example, if select signal SEL to be changed (for example, deactivation), then select circuit 600 that the page information that provides from steering logic piece 800 can be provided to second logic level (for example, low logic level or logical zero).To first logic level (for example, high logic level or logical one), then select circuit 600 can select the output of column select circuit 500 if select signal SEL to be changed (for example, activating).
In the example embodiment of Fig. 4, input/output interface 700 can provide external interface (for example, having Memory Controller).Voltage generation circuit 900 can be by 800 controls of steering logic piece, and can be configured to produce the program/erase/read operation that is used for flash memory device 1000 each voltage (for example, word line voltage, main body (bulk) voltage, read voltage, by (pass) voltage) etc.
Fig. 6 to Fig. 8 illustrates the tag unit programming process according to flash memory device 1000 example embodiment of the present invention, Fig. 4.In an example, flash memory device 1000 can reduce the F-poly coupling between (for example, minimizing) tag unit, as describing in more detail now with reference to Fig. 6 to 8.
In the example embodiment of Fig. 6, in the tag unit zone, can provide two pairs the sign bit lines (FBLe0, FBLo0) and (FBLe1, FBLo1 ).Page buffer 302a and 302b can be connected respectively to corresponding sign bit line to (FBLe0, FBLo0) and (FBLe1, FBLo1).As shown in Figure 6, compare with master unit, tag unit can be programmed in a different manner.As mentioned above, given row/word line can comprise two pages (for example, odd and even number numbering pages or leaves).The even-numbered page or leaf can be included in given word line (for example, WL0) and the master unit arranged of even-numbered bit line (BLe) intersection.The odd-numbered page or leaf can be included in given word line (for example, WL0) and the master unit arranged of odd-numbered bit line (BLo) intersection.(FBLe0 FBLo0) can be connected to page buffer 302a to the sign bit line, and indicates that (FBLe1 FBLo1) can be connected to page buffer 302b to bit line.
In the example embodiment of Fig. 6, if 1. (for example by the master unit of word line WL0 and even-numbered bit line BLe definition, corresponding with the page or leaf of even-numbered) be programmed, then relevant information with the even-numbered page or leaf, can in corresponding page buffer 302a, be set up by steering logic piece 800, and by the tag unit of word line WL0 and sign bit line FBLe0 definition 1., can be programmed to have given state (for example, as the state of going up the most ST4 among Fig. 1).If 2. (for example by the master unit of word line WL0 and bit line BLo definition, corresponding with the page or leaf of odd-numbered) be programmed, then relevant information with the odd-numbered page or leaf, can in corresponding page buffer 302a, be set up by steering logic piece 800, and 2. by the tag unit of word line WL0 and sign bit line FBLo0 definition, can be programmed to have given state (for example, as the state of going up the most ST4 among Fig. 1).
In the example embodiment of Fig. 6, the page information relevant with next word line WL1 (for example, adjacent word line) can be stored in and be connected to another right sign bit line (FBLe1 is in tag unit FBLo1).For example, if 3. (for example by the master unit of word line WL1 and bit line BLe definition, corresponding to the even-numbered page or leaf) be programmed, then relevant information with the even-numbered page or leaf, can in corresponding page buffer 302b, be set up by steering logic piece 800, and by the tag unit of word line WL1 and sign bit line FBLe1 definition 3., can be programmed to have given state (for example, as the state of going up the most ST4 among Fig. 1).If 4. (for example by the master unit of word line WL1 and bit line BLo definition, corresponding to the odd-numbered page or leaf) be programmed, then relevant information with the odd-numbered page or leaf, can in corresponding page buffer 302b, be set up by steering logic piece 800, and 4. by the tag unit of word line WL1 and sign bit line FBLo1 definition, can be programmed to have given state (for example, as the state of going up the most ST4 among Fig. 1).
In the example embodiment of Fig. 6,1., 2. and 3. tag unit may experience relatively limited F-poly coupling.If the page information relevant with word line WL2 is programmed, if then tag unit (for example, being defined by WL2 and FBLo0) is programmed, 3. tag unit can receive the F-poly coupling of generation so.Yet, will recognize that the F-poly coupling that takes place is compared with traditional technology, can be lowered when tag unit is programmed.Therefore, the increase of the threshold voltage of the tag unit by F-poly coupling can be lowered equally.Therefore, because the reduction of electric current on the unit, can be lowered with respect to the generation of the read error of tag unit, and the reliability of flash memory device 1000 can be enhanced thus.
Fig. 7 illustrates the tag unit programming process that substitutes according to flash memory device 1000 another example embodiment of the present invention, Fig. 4.In the example embodiment of Fig. 7, in the tag unit zone, can provide two the sign bit lines to (FBLe0, FBLo0) and (FBLe1, FBLo1).The sign bit line is to (FBLe0 is FBLo0) with (FBLe1 FBLo1) can be connected respectively to corresponding page buffer 302a and 302b.
In the example embodiment of Fig. 7, if 1. (for example by the master unit of word line WL0 and bit line BLe definition, corresponding to the even-numbered page or leaf) be programmed, then relevant information with the even-numbered page or leaf, can in corresponding page buffer 302a, be set up by steering logic piece 800, and by the tag unit of word line WL0 and sign bit line FBLe0 definition 1., can be programmed to have given state (for example, as the state of going up the most ST4 among Fig. 1).If 2. (for example by the master unit of word line WL0 and bit line BLo definition, corresponding with the odd-numbered page or leaf) be programmed, then relevant information with the odd-numbered page or leaf, can in corresponding page buffer 302b, be set up by steering logic piece 800, and 2. by the tag unit of word line WL0 and sign bit line FBLo1 definition, can be programmed to have given state (for example, as the state of going up the most ST4 among Fig. 1).
In the example embodiment of Fig. 7, if 3. (for example by the master unit of word line WL1 and bit line BLe definition, corresponding to the even-numbered page or leaf) be programmed, then relevant information with the even-numbered page or leaf, can in corresponding page buffer 302b, be set up by steering logic piece 800, and by the tag unit of word line WL1 and sign bit line FBLe1 definition 3., can be programmed to have given state (for example, as the state of going up the most ST4 among Fig. 1).If 4. (for example by the master unit of word line WL1 and bit line BLo definition, corresponding to the odd-numbered page or leaf) be programmed, then relevant information with the odd-numbered page or leaf, can in corresponding page buffer 302a, be set up by steering logic piece 800, and 4. by the tag unit of word line WL1 and sign bit line FBLo0 definition, can be programmed to have given state (for example, as the state of going up the most ST4 among Fig. 1).
In the example embodiment of Fig. 7,1., 2. and 3. tag unit may experience relatively limited F-poly coupling.If the page information relevant with word line WL2 is programmed, then 3. and 4. tag unit can receive the F-poly coupling by tag unit (for example, by WL2 and FBLe0 and WL2 and FBLe1 definition) generation.Yet, will recognize that the F-poly coupling that takes place is compared with traditional technology, can be lowered when tag unit is programmed.Therefore, the increase of the threshold voltage of the tag unit by F-poly coupling can be lowered equally.Therefore, because the reduction of electric current on the unit, can be lowered with respect to the generation of the read error of tag unit, the reliability of flash memory device 1000 can be enhanced thus.
Fig. 8 illustrates another the tag unit programming process that substitutes according to flash memory device 1000 another example embodiment of the present invention, Fig. 4.In the example embodiment of Fig. 8, in the tag unit zone, provide 4 the sign bit lines to (FBLe0, FBLo0), (FBLe1, FBLo1), (FBLe2, FBLo2) and (FBLe3, FBLo3).The sign bit line to (FBLe0, FBLo0), (FBLe1, FBLo1), (FBLe2, FBLo2) and (FBLe3 FBLo3) can be connected to corresponding page buffer 302a, 302b, 302c and 302d respectively.
In the example embodiment of Fig. 8, if 1. (for example by the master unit of word line WL0 and bit line BLe definition, corresponding to the even-numbered page or leaf) be programmed, then relevant information with the even-numbered page or leaf, can in corresponding page buffer 302a, be set up by steering logic piece 800, and by the tag unit of word line WL0 and sign bit line FBLe0 definition 1., can be programmed to have given state (for example, as the state of going up the most ST4 among Fig. 1).If 2. (for example by the master unit of word line WL0 and bit line BLo definition, corresponding with the odd-numbered page or leaf) be programmed, then relevant information with the odd-numbered page or leaf, can in corresponding page buffer 302c, be set up by steering logic piece 800, and 2. by the tag unit of word line WL0 and sign bit line FBLo2 definition, can be programmed to have given state (for example, as the state of going up the most ST4 among Fig. 1).
In the example embodiment of Fig. 8, if 3. (for example by the master unit of word line WL1 and bit line BLe definition, corresponding to the even-numbered page or leaf) be programmed, then relevant information with the even-numbered page or leaf, can in corresponding page buffer 302b, be set up by steering logic piece 800, and by the tag unit of word line WL1 and sign bit line FBLe1 definition 3., can be programmed to have given state (for example, as the state of going up the most ST4 among Fig. 1).If 4. (for example by the master unit of word line WL1 and bit line BLo definition, corresponding to the odd-numbered page or leaf) be programmed, then relevant information with the odd-numbered page or leaf, can in corresponding page buffer 302d, be set up by steering logic piece 800, and 4. by the tag unit of word line WL1 and sign bit line FBLo3 definition, can be programmed to have given state (for example, as the state of going up the most ST4 among Fig. 1).
Therefore, in the example embodiment of Fig. 8, will recognize that the F-poly coupling between each tag unit can be lowered, make because the increase of the threshold voltage of the tag unit that the F-poly coupling causes can be lowered equally.
In the one exemplary embodiment of Fig. 4 to 8, under the control of steering logic piece 800, page information can be read by page buffer 302, and the described page information that reads can be provided for steering logic piece 800.Steering logic piece 800 can output to external entity (entity) with the page information of importing by selecting circuit 600.Therefore, defective tag unit can more easily be determined, and replaced with redundant or alternative bit line.
For example, with reference to Fig. 4 to 8, in order to export the data that read by page buffer 301, steering logic piece 800 can change (for example, activating) and select signal SEL to first logic level (for example, high logic level or logical one).If select signal SEL to be converted to first logic level, then the page information that sends from steering logic piece 800 can be output to external entity or device by selecting circuit and input/output interface 700.Subsequently, detection information may be programmed into the steering logic piece 800 and/or the fuse box (not shown) of flash memory device 1000, and described program detection information can be used to (for example reduce, prevent) the defective sign bit line of visit, and the redundant sign of visit bit line (for example, substituting defective unit).Therefore, the reliability (for example, can cause the situation of fatal operating mistake in defective tag unit potentially) that is stored in the information in the tag unit can be enhanced.
Therefore example embodiment of the present invention is described, and inciting somebody to action obviously can be in many ways to its change.For example, although with respect to the NAND flash memory device, aforesaid example embodiment of the present invention is usually described and is illustrated, to recognize, other example embodiment of the present invention needn't so be limited, and can be directed to the volatibility and/or the nonvolatile memory device (for example, NOR flash device etc.) of any kind.And, be appreciated that in example embodiment of the present invention aforesaid first and second logic levels can correspond respectively to high level and low logic level.Perhaps, in other example embodiment of the present invention, first and second logic levels/state can correspond respectively to low logic level and high logic level.
Such variation is not considered to depart from the spirit and scope of one exemplary embodiment of the present invention, and as for those skilled in the art with conspicuous, the modification that all are such, the intention be to be included in the scope of claim.
Prioity claim
The non-temporary patent application of this U.S. requires in the right of priority of korean patent application No.2006-52605 under 35 U.S.C. § 119 of submission on June 12nd, 2006, and the full content of this korean patent application is incorporated at this by reference.
Claims (20)
1. nonvolatile memory device comprises:
A plurality of master units, each in these a plurality of master units be arranged on one of a plurality of word lines and a plurality of main bit line to one of between first intersecting area; And
A plurality of tag unit, each of these a plurality of tag unit be arranged on a plurality of sign bit lines to and a plurality of word line in one between second intersecting area, each of these a plurality of tag unit is configured to memory page information in such a way, make with corresponding to main bit line to one of the page information that is associated of master unit, be stored in and more than a described sign bit line in corresponding each tag unit.
2. nonvolatile memory device as claimed in claim 1 also comprises:
A plurality of first page buffers, each of these a plurality of first page buffers be connected to described a plurality of main bit line to one of;
A plurality of second page buffers, each of these a plurality of second page buffers be connected to these a plurality of sign bit lines to one of; And
The steering logic piece disposes it for the mode of memory page information in tag unit, manages described second page buffer.
3. nonvolatile memory device as claimed in claim 1, wherein each in these a plurality of word lines comprises two pages, and described a plurality of sign bit line is right to comprising the first and second sign bit lines.
4. nonvolatile memory device as claimed in claim 3, first page information that is associated with given even-numbered word line in a plurality of word lines wherein, be programmed in the tag unit that is connected with the right even-numbered sign bit line of the described first sign bit line, and second page information that is associated with described given even-numbered word line, be programmed in the tag unit that is connected with the right odd-numbered sign bit line of the described first sign bit line
And wherein even number and odd number mark is distinguished the right not corresponding lines of bit line.
5. nonvolatile memory device as claimed in claim 4, first page information that is associated with given odd-numbered word line in a plurality of word lines wherein, be programmed in the tag unit that is connected with the right even-numbered sign bit line of the described second sign bit line, and, be programmed in the tag unit that is connected with the right odd-numbered sign bit line of the described second sign bit line with second page information that described given odd-numbered word line is associated.
6. nonvolatile memory device as claimed in claim 3, first page information that is associated with given odd-numbered word line in a plurality of word lines wherein, be programmed in the tag unit that is connected with the right even-numbered sign bit line of the described second sign bit line, and second page information that is associated with described given odd-numbered word line, be programmed in the tag unit that is connected with the right odd-numbered sign bit line of the described second sign bit line
And wherein even number and odd number mark is distinguished the right not corresponding lines of bit line.
7. nonvolatile memory device as claimed in claim 3, first page information that is associated with given even-numbered word line in a plurality of word lines wherein, be programmed in the tag unit that is connected with the right even-numbered sign bit line of the described first sign bit line, and second page information that is associated with described given odd-numbered word line, be programmed in the tag unit that is connected with the right odd-numbered sign bit line of the described second sign bit line
And wherein even number and odd number mark is distinguished the right not corresponding lines of bit line.
8. nonvolatile memory device as claimed in claim 7, first page information that is associated with given odd-numbered word line in a plurality of word lines wherein, be programmed in the tag unit that is connected with the right even-numbered sign bit line of the described second sign bit line, and, be programmed in the tag unit that is connected with the right odd-numbered sign bit line of the described first sign bit line with second page information that described given odd-numbered word line is associated.
9. nonvolatile memory device as claimed in claim 3, first page information that is associated with given odd-numbered word line in a plurality of word lines wherein, be programmed in the tag unit that is connected with the right even-numbered sign bit line of the described second sign bit line, and second page information that is associated with described given odd-numbered word line, be programmed in the tag unit that is connected with the right odd-numbered sign bit line of the described first sign bit line
And wherein even number and odd number mark is distinguished the right not corresponding lines of bit line.
10. nonvolatile memory device as claimed in claim 1, each in wherein said a plurality of word lines comprises two pages, and described a plurality of sign bit line comprises that first to fourth sign bit line is right.
11. nonvolatile memory device as claimed in claim 10, first page information that is associated with given even-numbered word line in a plurality of word lines wherein, be programmed in the tag unit that is connected with the right even-numbered sign bit line of the described first sign bit line, and second page information that is associated with described given even-numbered word line, be programmed in the tag unit that is connected with the right odd-numbered sign bit line of described the 3rd sign bit line
And wherein even number and odd number mark is distinguished the right not corresponding lines of bit line.
12. nonvolatile memory device as claimed in claim 11, first page information that is associated with given odd-numbered word line in a plurality of word lines wherein, be programmed in the tag unit that is connected with the right even-numbered sign bit line of the described second sign bit line, and, be programmed in the tag unit that is connected with the right odd-numbered sign bit line of described the 4th sign bit line with second page information that described given odd-numbered word line is associated.
13. nonvolatile memory device as claimed in claim 2 also comprises:
Column select circuit is used for during read operation, selects to have described first page buffer of given length;
Multiplexer, it is controlled by described steering logic piece, and is configured to select one or more outputs of described first page buffer selected by described column select circuit; And
Input/output interface, the output that is used to export described multiplexer.
14. nonvolatile memory device as claimed in claim 13, if wherein select one of a plurality of word lines, then described second page buffer is under the control of described steering logic piece, read page information from the tag unit of selected word line, and described steering logic piece is controlled this multiplexer, makes the page information that is read export via input/output interface.
15. nonvolatile memory device as claimed in claim 1 also comprises:
At least one redundant sign bit line is right, and it is right to be used for substituting the defective sign bit line of described a plurality of sign bit line pairs; And
Redundant page buffer, it is controlled by described steering logic piece, and it is right to be connected to described redundant bit line.
16. nonvolatile memory device as claimed in claim 1, wherein, described nonvolatile memory device is a flash memory device.
17. nonvolatile memory device as claimed in claim 16, wherein said flash memory device are the NAND flash memory devices.
18. a method of operating nonvolatile memory device comprises:
One of a plurality of word lines and a plurality of main bit line to one of between first intersecting area, arrange each in a plurality of master units; And
Page information is stored at least one of described a plurality of tag unit, each of these a plurality of tag unit be arranged on a plurality of sign bit lines to and a plurality of word line in one between second intersecting area, described page information is stored in such a way, make with corresponding to main bit line to one of the page information that is associated of master unit, be stored in and more than a described sign bit line in corresponding each tag unit.
19. method as claimed in claim 18, wherein said storage, with two the sign bit lines to the tag unit that is associated in the storage described page information.
20. method as claimed in claim 18, wherein said storage, with four the sign bit lines to the tag unit that is associated in the storage described page information.
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| KR52605/06 | 2006-06-12 | ||
| KR1020060052605A KR100733952B1 (en) | 2006-06-12 | 2006-06-12 | Multi-bit flash memory device capable of minimizing coupling between flag cells and program method thereof |
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| CN101089994A true CN101089994A (en) | 2007-12-19 |
| CN101089994B CN101089994B (en) | 2012-03-21 |
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| US (1) | US7623374B2 (en) |
| JP (1) | JP5336053B2 (en) |
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| CN102568595A (en) * | 2010-12-30 | 2012-07-11 | 海力士半导体有限公司 | Semiconductor memory device and method of operating the same |
| CN102682848A (en) * | 2011-03-16 | 2012-09-19 | 三星电子株式会社 | Memory device, memory card, solid state drive, system, and operation method thereof |
| CN103117089A (en) * | 2011-10-27 | 2013-05-22 | 爱思开海力士有限公司 | Semiconductor memory device |
| CN103971750A (en) * | 2013-01-29 | 2014-08-06 | 中国航空工业集团公司西安飞机设计研究所 | Sensitive fault detection method of 9 adjacent units of RAM |
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| KR101397549B1 (en) * | 2007-08-16 | 2014-05-26 | 삼성전자주식회사 | Non-volatile semiconductor memory device and system capable of fast rogramming and read method thereof |
| KR100859258B1 (en) | 2007-09-10 | 2008-09-18 | 주식회사 하이닉스반도체 | Apparatus for flash memory device and operating method thereof |
| US8238178B2 (en) * | 2010-02-12 | 2012-08-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Redundancy circuits and operating methods thereof |
| KR20120119331A (en) * | 2011-04-21 | 2012-10-31 | 에스케이하이닉스 주식회사 | Memory and method for operating the same |
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| CN102568595A (en) * | 2010-12-30 | 2012-07-11 | 海力士半导体有限公司 | Semiconductor memory device and method of operating the same |
| CN102568595B (en) * | 2010-12-30 | 2015-07-22 | 海力士半导体有限公司 | Semiconductor memory device and method of operating the same |
| CN102682848A (en) * | 2011-03-16 | 2012-09-19 | 三星电子株式会社 | Memory device, memory card, solid state drive, system, and operation method thereof |
| CN103117089A (en) * | 2011-10-27 | 2013-05-22 | 爱思开海力士有限公司 | Semiconductor memory device |
| CN103971750A (en) * | 2013-01-29 | 2014-08-06 | 中国航空工业集团公司西安飞机设计研究所 | Sensitive fault detection method of 9 adjacent units of RAM |
| CN103971750B (en) * | 2013-01-29 | 2017-02-08 | 中国航空工业集团公司西安飞机设计研究所 | Sensitive fault detection method of 9 adjacent units of RAM |
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| US20070291536A1 (en) | 2007-12-20 |
| US7623374B2 (en) | 2009-11-24 |
| JP5336053B2 (en) | 2013-11-06 |
| JP2007335069A (en) | 2007-12-27 |
| KR100733952B1 (en) | 2007-06-29 |
| CN101089994B (en) | 2012-03-21 |
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