CN101083637B - System and method for decoupling multiple control loops - Google Patents

Abstract

The present invention provides systems and methods for decoupling multiple control loops. The method includes: applying at least one of loss compensation and offset compensation to the signal before or after distortion to generate an output signal; sampling the output signal with a clock signal to generate a plurality of data values and boundary values; A group monitors sample values; detects a data pattern in a first data pattern group in the sample values; and adjusts loss compensation applied to the signal based on a boundary value associated with the detected data pattern and one or more sample data values and at least one of offset compensation; after adjusting at least one of the loss compensation and the offset compensation, monitoring the sampled values for the second set of data patterns; detecting a data pattern in the second set of data patterns in the sampled values; and adjusting at least one of loss compensation and offset compensation applied to the signal based on the boundary value and the one or more sampled data values associated with the detected data pattern.

Description

System and method for decoupling multiple control loops

technical field

The present invention relates generally to signal communication, and more particularly to a system and method for decoupling multiple control loops.

Background technique

When signals are transmitted through communication media, they suffer from attenuation due to phenomena such as skin effect and dielectric absorption. Signal receivers may include equalizers that compensate for this attenuation to improve the accuracy and efficiency of signal communication. It is desirable that the amount of compensation applied by the equalizer match as closely as possible the degree of attenuation due to the medium to keep the output characteristics of the signal consistent regardless of the particular communication path used to transmit the signal.

Contents of the invention

In one embodiment of the present invention, a method for conditioning a signal includes: applying at least one of loss compensation for frequency-dependent distortion and offset compensation for DC offset distortion to a signal before or after the distortion occurs. Generate an output signal. The method also includes sampling the output signal using a clock signal to generate a plurality of data values and boundary values. The method also includes monitoring the sampled values for the first set of data patterns. The method also includes detecting a data pattern in the first set of data patterns in the sampled values. The method further includes applying the loss to the signal based on one or more sampled data values and boundary values associated with the detected data patterns in the first set of data patterns At least one of compensation and said offset compensation is adjusted. The method also includes monitoring the sampled values for a second set of data patterns after adjusting at least one of the loss compensation and the offset compensation. The method also includes detecting data patterns in the second set of data patterns in the sampled values. The method further includes applying the loss to the signal based on one or more sampled data values and boundary values associated with the detected data patterns in the second set of data patterns At least one of compensation and said offset compensation is adjusted.

One technical advantage of certain embodiments is equalizing the output signal. Certain embodiments compensate for signal attenuation caused by the communication medium used to transmit the signal. This allows the output characteristics of the signal to be consistent independent of the communication path used to transmit the signal. Advantages associated with consistent output characteristics may include improved response of components since signal levels may be selected to fall within the dynamic range of system components. Furthermore, the signal can be maintained at a sufficient level to prevent loss of information.

Other technical advantages of certain embodiments include adaptability to different communication media. Certain embodiments use variable gain amplifiers to adjust the degree of compensation applied to incoming signals. Such embodiments may allow the amount of compensation to be adjusted for different media, thereby increasing the versatility of equalizers implementing these techniques. In addition, these embodiments can also accommodate changes in media properties associated with process, voltage, and temperature changes.

Yet another technical advantage of certain embodiments is that the maximum operating speed of the equalizer is increased and/or the power consumed by the equalizer is reduced. Certain embodiments use existing clock and data recovery (CDR) functionality to generate output signal values that are used to monitor residual gain error and/or residual DC offset in the output signal. By using the existing CDR function to generate the output signal value, it is no longer necessary to use a dedicated monitoring circuit. By not using a dedicated monitoring circuit, it is possible to reduce the load on the equalizer output, increase the maximum operating speed of the equalizer and/or reduce the power consumed by the equalizer. Additionally, chip area may be reduced and, in particular embodiments, existing equalizer components and/or functions may be reused. In addition, the design effort for the equalizer can be reduced by not using a dedicated monitoring circuit.

Yet another technical advantage of certain embodiments is increased flexibility with respect to data patterns usable by the equalizer. Particular embodiments may use data patterns with a single transition, and are not limited to high frequency data patterns and/or data patterns with at least two transitions. This flexibility has many advantages including, for example, enabling additional filter modes (ie modes with single transitions) to be applied to the output signal to counteract duty cycle distortion as will be discussed below.

Another technical advantage of particular embodiments is the ability to adjust more than one independent control parameter associated with an input signal using only the output signal value. As mentioned above, the use of output signal values provides several advantages over the use of monitoring circuits. Additionally, adjustments to more than one independently controlled parameter can increase the effectiveness of the equalizer in compensating for signal attenuation.

Yet another technical advantage of particular embodiments is the consistent control of adaptive equalizers for periodic, quasi-periodic, and fully randomized sequences. Another technical advantage of particular embodiments is that duty cycle distortion and negative effects of quasi-periodic and periodic signals are reduced by applying a filter pattern to the signal prior to gain adjustment. The filter pattern corresponds to the pattern of values that occur substantially equally in the sequence beginning at even or odd data in the signal. Applying filter patterns to the signal avoids unacceptable results in gain control by balancing the adaptive action bias (duty cycle distortion) in sequences starting at even or odd data.

Yet another technical advantage of particular embodiments is to use the list of useful filter patterns in a balanced manner in conjunction with (quasi)periodic signals to reduce the negative effects of duty cycle distortion and (quasi)periodic signals. In these embodiments, the list of useful filter patterns associated with (quasi) periodic signals may be predetermined and fixed. In an alternative embodiment, the list of useful filter patterns may be adapted to the incoming (quasi) periodic signal. The filter modes in this list can be used in a balanced manner to enhance their applicability to (quasi-)periodic signals. The filter patterns in the list can be used in a balanced manner by selecting them from the list sequentially, randomly or simultaneously. A timer may be used in particular embodiments to skip undetected filter patterns, thereby increasing the frequency of adaptive actions.

Yet another technical advantage of certain embodiments is to adjust for residual DC offset observed in the output signal. Adjusting the DC offset compensation can improve component response (eg, increased sensitivity). In particular embodiments, the DC offset compensation can be adjusted using the output signal value without generating data errors in the signal. As mentioned above, using the output signal value (generated using existing CDR functionality) provides several advantages over using a monitoring circuit. In addition, because no data error is generated in the signal, the DC offset compensation can be adjusted not only during the receiving process of the signal carrying only the test service, but also during the receiving process of the signal including the real data service. By making adjustments to the DC offset compensation during reception of signals comprising real data traffic (not just test traffic), component sensitivity during reception of real data traffic can be increased.

Yet another technical advantage of particular embodiments is to correct for possible false lock problems that accompany adjustments for residual DC offsets observed in the output signal. False lock problems arise when clock recovery and skew cancellers interact incorrectly, which causes sample boundaries and data values to be swapped. Embodiments correct for the false lock problem by adjusting the DC offset compensation based on the high or low value of each boundary value whether or not the boundary value is between consecutive data values including transitions. To correct for false lock problems in (quasi) periodic signals using resampling, embodiments first use the output signal values to monitor data DC imbalance (synonymous for false lock problems). If an imbalance is detected, the DC offset compensation is adjusted based on the detected imbalance. If no imbalance is detected, the DC offset compensation is adjusted based on high or low values of only those boundary values between successive data values comprising transitions. In this way, the data DC imbalance can vary within an acceptable range, even when resampling is used for (quasi-)periodic data sequences.

Yet another technical advantage of particular embodiments is the use of output signal values to cancel out skew in each path in a multipath equalizer. In a specific embodiment, the skew in each path can be canceled without using any additional circuitry to monitor the internal residual skew in the equalizer, additionally, in a specific embodiment, in the equalizer Offset cancellation control may be used during operation (ie without turning off any part of the equalizer circuitry) and during reception of signals including real data traffic (not only during reception of signals carrying only test traffic). By making adjustments to the DC offset compensation during reception of signals comprising real data traffic (not just test traffic), component sensitivity during reception of real data traffic can be increased.

Yet another technical advantage of embodiments using resampling is to avoid any locking of the resampling period to the (quasi) periodic signal. When lock-in occurs, the data pattern observed in the resampled data differs from the data pattern in the overall (quasi-)periodic signal, potentially delaying the control actions performed by the equalizer controller. Particular embodiments can avoid locking by varying the point at which a (quasi) periodic signal is resampled in each resampling period.

Yet another technical advantage of particular embodiments is the decoupling of multiple control loops, such as an adaptive equalizer controller and an offset canceller. Decoupling of multiple control loops can avoid lag in convergence time and potential instability in the control loops. Particular embodiments may decouple multiple control loops by making the loops insensitive to each other. For example, the adaptive equalizer control can be made insensitive to residual offset and the offset canceller can be made insensitive to residual inter-symbol interference (ISI). In order to make the adaptive equalizer control and the offset canceller mutually insensitive, in a particular embodiment two sets of complementary data patterns are used in a balanced manner by the adaptive equalizer control and the offset canceller.

Yet another technical advantage of particular embodiments is the generation of specific average values of binary target variables (e.g., ISI degree, equilibrium level, or any other target variables), as is the case in a typical stop-start control system. The binary target variable may, for example, be an anticorrelation function applied to the boundary value between opposite data values and the data value 1.5 bits (or signs) before the boundary value. In a specific case, the optimal mean value of a binary target variable in equilibrium (eg, degree of ISI, level of equalization, or any other target variable) can be greater than or less than zero. Thus, embodiments that generate a mean value of the binary target variable that converges closer to the optimal mean value (ie zero) are advantageous.

Yet another technical advantage of particular embodiments is to dynamically generate a control target for an average value of a binary target variable (eg, ISI degree, equalization level, or any other target variable) at equilibrium. In a particular embodiment, the optimal average ISI level may be high for high loss channels and low for low loss channels. Thus, an embodiment that includes a control value for the mean value of a binary target variable that changes dynamically with the value of the control variable may be advantageous.

Other technical advantages will be readily apparent to those skilled in the art from the drawings, specification and claims. Moreover, while specific advantages are enumerated above, particular embodiments may include some, all, or none of the enumerated advantages.

Description of drawings

1 is a block diagram illustrating an example digital signal transmission system;

FIG. 2 is a block diagram illustrating the example digital signal transmission system of FIG. 1 in more detail;

3 is a block diagram illustrating an example receiver of the example digital signal transmission system of FIG. 2, according to a particular embodiment;

Figures 4A, 4B and 4C illustrate various examples of clock signals in contrast to equalizer output signals exhibiting various types of inter-symbol interference effects;

5 is a flowchart illustrating a method for interpreting output signal values to compensate for residual intersymbol interference in accordance with certain embodiments of the invention;

FIG. 6 is a table illustrating an example gain control scheme associated with the method of FIG. 5;

7 is a flowchart illustrating an example method for interpreting output signal values for a plurality of independent control parameters in an analog second derivative equalizer in accordance with certain embodiments of the invention;

FIG. 8 is a table illustrating an example gain control scheme associated with the method of FIG. 7;

9 is a flowchart illustrating an example method for interpreting output signal values for a plurality of equalizer parameters in a 3-tap FIR filter in accordance with certain embodiments of the invention;

FIG. 10 is a table illustrating an example gain control scheme associated with the method of FIG. 9;

Figure 11 illustrates example boundary information affected by duty cycle distortion;

12 is a flowchart illustrating an example method for selecting a filter pattern to reduce the negative impact of duty cycle distortion in accordance with certain embodiments of the invention;

13 is a table illustrating example distributions of six-bit data patterns in even 8B10B idle data sequences and odd 8B10B idle data sequences;

14 is a table illustrating an example gain control scheme associated with adjusting the gain applied to the unchanged, first derivative, and second derivative components of the input signal using an example filter pattern derived from the table of FIG. 13 ;

15 is a table illustrating example distributions of six-bit data patterns in even 8B10B CJPAT data sequences and odd 8B10B CJPAT data sequences;

16 is a table illustrating an example gain control scheme associated with adjusting the gain applied to the unchanged, first derivative, and second derivative components of the input signal using an example filter pattern derived from the table of FIG. 15 ;

17 is a flowchart illustrating an example method for dynamically generating a list of useful filter patterns according to certain embodiments of the invention;

18 is a flowchart illustrating another example method for dynamically generating a list of useful filter patterns according to certain embodiments of the invention;

19 is a flowchart illustrating yet another example method for dynamically generating a list of useful filter patterns according to certain embodiments of the invention;

20 is a flowchart illustrating an example method for using filter modes in a balanced manner, according to certain embodiments of the invention;

21 is a flowchart illustrating another example method for using filter modes in a balanced manner, according to certain embodiments of the invention;

22 is a flowchart illustrating an example method for skipping undetected filter patterns after a certain period of time according to certain embodiments of the invention;

Figures 23A, 23B and 23C illustrate various examples of clock signals in contrast to equalizer output signals exhibiting various types of residual DC offset;

24 is a flowchart illustrating a method for interpreting output signal values to cancel residual DC offsets in accordance with certain embodiments of the invention;

Figure 25 is a table illustrating an example offset control scheme associated with the method of Figure 24;

FIG. 26 is a flow diagram illustrating a method for correcting a false lock that occurs in canceling a residual DC offset in accordance with certain embodiments of the present invention;

Figure 27 is a table illustrating an example offset control scheme associated with the method of Figure 26;

FIG. 28 is a flowchart illustrating another method for correcting a false lock that occurs in canceling a residual DC offset in accordance with certain embodiments of the present invention;

Figure 29 is a table illustrating an example offset control scheme associated with the method of Figure 28;

Figure 30 illustrates a DC path output exhibiting a negative residual DC offset, a first derivative path output exhibiting a positive residual DC offset, and a predominantly zero residual DC offset in an example first derivative equalizer compared to a clock signal. Example of an offset equalizer output signal;

31 is a flowchart illustrating an example method for canceling residual DC offset in a first derivative analog equalizer in accordance with certain embodiments of the invention;

Figure 32 is a table illustrating an example offset control scheme associated with the method of Figure 31;

33 is a flowchart illustrating another example method for canceling residual DC offset in a first derivative analog equalizer in accordance with certain embodiments of the invention;

Figure 34 is a table illustrating an example offset control scheme associated with the method of Figure 33;

35 is a flowchart illustrating yet another example method for canceling residual DC offset in a first derivative analog equalizer in accordance with certain embodiments of the invention;

Figure 36 is a table illustrating an example offset control scheme associated with the method of Figure 35;

37 is a flowchart illustrating yet another example method for canceling residual DC offset in a first derivative analog equalizer in accordance with certain embodiments of the present invention;

Figure 38 is a table illustrating an example offset control scheme associated with the method of Figure 37;

39 is a flowchart illustrating an example method for canceling residual DC offset in a second derivative analog equalizer in accordance with certain embodiments of the invention;

Figure 40 is a table illustrating an example offset control scheme associated with the method of Figure 39;

41 is a flowchart illustrating an example method for reducing the effects of duty cycle distortion in accordance with certain embodiments of the invention;

42 is a flowchart illustrating another example method for reducing the effects of duty cycle distortion in accordance with certain embodiments of the invention;

43 is a flowchart illustrating an example method for varying the point at which resampling occurs during each resampling cycle, according to certain embodiments of the invention;

44 is a flowchart illustrating another example method for varying the point at which resampling occurs during each resampling cycle, according to certain embodiments of the invention;

45 is a flowchart illustrating yet another example method for varying the point at which resampling occurs in each resampling cycle, according to certain embodiments of the invention;

46 is a flowchart illustrating an example method for decoupling multiple control loops in accordance with certain embodiments of the invention;

47 is a flowchart illustrating another example method for decoupling multiple control loops according to certain embodiments of the invention;

48 is a flowchart illustrating an example method for generating a particular average of a binary target variable (e.g., ISI level, EQ level, or residual offset) at equilibrium, according to certain embodiments of the invention;

49 is a flowchart illustrating an example method for dynamically generating a control target for an average value of a binary target variable (eg, ISI level) in equilibrium, according to certain embodiments of the invention;

50 is a graph illustrating the results of applying an example control objective formula to dynamically generate an example control objective for an average value of a binary objective variable at equilibrium in equalizer gain control according to certain embodiments of the present invention;

Figure 51 is a table illustrating an example scheme for converting high frequency gain codes to DC path gain codes and first order path gain codes in accordance with certain embodiments of the invention; and

52A and 52B are graphs illustrating the results of applying the example scheme of FIG. 51 for converting high frequency gain codes to DC path gain codes and first order path gain codes, according to certain embodiments of the invention.

Detailed ways

FIG. 1 is a block diagram illustrating an example digital signal transmission system 10 . The digital signal transmission system 10 includes a transmitter 20 , a communication channel 30 and a receiver 40 . Transmitter 20 may comprise any suitable transmitter operable to transmit a signal carrying digital information over channel 30 to receiver 40 . In certain embodiments, transmitter 20 may transmit information at a relatively fast rate. Channel 30 may comprise any suitable channel or other communication medium. Channel 30 may include, for example, a cable carrying a signal, an insulator to insulate the cable, an enclosure around the cable, and/or connections. Channel 30 is operable to receive signals from transmitter 20 and to forward these signals to receiver 40 . Receiver 40 may comprise any suitable receiver operable to receive signals from transmitter 20 over channel 30 and to appropriately process the digital information in the received signals.

In a typical digital signal transmission system (such as a high-speed communication system), as illustrated in FIG. 32, the signal received by the receiver 40 is usually distorted due to frequency-dependent attenuation. In general, there are two important reasons for signal attenuation in conductive communication media. The first important reason is the skin effect due to the conduction of signals along the communication medium. The second important reason is the dielectric absorption of the signal by the communication medium. In general, the amount of signal loss in decibels due to skin effect is the product a _s x √f, where a _s is the skin effect coefficient of the material, x is the length of propagation along the material, and f is the frequency of the signal . The amount of loss due to dielectric absorption is the product a _d x f, where a _d is the dielectric absorption coefficient of the material.

The relative importance of these effects can vary widely depending on the material and signal frequency. Thus, for example, a cable may have a dielectric absorption coefficient much smaller than the skin effect coefficient, so that losses due to skin effect dominate except at high frequencies. Backplane traces, on the other hand, may have a high dielectric absorption coefficient such that losses due to dielectric absorption are comparable or greater than losses due to skin effect. In addition, changes in operating conditions, such as temperature changes, may also affect signal characteristics.

The signal processed by receiver 40 may also exhibit residual DC offset distortion. For example, residual DC offsets may be due to fabrication techniques (such as device geometry mismatch or threshold voltage mismatch) and/or the receiver components themselves. As described further below in connection with FIGS. 2 and 3 , an equalizer may be used to compensate for the frequency-dependent attenuation, and an offset canceller may be used to cancel the residual DC offset.

FIG. 2 is a block diagram illustrating the example digital signal transmission system of FIG. 1 in more detail. As can be observed, transmitter 20 includes transmitter logic 22 and transmitter equalizer 24 . Transmitter logic 22 may include any suitable logic operable to encode and transmit information. Transmitter equalizer 24 may comprise any suitable equalizer operable to compensate (eg, by adjusting the gain of the signal to be transmitted) for distortion that the transmitted signal may experience on channel 30 due to frequency-dependent attenuation. By way of example only, in certain embodiments, the gain may be compensated as illustrated in FIG. 26 . In this manner, equalizer 24 may precompensate (or equalize) the signal before distortion occurs (using, for example, transmitter pre-emphasis equalization). In particular embodiments, transmitter equalizer 24 may operate similarly to receiver equalizer 42 described below in connection with FIG. 3 based on feedback from receiver logic 47 . It should be noted, however, that equalizer 24 may compensate the signal before distortion occurs, while equalizer 42 may compensate the signal after distortion occurs. It should also be noted that some or all of the logic 47 (described below) may be located in the transmitter 20 or any other suitable location, and not necessarily all in the receiver 40 .

Receiver 40 includes receiver equalizer 42 , equalizer output 46 , receiver logic 47 , gain control signal 48 , and offset control signal 49 . Receiver equalizer 42 may include any suitable equalizer operable to receive an input signal, including an input data signal, at an input port and apply gain and/or offset to the received input data signal. Receiver logic 47 may include any suitable component or group of components operable to receive a clock signal, such as a sampler. The clock signal may include any suitable clock signal that can be recovered from an input signal by a clock and data recovery (CDR) circuit, such as a recovered clock signal. Using the received clock signal, receiver logic 47 is operable to sample the equalizer output 46 and, based on the sampling, to sample the gain control signal 48 and/or Or offset control signal 49 is adjusted to compensate for signal distortion. By way of example only, in certain embodiments, the gain may be compensated as illustrated in FIG. 52 . In a particular embodiment, the compensation of the gain results in an equalizer output 46 that is fully compensated for frequency-dependent distortion as illustrated in FIG. 54 . In alternative embodiments, equalizer output 46 may be under-compensated. In particular embodiments, receiver 40 is operable to communicate the information in equalizer output 46 downstream and to one or more of any suitable number of components in any suitable manner.

As described in more detail below, receiver 40 compensates for signal distortion without using dedicated monitor circuitry to detect the distortion. Receiver 40 may realize one or more technical advantages by not using a dedicated monitor circuit. These advantages may include, for example, increasing the maximum operating rate of the equalizer 42 and/or reducing the power consumed by the receiver 40 . In addition, chip area can be reduced, existing equalizer components and/or functionality can be reused, and/or the design effort required to design receiver 40 can be reduced (by not having to design dedicated monitor circuits).

It should be noted that in some particular embodiments, no precompensation may be performed and transmitter 20 may not include equalizer 24 . In these embodiments, receiver 40 may use equalizer 42 to compensate for the distortion. In some alternative embodiments, transmitter 20 may include equalizer 24 and may be precompensated (ie, transmitter pre-emphasis). In some of these embodiments, receiver 40 may also use equalizer 42 to compensate for distortion. In other of these embodiments, receiver 40 may not use equalizer 42 to compensate for distortion, and receiver 40 may not include equalizer 42 .

It should be noted that in certain embodiments, components that compensate the signal for distortion (e.g., logic 47 and equalizer 42, logic 47 and equalizer 24, and/or logic 47 and multiple equalizers) may be part of an adaptive equalizer. It should also be noted that adaptive equalizers may compensate in the manner described herein in environments other than signal transmission systems (as already described). For example, an adaptive equalizer may compensate as described herein (or in a similar manner) in a recording channel (eg, a magnetic recording channel or an optical recording channel). Also, any suitable type of equalizer may be used to perform compensation as described herein, including, for example, linear equalizers and decision feedback equalizers.

FIG. 3 is a block diagram illustrating an example receiver 40 in the example digital signal transmission system 10 of FIG. 2 according to a particular embodiment. Equalizer 42 is operable to compensate for attenuation of signals communicated to equalizer 42 using communication medium 30 . In the illustrated embodiment, receiver logic 47 includes an adaptive controller that adjusts the amount of gain applied to each of the three signal paths 101A, 101B, and 101C based on the output signal sampled by sampler 104 102. The performance of equalizer 42 may suffer from residual DC offset. Receiver logic 47 may thus also include an offset controller 106 that adjusts the amount of DC offset compensation applied to the incoming signal based on the DC offset of the output signal sampled by sampler 104 . Other components of the equalizer 42 include a variable gain limiting amplifier 110 , a math operator (S) 112 , a delay generator 114 , a variable gain amplifier 116 , a combiner 118 , and a driver amplifier 120 . Other components of receiver logic 47 include sampler 104 and clock 105 . The output signal from sampler 104 is illustrated as output 50 .

To compensate for frequency-dependent distortions, equalizer 42 may divide (using any suitable splitter) received input signal 108 over three signal paths 101A, 101B, and 101C and use variable gain amplifier 116 to selectively The portion of the signal on each path is amplified. The first path 101A does not perform mathematical operations on the received input signal portion. The second path 101B performs a first-order mathematical operation on the signal, such as a derivative operation. This operation may be based on the frequency of the signal and is exemplified as a math operator (S) 112 . As also described below, the third path 101C performs a second order mathematical operation on the signal, such as a second derivative operation. This operation can also be based on the frequency of the signal and is exemplified by applying two math operators (S) 112 . Equalizer 42 approximately compensates for frequency-dependent loss effects in channel 30 of FIG. 2 by selectively amplifying first and second order components of the signal. In alternative embodiments, equalizer 42 may have any suitable number of paths, such as only one path. The equalizer 42 may be an example of an equalizer that compensates for distortion in parallel. It should be noted that any suitable equalization technique (e.g. transmitter pre-emphasis equalization and/or receiver equalization) and any suitable equalizer (e.g. analog continuous time first derivative filter, analog continuous time second derivative Filters, multi-tap finite impulse response filters, and/or multi-tap decision feedback equalizers) perform compensation for distortion in parallel in any suitable manner (eg, before and/or after the distortion occurs). It should also be noted that in alternative embodiments, any suitable equalization technique (e.g., transmitter pre-emphasis equalization and/or receiver equalization) and any suitable equalizer (e.g., linear equalizer and/or decision Feedback equalizer) performs compensation for distortion serially in any suitable manner (eg, before and/or after the distortion occurs).

Adaptive controller 102 may include any suitable component or combination of components for analyzing information related to the output signal of equalizer 42 and for adjusting the respective gains of variable gain amplifiers 116 . Adaptive controller 102 may include analog and/or digital electronic components such as transistors, resistors, amplifiers, constant current sources, or other similar components. Adaptive controller 102 may also include suitable components for converting signals from analog to digital or vice versa. According to particular embodiments, adaptive controller 102 includes a digital processor, such as a microprocessor, microcontroller, embedded logic, or other information processing components.

In a particular embodiment, adaptive controller 102 receives data and boundary value information associated with the output signal from sampler 104 . The value information may include, for example, a high or low value (eg, "1" or "0") associated with each sampled data and/or boundary value. Based on this value information, the adaptive controller 102 is operable to make appropriate adjustments to the gain applied to the input data signal, as described further below. To adjust the gain, in certain embodiments, the adaptive controller 102 may adjust the bias current applied to each variable gain amplifier 116 to adjust the applied gain. One advantage of using bias current to control amplifier 116 is that it allows adjustment of the amount of gain applied to the amplifier without changing the bandwidth of the amplifier, so that the amplifier maintains its dynamic range even as the gain is increased.

Sampler 104 may comprise any suitable component designed to receive equalizer output 46 from, for example, driver amplifier 120 and a clock signal from, for example, clock 105 and to equalizer output 46 at set intervals defined by the clock signal. Take a sample. The samples may be samples of data values and/or boundary values associated with equalizer output 46 and may represent high or low values of each of these values. Sampler 104 is also operable to forward the sampled data values and boundary values to adaptive controller 102 and/or offset controller 106 . In certain embodiments, sampler 104 may include decision latches that perform sampling and 1-bit analog-to-digital conversion. In alternative embodiments, sampler 104 may include analog sample and hold (S/H) circuitry to sample and forward analog information for analog signal processing. In still alternative embodiments, sampler 104 may include a multi-bit analog-to-digital converter (ADC) and forward digital information for digital signal processing.

Offset controller 106 may include means for analyzing information related to equalizer output 46 of equalizer 42 and for adjusting the amount of DC offset compensation applied at one or more stages of variable gain amplifier 116 any suitable part or combination of parts. In particular embodiments, offset controller 106 may include a microprocessor, microcontroller, embedded logic, and/or any other suitable component or combination of components.

In a particular embodiment, offset controller 106 receives data and boundary value information associated with equalizer output 46 from sampler 104 . The value information may include, for example, the high or low value of each sample data and/or boundary value. As further described below, based on this value information, offset controller 106 is operable to make appropriate adjustments (i.e., corrections) to the compensation voltage applied to the input data signal to correct or compensate (i.e., cancel) any residual DC offset.

DC offset compensation may be imparted to the signal by various components of equalizer 42 , particularly by variable gain amplifier 116 . In a multistage variable gain amplifier, the DC offset can be accumulated from stage to stage. To correct for offset, offset controller 106 may apply a DC voltage to the signal being amplified by variable gain amplifier 116 . According to a particular embodiment, the offset controller 106 applies the compensation (ie, correction) voltage in multiple steps, with each step being performed at a different stage of the variable gain amplifier 116 . In such embodiments, the amount of voltage applied at each step may be determined in any suitable manner. For example, the total correction voltage may be divided evenly between the steps, or may be divided by an amount proportional to the gain of the corresponding stage. It should be noted that some or all of the tasks performed by offset controller 106 may alternatively be performed by any other suitable component, such as sampler 104 .

Variable gain limiting amplifier (VGLA) 110 represents a component or collection of components for conditioning input signal 108 received by equalizer 42 . The adjustment process adjusts the overall level of the input signal 108 to keep the signal within the dynamic range of the math operator (S) 112 and delay generator 114 . In certain embodiments, the amount of amplification applied by VGLA 110 is controlled by the bias current applied to VGLA 110.

Math operator (S) 112 represents any component or collection of components that generates an output that is linearly proportional to the derivative of an incoming signal with respect to time (referred to as a "first order operation"). Mathematical operator S112 may include any suitable electronic components or circuitry, such as a high-pass filter for performing desired mathematical operations. According to a particular embodiment, this operation is a derivative operation, which takes the derivative of the incoming signal with respect to time, such as the voltage change of the incoming signal per 100 picoseconds. The mathematical operator S112 may apply the signal one or more times to obtain an output signal proportional to the first, second, third or higher derivative of the incoming signal with respect to time based on the number of times of S112 application.

Delay generator 114 represents any component or collection of components that introduces a time delay in the transmission of a signal. Delay generator 114 may include any suitable electronic components or circuitry. According to a particular embodiment, the delay introduced to the signal by delay generator 114 is approximately equal to the amount of time required by math operator S112 to be applied to the signal. Thus, the delay generator 114 may be used to equalize the amount of time required for each portion of the output signal to travel down the corresponding path 101A, 101B or 101C. In this manner, the portions of the signal can be synchronized as they arrive at combiner (mixer) 118 .

Variable gain amplifier 116 represents any component or components for amplifying a signal. Variable gain amplifiers 116 may include any suitable electronic components, and in certain embodiments, each variable gain amplifier 116 is controlled by a bias current applied to a particular variable gain amplifier 116 . In some cases, the response time of certain components performing the amplification process may be too long for the amplifier to effectively amplify high-frequency signals that change rapidly between high and low values. Thus, variable gain amplifier 116 may include a series of stages, each stage performing a portion of the overall amplification process. Since no stage has the burden of performing all the amplification processing, each stage takes less time to perform its respective gain. This allows the multi-stage variable gain amplifier 116 to respond to higher frequency signals.

The variable gain amplifier 116 can also perform DC offset compensation on the signal. In multistage amplifiers, each stage can be compensated for DC offset. One method of correcting for DC offset is to apply a correction voltage to correct the DC offset in the signal. The correction voltage may be fully applied to the original signal before the original signal is amplified. However, applying the voltage all at one point may cause the signal to exceed the dynamic range of one or more stages of amplifier 116 . Furthermore, the applied voltage is recalculated and adjusted each time a new stage is added, so if the gain is variable among the stages, the DC offset may be unevenly distributed among the stages. To address this difficulty, certain embodiments may include applying correction voltages at multiple stages of the amplifier 116 . This allows the DC offset of a stage to be corrected at each stage, reducing the likelihood that the correction process would push the signal beyond the dynamic range of the amplifier and eliminating the need to recalculate the DC offset for the entire array each time a stage is added. Furthermore, when the gains of the stages are independently variable, having the correction voltages at the stages facilitates the correction of the DC offset, so that different stages can have different gains and can be imparted with different DC offsets.

Combiner 118 represents a component or collection of components for recombining signals on communication paths 101A, 101B, and 101C into a single signal. Combiner 118 may include any suitable electronic components. Combiner 118 provides the combined signal to driver amplifier 120 . Driver amplifier 120 represents any component or collection of components for amplifying a combined signal. Drive amplifier 120 performs any suitable amplification on the combined signal to generate equalizer output 46 from equalizer 42 that has a signal level high enough that the output signal can be efficiently passed to sampler 104 .

In operation, the equalizer 42 receives an input signal 108 comprising an input data signal that has been attenuated due to the communication process through the communication medium. VGLA 110 conditions the signal such that the signal level is within the dynamic range of math operator (S) 112 and delay generator 114. Equalizer 42 divides the input signal between three paths 101A, 101B and 101C. The signal on the path 101A is delayed twice by the delay generator 114 so that the signal on the path 101A is synchronized with the signal on the path 101B (which is processed once by the mathematical operator 112 and delayed by the delay generator 114 once), and is synchronized with the signal on the path 101B The signal on 101C (which is processed twice by math operator 112) is synchronized. Thus, the input signal components on the three paths 101A, 101B, and 101C correspond to input signals not subjected to mathematical operations, subjected to first-order operations, and subjected to second-order operations, respectively, and (using delay generator 114) these three The components arrive synchronously at combiner 118 at approximately the same time.

The equalizer 42 then amplifies the signal on each path using a corresponding variable gain amplifier 116 . The gain of each amplifier 116 is controlled by the adaptive controller 102 and may be different for each path 101A, 101B, and 101C. This allows equalizer 42 to provide varying degrees of compensation for multiple loss effects that have different scaling relationships with the frequency of the signal. In general, the amount of compensation for a particular effect relative to the base signal is proportional to a ratio of the amplification of the corresponding path to the amplification of the unchanged signal on path 101A. Thus, path 101A may have no gain applied or a slightly negative gain (in dB) applied to increase the relative effect of the compensation applied to the other paths. Offset controller 106 corrects for any DC offset imparted to respective signals on respective paths 101A, 101B, and 101C via corresponding amplifiers 116 and/or any other suitable components.

The amplified signals from the various paths are combined into a single signal by a combiner 118 . The drive amplifier 120 amplifies the output signal so that the output signal can be effectively transmitted to another destination. Sampler 104 receives equalizer output signal 46 from driver amplifier 120 and a clock signal from clock 105 . Sampler 104 samples equalizer output signal 46 at set intervals defined by the clock signal to generate data values and boundary values associated with equalizer output signal 46 . Alternatively, sampler 104 may sample equalizer output signal 46 to generate only data values and forward the sampled data values and other suitable phase information to adaptive controller 102 and offset controller 106 . Adaptive controller 102 and offset controller 106 may then use the forwarded data values and phase information to derive one or more boundary values. Typically, if the phase is earlier, the high or low value of the boundary value is the same as the high or low value of the immediately preceding data value. If the phase is later, the high or low value of the boundary value is the same as the high or low value of the immediately following data value.

As described in more detail below, the adaptive controller 102 analyzes the samples and boundary values associated with the equalizer output signal 46 to adjust the The amount of gain is adjusted to properly compensate for residual frequency-dependent attenuation. Offset controller 106 analyzes samples and boundary values associated with equalizer output signal 46 to adjust the amount of correction voltage applied to one or more of paths 101A, 101B, and 101C to appropriately Cancels the residual DC offset.

One advantage of not using a dedicated monitor circuit (as is used in many typical systems) in the adaptive equalizer described above is that the loading on the equalizer output 46 can be reduced in certain embodiments. Especially in high speed circuits, reducing the loading of the equalizer output 46 increases the maximum operating speed of the equalizer 42 and/or reduces the power consumed by the equalizer 42 . Elimination of dedicated monitor circuits also reduces chip area, allows for efficient reuse of existing receiver components (such as clock 105), and reduces the design effort required to design dedicated monitor circuits.

Although a particular embodiment of equalizer 42 has been described in detail, many other possible embodiments exist. Possible variations include, for example: performing different or additional mathematical operations on paths 101A, 101B, and 101C to compensate for different loss properties; increasing or decreasing the number of paths; using manual control for controllers 102 and 106 instead of automatic feedback control; use of a single stage amplifier 116; receiving (and appropriately conditioning) signals comprising differential sequences such as low voltage differential signaling (LVDS); and other variations suggested by the above description. In general, components may be rearranged, modified, or omitted in any suitable manner, and the functions performed by these components may be distributed among different or additional components or combined in a single component in any suitable manner. Accordingly, it should be appreciated that implementations of receiver 40, equalizer 42, and receiver logic 47 may include any such variations, and that particular embodiments of the invention may be used in any suitable equalizer context. For more details regarding specific example equalizer components that may be used, see non-provisional US application (Serial No. 10/783,170), filed February 20, 2004, entitled "Adaptive Equalizer with DC Offset Compensation."

As discussed above, the signal transmitted over channel 30 and received at receiver 40 is subject to frequency dependent attenuation. At the receiver 40, an equalizer 42 may apply gain to the received input signal to compensate for attenuation exhibited by the signal. Receiver logic 47 may analyze adjusted equalizer output signal 46 for residual attenuation and adjust the gain applied to the input signal by equalizer 42 based on this feedback. In particular, sampler 104 may receive equalizer output signal 46 (the conditioned input signal) and a clock signal and sample the output signal at particular points determined by the clock signal to generate data values and boundary values. Sampler 104 may then forward these data and boundary values to adaptive controller 102 for appropriate analysis (as shown below). Based on this analysis, the adaptive controller 102 may adjust the gain applied to the incoming input signal.

Figures 4A, 4B and 4C illustrate several examples of clock signals in contrast to equalizer output signals exhibiting various types of inter-symbol interference effects. In particular embodiments, sampler 104 may receive signals such as those illustrated in these figures and sample the output signal according to a 2x oversampled clock and data recovery (CDR) scheme. In this scheme, sampler 104 may sample the received signal twice per data bit period (which may be defined by a clock signal). For one data bit period, sampler 104 may sample the output signal once at a point in the output signal that should correspond to a data value and once at a point in the output signal that should correspond to a boundary value. Based on an analysis of certain data and boundary values, adaptive controller 102 may adjust the gain applied to the signal received by equalizer 42 as described further below.

FIG. 4A illustrates an example clock signal 200 in contrast to an equalizer output signal 46 that is in phase with the clock signal and exhibits no inter-symbol interference effects. The clock signal defines data points (illustrated as arrows corresponding to D0 to D5) and boundary points (illustrated as arrows corresponding to E0 to E4). The sampler 104 may sample the equalizer output signal 46 at data points to generate data values (i.e., D0 to D5) and sample the equalizer output signal 46 at boundary points to generate boundary values (i.e., E0 to E4 ). Each sampled data value and boundary value can include a low value (illustrated as "L"), a high value (exemplified as "H"), or a random value that randomly takes either a high value or a low value (exemplified as "X"). In a particular embodiment, the low value may include "0," the high value may include "1," the random value may randomly include either "0" or "1," and the average of the random values may include "0.5." In an alternative embodiment, the low value may include "-1", the high value may include "1", the random value may randomly include either "-1" or "1", and the average of the random values may include " 0". Sampler 104 may forward the sampled data values and boundary values to adaptive controller 102 for proper processing and adjustment of the gain.

A change from a high value to a low value or from a low value to a high value between two consecutive data values is called a transition. In the illustrated example 200, transitions occur between low data value D2 and high data value D3, between high data value D3 and low data value D4, and between low data value D4 and high data value D5. In signals that do not exhibit residual intersymbol interference effects (as in example 200), each boundary value between two consecutive data values that include opposite values (for example, boundary values E2, E3, and E4) includes A random value (instantiated as "X"). For such signals, the adaptive controller 102 can randomly adjust the gain applied to the input signal up or down since the intersymbol interference effects are fully compensated or absent. If the amount of up and down adjustments is substantially equal, the gain applied to the input signal remains on average at the same level. If the amount of up and down adjustments is not substantially equal, the gain applied to the input signal will drift slightly from the initial level. This shift in gain level produces slight residual intersymbol interference. As exemplified below, an equalizer receiver can detect this interference and correct the gain back to the average initial level.

FIG. 4B illustrates an example clock signal 300 in contrast to an equalizer output signal 46 that is in phase with the clock signal but exhibits undercompensated residual intersymbol interference effects. In this case, the equalizer did not fully compensate the signal, so the signal has a low frequency bias. In low-frequency inclined signals, if a data pulse (for example, the data pulse at D3) occurs after several consecutive data values (for example, D0 to D2) that have passed the same high or low value, the data pulse height will be Reduced due to lack of high frequency components. Also, the boundary value before (eg, E2) or after the data pulse (eg, E3) will likely be the same as the high or low value of the data value (eg, D2) preceding the pulse (i.e., they will not include random value). Accordingly, when analyzing certain data values and boundary values, the adaptive controller 102 may increase the gain applied to the input signal to compensate for low frequency distortion, as described further below. It should be noted, however, that in certain embodiments and as described below, adaptive controller 102 may not be able to compensate for low frequency distortion exhibited by the output signal until a transition (eg, between D2 and D3) occurs. Boundary values after a few consecutive transitions (e.g. at E4) may include a random value "X", since such consecutive transitions may increase high-frequency components and decrease low-frequency components in the signal, thus, possibly reducing the Boundary value for sensitivity to residual inter-symbol interference.

FIG. 4C illustrates an example clock signal 400 in contrast to an equalizer output signal 46 that is in phase with the clock signal but exhibits overcompensated residual intersymbol interference effects. In this case, the equalizer is compensating too much for the input signal, so the signal has a high frequency bias. In high-frequency inclined signals, if a data pulse (for example, the data pulse at D3) occurs after several consecutive data values (for example, D0 to D2) that have passed the same high or low value, the pulse height is measured by The enhanced high-frequency components are elevated. Also, the boundary value before the data pulse (e.g. E2) or the boundary value after the data pulse (e.g. E3) will likely be the opposite of the high or low value of the data value before the data pulse (e.g. D2) (i.e. they will not include random value). Accordingly, when analyzing certain data values and boundary values, the adaptive controller 102 may reduce the gain applied to the input signal to compensate for high frequency distortion, as described further below. It should be noted, however, that in certain embodiments and as described below, the adaptive controller 102 may not be able to compensate for the high frequency distortion exhibited by the output signal until a transition (eg, between D2 and D3) occurs. The boundary value after several successive transitions (e.g. at E4) may comprise a random value "X", since such successive transitions may increase high-frequency components and decrease low-frequency components in the signal, thus, possibly lowering the boundary Value for sensitivity to residual intersymbol interference.

FIG. 5 is a flowchart illustrating a method 500 for interpreting output signal values to compensate for residual intersymbol interference in accordance with certain embodiments of the invention. The method starts at step 510 where an output signal is sampled using a clock signal. As described above in connection with FIG. 3, the output signal may be the output of an equalizer, and the output signal may be sampled according to a clock signal.

In certain embodiments, the output signal may be sampled at reference data points and boundary points determined by the clock signal. Alternatively, the output signal may not be sampled at boundary points, but boundary values corresponding to these non-sampled points may be derived. In certain embodiments, adaptive controller 102 may derive boundary values based on the sampled data values and other phase information (ie, whether the phase of the output signal is early or late). For example, if the phase of the output signal is early, the adaptive controller 102 may determine that the high or low value of the boundary value is the same as the high or low value of the data value immediately preceding the boundary value. If the phase of the output signal is late, the adaptive controller 102 may determine that the high or low value of the boundary value is the same as the high or low value of the data value immediately following the boundary value.

At step 520, after sampling the output signal, the sampled data values may be analyzed to determine whether transitions have occurred in the values. For example, the analysis may be performed by adaptive controller 102 . At step 530 , if no transition is detected, the method returns to step 520 . If a transition is detected between successive data values, the method proceeds to step 540 . It should be noted that in certain embodiments transitions may be detected by directly comparing received data values to each other. In an alternative embodiment, transitions may be detected by comparing received data values and boundary values to predefined patterns of values that include transitions (and correspond to particular adaptive control actions). It should also be noted that in certain embodiments, adaptive actions may be performed after only one transition is detected.

If a transition is detected, then at step 540 the boundary value between consecutive data values including the transition is compared to the data value 1.5 bits (or symbols) preceding the boundary value. In certain embodiments, the relationship between the boundary value and the data value 1.5 bits (or symbols) preceding the boundary value may determine the adaptive equalizer action response. For example, in certain embodiments, an exclusive OR (XOR) operation (or a non-exclusive OR (XNOR) operation) may be performed on the two values. In such an embodiment, the result of the XOR operation (or XNOR operation) may correspond to a particular type of intersymbol interference exhibited by the output signal, and thus may be used to determine the adaptive equalizer action response. In an alternative embodiment, an anti-correlation function (or correlation function) may be applied to these two values. In such an embodiment, the result of the anticorrelation function (or correlation function) may correspond to a particular type of intersymbol interference exhibited by the output signal, and thus may be used to determine the adaptive equalizer action response. In yet another alternative embodiment, the boundary value and the preceding 1.5 bits of the boundary value may be compared by comparing the received data value and the boundary value with a predefined value pattern (which corresponds to a particular adaptive control action). (or symbol) data values for comparison. Also, in alternative embodiments, data values closer or farther from the boundary value may be used, rather than necessarily 1.5 bits (or symbols) before the boundary value. It should be noted that although some of the discussion herein is expressed in units of bits, such discussion could alternatively be interpreted to represent symbols, if appropriate.

It should be noted that the analysis of the above (and below) boundary values is only an example. More generally, based on sampling the output signal, the error value (specific boundary value as already described) may represent the residual amount of distortion (frequency dependent distortion and/or DC offset distortion discussed further below). Based on the generated error value, adjustments may be made to loss compensation (and/or offset compensation) applied to the data signal. In a particular embodiment, for example, the error value may include a pulse width value (wide, narrow, or typical) and may be derived from 2 consecutive boundary and intermediate data values out of 3 consecutive data values with two transitions Output pulse width value. This pulse width value can be used to adjust the loss compensation performed.

At step 550, a determination is made whether the boundary value has the same high or low value as the data value 1.5 bits (or symbols) preceding the boundary value. In certain embodiments, the two values may be compared in an XOR (or XNOR) operation, as described above. In an alternative embodiment, an anti-correlation function (or correlation function) may be applied to these two values. In yet another alternative embodiment, the two values may be compared by comparing them to a predefined pattern. If the two values have the same high or low value (for example, if the XOR result is equal to "0", if the anticorrelation function result is equal to "-1", or if the values correspond to a specific predefined pattern of values), The method then proceeds to step 560 . At step 560, the equalizer increases the gain applied to the signal. In a particular embodiment, the increase in gain compensates for undercompensated residual intersymbol interference exhibited by the signal. As illustrated in Figure 4B, this interference is revealed by a "0" XOR result.

It should be noted that in alternative embodiments, the adaptive control action may be any suitable adaptive control action employing various conventional adaptive control algorithms. For example, adaptive control actions may be based on conventional adaptive control algorithms such as least mean square (LMS) algorithm, sign-sign least mean square (SS-LMS) algorithm, zero forcing (ZF) algorithm, and the like.

If it is determined at step 550 that the boundary value has an opposite high or low value to the data value 1.5 bits (or symbols) before the boundary value (for example, if the XOR result is equal to "1", if the anticorrelation function result is equal to "+1 ", or if these values correspond to a particular predefined value pattern), the method proceeds to step 570. At step 570, the equalizer reduces the gain applied to the signal. In a particular embodiment, the reduction in gain compensates for overcompensated residual intersymbol interference exhibited by the signal. As illustrated in Figure 4C, this interference is revealed by a "1" XOR result.

It should be noted that in certain embodiments, steps 550 , 560 , and 570 may be performed by adaptive controller 102 and the applied gain may be adjusted using variable gain amplifier 116 . Also, in certain embodiments, if gain is applied to more than one signal path (eg, to path 101 in example equalizer 42 ), the applied gain may be adjusted in one path and fixed for other paths. In an alternative embodiment, the independent control variables may be mapped to multiple paths using a specific function, and the paths may be augmented according to the mapping process. Alternatively, the gain may be adjusted independently for each path, as discussed further below in connection with FIGS. 7-10.

FIG. 6 is a table 600 illustrating an example gain control scheme associated with method 500 of FIG. 5 . Each row 602 corresponds to a particular value pattern for which a particular adaptive equalizer control action is performed. Column 610 includes a high or low value for each of the sampled series data and boundary values (although it could be "1" or "0", or any other suitable value in other examples, but in this "+1" or "-1" in the specific example). Column "D1" contains the first sampled data value of the output signal, column "D2" contains the second sampled data value of the output signal, column "D3" contains the third sampled data value of the output signal, and column "E2" contains the second data value value and the boundary value between the third data value. These values are similar to those illustrated in Figures 4A to 4C. As can be observed, in each pattern a transition occurs between the data values of columns "D2" and "D3".

It should be noted that the pattern of values in each row 602 may be sampled by the sampler 104 and sent to the adaptive controller 102 . In particular embodiments, adaptive controller 102 may receive a greater number of values than illustrated, for example, including boundary values between data values in columns "D1" and "D2." Alternatively, as discussed above, the adaptive controller 102 may only receive sampled data and other phase information, and may derive certain boundary values from these data values and phase information (including, for example, the boundaries in column E2 value) (and may not be sampled by the sampler 104).

Column 612 includes the degree of ISI. The degree of ISI is derived from a specific value associated with the output signal. For example, the degree of ISI may be the result of applying an anti-correlation function to a boundary value between two data values comprising a transition and to data values 1.5 bits preceding the boundary value. In certain embodiments, the ISI level may be calculated as the inverse of the product of the boundary value and the data value, with "+1/-1" values corresponding to "high/low" values. In table 600, the degree of ISI in column 612 is the result of applying an anti-correlation function to the boundary value in column E2 and the data value in column D1 (1.5 bits before the boundary value) in the same row 602 . The degree of ISI can be calculated as the inverse of the product of E2 and D1 using "+1/-1" values corresponding to "high/low" values. As illustrated in columns 614 and 616, an ISI degree of "-1" is associated with a degree of undercompensated equalization and an increase in equalizer compensation. An ISI degree of "+1" is associated with a degree of overcompensation equalization and a reduction in equalizer compensation. Therefore, based on the degree of ISI, certain adaptive equalizer actions are taken. In alternative embodiments, the received data and boundary values may be compared to predefined value patterns, and these predefined value patterns may correspond to specific adaptive control actions.

It should be noted that in certain embodiments, the adaptive controller 102 may receive a stream of sampled values and select an appropriate value from among these values (e.g., a boundary value between two data values including a transition and 1.5-bit data value). Adaptive controller 102 may then derive the degree of ISI from these selected values, eg, by applying an anti-correlation function to these selected values. The adaptive controller 102 can then take appropriate adaptive control actions based on the results of the anti-correlation function. Alternatively, the adaptive controller 102 may compare these sampled values to a predefined pattern of values (which correspond to a particular adaptive control action). Based on the specific predefined value patterns corresponding to these sampled values, the adaptive controller 102 can perform corresponding adaptive control actions.

Modifications, additions, or omissions may be made to the systems and methods without departing from the scope of the present invention. Components of the described systems and methods may be integrated or separated according to particular needs. Additionally, the operations of the systems and methods may be performed by more, fewer or other components.

In certain embodiments, an equalizer, such as equalizer 42 of FIG. 3 , may control more than one independent parameter, such as an unchanged component, a first-order component, and a second-order component of a signal. Examples of multiparametric (multidimensional) equalizers include second order derivative equalizers and 3-tap finite impulse response (FIR) filters. As discussed above, the method 500 may be used in a multidimensional equalizer if, for example, the applied gain is adjusted for one parameter and the gain of the other parameter is fixed. Alternatively, method 500 may be used in a multidimensional equalizer if the applied gain is adjusted according to a specific function incorporating multiple independent parameters (but the gain is not adjusted independently for each independent parameter). In this alternative, the applied gain may be adjusted independently for each independently controlled parameter. As described further below, in a 3-tap FIR filter, for example, adjustments to the second and third tap coefficients may be made independently, and each of these adjustments may include adjustments to compensation for distortion.

Compensation such as gain can be independently adjusted for each independent control parameter based on a specific relationship between one or more sampled data values and the sampled data value 1.5 bits before the boundary value that lies between consecutive data values including transitions Make adjustments. A particular relationship may eg correspond to a particular type of inter-symbol interference for a particular independent control parameter. When, for example, adaptive controller 102 detects such a relationship between a plurality of sampled data values (e.g., using a predefined pattern of data values), adaptive controller 102 may perform a specific adaptive equalizer control action for a specific one or more independent control parameters for adjustment.

The predefined data value patterns used by the adaptive controller 102 for comparison with the incoming stream of sampled data values may be particularly sensitive to inter-symbol interference for certain independent control parameters. These modes may be selected, for example, based on the sensitivity of boundaries between data values including transitions to the individual control parameters being adjusted. In particular, the modes may be selected based on a partial derivative of the equalized channel impulse response with respect to the independent control parameter (eg, based on the sign and magnitude of the partial derivative). This is because the equalizer output signal 46 is represented as a convolution of the transmitted data sequence with the equalized channel impulse response.

For example, in an analog, second derivative equalizer, the partial derivatives of the equalized channel impulse response with respect to the first derivative gain may be assumed to be negative at 1.5 and 2.5 bits after the peak. Therefore, if the first derivative gain is too high, the correlation between a boundary value and data values 1.5 and 2.5 bits before that boundary value may both be negative. On the other hand, if the first derivative gain is too low, the correlation between the boundary value and the data values 1.5 and 2.5 bits before the boundary value may both be positive. This is because the data corresponds to the peak of the impulse response and the boundary corresponds to the tail after the peak in the impulse response. The partial derivative of the equalized channel impulse response with respect to the second derivative gain may be assumed to be negative 1.5 bits after the peak and positive 2.5 bits after the peak. Therefore, if the second derivative gain is too high, the correlation between the boundary value and the data value 1.5 bits before the boundary value may be negative, and the correlation between the boundary value and the data value 2.5 bits before the boundary value The correlation may be positive. On the other hand, if the second derivative gain is too low, the correlation between the boundary value and the data value 1.5 bits before the boundary value may be positive, and the correlation between the boundary value and the data value 2.5 bits before the boundary value may be positive. The correlation between them may be negative. Using these relationships, various techniques (eg, method 700 described below) can be used to adjust the gain applied to the first derivative component of the input signal and the gain applied to the second derivative component of the input signal.

As another example, in a 3-tap finite impulse response (FIR) filter equalizer where the main tap is the first tap, the partial derivative of the equalized channel impulse response with respect to the second tap coefficient can be assumed to be after the peak The 1.5 and 2.5 places are positive. The partial derivative of the equalized channel impulse response with respect to the third tap coefficient may be assumed to be zero 1.5 bits after the peak and positive 2.5 bits after the peak. Using these relationships, various techniques (eg, method 1000 described below) can be used to adjust the second and third tap coefficients. In this way, the FIR filter equalizer can perform multi-tap FIR filter equalization in parallel. It should be noted that different relationships may be utilized for different types of equalizers. For example, a different relationship can be exploited for a multi-tap decision-feedback equalizer that performs multi-tap decision-feedback equalization in parallel.

7 is a flowchart illustrating an example method 700 for interpreting output signal values for multiple independent control parameters in an analog second derivative equalizer, in accordance with certain embodiments of the invention. For an analog second-order derivative equalizer, three independent control parameters (e.g., gain applied to the unaltered portion of the input signal, gain applied to the portion of the input signal that is altered to be the first derivative of the input signal, and The gain applied to the portion of the input signal that is changed to the second derivative of the input signal) is controlled. For example, parallel compensation can be performed by analog continuous-time first derivative filter equalization and/or analog continuous-time second derivative filter equalization.

Method 700 begins at step 710 . Steps 710 to 770 may be the same as steps 510 to 570 in the above method 500, so they will not be described in detail again. However, it should be noted that in steps 710 to 770, the first independent parameter may be controlled for the first path. For example, steps 710 to 770 may be used to adjust the gain applied to the unchanged portion of the input signal in the first path (eg, path 101A of equalizer 42 ). In a particular embodiment, the equalizer compensation in the first path can be increased by reducing the gain applied to the unchanged portion of the input signal in the first path, and can be increased by increasing the gain applied to the input signal in the first path The equalizer compensation in the first path is reduced by the unaltered portion of the applied gain. This is because the amount of equalizer compensation depends on the relative gain of the second and third paths to the first path, so increasing the gain of the first path will effectively reduce the gain of the second and third paths to the first path. relative gain. In steps 780 to 850, the second independent parameter and the third independent parameter may be controlled for the second path and the third path, respectively. For example, steps 780 to 850 may be used to adjust the gain applied to the portion of the input signal in the second path (e.g., path 101B of equalizer 42) that is changed to the first derivative of the input signal, and to adjust the gain applied to the input signal The gain of the portion changed to the second order derivative of the input signal in the third path (eg, path 101C of equalizer 42 ) is adjusted.

In steps 780 and 790, if the boundary value between the data values comprising the transition and the data value 1.5 bits before the boundary value have different values (high or low), then the 1.5 bits preceding the boundary value Determine whether the value (high value or low value) of the data value of the boundary value is the same as or opposite to the value of the data value 2.5 bits before the boundary value. This determination may be made, for example, by performing suitable operations or by comparing received data values and boundary values with predefined value patterns (which correspond to specific adaptive control actions). If the two values are different (opposite), method 700 proceeds to step 800 and reduces the gain applied to the second derivative component of the input signal in the third path. If the two values are the same, method 700 proceeds to step 810 and the gain applied to the first derivative component of the input signal in the second path is reduced.

At steps 820 and 830, if the boundary value between the data values comprising the transition and the data value 1.5 bits before the boundary value have the same value (high value or low value), then 1.5 bits before the boundary value Determine whether the value (high value or low value) of the data value of the boundary value is the same as or opposite to the value of the data value 2.5 bits before the boundary value. Again, this determination may be made, for example, by performing suitable operations or by comparing received data values and boundary values with predefined value patterns (which correspond to specific adaptive control actions). If the two values are different (opposite), method 700 proceeds to step 840 and increases the gain applied to the second derivative component of the input signal in the third path. If the two values are the same, method 700 proceeds to step 850 and increases the gain applied to the first derivative component in the second path.

It should be noted that, as described above in method 700, the number of independent control parameters may be the same as the number of adjusted parameters in certain embodiments. In alternative embodiments, the number of independent control parameters may be less than the number of adjusted parameters. For example, in an analog second derivative equalizer there may be 2 independent control parameters (i.e. a first gain applied to the first derivative component of the input signal and a second gain applied to the second derivative component of the input signal), And there may be 3 adjusted parameters (ie a third gain (fixed gain) applied to the unchanged component of the input signal). As another example, a first independent control variable may control the relationship between the gain applied to the unchanged component and the gain applied to the first derivative component, and the second control variable may control the relationship between the gain applied to the second derivative component and the gain applied to the Controls the relationship between the gain of the unchanged component and the gain applied to the first derivative component, whichever is larger. Method 700 can be modified, if appropriate, to accommodate these different circumstances.

FIG. 8 is a table 900 illustrating an example gain control scheme associated with method 700 of FIG. 7 . Each row 902 corresponds to a particular value pattern for which a particular adaptive equalizer control action is performed. Column 910 includes a pattern consisting of sampled data and boundary values, where values can have a high ("1") value or a low ("0") value. Column "D0" contains the zeroth sampled data value of the output signal, column "D1" contains the first sampled data value of the output signal, column "D2" contains the second sampled data value of the output signal, and column "D3" contains the For the third sampled data value, column "E2" includes boundary values between the second data value and the third data value. These values are similar to those illustrated in Figures 4A to 4C. As can be observed, in each pattern a transition occurs between the data values of columns "D2" and "D3".

It should be noted that the values in each row 902 may be sampled by sampler 104 and sent to adaptive controller 102 . Adaptive controller 102 may compare the sampled values to one or more predetermined patterns of values. In particular embodiments, adaptive controller 102 may take an associated set of one or more adaptive equalizer actions when a match is detected. In such an embodiment, the particular relationship between these values may already be known (eg, because a predetermined pattern of values is being used), so one or more of the steps described above in method 700 (eg, steps 780, 790 ) need not be performed. , 820, and 830).

It should also be noted that in certain embodiments, adaptive controller 102 may receive a greater number of values than illustrated, including, for example, the boundary values between the data values in columns "D0" and "D1" and the boundary value between the data values in columns "D1" and "D2". Alternatively, as discussed above, the adaptive controller 102 may receive only sampled data values and other phase information from which certain boundary values (such as those included in column E2 The boundary value of ) (and thus may not be sampled by the sampler 104).

Column 920 includes an alternative boundary value for each row 902 at column "E2". Column 924 includes the particular degree of compensation and adaptive equalizer action associated with the unchanged component of the input signal for the particular mode. Adaptive equalizer actions may be applied as discussed above in method 700 . Column 930 includes the particular degree of compensation and adaptive equalizer action associated with the first derivative component of the input signal for the particular mode. These adaptive equalizer actions may also be applied as discussed above in method 700 . Column 940 includes the particular degree of compensation and adaptive equalizer action associated with the second derivative component of the input signal for the particular mode. These adaptive equalizer actions may also be applied as discussed above in method 700 .

9 is a flowchart illustrating an example method 1000 for interpreting output signal values for a plurality of equalizer parameters in a 3-tap FIR filter in accordance with certain embodiments of the invention. Method 1000 begins at step 1010 . Steps 1010 to 1030 may be similar to steps 510 to 530 in the above-mentioned method 500, so they will not be described in detail. In a particular embodiment, the first tap coefficient may be fixed and it is not adjusted by adaptive control. Steps 1080 to 1170 may adjust the second tap coefficient and the third tap coefficient. It should be noted that in a 3-tap FIR filter, as described further below, adjustments to the second and third tap coefficients can be made independently, and each of these adjustments can include adjustments to Compensation adjustment. In general, even in the context of a 3-tap FIR filter equalizer, an analog derivative filter equalizer, or any other suitable equalizer, even if each path only performs a portion of the compensation and the outputs from all paths are combined in The compensation occurs in combination only together, and the action performed on each path can also be said to apply or adjust the compensation for the distortion.

In steps 1080 and 1090, the value of the data value 1.5 bits before the boundary value between the data values including the transition (high value or low value) is the same as the value of the data value 2.5 bits before the boundary value or vice versa. This determination may be made, for example, by performing suitable operations or by comparing received data values and boundary values with predefined value patterns (which correspond to specific adaptive control actions). If the two values are different (opposite), method 1000 proceeds to step 1100 . If the two values are the same, method 1000 proceeds to step 1140 .

At steps 1100 and 1110, a determination is made as to whether the value (high or low) of the data value located 2.5 bits prior to the boundary value between the data values including the transition is the same as or opposite to the value of the boundary value. This determination may be made, for example, by performing suitable operations or by comparing received data values and boundary values with predefined value patterns (which correspond to specific adaptive control actions). If the two values are different (opposite), method 1000 proceeds to step 1120 and the third tap coefficient is incremented. If the two values are the same, method 1000 proceeds to step 1130 and the third tap coefficient is decreased.

At steps 1140 and 1150, a determination is made as to whether the value (high value or low value) of the data value located 2.5 bits before the boundary value between the data values comprising the transition is the same as or opposite to the value of the boundary value. Again, this determination may be made by performing suitable operations or by comparing received data values and boundary values with predefined value patterns (which correspond to specific adaptive control actions). If the two values are different (opposite), method 1000 proceeds to step 1160 and the second and third tap coefficients are incremented. If the two values are the same, method 1000 proceeds to step 1170, and the second tap coefficient and the third tap coefficient are decreased.

FIG. 10 is a table 1200 illustrating an example gain control scheme associated with the method of FIG. 9 . Each row 1202 corresponds to a particular value pattern for which a particular adaptive equalizer control action is performed. Column 1210 includes a pattern consisting of sampled data and boundary values, where a value can be a high ("1") value or a low ("0") value. Column "D0" contains the zeroth sampled data value of the output signal, column "D1" contains the first sampled data value of the output signal, column "D2" contains the second sampled data value of the output signal, and column "D3" contains the For the third sampled data value, column "E2" includes boundary values between the second data value and the third data value. These values are similar to those illustrated in Figures 4A to 4C. As can be observed, in each pattern a transition occurs between the data values of columns "D2" and "D3".

It should be noted that sampler 104 may sample the pattern of values in each row 1202 and send it to adaptive controller 102 . Adaptive controller 102 may compare the sampled values to one or more predetermined patterns of values. In particular embodiments, adaptive controller 102 may take an associated set of one or more adaptive equalizer actions when a match is detected. In such an embodiment, the particular relationship between the values may already be known (eg, because a predetermined pattern of values is being used), so one or more of the steps described above in method 1000 (eg, step 1080 ) need not be performed.

It should also be noted that in certain embodiments, adaptive controller 102 may receive a greater number of values than illustrated, including, for example, the boundary values between the data values in columns "D0" and "D1" and the boundary value between the data values in columns "D1" and "D2". Alternatively, as discussed above, the adaptive controller 102 may receive only sampled data values and other phase information from which certain boundary values (including, for example, Boundary value) (thus may not be sampled by sampler 104).

Column 1220 includes an alternative boundary value for each row 1202 at column "E2". Column 1230 includes the particular coefficient level and adaptive equalizer action associated with the second tap coefficient for the particular mode. These adaptive equalizer actions may also be applied as discussed above in method 1000 . Column 1240 includes the particular coefficient level and adaptive equalizer action associated with the third tap coefficient for the particular mode. These adaptive equalizer actions may also be applied as discussed above in method 1000 .

Modifications, additions, or omissions may be made to the systems and methods without departing from the scope of the present invention. Components of the systems and methods may be integrated or separated according to particular needs. Additionally, the operations of the systems and methods may be performed by more, fewer or other components.

As discussed above in connection with FIG. 5, the relationship between a boundary value between consecutive data values that include a transition and the data value 1.5 bits preceding the boundary value may be related to a particular degree of equalization of the signal. The correlation will be especially accurate for signals with sufficiently randomized data sequences. However, if the signal has a periodic or quasi-periodic data sequence, the correlation is affected by the periodicity of the sequence. In particular, the correlation can be affected even more severely by the periodicity of the sequence if the incoming signal or the clock signal has a duty cycle distortion.

Typically, periodic or quasi-periodic data sequences have strong correlations between multiple data values, such as adjacent data values, thereby affecting the frequency spectrum of the signal. For example, if adjacent data values are more likely to be the same value than different values, the signal is low-frequency biased, while if adjacent data values are more likely to be different values than the same value, the signal is high prone to frequent. This distortion of the signal spectrum can affect the ability of the adaptive equalizer to flatten the signal spectrum. Typically, periodic or quasi-periodic data sequences have this negative effect on the adaptive gain control of the equalizer even in the absence of duty cycle distortion.

This negative effect of periodic and quasi-periodic sequences on the equalizer's adaptive gain control is enhanced by duty cycle distortion. For example, assume that incoming data can be marked as even data and odd data in turn. It is also possible to label the boundaries between data as even boundaries and odd boundaries in sequence. Here, an even boundary may mean a boundary after even data and before odd data, and an odd boundary may mean a boundary after odd data and before even data. Duty cycle distortion can cause the even and odd boundary values of the receiver logic to shift heavily to an "early" phase (i.e., the same phase as the previous data value) or a "late" phase (i.e., the same phase as the next data value). phase) deviation. For example, an even boundary value will shift toward "early" phase, while an odd boundary value will shift toward "late" phase.

If the period of the periodic or quasi-periodic data sequence is a multiple of two data values, then the number of transitions at even boundaries will also deviate from the number of transitions at odd boundaries. For example, transitions may occur more frequently at even boundaries than at odd boundaries in a periodic or quasi-periodic data sequence. The equalizer control is affected by how the boundary values at the even or odd boundaries dominating transitions in a periodic or quasi-periodic data sequence are deviated (i.e. "early" phase or "late" phase), This deviation is due to duty cycle distortion. This effect is not determinable until the recovered clock locks to this incoming periodic or quasi-periodic incoming data sequence, since at boundary values with "early or late" phase due to duty cycle distortion The correspondence between deviations and deviations from boundaries with "dominant or non-dominant" transitions due to periodic or quasi-periodic data sequences may depend on how a recovered clock in the presence of duty cycle distortion locks to this incoming periodicity or quasi-periodic data series.

Due to this deviation of boundary values ("early" phase or "late" phase), the equalizer control action is also There will be deviations. Unbalanced deviations towards a particular equalizer control action can produce unacceptable results for the equalizer control.

FIG. 11 illustrates example boundary information 1300 affected by duty cycle distortion. Signal 1310 is received at receiver logic and sampled using a four-phase half-rate clock with duty cycle distortion. Even data values can be sampled on the rising edge of clock A (CLKA) 1320, odd data values can be sampled on the rising edge of clock C (CLKC) 1340, and can be sampled on the rising edge of clock B (CLKB) 1330. Even boundary values, and odd boundary values can be sampled on the rising edge of clock D (CLKD) 1350 . In this example, clock B 1330 has a duty cycle of more than 50%, and clock D 1350 has a duty cycle of less than 50%. As a result, even boundary values sampled on the rising edge of clock B 1330 are heavily phased "early" and odd boundary values sampled on the rising edge of clock D 1350 are heavily phased "late". If the "early" and "late" counts are averaged, the clock recovery loop can lock on to that phase position. If the incoming periodic or quasi-periodic signal has a deviating transition between even and odd boundaries, the deviating phase at the boundary dominating the transition will bias the adaptive control action. For example, if an even boundary sampled at the rising edge of clock B (CLKB) 1330 has more transitions than an odd boundary sampled at the rising edge of clock D (CLKD) 1350, adaptive control Actions will deviate towards the "early" phase. If these deviations are not taken into account in the equalizer's adaptive gain controller, the result of the equalizer's adaptive operation will be affected.

One way to account for opposite deviations in even and odd boundary values is to balance these deviations. This balance can be achieved by applying adaptive equalizer action only when the controller detects a particular data pattern (with approximately equal probability of occurrence) that is approximately equally distributed in the two phases. These specific data patterns (which may be called filter patterns) can be used to balance out deviations produced in (quasi) periodic data sequences, and these specific data patterns can also be used with sufficiently randomized data sequences without what is the problem. In this way, the properties of the adaptive equalizer control can be made consistent for (quasi-)periodic and substantially randomized data sequences. If there is more than one independent control parameter, the adaptive equalizer control may use a specific filter pattern to control the gain applied to each specific independent control parameter. In certain embodiments, as discussed above in connection with FIGS. 7 through 10 , a selection may be made from a set of approximately equally occurring modes based on the partial differential gradient of the equalized channel impulse response for a particular independent control parameter to apply The filter mode that controls the gain of this parameter.

FIG. 12 is a flowchart illustrating an example method 1400 for selecting a filter pattern to reduce the negative impact of duty cycle distortion in accordance with certain embodiments of the invention. Method 1400 may be used to select filter patterns for use with periodic or quasi-periodic data sequences such as the 8B10B idle sequence and the 8B10B CJPAT test sequence as defined by the Institute of Electrical and Electronics Engineers (IEEE) 802.3ae standard.

Method 1400 begins at step 1410, where groups of even and odd data sequences are monitored. The even data sequence group includes data sequences starting with even (ie, at even phase) data followed by odd data, even data, odd data, and so on. The odd data sequence group includes data sequences starting with odd (ie, at odd phase) data followed by even data, odd data, even data, and so on. At step 1420, a distribution of data patterns in the even and odd data sequences is determined. In a particular embodiment, the data pattern may include 6 bits. In an alternative embodiment, the data pattern may include 5 bits. In yet another alternative embodiment, the data pattern may include any other suitable number of bits. At steps 1430 and 1440, only those patterns observed in both the even and odd data sequences are further analyzed. Those patterns not observed in both sequences are not selected as filter patterns at step 1500 .

At steps 1450 and 1460, for those patterns observed in the data pattern distributions of both the even and odd data sequences, a question is asked whether any of these patterns are equally (or approximately equally) distributed in the even data The determination is made in both sequence and odd data sequence. As discussed above, selecting approximately equally distributed data patterns as filter patterns cancels out deviations due to duty cycle distortion. For those modes that are equally (or approximately equally) distributed, method 1400 proceeds to step 1470 . Any modes that are not approximately equally distributed are not selected as filter modes at step 1500 .

At steps 1470 and 1480, a determination is made as to whether there is a transition between the last two bits for any of the remaining patterns. As discussed above, the relationship between a boundary value between successive data values comprising a transition and one or more data values preceding the boundary value is used to determine the adaptive equalizer action to apply. Therefore, certain embodiments may select only those data patterns where there is a transition between the last two bits. In such an embodiment, any pattern for which there is no transition between the last two bits is thus not selected as a filter pattern at step 1500 .

At step 1490, those patterns observed in both sequences, distributed (approximately) equally in both sequences, and with a transition between the last two bits are selected as filter patterns. However, it should be noted that even further analysis of these modes is possible before selecting them as filter modes. For example, as described further below, a particular mode(s) of the modes may be selected for controlling a particular independent control parameter if that particular mode(s) is more suitable for controlling that particular independent control parameter. These filter modes can then be used to make equalizer control adjustments as discussed herein.

13 is a table illustrating an example distribution 1600 of six-bit data patterns in even 8B10B idle data sequences and odd 8B10B idle data sequences. Column 1610 includes a number of six-bit data patterns, column 1620 includes the probability of observing a particular pattern in an even 8B10B idle data sequence, and column 1630 includes the probability of observing a particular pattern in an odd 8B10B idle data sequence. Here, the even data sequence refers to a data sequence starting with even data followed by odd data, even data, odd data, and so on. An odd data sequence refers to a data sequence starting with odd data followed by even data, odd data, even data, and so on. For each data pattern in column 1610, the earlier bits are to the left of the later bits. Blank cells in column 1620 or column 1630 indicate that the probability of observing the associated data pattern in the associated data sequence is zero.

As illustrated in distribution 1600, 4 data sequences are observed in both the even 8B10B idle data sequence and the odd 8B10B idle data sequence: 000010, 111010, 000101, and 111101. Also the 4 patterns are equally distributed in both sequences, each pattern is observed 4.796% of the time. Furthermore, these 4 patterns have transitions between the last two bits. Thus, in certain embodiments, method 1400 may be utilized to select these data sequences as filter patterns, and adaptive control actions may be applied only when these filter patterns are observed. With these filter modes, the negative impact of duty cycle distortion can be reduced. Furthermore, the control behavior for the 8B10B idle data sequence can be consistent with the control behavior for the fully randomized data sequence.

It should be noted that in certain embodiments (eg, in a second derivative equalizer) multiple independent control parameters may be utilized to adjust the gains applied to the first and second derivative components of the input signal. In this case, a particular one of the observed and equally distributed filter patterns may be more suitable for these independent control parameters when receiving 8B10B idle data sequences. For example, well-suited filter patterns may include filter patterns that have boundary values between successive data values including transitions that are relatively sensitive to the gain applied to the first or second derivative components. Thus, in this example, well-suited filter patterns include those that enable the adaptive controller to effectively equalize the first or second derivative components of the signal.

For the 8B10B idle data sequence, a well-suited filter pattern may include 000010 and 111101 for applying gain to the first derivative component. In a particular embodiment, adaptive control action may thus be applied to the first derivative components only when data values corresponding to these filter modes are observed at the equalizer. In this way, the first derivative components of the signal can be effectively equalized. To apply gain to the second derivative component (in the context of 8B10B idle data sequences), well-suited filter patterns may include 000101 and 111010. In a particular embodiment, adaptive control action may thus be applied to the second derivative component only when data values corresponding to these filter modes are observed at the equalizer. In this way, the second derivative components of the signal can be effectively equalized.

14 is a table illustrating an example gain control scheme associated with adjusting the gain applied to the unchanged, first derivative, and second derivative components of the input signal using an example filter pattern derived from the table of FIG. 13 1700. The input signal can be, for example, an 8B10B idle data sequence, another (quasi) periodic signal (where the filter patterns of FIG. 13 are approximately equally distributed), or a well randomized signal. Each row 1702 corresponds to a particular value pattern for which a particular adaptive equalizer control action is performed. Each data pattern in these rows 1702 corresponds to one of the selected filter patterns described above in connection with FIG. 13 .

Column 1710 includes patterns consisting of sampled data and boundary values, where values can be high ("1") or low ("0") values. Column "D0" contains the zeroth sampled data value of the output signal, column "D1" contains the first sampled data value of the output signal, column "D2" contains the second sampled data value of the output signal, and column "D3" contains the The third sampled data value, column "D4" contains the fourth sampled data value of the output signal, column "D5" contains the fifth sampled data value of the output signal, column "E4" contains the the boundary value of . As can be observed, in each pattern a transition occurs between the data values of columns "D4" and "D5".

It should be noted that the pattern of values in each row 1702 may be sampled by sampler 104 and sent to adaptive controller 102 . Adaptive controller 102 may compare the sampled values to one or more predetermined filter patterns. In particular embodiments, when a match is detected, adaptive controller 102 may take an associated set of one or more adaptive equalizer actions, as described herein.

It should also be noted that in certain embodiments, adaptive controller 102 may receive a greater number of values than illustrated, including, for example, boundary values between data values in columns "D0" through "D4" . Alternatively, as discussed above, the adaptive controller 102 may only receive sampled data values and other phase information, and may derive certain boundary values from these data values and other phase information (such as included in column E4 The boundary value of ) (and thus may not be sampled by the sampler 104).

Column 1720 includes the alternative boundary value for each row 1702 at column "E4". For a particular mode, column 1724 includes the particular degree of compensation and adaptive equalizer action associated with the unchanged component of the input signal. Adaptive equalizer action may be controlled in any suitable manner (including, for example, by analyzing specific values). For a particular mode, column 1730 includes a particular degree of compensation and adaptive equalizer action associated with the first derivative component of the input signal. These adaptive equalizer actions may also be controlled in any suitable manner (including, for example, by analyzing specific values). For a particular mode, column 1740 includes the particular degree of compensation and adaptive equalizer action associated with the second derivative component of the input signal. These adaptive equalizer actions may also be controlled in any suitable manner (including, for example, by analyzing specific values).

15 is a table illustrating an example distribution 1800 of six-bit data patterns in an even 8B10B CJPAT data sequence and an odd 8B10B CJPAT data sequence. Column 1810 includes a plurality of six-bit data patterns, column 1820 includes the probability of observing a particular pattern in an even 8B10B CJPAT data sequence, and column 1830 includes the probability of observing a particular pattern in an odd 8B10B CJPAT data sequence. Here, the even data sequence refers to a data sequence starting with even data followed by odd data, even data, odd data, and so on. An odd data sequence refers to a data sequence starting with odd data followed by even data, odd data, even data, and so on. For each data pattern in column 1810, the earlier bits are to the left of the later bits. Blank cells in column 1820 or column 1830 indicate that the probability of observing the associated data pattern in the associated data sequence is zero. It should be noted that distribution 1800 is a distribution of data patterns in a "CJPAT-like" data sequence. The CJPAT-like data sequence is identical to the 8B10B CJPAT data sequence of the IEEE 802.3ae standard, except for lane-to-lane differences (such as start-up, preamble, CRC, and IPG sequences). The overall characteristics of the CJPAT-like data sequence are relatively similar to the actual 8B10B CJPAT data sequence.

As exemplified in distribution 1800, the patterns 001110 and 110001 were observed in both the even 8B10B CJPAT test sequence and the odd 8B10B CJPAT test sequence. Furthermore, the 2 modes are also roughly equally distributed in the two sequences. The probability of observing the pattern 001110 is 7.340% in the even sequence and 7.394% in the odd pattern. The probability of observing the pattern 110001 is 7.394% in the even sequence and 7.394% in the odd pattern. Also, there is a transition between the last two bits for both modes. Thus, in certain embodiments, method 1400 may be utilized to select these data sequences as filter patterns, and adaptive control actions may be applied only when these filter patterns are observed. With these filter modes, the negative impact of duty cycle distortion can be reduced. Furthermore, the control behavior for 8B10B CJPAT data sequences can be consistent with the control behavior for fully randomized data sequences.

It should be noted that in certain embodiments, an equalizer receiving an 8B10B idle data sequence, an 8B10BCJPAT data sequence, and a random sequence may simultaneously use the filter pattern selected for the 8B10B idle data sequence and for the 8B10B CJPAT data sequence. As can be observed in the 8B10B CJPAT data sequence distribution 1800, the 8B10B idle filter patterns occur disproportionately in the even and odd sequences: 000010, 111101, 000101 and 111010. However, since these unbalanced filter modes are only observed with relatively low probability during reception of 8B10B CJPAT data sequences, using them during reception of 8B10B CJPAT data sequences generally does not lead to bad results for adaptive control. As can be observed in the 8B10B idle data sequence distribution 1600, the use of the 8B10B CJPAT filter patterns 001110 and 110001 during the reception of the 8B10B idle data sequence does not lead to bad results for the adaptive control because in the 8B10B idle data sequence These filter modes have never been observed in .

It should also be noted that (eg, in a second derivative equalizer) multiple independent control parameters may be utilized to adjust the gains applied to the first and second derivative components of the input signal. In this case, a particular one of the observed and equally distributed filter patterns may be more suitable for these independent control parameters when receiving 8B10B CJPAT data sequences.

For 8B10B CJPAT data sequences, well-suited filter patterns for applying gain to the first derivative component may include 110001 and 001110. In a particular embodiment, adaptive control action may thus be applied to the first derivative components only when data values corresponding to these filter modes are observed at the equalizer. In this way, the first derivative components of the signal can be effectively equalized. In an embodiment as described above that also uses the 8B10B idle filter pattern, well-suited filter patterns for applying gain to the first derivative component may also include 000010 and 111101.

To apply gain to the second derivative component (in the context of the 8B10B CJPAT data sequence), well-suited filter patterns may include 000101 and 111010. It should be noted that these filter patterns are the same as those used by the equalizer to apply gain to the second order derivative component in the 8B10B idle data sequence. It should also be noted that these two filter modes occur disproportionately in the even and odd data sequences in the 8B10B CJPAT data sequence. However, since these unbalanced filter patterns are only observed with relatively low probability, their use during reception of 8B10B CJPAT data sequences should not lead to bad results for adaptive control.

16 is a table 1900 illustrating an example gain control scheme associated with adjusting gains applied to unchanged, first derivative, and second derivative components of an input signal using the example filter pattern derived from FIG. 15 . The input signal can be, for example, an 8B10B CJPAT data signal, another (quasi) periodic signal (where the filter patterns of FIG. 15 are approximately equally distributed), or a well randomized signal. Each row 1902 corresponds to a particular value pattern for which a particular adaptive equalizer control action is performed. Each data pattern in these rows 1902 corresponds to one of the selected filter patterns described above in connection with FIG. 15 .

Column 1910 includes patterns for sampled data and boundary values, where values can be high ("1") or low ("0") values. Column "D0" contains the zeroth sampled data value of the output signal, column "D1" contains the first sampled data value of the output signal, column "D2" contains the second sampled data value of the output signal, and column "D3" contains the The third sampled data value, column "D4" contains the fourth sampled data value of the output signal, column "D5" contains the fifth sampled data value of the output signal, column "E4" contains the the boundary value of . As can be observed, in each pattern a transition occurs between the data values of columns "D4" and "D5".

It should be noted that the pattern of values in each row 1902 may be sampled by sampler 104 and sent to adaptive controller 102 . Adaptive controller 102 may compare the sampled values to one or more predetermined filter patterns. In particular embodiments, when a match is detected, adaptive controller 102 may take an associated set of one or more adaptive equalizer actions, as described herein.

It should also be noted that in certain embodiments, adaptive controller 102 may receive a greater number of values than illustrated, including, for example, boundary values between data values in columns "D0" through "D4" . Alternatively, as discussed above, the adaptive controller 102 may only receive sampled data values and other phase information, and may derive certain boundary values from these data values and other phase information (such as included in column E4 The boundary value of ) (and thus may not be sampled by the sampler 104).

Column 1920 includes an alternative boundary value for each row 1902 at column "E4". For a particular mode, column 1924 includes the particular degree of compensation and adaptive equalizer action associated with the unchanged component of the input signal. Adaptive equalizer action may be controlled in any suitable manner (including, for example, by analyzing specific values). For a particular mode, column 1930 includes the particular degree of compensation and adaptive equalizer action associated with the first derivative component of the input signal. These adaptive equalizer actions may also be controlled in any suitable manner (including, for example, by analyzing specific values). For a particular mode, column 1940 includes the particular degree of compensation and adaptive equalizer action associated with the second derivative component of the input signal. These adaptive equalizer actions may also be controlled in any suitable manner (including, for example, by analyzing specific values).

Modifications, additions, or omissions may be made to the described systems and methods without departing from the scope of the present invention. Components of the systems and methods may be integrated or separated according to particular needs. Additionally, operations of the described systems and methods may be performed by more, fewer, or other components.

A filter pattern may be utilized in certain embodiments to reduce duty cycle distortion and the negative effects of certain (quasi-)periodic signals. As discussed above, the filter pattern may be selected based on a well-balanced representation of the patterns in the set of even and odd sequences of the one or more (quasi-)periodic signals. In certain embodiments, filter modes may be specifically selected for certain predefined signals, such as 8B10B idle signals or 8B10B CJPAT signals. These filter patterns can then be utilized to cause the adaptive control to only perform actions when these filter patterns are detected. The use of filter modes reduces the negative impact of duty cycle distortion during the equalizer receiving a particular predefined, periodic signal for which the filter mode has been specifically selected. However, the use of filter modes can lead to unacceptable results for adaptive equalizer control where the equalizer receives other periodic signals for which the filter mode has not been specifically chosen, since for these other periodic signals These filter patterns may not be well balanced.

One solution to the problem of limited applicability to a selected filter mode is to freeze (disable or not use) the adaptive equalizer control when it cannot be determined that the filter mode is compatible with the incoming signal. For example, the adaptive equalizer control may be frozen for an incoming data sequence that is identified as not being well randomized or not a (quasi) periodic data sequence for selecting the filter mode(s). For incoming data sequences that cannot be identified as compatible or incompatible, the adaptive equalizer can additionally or alternatively be frozen. For example, the adaptive equalizer may be frozen for a seemingly well randomized sequence if it cannot be determined whether an incompatible (quasi) periodic sequence is included in the seemingly well randomized sequence.

Temporarily freezing the adaptive equalizer control is acceptable because the channel characteristics are unlikely to change in the short term. However, freezing the equalizer control for a relatively long period of time may be disadvantageous because of changes in channel characteristics affecting inter-symbol interference. For example, environmental changes such as temperature drift or cable movement may occur that affect inter-symbol interference. If the channel characteristics change thereby affecting inter-symbol interference, adaptive control of the equalizer may be required to compensate for the changed signal attenuation. Thus, freezing the adaptive control for long periods of time while waiting for a data sequence compatible with the selected filter pattern may be disadvantageous in certain situations.

A second solution is to choose a useful set (or list) of filter patterns that, when applied in a balanced manner by the equalizer control, is compatible with any (quasi)periodic data signal compatible. In a particular embodiment, these filter patterns do not necessarily depend on their distribution in a particular (quasi-)periodic signal. Therefore, one or more filter modes in this list may appear unequally in the even and odd sequences of a particular (quasi) periodic data signal; however, for the various filter modes which may be unequally distributed A balanced application of will cancel out the deviation of the filter modes that are not equally distributed. A balanced application would result in even and odd modes being observed approximately equally and acting approximately equally, canceling their adaptive bias and reducing duty cycle distortion and the negative impact of any type of incoming (quasi) periodic signal.

In addition to counteracting adaptive deviations due to duty cycle distortion, balanced application of filter patterns can provide for any (quasi)periodic Consistent results for adaptive control on sexual data or well-randomized data. In other words, if the application to the filter pattern is unbalanced, the adaptive control results strongly towards the dominant filter pattern that may vary in various (quasi)periodic or well-randomized data sequences. Deviation, therefore, the adaptive control result will depend on the incoming data sequence. For example, if the incoming data is low frequency biased, the adaptive control will deviate towards the low frequency mode, so the adaptive control result may be high frequency biased. If the incoming data is high-frequency biased, the adaptive control will deviate to the high-frequency mode, so the adaptive control result may be low-frequency biased. If the application of the filter modes is balanced, the adaptive control acts on each filter mode with approximately equal probability, so that for any (quasi) periodic data or well randomized data, the adaptive control results will be become consistent.

In certain embodiments, during operation of the equalizer adaptive control, a list of useful filter modes may be generated initially and then remain unchanged (ie, "fixed"). If the list includes multiple six-bit filter patterns, the list may include all possible variants of the six-bit pattern. Alternatively, the list may include all possible variations of the six-bit pattern with data transitions between certain consecutive two data bits (eg, the last two data bits). In yet another alternative embodiment, the list may only include a subset of all possible variations of the six-bit pattern, and the generator of the list may determine that this particular subset is useful. In any event, the adaptive control may cycle through the fixed list of useful filter modes in any suitable manner. For example, adaptive control may cycle through the fixed list as discussed below in connection with FIGS. 20-22.

Although in certain embodiments a fixed list may be used, in alternative embodiments it may be advantageous to use a dynamic list which may be adapted to the incoming sequence. In certain embodiments, the use of a dynamic list that can be adapted to the incoming sequence can increase the frequency of adaptive control actions to more quickly account for changing channel characteristics. The adaptive control may cycle through the dynamic list in any suitable manner. For example, the adaptive control may cycle through the fixed list as discussed below in connection with FIGS. 20-22. It should be noted that in certain embodiments, this equalizer adaptive control may be constantly enabled while using a fixed or dynamic list. It should also be noted that if there is more than one independent control parameter, separate (fixed or dynamic) useful filter pattern lists may be used for each independent control parameter in certain embodiments.

On the other hand, considering the consistency of adaptive control results in various (quasi-)periodic data or well-randomized data, a fixed list may be more beneficial than a dynamic list, which may suffer due to dynamically changing filter mode list while compromising some consistency of the adaptive control results, while the fixed list does not compromise any consistency of the adaptive control results by sticking to the fixed filter mode list.

FIG. 17 is a flowchart illustrating an example method 2000 for dynamically generating a list of useful filter patterns in accordance with certain embodiments of the invention. Method 2000 may be performed, for example, to update the list of useful filter patterns to include useful patterns observed in incoming sequences, and to remove patterns that are no longer useful. Method 2000 begins at step 2010 where a new list of useful filter patterns is used. In certain embodiments, the new list of useful filter patterns may be used in a balanced manner, as discussed below in connection with FIGS. 20 and 21 . Additionally, as discussed below in connection with FIG. 22, undetected filter patterns may be skipped.

At step 2020, the incoming sequence(s) are monitored for data patterns so that useful and undesired data patterns can be detected. In a particular embodiment, only data patterns of a certain bit size (corresponding to the size of the applied filter pattern) are monitored. A useful data pattern may include, for example, a data pattern frequently observed in the incoming sequence(s) and a data pattern comprising at least one transition between successive data values in the pattern. In certain embodiments, it may also be that a pattern is only useful if a transition occurs between certain two data values in the data pattern, such as the last two data values. The data pattern may also be useful, for example, if it increases the sensitivity of the controlled parameter to boundary values. For example, for controlling the gain of the first derivative component of an analog second derivative equalizer, a data pattern in which the data value 1.5 bits before the boundary is the same as the data value 2.5 bits before the boundary may be useful, while For controlling the gain of the second derivative component of an analog second derivative equalizer, a data pattern in which the data values 1.5 bits before the boundary differ from the data values 2.5 bits before the boundary may be useful. Unhelpful patterns may include unobserved or rarely observed patterns, patterns that do not include at least one transition between successive data values in the pattern, or patterns that reduce the sensitivity of the controlled parameter to boundary values. For example, a data pattern with a different data value 1.5 bits before a boundary than 2.5 bits before that boundary may be useless for controlling the gain of the first derivative component of an analog second derivative equalizer, while A data pattern in which the data value 1.5 bits before the boundary is the same as the data value 2.5 bits before the boundary may be useless for controlling the gain of the second derivative component of an analog second derivative equalizer. These modes may be useless since they do not increase the frequency of adaptive control actions (which is the purpose of using a dynamic list), or do not contribute effectively to adaptive control. After being detected, the useful patterns can be collected in a list, or stored. In certain embodiments, the useless patterns may also be collected in a list, or the useless patterns may be stored.

In step 2030, a determination is made as to whether enough incoming sequence(s) have been monitored. If not enough incoming sequence(s) have been monitored, the method returns to step 2020 . If enough incoming sequence(s) have been monitored, the method proceeds to step 2040 . For example, sufficient incoming sequence(s) may have been monitored after a certain number or type of useful data patterns have been detected or after a certain amount of time has passed.

At step 2040, the list of useful filter patterns is updated, eg, with the assembled list of useful patterns detected in the incoming data sequence(s). In certain embodiments, one or more (or all) useful patterns detected in the incoming data sequence(s) may be added to or replaced by the list of useful filter patterns. Alternatively, the list of useful filter patterns may already include the detected patterns, so it is not necessary to modify the list of useful filter patterns to include the detected patterns. In either case, useless filter patterns can be deleted from the list of useful filter patterns. In certain embodiments, the compiled list of detected useless patterns may also be deleted. After updating the list of useful filter patterns, the method returns to step 2010 where the new list of useful filter patterns is used.

FIG. 18 is a flowchart illustrating another example method 2100 for dynamically generating a list of useful filter patterns in accordance with certain embodiments of the invention. Similar to method 2000, method 2100 may be performed to update the list of useful filter patterns to include useful patterns observed in incoming sequences and to remove patterns that are no longer useful. Method 2100 can also create separate dynamic lists for even and odd data sequences. Method 2100 may also optionally edit these lists such that neither even nor odd sequences dominate the adaptive control. Doing so will reduce the negative impact of duty cycle distortion.

Method 2100 begins at step 2110, where a new list of useful filter patterns is used. In certain embodiments, the new list of useful filter patterns may be used in a balanced manner, as discussed below in connection with FIGS. 20 and 21 . As discussed below in connection with FIG. 22, the new filter pattern list may also be used in conjunction with timeout detection to skip undetected filter patterns after a certain period of time.

At step 2120, the even and odd data sequences (either starting with an even bit followed by odd, even, odd, etc., or starting with an odd bit followed by even, odd, even etc.), and detect useful and useless data patterns in each data series. A useful data pattern may include, for example, a data pattern that is frequently observed in an incoming data sequence and a data pattern that includes at least one transition between successive data values in the pattern. In certain embodiments, it may also be that a data pattern is only useful if a transition occurs between certain two data values in the data pattern. The data pattern may also be useful, for example, if it increases the sensitivity of the controlled parameter to boundary values. For example, for controlling the gain of the first derivative component of an analog second derivative equalizer, a data pattern in which the data value 1.5 bits before the boundary is the same as the data value 2.5 bits before the boundary may be useful, while For controlling the gain of the second derivative component of an analog second derivative equalizer, a data pattern in which the data values 1.5 bits before the boundary differ from the data values 2.5 bits before the boundary may be useful. Unhelpful patterns may include unobserved or rarely observed patterns, patterns that do not include at least one transition between successive data values in the pattern, or patterns that reduce the sensitivity of the controlled parameter to boundary values. For example, a data pattern with a different data value 1.5 bits before a boundary than 2.5 bits before that boundary may be useless for controlling the gain of the first derivative component of an analog second derivative equalizer, while A data pattern in which the data value 1.5 bits before the boundary is the same as the data value 2.5 bits before the boundary may be useless for controlling the gain of the second derivative component of an analog second derivative equalizer. The detected useful patterns can be collected or stored in separate lists for even and odd data sequences, respectively. In certain embodiments, the garbage patterns may also be collected in separate lists for even and odd data sequences or stored separately.

At step 2130, a determination is made whether enough incoming even and odd sequences have been monitored. If not enough sequences have been monitored, the method returns to step 2120. If enough sequences have been monitored, the method proceeds to step 2140 . For example, sufficient incoming sequences may have been monitored after a certain number or type of useful data patterns have been detected or after a certain amount of time has passed.

At step 2140, among those detected useful patterns, the patterns that only appear in one of the even sequence and the odd sequence are ignored. In certain embodiments, useful patterns detected in an even data sequence may be compared to useful patterns detected in an odd data sequence, and those patterns observed in only one of the even and odd sequences Removed from consideration as a filter pattern in the new filter pattern list. For example, these patterns can be disregarded by removing them from the assembled even or odd list of useful patterns. In certain embodiments, these patterns may be placed in the even or odd list of the assembled detected garbage patterns.

At step 2150, the list of useful filter patterns is updated. In a particular embodiment, one or more of the assembled detection pattern lists may be removed from the assembled list of detection patterns after those patterns that occur only in one of the even and odd sequences have been removed. (or all) useful patterns are added to or replace the list of useful filter patterns. Alternatively, the list may already include the detected patterns, so the list does not have to be modified to include the detected patterns. In either case, useless filter patterns can be deleted from the list of useful filter patterns. In certain embodiments, even or odd lists of collected useless detection patterns may also be deleted. After updating the list of useful filter patterns, the method returns to step 2110 where the new list of useful filter patterns is used.

FIG. 19 is a flowchart illustrating yet another example method 2200 for dynamically generating a list of useful filter patterns in accordance with certain embodiments of the invention. Similar to methods 2000 and 2100, method 2200 may update the list of useful filter patterns to include useful patterns observed in incoming sequences and remove patterns that are no longer useful. Similar to method 2100, method 2200 can also create separate dynamic lists (i.e., even and odd lists) for data sequences starting with even and odd bits, and edit these lists so that neither even nor odd Adaptive control dominates. Method 2200 may do this by counting the number of patterns in the even list and the number of patterns in the odd list, comparing the two numbers, and removing patterns from the list with more patterns until the number of patterns in the even list The number of patterns in is equal to the number of patterns in the odd list. In this way, the effect of duty cycle distortion can be reduced. Also, the method 2200 will be relatively less dependent on the incoming data sequence.

Method 2200 begins at step 2210, where a new list of useful filter patterns is used. In certain embodiments, this new list of useful filter patterns may be used in a balanced manner, as discussed below in connection with FIGS. 20 and 21 . As discussed below in connection with FIG. 22, the new filter pattern list may also be used in conjunction with timeout detection to skip undetected filter patterns after a certain period of time.

At step 2220, the data pattern in the even data sequence (which starts with an even bit followed by odd, even, odd, etc.) and the odd data sequence (which starts with an odd bit followed by even, odd , even bits, etc.) and detect useful and unwanted patterns in each data sequence. A useful data pattern may include, for example, a data pattern that is frequently observed in an incoming data sequence and a data pattern that includes at least one transition between successive data values in the pattern. In certain embodiments, it may also be that a data pattern is only useful if a transition occurs between two particular data values in the data pattern, such as between the last two data values. The data pattern may also be useful, for example, if it increases the sensitivity of the controlled parameter to boundary values. For example, for controlling the gain of the first derivative component of an analog second derivative equalizer, a data pattern in which the data value 1.5 bits before the boundary is the same as the data value 2.5 bits before the boundary may be useful, while A data pattern in which the data values 1.5 bits before the boundary differ from the data values 2.5 bits before the boundary may be useful for controlling the gain of the second derivative component of an analog second derivative equalizer. Unhelpful patterns may include unobserved or rarely observed patterns, patterns that do not include at least one transition between successive data values in the pattern, or patterns that reduce the sensitivity of the controlled parameter to boundary values. For example, a data pattern with a different data value 1.5 bits before a boundary than 2.5 bits before that boundary may be useless for controlling the gain of the first derivative component of an analog second derivative equalizer, while A data pattern in which the data value 1.5 bits before the boundary is the same as the data value 2.5 bits before the boundary may be useless for controlling the gain of the second derivative component of an analog second derivative equalizer. The detected useful patterns may be collected or otherwise stored in separate lists for even and odd data sequences ("even" list and "odd" list), respectively. In certain embodiments, the garbage patterns may also be collected or stored in separate lists for even and odd data sequences, respectively.

At step 2230, a determination is made whether enough incoming even and odd sequences have been monitored. If not enough sequences have been monitored, the method returns to step 2220. If enough sequences have been monitored, the method proceeds to step 2240 . For example, sufficient incoming sequences have been monitored after a certain number or type of useful data patterns have been detected or after a certain amount of time has passed.

At step 2240, the even list is compared to the detected patterns in the odd list, counting the number of patterns that only appear in the even list and the number of patterns that only appear in the odd list. At step 2250, a determination is made as to whether the number of patterns appearing only in the even list is the same as the number of patterns appearing only in the odd list. If these quantities are different, the method proceeds to step 2260. If these numbers are the same, the method proceeds to step 2270.

At step 2260, if the number of patterns that only appear in the even list is different than the number of patterns that only appear in the odd list, then remove a pattern from the list with more patterns. In particular embodiments, any suitable pattern may be removed from the list of more patterns in any suitable manner. For example, in certain embodiments, patterns that occur most frequently in even or odd data sequences may be removed. After the pattern has been removed from the list with more patterns, the method returns to step 2240 and the number of patterns that only appear in the even list is counted and compared to the number of patterns that only appear in the odd list.

At step 2270, if the number of patterns appearing only in the even list is the same as the number of patterns appearing only in the odd list, the list of useful filter patterns is updated using, for example, the edited list of detection patterns. In certain embodiments, one or more (or all) useful patterns in the edited list of detection patterns may be added to or replaced in the list of useful filter patterns. Alternatively, the list of useful filter patterns may already include the detected patterns, so the list need not be modified to include the detected patterns. In either case, useless filter patterns can be deleted from the list of useful filter patterns. In certain embodiments, even or odd lists of collected useless detection patterns may also be deleted. After updating the list of useful filter patterns, the method returns to step 2210 where the new list of useful filter patterns is used.

Modifications, additions, or omissions may be made to the systems and methods without departing from the scope of the present invention. The components of the method can be integrated or separated according to specific needs. Additionally, the operations of the methods may be performed by more, fewer, or other components.

As discussed above, the list of useful filter patterns can be fixed or dynamic. The equalizer control can use either type of filter mode in the list in a balanced manner to reduce the negative effects of duty cycle distortion. Using filter modes in a balanced manner generally means using each filter mode in the filter mode list equally or giving equal weight or selection probability to each filter mode in the list.

FIG. 20 is a flowchart illustrating an example method 2300 for using filter modes in a balanced manner, according to certain embodiments of the invention. Method 2300 begins at step 2310 where a filter mode is selected from a list of available filter modes. The list of useful filter patterns can be fixed or dynamic. A filter mode may be selected from the list of available filter modes in any suitable manner. In certain embodiments, filter modes may be selected sequentially from a list. In an alternative embodiment, the filter pattern may be randomly selected from the list with equal probability. It should be noted that the filter pattern may for example comprise a six-bit pattern and there may be a transition between certain two bits such as the last two bits.

At step 2320, the incoming signal's data sequence(s) may be monitored for the selected filter mode. At step 2330, if the selected filter pattern is not detected, monitoring of the incoming signal's data sequence(s) may continue. If the selected filter mode is detected, the method proceeds to step 2340 .

At step 2340, appropriate control actions are taken to control the equalizer parameters. In certain embodiments, the detected pattern data and boundary value information may be analyzed and appropriate control actions taken, as discussed above. Example methods for interpreting output signal values are discussed above in connection with FIGS. 5 , 7 and 9 . After analyzing the output signal values, the equalizer can apply appropriate control actions to the signal. In another embodiment of the present invention, the adaptive control action taken at step 2340 may be any suitable adaptive control action employing various conventional adaptive control algorithms. For example, the adaptive control action at step 2340 may be based on conventional adaptive control algorithms such as least mean square (LMS) algorithm, sign-sign least mean square (SS-LMS) algorithm, zero forcing (ZF) algorithm, and the like. These conventional adaptive control algorithms generally require that the incoming data be well randomized and may produce unacceptable results if the incoming data is (quasi) periodic. In a particular embodiment, a balanced application of adaptive control actions utilizing filter patterns is such that these conventional adaptive control algorithms can provide consistent adaptive results over a wide variety of (quasi)periodic and well randomized data sequences . Since these conventional adaptive control algorithms do not necessarily require data transitions to take adaptive control actions, the filter patterns do not necessarily include data transitions in certain embodiments. After the control action is applied, the method returns to step 2310 where a new filter mode is selected. In this way, the filter pattern is used in a balanced manner, reducing the negative impact of duty cycle distortion and providing consistent adaptation results over a wide variety of (quasi) periodic and well randomized data sequences.

FIG. 21 is a flowchart illustrating another example method 2400 for using filter modes in a balanced manner, according to certain embodiments of the invention. In method 2400, while monitoring the filter patterns in the list, marking or identifying those filter patterns that have been detected and for which adaptive action has been taken, and then no longer monitoring these filter patterns, And these flags are cleared when all filter patterns have been detected. In this way, the filter patterns are used in a balanced manner, reducing the negative impact of duty cycle distortion.

Method 2400 begins at step 2410 . At step 2410, all flags are cleared such that none of the patterns are flagged. The absence of a flag associated with a pattern indicates that the incoming data sequence(s) can be monitored for that pattern (since the pattern has not been detected). A flag indicates that the incoming data sequence(s) can no longer be monitored for the flag's corresponding pattern (because the pattern has been detected). It should be noted that although flags are used in this embodiment, in alternative embodiments any suitable technique for indicating when a certain pattern has been detected may be implemented. It should also be noted that the list of useful filter patterns can be fixed or dynamic.

At step 2420, the incoming data sequence(s) are monitored for those filter patterns that have not been flagged. Thus, immediately after all flags are cleared, the incoming data sequence(s) are monitored for all filter patterns in the list of useful filter patterns. In certain embodiments, all unmarked filter patterns can be monitored simultaneously. As filter patterns are detected, activated and marked, the incoming data sequence(s) are monitored for fewer filter patterns (unmarked filter patterns).

At step 2430, a determination is made whether any monitored filter patterns have been detected in the incoming data sequence(s). If a filter pattern is not detected, the incoming data sequence(s) may continue to be monitored for these filter patterns, and the corresponding flags for each filter pattern remain unchecked. If a filter pattern is detected, the method proceeds to step 2440.

At step 2440, appropriate control actions are taken to control the equalizer parameters. In certain embodiments, data and boundary value information of detected patterns may be analyzed and control actions taken. Example methods for interpreting output signal values are discussed above in connection with FIGS. 5 , 7 and 9 . After analyzing the output signal values, the equalizer can apply appropriate control actions to the signal. In alternative embodiments, the adaptive control action taken at step 2440 may be any suitable adaptive control action employing various conventional adaptive control algorithms. For example, the adaptive control action at step 2440 may be based on algorithms such as Least Mean Square (LMS), Sign-Symbol Least Mean Square (SS-LMS), or Zero-Forcing (ZF) algorithms, among others. These conventional adaptive control algorithms generally require the incoming data to be well randomized and may not yield good results if the incoming data is (quasi) periodic. The balanced application of adaptive control actions with filter patterns enables these conventional adaptive control algorithms to provide consistent adaptive results over a wide variety of (quasi) periodic and well randomized data sequences. After a filter pattern is detected (and optionally after a control action is taken), the detected filter pattern is flagged.

At step 2450, a determination is made whether all filter patterns in the useful filter pattern list have been marked. If not, the method returns to step 2420 and the incoming data sequence(s) are monitored for those filter patterns that have not been flagged. If all filter patterns in the useful filter pattern list have been flagged, the method proceeds to step 2410 where all flags are cleared. In this way, the filter pattern is used in a balanced manner, reducing the negative impact of duty cycle distortion and providing consistent adaptation results over a wide variety of (quasi) periodic and well randomized data sequences.

Modifications, additions, or omissions may be made to the systems and methods without departing from the scope of the present invention. Components of the systems and methods may be integrated or separated according to particular needs. Additionally, the operations of the systems and methods may be performed by more, fewer or other components.

As discussed above, filter patterns can be used in a balanced manner to reduce the negative impact of duty cycle distortion and to provide consistent adaptation results between various (quasi)periodic and well randomized data sequences , and an example method for using filter modes in a balanced manner is discussed in conjunction with FIGS. 20 and 21 . However, when making a determination regarding whether a filter pattern has been detected in step 2330 of method 2300 or step 2430 of method 2400, these methods stall if, for example, the desired filter pattern is not detected. . In other words, if a particular filter pattern is not detected, no other adaptive action will be taken. Freezing the adaptive control in this way, for example for a short period, may not be disadvantageous since channel characteristics are unlikely to change. However, even in the short term and especially in the long term, forcing the method to skip undetected filter patterns after a certain period may allow the equalizer to adapt more quickly to changing conditions. By enabling more frequent adaptive control actions, skipping undetected filter patterns may prevent adaptive control from stalling when channel characteristics change.

FIG. 22 is a flowchart illustrating an example method 2500 for skipping undetected filter patterns after a certain period of time in accordance with certain embodiments of the invention. In method 2500, a timeout may be detected after a certain period of time for which the filter pattern is not detected in the incoming data sequence(s). After detecting the timeout, the filter mode may be skipped (eg, in step 2330 of method 2300) or flagged (eg, in step 2430 of method 2400 above).

It should be noted that timeout detection can be used in conjunction with a fixed or dynamic list of useful filter patterns. However, fewer timeout detections occur when using a dynamic list than when using a fixed list, because the filter patterns in the dynamic list are updated based on their frequency in the incoming sequence. In other words, if patterns that are frequently observed in the incoming sequence are included in the list of useful filter patterns and patterns that are not frequently observed are removed, there will be fewer chances of detecting a timeout. Method 2500 can still be used in conjunction with dynamic lists to compensate for any delay in the update process to the dynamic list after changing the incoming sequence.

Method 2500 begins at step 2510 where a timer is reset. In conjunction with method 2300, the timer may be reset after the next filter mode is selected at step 2310. In connection with method 2400 , the timer may be reset, for example, after initially clearing all flags at step 2410 and/or after detecting a filter pattern at step 2430 . A timer may be set to a period after which the filter mode (or filter modes are skipped in method 2400) is to be skipped. The time period set by the timer may include any suitable time period.

At step 2520, a determination is made whether a filter pattern has been detected in the incoming data sequence(s). If a filter pattern has been detected, the method returns to step 2510 and the timer is reset. If no filter pattern has been detected, the method proceeds to step 2530 .

At step 2530, a determination is made whether a timeout has occurred. A timeout is when the time set by the timer has run out. If the timeout has not occurred, the method returns to step 2520. If a timeout has occurred, the method proceeds to step 2540.

After a timeout occurs, non-detected filter pattern(s) are skipped at step 2540 . In conjunction with method 2300, the filter mode is skipped and at step 2310 the next filter mode is selected. In conjunction with method 2400, all remaining unflagged filter patterns are skipped (eg, they may all be flagged) and all flags are cleared at step 2410 so that the process can be restarted. In a particular embodiment, any skipped mode(s) may be removed from the list of useful filter modes (to prevent the skipped mode(s) from stalling the adaptive equalizer again). Method 2500 then returns to step 2510 where the timer is reset. In this way, undetected filter patterns can be skipped and adaptive control actions can be taken more frequently, preventing adaptive control from stalling for undetected filter patterns.

On the other hand, in certain embodiments, it may be more beneficial for the consistency of adaptive control results in various (quasi-)periodic data or well-randomized data not to perform detection of timeouts, since the detection of timeouts detection may compromise some consistency of the adaptive control results by skipping undetected filter modes, while not performing the detection does not compromise any of the adaptive control results by sticking to all filter modes even if stalls occur consistency. In certain embodiments, pauses may not be a problem, or may even be the most preferred scheme for certain data sequences such as the continuous 0101 data sequence, since such highly periodic data sequences lack spectrum in the frequency domain and therefore Might not include enough information for adaptive control. If the adaptive control does not stall for highly periodic data sequences such as continuous 0101, then the control parameters may drift to poor values. Therefore, in certain embodiments, pausing may be the most popular scheme for such highly periodic data sequences. Not performing detection of timeouts may allow stalling for such highly periodic data sequences.

Modifications, additions, or omissions may be made to the systems and methods without departing from the scope of the present invention. Components of the systems and methods may be integrated or separated according to particular needs. Additionally, the operations of the systems and methods may be performed by more, fewer or other components.

Much of the above discussion has focused on a type of signal distortion known as residual intersymbol interference. Another type of signal distortion that occurs in electrical communications is a residual DC offset in the signal. If not cancelled, ie, compensated for, the residual DC offset degrades the input sensitivity at the receiver. Therefore, it is beneficial to cancel the residual DC offset at the receiver. Canceling the residual dc offset can be especially beneficial if the receiver has an analog front-end circuit such as an equalizer or a limiting amplifier before its decision circuit, since these components add offset to the signal.

Referring again to FIGS. 1-3 , in addition to intersymbol interference, signals transmitted over communication channel 30 are subject to DC offset distortion, and this DC offset distortion is further enhanced at receiver equalizer 42 . Receiver equalizer 42 may apply DC offset compensation (ie, correction) to the received input signal to counteract the DC offset exhibited by the signal. Receiver logic 47 may then analyze the conditioned output signal for residual DC offset. In particular, sampler 104 may receive equalizer output signal 46 (conditioned output signal) and a clock signal. Sampler 104 may then sample the output signal at particular points determined by the clock signal to generate data values and boundary values. Sampler 104 may forward these data and boundary values to offset controller 106 for appropriate analysis (as described below). Based on this analysis, offset controller 106 of receiver logic 47 and equalizer 42 may correct for DC offset distortion in the incoming input signal.

23A, 23B, and 23C illustrate several examples of clock signals in contrast to equalizer output signal 46 exhibiting various types of residual DC offset. In particular embodiments, the sampler 104 may receive an equalizer output signal 46 such as those illustrated in these figures and sample the equalizer output signal 46 according to a 2x oversampled clock and data recovery (CDR) scheme. In this scheme, sampler 104 may sample equalizer output signal 46 twice per data bit period (which may be defined by a clock signal). For one data bit period, the sampler 104 may sample the equalizer output signal 46 once at points in the equalizer output signal 46 that should correspond to data values, and at points in the equalizer output signal 46 that should correspond to boundary values. The equalizer output signal 46 is sampled once at the point . Sampler 104 may then forward these data values and boundary values to offset controller 106 . Based on an analysis of particular data values and boundary values, offset controller 106 may make adjustments to the DC offset compensation applied to the signal received by equalizer 42 as described further below. It should be noted that in certain embodiments, the same data values and boundary value information forwarded to offset controller 106 may also be forwarded to adaptive controller 102 and used in conjunction with adaptive gain control, as described above. The above data value and boundary value information.

FIG. 23A illustrates an example clock signal 2600 in comparison to an equalizer output signal 46 that exhibits no residual DC offset. Example 2600 is similar to example 200 described above in connection with FIG. 4A and thus will not be described in detail. However, it should be noted that in signals that exhibit no residual DC offset (as in example 2600), as discussed above, each boundary value between two consecutive data values that includes a transition (e.g. Boundary values at E2, E3, and E4) randomly include either high or low values (illustrated as "X"). For such signals, the offset controller 106 may randomly adjust the DC offset compensation applied to the input signal up or down since the DC offset distortion is fully compensated or absent. If the number of up and down adjustments is substantially equal, the DC offset compensation applied to the input signal remains on average at the same level. If the number of up and down adjustments is not approximately equal, the DC offset compensation applied to the input signal will drift slightly from the initial level. This drift in the DC offset compensation level produces slight DC offset distortion. As exemplified below, an equalizer receiver can detect this distortion and correct the DC offset compensation back to the average original level.

FIG. 23B illustrates an example clock signal 2650 in contrast to an equalizer output signal 46 exhibiting a positive residual DC offset. An equalizer output signal 46 exhibiting a positive residual DC offset drifts upwards (as in the example diagram) relative to a signal exhibiting no residual DC offset. Also, the value of the boundary value (eg E2 ) or the boundary value (eg E3 ) after the high pulse (eg the pulse at D3 ) will likely be the same as the data value at that pulse (eg D3 ). The values of the boundary values before and after the low pulse will likely be different (opposite) than the data value at that pulse. Accordingly, as described further below, the offset controller 106 may reduce the DC offset compensation applied to the input signal to counteract the positive residual DC offset when analyzing certain data values and boundary value(s). It should be noted that in certain embodiments and as described below, the offset controller 106 may not be able to cancel the positive residual DC offset exhibited by the output signal until a transition (eg, between D2 and D3) occurs.

Figure 23C illustrates an example clock signal 2700 in comparison to an equalizer output signal 46 exhibiting a negative residual DC offset. An equalizer output signal 46 exhibiting a negative residual DC offset is drifted downward (as in the example figure) relative to a signal exhibiting no residual DC offset. Also, the value of the boundary value (eg E2 ) or the boundary value (eg E3 ) after the high pulse (eg the pulse at D3 ) will likely be different (opposite) than the data value at that pulse. The value of the boundary value before and after the low pulse will likely be the same as the data value at that pulse. Accordingly, as described further below, the offset controller 106 may increase the DC offset compensation applied to the input signal to counteract the negative residual DC offset when analyzing certain data values and boundary value(s). It should be noted that in certain embodiments and as described below, the offset controller 106 may not be able to cancel the negative residual DC offset exhibited by the output signal until a transition (eg, between D2 and D3) occurs.

24 is a flowchart illustrating a method 2800 for interpreting output signal values to cancel residual DC offsets in accordance with certain embodiments of the invention. Method 2800 begins at step 2810 where output signal 46 is sampled using a clock signal. As described above in connection with FIG. 3, the output signal 46 may be the output of an equalizer, and the output signal may be sampled according to a clock signal.

In certain embodiments, the output signal may be sampled at reference data points and boundary points determined by the clock signal. Alternatively, the output signal may not be sampled at boundary points, but boundary values corresponding to these non-sampled points may be derived. In certain embodiments, offset controller 106 may derive boundary values based on sampled data values and other phase information (ie, whether the phase of the output signal is early or late). For example, if the phase of the output signal is early, the offset controller 106 may determine that the high or low value of the boundary value is the same as the high or low value of the data value immediately preceding the boundary value. If the phase of the output signal is late, the offset controller 106 may determine that the high or low value of the boundary value is the same as the high or low value of the data value immediately following the boundary value.

At step 2820, after the output signal is sampled, the sampled data values may be analyzed to determine whether transitions have occurred in the values. At step 2830, if no transition is detected, the method returns to step 2820. If a transition is detected between consecutive data values, the method proceeds to step 2840 . It should be noted that in certain embodiments transitions may be detected by directly comparing received data values to each other. In an alternative embodiment, transitions may be detected by comparing received data values and boundary values to a predefined pattern of values that includes transitions (and corresponds to specific offset canceling actions). It should also be noted that in certain embodiments, offset cancellation actions may be performed after only one transition is detected.

If a transition is detected, then at step 2840 the value (high or low) of the boundary value between the data values comprising the transition is identified. At step 2850, if the boundary value is high, the method proceeds to step 2860 and negative offset cancellation action is taken to adjust the signal down (since the residual DC offset is positive). If the margin is low, the method proceeds to step 2870 and positive offset cancellation action is taken to adjust the signal up (since the residual DC offset is negative). In certain embodiments, boundary values may be identified and offset offsetting actions taken by comparing the boundary values to predefined patterns (which correspond to specific offset offsetting actions).

It should be noted that in certain embodiments, steps 2820 through 2870 may be performed by offset controller 106 and the DC offset cancellation action may be applied, eg, using variable gain amplifier 116 . Also, in certain embodiments, if DC offset compensation is applied to more than one signal path (eg, to path 101 in example equalizer 42), the applied DC offset compensation can be adjusted and fixed in one path DC offset compensation for other paths. In an alternative embodiment, the independent control variables may be mapped to multiple paths using a specific function, and DC offset compensation may be applied to these paths according to the mapping process. Alternatively, DC offset compensation may be adjusted independently for each path, as discussed further below in connection with FIGS. 30-40 .

FIG. 25 is a table illustrating an example DC offset control scheme 2900 associated with the method 2800 of FIG. 24 . Each row 2902 corresponds to a particular value pattern for which a particular offset canceller action is performed. Column 2910 includes the high and low values ("1" or "0") for each of the data and boundary values in the sampled series of data and boundary values. Column "D1" includes first sampled data values of the output signal, column "D2" includes second sampled data values of the output signal, and column "E1" includes boundary values between the first and second data values. These values are similar to those illustrated in Figs. 23A to 23C. As can be observed, in each pattern a transition occurs between the data values of columns "D1" and "D2".

It should be noted that the pattern of values in each row 2902 may be sampled by sampler 104 and sent to offset controller 106 . Alternatively, offset controller 106 may only receive sampled data values and other phase information, and may derive certain boundary values (e.g., including those in column E1) from these data values and phase information (thus may not be determined by sampler 104 to sample out).

Column 2912 includes an alternative boundary value for each row 2902 at column "E1". For a particular mode, column 2914 includes a particular residual DC offset level. For a particular mode, column 2916 includes a particular action for offset cancellation settings to compensate for a particular residual DC offset level. Actions for offset cancellation settings may be applied as discussed above in method 2800 .

It should be noted that in certain embodiments, offset controller 106 may receive a stream of sampled values and select an appropriate value from among these values (eg, a boundary value between two data values including a transition). The offset controller 106 can then perform appropriate offset cancellation actions based on the boundary value. Alternatively, offset controller 106 may compare these sampled values to a predefined pattern of values (which correspond to a particular offset canceling action). Based on the specific predefined value pattern to which these sampled values correspond, the offset controller 106 can apply a corresponding offset canceling action.

Modifications, additions, or omissions may be made to the systems and methods without departing from the scope of the present invention. Components of the described systems and methods may be integrated or separated according to particular needs. Additionally, the operations of the systems and methods may be performed by more, fewer or other components.

One challenge that arises from using the output signal value to estimate the residual DC offset is the problem of false lock. False lock problems arise when the clock signal interacts incorrectly with the skew canceller to create a false lock condition. For example, a false-lock condition can arise where the initial residual offset is as high as the input signal amplitude. In the false lock state, the sampling phases of the boundary values and data values are swapped. The offset is also largely moved away from the true center, locking the boundary samples at intersections above or below the true eye opening. The false locking problem distorts the estimation of the residual DC offset using the value of the output signal.

FIG. 26 is a flowchart illustrating a method 3000 for correcting a false lock that occurs during the process of canceling out residual DC offsets, according to certain embodiments of the present invention. Method 3000 corrects the false lock problem by adjusting the DC offset compensation based on the value (high or low) of each boundary value. Thus, unlike method 2800, DC offset compensation may be adjusted based on boundary values between data values having the same value (in addition to being based on boundary values between data values that include transitions). As a result, transitions do not have to be identified in method 3000 before DC offset compensation is adjusted. By adjusting DC offset compensation in this manner, method 3000 can nudge a signal that is in a false lock state out of a false lock state. It should be noted that method 3000 may be similar to method 2800 described above in FIG. 24 (except for steps 2820 and 2830 ).

Method 3000 begins at step 3010 where an output signal is sampled using a clock signal. As described above in connection with FIG. 3, the output signal may be the output of an equalizer, and the output signal may be sampled according to a clock signal. In certain embodiments, the output signal may be sampled at reference data points and boundary points determined by the clock signal. Alternatively, the output signal may not be sampled at boundary points, but boundary values corresponding to these non-sampled points may be derived. It should be noted that at this time, the signal may be in a false lock state.

After sampling the output signal, at step 3020, the value (high or low) of the boundary value can be identified. At step 3030, if the boundary value is high, the method proceeds to step 3040 and a negative offset cancellation action is taken to adjust the signal down. If the boundary value is low, the method proceeds to step 3050 and a positive offset cancellation action is taken to adjust the signal upward. In certain embodiments, boundary values may be identified and offset offsetting actions taken by comparing the boundary values to predefined patterns (which correspond to specific offset offsetting actions).

A signal that is in a false-lock state can be nudged out of the false-lock state by taking offset canceling actions based on any boundary value (ie, whether or not a transition has been identified). Additionally, offset adjustments can also counteract residual DC offsets since some of the boundary values used may occur between consecutive data values including transitions.

FIG. 27 is a table 3100 illustrating an example offset control scheme associated with the method 3000 of FIG. 26 . Each row 3102 corresponds to a particular value pattern for which a particular offset canceller action is performed. Column 3110 includes the high or low value ("1" or "0") of each data and boundary value in the sampled data and boundary value series. Column "D1" includes first sampled data values of the output signal, column "D2" includes second sampled data values of the output signal, and column "E1" includes boundary values between the first and second data values. These values are similar to those illustrated in Figs. 23A to 23C. As can be observed, transitions do not necessarily occur between the data values of columns "D1" and "D2" in each schema.

It should be noted that the pattern of values in each row 3102 may be sampled by sampler 104 and sent to offset controller 106 . Alternatively, offset controller 106 may only receive sampled data values and other phase information, and may derive certain boundary values (e.g., including those in column E1) from these data values and phase information (thus may not be determined by sampler 104 to sample out).

Column 3112 includes the alternative boundary value at column "E1" for each row 3102. For a particular mode, column 3114 includes a particular residual DC offset level. For a particular mode, column 3116 includes the particular action set for the offset offset. Actions for offset cancellation settings may be performed as discussed above in method 3000 .

It should be noted that the specific boundary values in column 3112 are enclosed in parentheses. Boundary values in parentheses are those boundary values that have a different high or low value than the high or low values of the two values immediately surrounding the boundary value. This situation may be atypical in certain embodiments. However, offset canceller action may be taken based on a high or low value of the boundary value in certain embodiments.

Especially when method 3000 is applied to random signals or without resampling techniques (sampling at a lower rate than the data rate), method 3000 can provide an effective solution to the false lock problem. However, if the incoming signal is a (quasi) periodic signal and a resampling technique is used, the method 3000 may not prevent systematic residual offsets from appearing in the signal in some cases. This may be the case, for example, where the resampling period is locked to the period of the periodic signal. Therefore, in certain cases an offset canceller that can correct the mislocking problem and properly adjust for the residual DC offset of (quasi) periodic signals may be useful in the case of resampling techniques.

FIG. 28 is a flow diagram illustrating another method 3200 for correcting a false lock that occurs during the process of canceling out a residual DC offset, in accordance with certain embodiments of the present invention. Method 3200 corrects for false lock problems in periodic signals by first monitoring the data DC imbalance (synonymous with false lock problems) using the output signal value. When an imbalance is detected, DC offset compensation is adjusted based on the detected imbalance. If no imbalance is detected, DC offset compensation is adjusted based only on values (high or low) including those boundary values between consecutive data values that transition (similar to method 2800 described above). Using the method 3200, the data DC imbalance can be controlled within an acceptable range even when the (quasi-)periodic data signal is sampled using resampling techniques.

Method 3200 begins at step 3210 where an output signal is sampled using a clock signal. As described above in connection with FIG. 3, the output signal may be the output of an equalizer, and the output signal may be sampled according to a clock signal. In certain embodiments, the output signal may be sampled at reference data points and boundary points determined by the clock signal. Alternatively, the output signal may not be sampled at boundary points, but boundary values corresponding to these non-sampled points may be derived. In certain embodiments, offset controller 106 may derive boundary values based on sampled data values and other phase information (eg, whether the phase is early or late).

At step 3220, while the output signal is being sampled, the number of low data values (e.g. "0") and the number of high data values (e.g. "1") are counted and the signal is updated while the signal is being sampled. count. In certain embodiments, the number of data values (low and high) in each count may only include a certain number of previously observed data values. In alternative embodiments, the number of data values in each count may include only those data values that were previously observed during a certain period of time. Any suitable counter(s) may store the number of high and low data values observed, and the counter(s) may be updated based on the high or low value of the incoming data value.

At step 3230, the counts of high data values are compared to the counts of low data values, and a determination is made as to whether one type of data value is observed much more frequently than the other type of data value (to determine the signal Whether it is in an incorrectly locked state). Method 3200 proceeds to step 3240 if data values of one type are observed much more frequently (more than 3 times more frequently, by way of example only) than data values of another type. If none of the data values of one type are observed much more frequently than the other type of data value, method 3200 proceeds to step 3270 . In certain embodiments, the difference in the number of data values of each type or the ratio of the number of data values of each type may be compared to a predetermined number or ratio, respectively.

At step 3240, a determination is made as to whether high data values are observed much more frequently than low data values. If high data values are observed much more frequently than low data values, method 3200 proceeds to step 3250 and negative offset cancellation actions are taken to adjust the signal downward. If low data values are observed much more frequently than high data values, then method 3200 proceeds to step 3260 and positive offset cancellation actions are taken to adjust the signal upward. By adjusting the applied DC offset compensation in this manner, a signal that is in a mis-locked state can be nudged out of the false-locked state.

It should be noted that while method 3200 monitors data DC imbalances by counting and comparing output data values, in alternative embodiments output data values and/or boundary values may be counted and compared in a similar manner , to monitor data DC imbalance. The counting of data values and/or limit values can also be evaluated in a similar manner in order to adjust the offset compensation applied to the incoming data signal.

If at step 3230 none of the data values of one type are observed much more frequently than the other type of data value, then method 3200 proceeds to step 3270 . At step 3270, the sampled data values may be analyzed to determine whether a transition has occurred in the values. At step 3280, if no transition is detected, the method returns to step 3210 and the output signal is sampled. If a transition is detected between consecutive data values, the method proceeds to step 3290. It should be noted that in certain embodiments transitions may be detected by directly comparing received data values to each other. In an alternative embodiment, transitions may be detected by comparing received data values and boundary values to a predefined pattern of values that includes transitions (and corresponds to specific offset canceling actions). It should also be noted that in certain embodiments, offset cancellation actions may be performed after only one transition is detected.

If a transition is detected, then at step 3290 the value (high or low) of the boundary value between the data values comprising the transition is identified. At step 3300, if the boundary value is high, the method proceeds to step 3250 and negative offset cancellation action is taken to adjust the signal down (since the residual DC offset is negative). If the margin is low, the method proceeds to step 3260 and positive offset cancellation action is taken to adjust the signal up (since the residual DC offset is negative). In certain embodiments, boundary values may be identified and offset offsetting actions taken by comparing the boundary values to predefined patterns (which correspond to specific offset offsetting actions). Method 3200 then returns to steps 3210 and 3220 to sample the output signal and update the counted numbers of low and high data values.

It should be noted that in certain embodiments, steps 3220 to 3300 may be performed by offset controller 106 and the DC offset cancellation action may be applied, eg, using variable gain amplifier 116 . Also, in certain embodiments, if DC offset compensation is applied to more than one signal path (eg, to path 101 in example equalizer 42), the applied DC offset compensation can be adjusted and fixed in one path DC offset compensation for other paths. In an alternative embodiment, the independent control variables may be mapped to multiple paths using a specific function, and DC offset compensation may be applied to these paths according to the mapping process. Alternatively, DC offset compensation may be adjusted independently for each path, as discussed further below in connection with FIGS. 30-40 .

As can be observed, the method 3200 divides the ways of adjusting DC offset compensation into two based on the relative frequency at which particular data values are observed. If another type of data value is observed much more frequently than one type of data value, the method 3200 corrects for this imbalance, possibly due to a false lock. If no data value of one type is observed much more frequently than another type of data value, the method 3200 assumes that the signal is not in a false lock state and only performs a test on those boundary values between consecutive data values that include transitions. Analyze to correct for residual DC offset. In this manner, method 3200 can keep any data DC imbalance within acceptable limits. In certain embodiments, the data DC imbalance can be kept within an acceptable range even if the incoming signal is (quasi-)periodic and a resampling technique is used.

FIG. 29 is a table 3400 illustrating an example offset control scheme associated with the method 3200 of FIG. 28 . Each row 3402 corresponds to a particular value pattern for which a particular offset canceller action is performed. Column 3410 includes the high or low value ("1" or "0") of each data and boundary value in the sampled series of data and boundary values. Column "D1" includes first sampled data values of the output signal, column "D2" includes second sampled data values of the output signal, and column "E1" includes boundary values between the first and second data values. These values are similar to those illustrated in Figs. 23A to 23C. As can be observed, transitions do not necessarily occur between the data values of columns "D1" and "D2" in each schema.

It should be noted that the pattern of values in each row 3402 may be sampled by sampler 104 and sent to offset controller 106 . Alternatively, offset controller 106 may only receive sampled data values and other phase information, and may derive certain boundary values (e.g., including those in column E1) from these data values and phase information (thus may not be determined by sampler 104 to sample out).

Column 3412 includes the alternative boundary value at column "E1" for rows 3402a and 3402b. An "X" is included in column 3412 for rows 3402c and 3402d because, for consecutive data values with the same value, boundary values are not considered when taking offset canceller action. Instead, only the relative frequency of high or low data values is considered, as described above in method 3200 . For a particular mode, column 3414 includes a particular residual DC offset level. For a particular mode, column 3416 includes the particular action set for the offset offset. Actions for offset cancellation settings may be applied as discussed above in method 3200 .

Modifications, additions, or omissions may be made to the systems and methods without departing from the scope of the present invention. Components of the described systems and methods may be integrated or separated according to particular needs. Additionally, the operations of the systems and methods may be performed by more, fewer or other components.

In certain embodiments, an equalizer, such as equalizer 42 of FIG. 3 , may apply a DC offset canceling action to more than one signal path, such as the unchanged (DC) component, the first order component, and the second order component of the signal. An example of an equalizer that can apply a DC offset canceling action to more than one signal path includes a second derivative equalizer. In some equalizers, DC offset cancellation can be applied to multiple signal paths in a programmed manner. Applying the DC offset cancellation action in a programmed manner includes adjusting the DC offset gain in one path and fixing the DC offset compensation of the other path. Alternatively, applying the DC offset cancellation action in a programmed manner includes using a specific function to map the independent control variable to a plurality of paths, and adjusting the DC offset compensation in these paths according to the mapping.

Applying DC offset cancellation actions to multiple signal paths in a programmed manner may be disadvantageous in certain situations. For example, if the residual DC offsets of multiple signal paths are in opposite directions (i.e., such that when the residual DC offsets are combined at combiner 118, they cancel each other out), the equalizer will not correct the signal paths residual DC offset in , so the DC offset can saturate signal components in one or more paths. Allowing residual DC offset to persist in one or more signal paths can degrade the performance of the equalizer, eg, limit the linear operating range of the equalizer circuit.

30 illustrates a DC path output 3510 exhibiting a negative residual DC offset, a first derivative path output 3520 exhibiting a positive residual DC offset, and a predominantly zero DC offset in an example first derivative equalizer compared to a clock signal. Example 3500 of equalizer output signal 3530 with residual DC offset. It should be noted that although DC path output 3510 and first derivative path output 3520 are illustrated in contrast to a clock signal, the receiver may not monitor outputs 3510 and 3520 individually or clock them. sampling. In the illustrated example, equalizer output 3530 is the sum of DC path output 3510 and first derivative path output 3520 . As can be observed, while the equalizer output 3530 exhibits mostly zero overall DC offset, the DC path output 3510 is saturated and exhibits a negative offset, while the first derivative path output 3520 exhibits a positive offset. Therefore, an equalizer that applies a DC offset cancellation action to a path in a programmed manner may not correct the residual offset in each path, and thus the residual offset will degrade the performance of the equalizer. Therefore, an equalizer that can cancel residual offsets in the constituent paths of a signal in certain cases is advantageous.

It should be noted that the equalizer output 3530 may exhibit mostly canceled overall offsets at boundaries E3 and E4, but it may exhibit a slight positive offset at boundary E2, which is consistent with the first derivative path output The offset of the 3520 is in the same polarity. This may be due to saturation of the DC path output 3510. In other words, if the DC path output 3510 and the first derivative path output 3520 have residual offsets of opposite polarity but same magnitude, then at the equalizer output 3530 they will be at the boundary after multiple successive transitions (as in E3 and E4 completely cancel each other out because the DC path output 3510 may not be saturated after multiple consecutive transitions. On the other hand, even if DC path output 3510 and first derivative path output 3520 have residual offsets of opposite polarity but same magnitude, at equalizer output 3530 they will not be after a few data bits of the same value Completely cancel each other out at the boundary of , such as at E2, and the equalizer output 3530 may tend to have the same polarity offset as the first derivative path output 3520 because the DC path output 3510 due to saturation of the DC path output 3510 The effect, which may occur after consecutive data bits of the same value, may have a slightly smaller offset value than the first derivative path output 3520. In this manner, residual offset in a single path, such as first derivative path output 3520, can be detected from overall equalizer output 3530 by selecting a boundary value based on the data pattern preceding the boundary.

31 is a flowchart illustrating an example method 3600 for canceling residual DC offset in a first derivative analog equalizer in accordance with certain embodiments of the invention. In certain cases, method 3600 can correct the residual DC offset in both paths by applying an offset cancellation action to one or both of the unchanged DC path and the first derivative path in the first derivative equalizer. Offset.

For example, an offset cancellation action may only be applied to the first derivative path when successive data values with the same high or low value are observed prior to the transition. Successive data values with the same value indicate that the DC path is saturated (assuming roughly cancels out the overall offset of the signal). Therefore, the values (high or low) that comprise the boundary values between transitioned data values likely correspond to residual DC offsets in the first derivative path. Offset cancellation actions can be applied to both the first derivative path and the DC path when consecutive multiple data values with different high or low values are observed prior to the transition. By applying the offset cancellation action in this manner, the method 3600 can correct for residual offset in each signal path even though the unchanged DC path and the first derivative path exhibit residual offset in opposite directions.

Method 3600 begins at step 3610 where an output signal is sampled using a clock signal. As described above in connection with FIG. 3, the output signal may be the output of an equalizer, and the output signal may be sampled according to a clock signal. In certain embodiments, the output signal may be sampled at reference data points and boundary points determined by the clock signal. Alternatively, the output signal may not be sampled at boundary points, but boundary values corresponding to these non-sampled points may be derived. In certain embodiments, offset controller 106 may derive boundary values from sampled data values and other phase information (eg, whether the output signal is early or late in phase).

At step 3620, after sampling the output signal, the sampled data values may be analyzed to determine whether transitions have occurred in the data values. At step 3630, if no transition is detected, the method returns to step 3620. If a transition is detected between consecutive data values, the method proceeds to step 3640 . It should be noted that in certain embodiments transitions may be detected by directly comparing received data values to each other. In an alternative embodiment, transitions may be detected by comparing received data values and boundary values to a predefined pattern of values that includes transitions (and corresponds to specific offset canceling actions). It should also be noted that in certain embodiments, offset cancellation actions may be performed after a single transition is detected.

If a transition is detected, then at step 3640 a value comprising a boundary value between successive data values of the transition is identified. At step 3650, if the boundary value is high, the method proceeds to step 3660. If the boundary value is low, the method proceeds to step 3690.

At step 3660, a determination is made whether the data values 0.5 and 1.5 bits before the boundary value are the same. If so, the DC path may be saturated, and the value of this boundary value may reflect a residual DC offset in the first derivative path. Thus, if the data values 0.5 and 1.5 bits before the boundary value are the same, method 3600 proceeds to step 3670 and applies a negative offset cancellation action to the first derivative path to adjust the signal down (since the residual first derivative path offset is positive). If the data values 0.5 and 1.5 bits before the boundary value are different, method 3600 proceeds to step 3680 and applies a negative offset cancellation action to the unchanged DC path and the first derivative path to downscale the signal (due to residual equalization device offset is positive). It should be noted that in certain embodiments, boundary values can be identified, data values compared, and offset cancellations taken by comparing the boundary values and data values to predefined patterns (which correspond to specific offset cancellation actions) action.

If at step 3650 the boundary value is low, then method 3600 proceeds to step 3690 . At step 3690, a determination is made whether the data values 0.5 and 1.5 bits before the boundary value are the same. If so, the DC path may be saturated, and the value of this boundary value may reflect a residual DC offset in the first derivative path. Therefore, if the data values 0.5 and 1.5 bits before the boundary value are the same, method 3600 proceeds to step 3700 and applies a positive offset cancellation action to the first derivative path to adjust the signal upward (since the residual first derivative path is skewed shift is negative). If the data values 0.5 and 1.5 bits before the boundary value are different, method 3600 proceeds to step 3710 and applies a positive offset cancellation action to the unchanged DC path and the first derivative path to adjust the signal up (because the residual equalizer offset is negative). It should be noted that in certain embodiments, boundary values can be identified, data values compared, and offset cancellations taken by comparing the boundary values and data values to predefined patterns (which correspond to specific offset cancellation actions) action.

It should be noted that in certain embodiments, steps 3620 to 3710 may be performed by offset controller 106 and the DC offset cancellation action may be applied, eg, using variable gain amplifier 116 . It should also be noted that while the relationship between data values 0.5 and 1.5 bits before the boundary value is used to determine the set of paths to which offset compensation is applied, any suitable relationship between data values (e.g. , taking into account the data value 2.5 bits before the boundary value). It should also be noted that method 3600 can be generalized to equalizers associated with any suitable number of signal paths.

FIG. 32 is a table 3800 illustrating an example offset control scheme associated with the method 3600 of FIG. 31 . Each row 3802 corresponds to a particular value pattern for which a particular offset canceller action is performed (either for the first derivative path or for both the first derivative path and the unchanged DC path). Column 3810 includes the high or low value ("1" or "0") of each data value and boundary value in the series of sampled data values and boundary values. Column "D0" contains the zeroth sampled data value of the output signal, column "D1" contains the first sampled data value of the output signal, column "D2" contains the second sampled data value of the output signal, and column "E1" contains the first data value The boundary value between the value and the second data value. These values are similar to those illustrated in Figs. 23A to 23C. As can be observed, in each pattern a transition occurs between the data values of columns "D1" and "D2".

It should be noted that the pattern of values in each row 3802 may be sampled by sampler 104 and sent to offset controller 106 . Alternatively, offset controller 106 may only receive sampled data values and other phase information, and may derive certain boundary values (e.g., including those in column E1) from these data values and phase information (thus may not be determined by sampler 104 to sample out).

Column 3812 includes the alternative boundary value for each row 3802 at column "E1". For a particular mode, column 3814 includes the particular degree of residual DC offset and DC offset cancellation action associated with the unchanged DC path of the input signal. DC offset cancellation actions may be performed as discussed above in method 3600 . For a particular mode, column 3816 includes the particular residual DC offset degree and DC offset cancellation action associated with the first derivative path of the input signal. DC offset cancellation actions may be performed as discussed above in method 3600 .

33 is a flowchart illustrating another example method 3900 for canceling residual DC offset in a first derivative analog equalizer in accordance with certain embodiments of the invention. Similar to method 3600 in FIG. 31 , method 3900 may, under certain circumstances, cancel out the unaltered DC path of the first-order derivative equalizer and any of the first-order derivative paths by applying an offset cancellation action to those paths. Residual DC offset.

In method 3900, an offset cancellation action may only be applied to the first derivative path when successive data values with the same high or low value are observed prior to the transition. Successive data values with the same value indicate that the DC path is saturated (assuming roughly cancels out the overall offset of the signal). Therefore, the value (high or low) of the boundary value between multiple data values comprising transitions likely corresponds to a residual DC offset in the first derivative path. Offset cancellation actions may only be applied to the unchanged DC path when successive data values with different high or low values are observed prior to the transition. By applying the offset cancellation action in this manner, the method 3900 can correct for residual offset in each signal path even though the unchanged DC path and the first derivative path exhibit residual offset in opposite directions.

Method 3900 begins at step 3910 where an output signal is sampled using a clock signal. Since steps 3910 to 3960 and 3990 may be the same as steps 3610 to 3660 and 3690 respectively, steps 3910 to 3960 and 3990 will not be described in detail. After determining whether the data values 0.5 and 1.5 bits before the boundary value are the same at step 3960, method 3900 proceeds to step 3970 if the values are the same and to step 3980 if the values are different . At step 3970, a negative offset cancellation action is applied to the first derivative path to adjust the signal down (since the residual first derivative path offset is positive). At step 3980, if the data values 0.5 and 1.5 bits before the boundary value are different, a negative offset cancellation action is applied to the unchanged DC path to adjust the signal down (since the residual equalizer offset is positive). It should be noted that in certain embodiments, boundary values can be identified, data values compared, and offset cancellations taken by comparing the boundary values and data values to predefined patterns (which correspond to specific offset cancellation actions) action.

After determining whether the data values 0.5 and 1.5 bits before the boundary value are the same at step 3990, method 3900 proceeds to step 4000 if the values are the same and to step 4010 if the values are different . At step 4000, a positive offset cancellation action is applied to the first derivative path to adjust the signal up (since the residual first derivative path offset is negative). At step 4010, if the data values 0.5 and 1.5 bits before the boundary value are different, a positive offset cancellation action is applied to the unchanged DC path to adjust the signal up (since the residual equalizer offset is negative). It should be noted that in certain embodiments, boundary values can be identified, data values compared, and offset cancellations taken by comparing the boundary values and data values to predefined patterns (which correspond to specific offset cancellation actions) action.

It should also be noted that in certain embodiments, steps 3920 through 4010 may be performed by offset controller 106 and the DC offset cancellation action may be applied, eg, using variable gain amplifier 116 . It should also be noted that although the relationship between data values 0.5 and 1.5 bits before the boundary value is used to determine the set of paths to which offset compensation is applied, any suitable relationship between data values may be used. relationship (eg, taking into account data values 2.5 bits before the transition boundary value). It should also be noted that method 3900 can be generalized to equalizers associated with any suitable number of signal paths.

FIG. 34 is a table 4100 illustrating an example offset control scheme associated with the method 3900 of FIG. 33 . Each row 4102 corresponds to a particular value pattern for which a particular offset canceller action is performed (either for the first derivative path or the unchanged DC path). Column 4110 includes the high or low value ("1" or "0") of each data value and boundary value in the series of sampled data values and boundary values. Column "D0" contains the zeroth sampled data value of the output signal, column "D1" contains the first sampled data value of the output signal, column "D2" contains the second sampled data value of the output signal, and column "E1" contains the first data value The boundary value between the value and the second data value. These values are similar to those illustrated in Figs. 23A to 23C. As can be observed, in each pattern a transition occurs between the data values of columns "D1" and "D2".

It should be noted that the pattern of values in each row 4102 may be sampled by sampler 104 and sent to offset controller 106 . Alternatively, offset controller 106 may only receive sampled data values and other phase information, and may derive certain boundary values (e.g., including those in column E1) from these data values and phase information (thus may not be determined by sampler 104 to sample out).

Column 4112 includes the alternative boundary value for each row 4102 at column "E1". For a particular mode, column 4114 includes the particular degree of residual DC offset and DC offset cancellation action associated with the unchanged DC path of the input signal. DC offset cancellation actions may be applied as discussed above in method 3900 . For a particular mode, column 4116 includes the particular residual DC offset degree and DC offset cancellation action associated with the first derivative path of the input signal. DC offset cancellation actions may be applied as discussed above in method 3900 .

35 is a flowchart illustrating yet another example method 4200 for canceling residual DC offset in a first derivative analog equalizer in accordance with certain embodiments of the invention. Similar to method 3600 in FIG. 31 , method 4200 may apply an offset cancellation action to either or both of the unaltered DC path and the first derivative path of the first derivative analog equalizer in some cases to cancel out these paths residual offset in . Method 4200 may do so by applying an offset cancellation action to both the unchanged DC path and the first derivative path when successive data values with the same high or low value are observed prior to the transition. Offset cancellation actions may only be applied to the unchanged DC path when successive data values with different high or low values are observed prior to the transition. By applying offset cancellation actions in this manner, method 4200 can correct for residual offset in each signal path.

Method 4200 begins at step 4210 where an output signal is sampled using a clock signal. Since steps 4210 to 4260 and 4290 may be the same as steps 3610 to 3660 and 3690 respectively, steps 4210 to 4260 and 4290 will not be described in detail. After step 4260 place determines whether the data values of 0.5 and 1.5 bits before the boundary value are the same, method 4200 proceeds to step 4270 if these values are the same, and proceeds to step 4280 if these values are different . At step 4270, a positive offset cancellation action is applied to the unchanged DC path to adjust the unchanged DC path up, and a negative offset cancellation action is applied to the first derivative path to adjust the first derivative path down (since a residual derivative path offset is positive). The offset of the unchanged DC path can be adjusted upwards in the opposite manner to the first derivative path to keep the overall offset correction at the same level, while the offset of the first derivative path is adjusted downward. At step 4280, if the data values 0.5 and 1.5 bits before the boundary value are different, a negative offset cancellation action is applied to the unchanged DC path to adjust the signal down (since the residual equalizer offset is positive). It should be noted that in certain embodiments, boundary values can be identified, data values compared, and offset cancellations taken by comparing the boundary values and data values to predefined patterns (which correspond to specific offset cancellation actions) action.

After step 4290 place determines whether the data values of 0.5 and 1.5 bits before the boundary value are the same, method 4200 proceeds to step 4300 if these values are the same, and proceeds to step 4310 if these values are different . At step 4300, a negative offset cancellation action is applied to the unchanged DC path to adjust the unchanged DC path downward, and a positive offset cancellation action is applied to the first derivative path to adjust the first derivative path upward (because a residual derivative path offset is negative). The offset of the unchanged DC path can be adjusted downward in the opposite manner to the first derivative path to keep the overall offset correction at the same level, while the offset of the first derivative path is adjusted upward. At step 4310, if the data values 0.5 and 1.5 bits before the boundary value are different, a positive offset cancellation action is applied to the unchanged DC path to adjust the unchanged DC path up (since the residual equalizer offset is negative ). It should be noted that in certain embodiments, boundary values can be identified, data values compared, and offset cancellations taken by comparing the boundary values and data values to predefined patterns (which correspond to specific offset cancellation actions) action.

It should also be noted that in certain embodiments, steps 4220 to 4310 may be performed by offset controller 106 and the DC offset cancellation action may be applied, eg, using variable gain amplifier 116 . It should also be noted that while the relationship between data values 0.5 and 1.5 bits before the boundary value is used to determine the set of paths to which offset compensation is applied, any suitable relationship between data values ( For example, the data value 2.5 bits before the transition boundary value is taken into account). It should also be noted that method 4200 can be generalized to equalizers associated with any suitable number of signal paths.

FIG. 36 is a table 4400 illustrating an example offset control scheme associated with the method 4200 of FIG. 35 . Each row 4402 corresponds to a particular value pattern for which a particular offset canceller action (either for the first derivative path and the DC path or only the DC path) is performed. Column 4410 includes the high or low value ("1" or "0") of the data values and boundary values in the sampled series of data values and boundary values. Column "D0" contains the zeroth sampled data value of the output signal, column "D1" contains the first sampled data value of the output signal, column "D2" contains the second sampled data value of the output signal, and column "E1" contains the first data value The boundary value between the value and the second data value. These values are similar to those illustrated in Figs. 23A to 23C. As can be observed, in each pattern a transition occurs between the data values of columns "D1" and "D2".

It should be noted that the pattern of values in each row 4402 may be sampled by sampler 104 and sent to offset controller 106 . Alternatively, offset controller 106 may only receive sampled data values and other phase information, and may derive certain boundary values (e.g., including those in column E1) from these data values and phase information (thus may not be determined by sampler 104 to sample out).

Column 4412 includes the alternative boundary value for each row 4402 at column "E1". For a particular mode, column 4414 includes the particular residual DC offset degree and DC offset cancellation action associated with the unchanged DC path of the input signal. DC offset cancellation actions may be applied as discussed above in method 4200 . For a particular mode, column 4416 includes the particular residual DC offset degree and DC offset cancellation action associated with the first derivative path of the input signal. DC offset cancellation actions may be applied as discussed above in method 4200 .

FIG. 37 is a flowchart illustrating yet another example method 4500 for canceling residual DC offset in a first derivative analog equalizer in accordance with certain embodiments of the invention. Similar to method 3600 in FIG. 31 , method 4500 may, in some cases, apply an offset cancellation action to both the unaltered DC path and the first derivative path of the first derivative analog equalizer in a biased manner to cancel out the residual offset. Method 4500 may do so by applying an offset cancellation action to both the DC path and the first derivative path when successive data values with the same high or low value are observed prior to the transition, where the first derivative path biased on. When successive data values with different high or low values are observed prior to transitions, an offset cancellation action can be applied to both the DC path and the first derivative path, biasing the DC path. By applying offset cancellation actions in this biased manner, method 4500 can correct for residual offset in each signal path even though the unchanged DC path and the first derivative path exhibit residual offset in opposite directions.

Method 4500 begins at step 4510 where an output signal is sampled using a clock signal. Since steps 4510 to 4560 and 4590 may be the same as steps 3610 to 3660 and 3690 respectively, steps 4510 to 4560 and 4590 will not be described in detail. After determining whether the data values 0.5 and 1.5 bits before the boundary value are the same at step 4560, method 4500 proceeds to step 4570 if the values are the same and to step 4580 if the values are different . At step 4570, a negative offset cancellation action is applied to the unchanged DC path to adjust the unchanged DC path down, and a larger negative offset cancellation action is applied to the first derivative path to adjust the first derivative path down (because the residual first derivative path offset is positive). At step 4580, if the data values 0.5 and 1.5 bits before the boundary value are different, a negative offset cancellation action is applied to the first derivative path to adjust the first derivative path down and a lower offset is applied to the unchanged DC path. A large negative offset cancels the action to adjust the unchanged DC path down (since the residual equalizer offset is positive). It should be noted that in certain embodiments, boundary values can be identified, data values compared, and offset cancellations taken by comparing the boundary values and data values to predefined patterns (which correspond to specific offset cancellation actions) action.

After determining whether the data values 0.5 and 1.5 bits before the boundary value are the same at step 4590, method 4500 proceeds to step 4600 if the values are the same, and to step 4610 if the values are different . At step 4600, a positive offset cancellation action is applied to the unchanged DC path to adjust the unchanged DC path upward, and a larger positive offset cancellation action is applied to the first derivative path to adjust the first derivative path upward (because Residual first derivative path offset is negative). At step 4610, if the data values 0.5 and 1.5 bits before the boundary value are different, apply a positive offset offset action to the first derivative path to adjust the first derivative path upward, and apply a larger offset to the unchanged DC path. The positive offset of the offset cancels the action to adjust the DC path up (since the residual equalizer offset is negative). It should be noted that in certain embodiments, boundary values can be identified, data values compared, and offset cancellations taken by comparing the boundary values and data values to predefined patterns (which correspond to specific offset cancellation actions) action.

It should also be noted that in certain embodiments, steps 4520 to 4610 may be performed by offset controller 106 and the DC offset cancellation action may be performed, eg, using variable gain amplifier 116 . It should also be noted that while the relationship between data values 0.5 and 1.5 bits before the boundary value is used to determine the set of paths to which offset compensation is applied, any suitable relationship between data values ( For example, data values 2.5 bits before the boundary value are taken into account). It should also be noted that method 4500 can be generalized to equalizers associated with any suitable number of signal paths.

FIG. 38 is a table 4700 illustrating an example offset control scheme associated with the method 4500 of FIG. 37 . Each row 4702 corresponds to a particular value pattern for which a particular offset canceller action is performed (for both the first derivative path and the DC path). Column 4710 includes the high or low value ("1" or "0") of each data value and boundary value in the sampled series of data values and boundary values. Column "D0" contains the zeroth sampled data value of the output signal, column "D1" contains the first sampled data value of the output signal, column "D2" contains the second sampled data value of the output signal, and column "E1" contains the first data value The boundary value between the value and the second data value. These values are similar to those illustrated in Figs. 23A to 23C. As can be observed, transitions occur between the data values of columns "D1" and "D2" in each schema.

It should be noted that the pattern of values in each row 4702 may be sampled by sampler 104 and sent to offset controller 106 . Alternatively, offset controller 106 may only receive sampled data values and other phase information, and may derive certain boundary values (e.g., including those in column E1) from these data values and phase information (thus may not be determined by sampler 104 to sample out).

Column 4712 includes the alternative boundary value for each row 4702 at column "E1". For a particular mode, column 4714 includes the particular residual DC offset degree and DC offset cancellation action associated with the unchanged DC path of the input signal. DC offset cancellation actions may be applied as discussed above in method 4500 . For a particular mode, column 4716 includes the particular residual DC offset degree and DC offset cancellation action associated with the first derivative path of the input signal. DC offset cancellation actions may be applied as discussed above in method 4500 .

39 is a flowchart illustrating an example method 4800 for canceling residual DC offset in a second derivative analog equalizer in accordance with certain embodiments of the invention. In some cases, method 4800 can apply an offset cancellation action to one or more of the DC path, the first derivative path, and the second derivative path of the second derivative analog equalizer to counteract the residual offset in these paths. shift. Method 4800 may do so by only applying an offset cancellation action to the second derivative path when 3 consecutive data values with the same high or low value are observed prior to the transition. When 2 consecutive data values with the same high or low value are observed prior to the transition, the method 4800 can apply an offset cancellation action to both the first and second derivative paths. When 2 consecutive data values with opposite high or low values are observed prior to the transition, method 4800 can apply offset cancellation actions to all 3 paths. By applying the offset cancellation action in this manner, the method 4800 can correct for the residual offset in each signal path even if the residual offsets of the three paths cancel each other out.

Method 4800 begins at step 4810 where an output signal is sampled using a clock signal. Since steps 4810 to 4850 may be the same as steps 3610 to 3650 respectively, steps 4810 to 4850 will not be described in detail. After determining whether the boundary value is high (i.e., equal to "1") at step 4850, method 4800 proceeds to step 4860 if the boundary value is high, and if the boundary value is low (i.e., equal to "0") ) proceed to step 4910.

At step 4860, a determination is made whether the data values 0.5, 1.5, and 2.5 bits before the boundary value are the same. If the values are the same, method 4800 proceeds to step 4870 and applies a negative offset cancellation action to adjust the second derivative path downward (since the residual second derivative path offset is positive). If at step 4860 it is determined that the values are not the same, method 4800 proceeds to step 4880 . It should be noted that in certain embodiments, boundary values can be identified, data values compared, and offset cancellations taken by comparing the boundary values and data values to predefined patterns (which correspond to specific offset cancellation actions) action.

At step 4880, a determination is made whether the data values 0.5, 1.5, and 2.5 bits before the boundary value are the same. Method 4800 proceeds to step 4890 if the values are the same, or to step 4900 if the values are not the same. At step 4890, a negative offset cancellation action is applied to each of the first and second derivative paths to adjust each of the first and second derivative paths downward (because the residual first and/or second derivative path offset is positive). At step 4900, if the data values 0.5 and 1.5 bits before the boundary value are different, a negative offset cancellation action is applied to each of the 3 paths to adjust each of the 3 paths down (because Residual EQ offset is positive). It should be noted that in certain embodiments, boundary values can be identified, data values compared, and offset cancellations taken by comparing the boundary values and data values to predefined patterns (which correspond to specific offset cancellation actions) action.

If at step 4850 it is determined that the boundary value is low, then method 4800 proceeds to step 4910 . At step 4910, a determination is made whether the data values 0.5, 1.5, and 2.5 bits before the boundary value are the same. If the values are the same, method 4800 proceeds to step 4920 and applies a positive offset cancellation action to the second derivative path to adjust the signal up (since the residual second derivative path offset is negative). If at step 4910 it is determined that the data values are not the same, method 4800 proceeds to step 4930 . It should be noted that in certain embodiments, boundary values can be identified, data values compared, and offset cancellations taken by comparing the boundary values and data values to predefined patterns (which correspond to specific offset cancellation actions) action.

At step 4930, a determination is made whether the data values 0.5 and 1.5 bits before the boundary value are the same. If the values are the same, method 4800 proceeds to step 4940. If the values are not the same, method 4800 proceeds to step 4950. At step 4940, a positive offset cancellation action is applied to each of the first and second derivative paths to adjust each of the first and second derivative paths upwards (since residual first and/or second order Derivative path offset is negative). At step 4950, if the data values 0.5 and 1.5 bits before the boundary value are different, then a positive offset cancellation action is applied to each of the 3 paths to adjust each of the 3 paths up (because the residual equalizer offset is negative). It should be noted that in certain embodiments, boundary values can be identified, data values compared, and offset cancellations taken by comparing the boundary values and data values to predefined patterns (which correspond to specific offset cancellation actions) action.

It should also be noted that in certain embodiments, steps 4820 through 4950 may be performed by offset controller 106 and the DC offset cancellation action may be applied, eg, using variable gain amplifier 116 . It should also be noted that although the relationship between data values 0.5, 1.5 and 2.5 bits before the boundary value is used to determine the set of paths to which offset compensation is applied, any suitable relationship between data values may be used (For example, data values 3.5 bits before the boundary value are taken into account). It should also be noted that method 4800 can be generalized to equalizers associated with any suitable number of signal paths.

FIG. 40 is a table 5000 illustrating an example offset control scheme associated with the method 4800 of FIG. 39 . Each row 5002 corresponds to a particular value pattern for which a particular offset canceller action is performed (for a group of one or more of the DC path, the first derivative path, and the second derivative path). Column 5010 includes the high or low value ("1" or "0") of each data value and boundary value in the sampled series of data values and boundary values. "X" indicates that the value can be "0" or "1". Column "D0" contains the zeroth sampled data value of the output signal, column "D1" contains the first sampled data value of the output signal, column "D2" contains the second sampled data value of the output signal, and column "D3" contains the For the third sampled data value, column "E2" includes boundary values between the second data value and the third data value. These values are similar to those illustrated in Figs. 23A to 23C. As can be observed, in each pattern a transition occurs between the data values of columns "D2" and "D3".

It should be noted that the pattern of values in each row 5002 of sampler 104 may be sampled and sent to offset controller 106 . Alternatively, offset controller 106 may only receive sampled data values and other phase information, and may derive certain boundary values (e.g., including the boundary values in column E2) from these data values and phase information (thus may not be determined by sampler 104 to sample).

Column 5012 includes the alternative boundary value for each row 5002 at column "E2". For a particular mode, column 5014 includes the particular residual DC offset degree and DC offset cancellation action associated with the unchanged DC path of the input signal. DC offset cancellation actions may be applied as discussed above in method 4800 . For a particular mode, column 5016 includes the particular residual DC offset degree and DC offset cancellation action associated with the first derivative path of the input signal. DC offset cancellation actions may be applied as discussed above in method 4800 . For a particular mode, column 5018 includes the particular residual DC offset degree and DC offset cancellation action associated with the second derivative path of the input signal. DC offset cancellation actions may be applied as discussed above in method 4800 .

It should be noted that in certain embodiments the embodiments illustrated in Figures 30-40 may be combined together. For example, in certain embodiments, steps 4280 and 4310 in method 4200 may be replaced with steps 3680 and 3710 in method 3600, respectively. In other embodiments, method 3600, 3900, 4200, or 4500 may be applied to a second derivative analog equalizer by applying the same offset compensation to the second derivative path and the first derivative path, since it may be difficult to implement Method 4800 effectively differentiates the residual offset of each path between first and second derivative paths, and independent offset control for first and second derivative paths can become uncontrolled. In such an embodiment, if the residual offsets in the first and second derivative paths are of opposite polarity, these residual offsets may not be fully canceled out. However, in certain embodiments, instead of using the method 4800 and letting them vary randomly and become uncontrollable due to the inability to effectively detect each residual offset between the first and second derivative paths, binding them might be more beneficial.

Modifications, additions, or omissions may be made to the systems and methods without departing from the scope of the present invention. Components of the systems and methods may be integrated or separated according to particular needs. Additionally, the operations of the systems and methods may be performed by more, fewer or other components.

As discussed above in connection with FIG. 11, duty cycle distortion may affect adaptive gain control for periodic or quasi-periodic data sequences. Duty cycle distortion may also affect offset cancellation control for periodic or quasi-periodic data sequences. If the period of the data is an even number of data values, the "even" or "odd" boundary values dominating the transitions in the data sequence may be heavily shifted towards "early" or "late" phase due to duty cycle distortion . Due to this deviation, the equalizer compensation may also deviate, for example, in the direction of increasing or decreasing the gain or offset of the signal, potentially pushing the adaptive gain control and offset control beyond acceptable operating conditions.

As discussed above in connection with Figures 12 to 22, a particular pattern can be selected as a filter pattern to reduce the negative impact of duty cycle distortion and provide consistent results across (quasi-)periodic signals. In certain embodiments, these filter modes may be specific to certain (quasi) periodic signals. As discussed above, one disadvantage of using filter modes specific to particular (quasi) periodic signals is that their applicability is limited. For example, in other (quasi)periodic signals, these filter patterns may not be approximately equally distributed between even and odd data sequences, so if they are used for these other (quasi)periodic signals, it may be result in unacceptable operating conditions

Another potential disadvantage of using filter patterns specific to a particular (quasi) periodic signal is that these filter patterns may not be approximately equally distributed between even and odd sequences when resampling techniques are employed. Here, resampling technique refers to "vector resampling technique" which periodically starts "vector sampling" at a rate less than the bare channel rate, but each "resampled" vector represents continuously at the bare channel rate A segment of samples of the data and boundary values is the same length as the filter pattern. Note that "resampled" vectors can overlap each other if the "resampled" period is shorter than the length of the filter pattern. When resampling is done with a period that is in harmony with the (quasi)periodic signal, the pattern will appear with a different probability than it would appear in the entire (quasi)periodic signal.

Some methods of addressing these types of distortions have been discussed above in connection with FIGS. 17-22. For example, filter modes may be selected sequentially, randomly or simultaneously from a list of static or dynamic useful filter modes and used in a balanced manner, rather than selecting them specifically for a specific (quasi-)periodic signal. However, there are other methods for reducing the negative effects of duty cycle distortion and/or resampling and (quasi-)periodic signals, which can be used as an alternative to the filter mode technique discussed above, or can be combined with the above The filter mode techniques discussed are used together with these methods.

41 is a flowchart illustrating an example method 5100 for reducing the effects of duty cycle distortion in accordance with certain embodiments of the invention. Method 5100 works by comparing an even data sequence (which starts with even data, followed by odd data, even data, odd data, etc.) with an odd data sequence (which starts with odd data, followed by even data, odd data, even data, etc. ) and take adaptive gain control actions and/or offset cancellation actions in a balanced manner to reduce duty cycle distortion and/or negative effects of resampling and (quasi) periodic signals. Method 5100 may be used in conjunction with, or as an alternative to, the filter mode techniques discussed above in connection with FIGS. 17 through 22 .

Method 5100 begins at step 5110. At step 5110, logic (eg, receiver logic 47) receives an incoming signal that includes even data and odd data in sequence. In a particular embodiment the incoming signal may be a (quasi) periodic signal. The logic monitors for sequences of even data starting with even data (rather than sequences of odd data starting with odd data) for conditions to take control action. In certain embodiments, the logic may utilize one or more filter patterns to monitor sequences of even data beginning with even data. It should be noted that although even data sequences are monitored first in method 5100, odd data sequences may be monitored first in alternative embodiments.

At step 5120, a determination is made as to whether a condition has been detected for a control action to be taken. Alternatively, a determination may be made as to whether a particular data pattern corresponding to a certain filter pattern has been detected. If the condition has not been detected, method 5100 returns to step 5110, whereupon the logic continues to monitor the sequence of even data beginning with even data for the condition. If the condition has been detected, method 5100 proceeds to step 5130 . At step 5130, a first control action is taken. The first control action may be an adaptive gain control action and/or an offset cancellation action. The first control action may be based, for example, on sampling boundary values and/or one or more data values as described above in connection with FIGS. Other suitable techniques for conventional adaptive control algorithms including the Sign-Sign Least Mean Square (SS-LMS) algorithm and the Zero-Forcing (ZF) algorithm.

Method 5100 proceeds to step 5140 after the first control action is taken. At step 5140, the logic monitors for a sequence of odd data starting with odd data (rather than a sequence of even data starting with even data) for the condition to take a control action. In certain embodiments, the logic may utilize one or more filter patterns to monitor for odd data sequences beginning with odd data. At step 5150, a determination is made whether a condition for a control action has been detected. Alternatively, a determination may be made as to whether a particular data pattern corresponding to a certain filter pattern has been detected. If the condition has not been detected, method 5100 returns to step 5140, whereupon the logic continues to monitor odd data sequences beginning with odd data for the condition. If the condition has been detected, method 5100 proceeds to step 5160 . At step 5160, a second control action is taken. The second control action may be an adaptive gain control action and/or an offset cancellation action. The second control action may be based, for example, on sampling boundary values and/or one or more data values as described above in connection with FIGS. Other suitable techniques for conventional adaptive control algorithms including the Sign-Sign Least Mean Square (SS-LMS) algorithm and the Zero-Forcing (ZF) algorithm. Method 5100 returns to step 5110 after the second control action is taken. By sequentially monitoring the even and odd data sequences, Method 5100 balances "early" or "late" phase deviations due to duty cycle distortion and reduces duty cycle distortion and/or resampling (quasi) period Negative effects of sexual signaling.

In certain embodiments, the method 5100 may be used in conjunction with randomizer techniques to avoid phase locking to the period of a (quasi) periodic signal and thereby avoid other possible distortions. Randomizer techniques include, for example, the random filter pattern selection embodiment of method 2300 discussed above and methods 5300 and 5400 discussed below. Also, as discussed above, method 5100 may be used in conjunction with adaptive gain control and/or offset cancellation control, and may be used as an alternative to or in conjunction with the filter mode technique discussed above Use method 5100 together.

42 is a flowchart illustrating another example method 5200 for reducing the effects of duty cycle distortion in accordance with certain embodiments of the invention. Method 5200 begins at step 5210. At step 5210, logic (eg, receiver logic 47) receives an incoming signal that includes even data and odd data in sequence. In a particular embodiment the incoming signal may be a (quasi) periodic signal. The logic randomly selects an even data sequence (which starts with even data, followed by odd data, even data, odd data, etc.) or an odd data sequence (which starts with odd data, followed by even data, odd data, etc.) with equal probability. , even data, etc.) for monitoring. In certain embodiments, the logic may, for example, generate a one-bit random number (eg, "1" or "0") and select an even or odd data sequence based on the value of the random number.

At step 5220, a determination is made as to whether an even or odd data sequence has been selected. For example, this determination may be made based on the value of the generated random number. If it is determined that an even data sequence has been selected, method 5200 proceeds to step 5230 . If it is determined that an odd data sequence has been selected, method 5200 proceeds to step 5260.

If it is determined that an even data sequence has been selected, then at step 5230 the logic checks the condition for the control action to be taken on the even data sequence starting at the received even data (instead of the odd data sequence starting at the received odd data) Monitor. In certain embodiments, the logic may utilize one or more filter patterns to monitor sequences of even data beginning with even data.

At step 5240, a determination is made whether a condition has been detected for a control action to be taken. Alternatively, a determination may be made as to whether a particular data pattern corresponding to a certain filter pattern has been detected. If the condition has not been detected, method 5200 returns to step 5230, whereupon the logic continues to monitor the sequence of even data beginning with even data for the condition. If the condition has been detected, method 5200 proceeds to step 5250 . At step 5250, a control action is taken. The control action may be an adaptive gain control action and/or an offset cancellation action. The control action may be based, for example, on sampling boundary values and/or one or more data values as described above in connection with FIGS. Other suitable techniques for conventional adaptive control algorithms include the Sign-Sign Least Mean Square (SS-LMS) algorithm and the Zero Forcing (ZF) algorithm. After the control action is taken, method 5200 returns to step 5210.

If an odd data sequence is selected at step 5220 , method 5200 proceeds to step 5260 . At step 5260, the logic monitors for a sequence of odd data starting with odd data (rather than a sequence of even data starting with even data) for the condition for a control action to be taken. In certain embodiments, the logic may utilize one or more filter patterns to monitor for odd data sequences beginning with odd data.

At step 5270, a determination is made whether a condition for a control action has been detected. Alternatively, a determination may be made as to whether a particular data pattern corresponding to a certain filter pattern has been detected. If the condition has not been detected, method 5200 returns to step 5260, whereupon the logic continues to monitor odd data sequences beginning with odd data for the condition. If the condition has been detected, method 5200 proceeds to step 5280. At step 5280, a control action is taken. The control action may be an adaptive gain control action and/or an offset cancellation action. The control action may be based, for example, on sampling boundary values and/or one or more data values as described above in connection with FIGS. Other suitable techniques for conventional adaptive control algorithms include the Sign-Sign Least Mean Square (SS-LMS) algorithm and the Zero Forcing (ZF) algorithm. After the control action is taken, method 5200 returns to step 5210.

By randomly selecting one of the data sequences beginning with even or odd data with equal probability, method 5200 can balance "early" or "late" phase deviations due to duty cycle distortion, and (especially is in the long run) to reduce the negative effects of duty cycle distortion and/or resampling and (quasi-)periodic signals. However, in the short term, method 5200 is not as effective as method 5100 in reducing duty cycle distortion and/or negative effects of resampling and (quasi-)periodic signals (e.g., because using method 5200 may successively randomly select to same even data sequence or odd data sequence). However, an advantage of method 5200 over method 5100 is that the random selection of the data sequence by method 5200 avoids phase locking to the period of the (quasi) periodic signal, thereby reducing other possible distortions. It should be noted that method 5200 may be used in conjunction with adaptive gain control and/or offset cancellation control. Furthermore, method 5200 may be used as an alternative to, or in conjunction with, the filter mode techniques discussed above.

It should be noted that in addition to adaptive gain control and/or offset cancellation control based on sampling boundary values and/or one or more data values as described above in connection with FIGS. , the methods 5100 and 5200 can also be applied to any other suitable control system utilizing the output of a decimator to reduce the negative effects of duty cycle distortion and/or resampling and (quasi-)periodic signals. For example, in certain embodiments, these methods can be applied to conventional adaptive Equalizer control. In certain embodiments, these methods can also be applied to clock and data recovery (CDR) systems that adjust the recovered clock for the sampler based on the output of the sampler.

Modifications, additions, or omissions may be made to the systems and methods without departing from the scope of the present invention. Components of the systems and methods may be integrated or separated according to particular needs. Additionally, the operations of the systems and methods may be performed by more, fewer or other components.

As discussed above, resampling refers to a "vector resampling technique" that periodically starts "vector sampling" at a rate less than the raw channel rate, but where each "resampled" vector represents A segment of data and boundary values sampled continuously at the channel rate, the segment being the same length as the filter pattern. Since the resampling period may be locked to the period of the (quasi)periodic signal being resampled, the data pattern observed in the resampled data may differ from the data pattern in the entire (quasi)periodic signal. For example, if a periodic signal with a period of 320 bits is resampled at a rate of 1/32, the periodic signal will be resampled repeatedly at the same 10 points in each cycle, never Will resample at the other 310 points. Sampling at only some of the total points in the (quasi) periodic signal may skew the control action performed by the equalizer.

One solution to counteract locking between the resampling period and the period of the (quasi)periodic signal is to change the point at which the (quasi)periodic signal is resampled in each resampling period. For example, if resampling is performed at a rate of 1/32, the resampling period is 32 bits and there are 32 possible points in each resampling period at which to resample the (quasi) periodic signal. The point at which resampling occurs can be chosen to vary with each 32-bit resampling period.

It should be noted that resampling during a resampling period may include, for example, sampling a number of data bits before, after, or around a particular point in the period. For example, if a resampling rate of 1/32 is employed and the resampling process includes resampling 6 bits, then 6 bits may be sampled before, after, or around a particular point in each 32 bit period. An example method for changing the point at which resampling occurs in each resampling cycle is discussed below in conjunction with FIGS. 43 to 45 .

An alternative solution to counteract locking between the resampling period and the period of the (quasi)periodic signal is to randomly choose to resample the (quasi)periodic signal without being constrained by the set resampling period next point. For example, after a first point is randomly selected and sampled, the next point is randomly selected and sampled, which is not necessarily limited to the resampling period, and so on. In certain embodiments, a pseudorandom number generator may be used and may be weighted in any suitable manner such that an average resampling rate results. For example, in certain embodiments, the pseudo-random number generator may be capped such that the next randomly selected point does not exceed a certain number of digits from the previous point. In such embodiments, the upper limit may serve to limit the average resampling rate. In alternative embodiments, the next point can be chosen under various constraints such that the resampling rate is always less than some maximum resampling rate.

Yet another alternative solution to counteract locking between the resampling period and the period of the (quasi-)periodic signal is to take control actions randomly with some fixed or variable probability on random numbers generated for each sampling point, instead of Randomly select resampling points or resampling periods for resampling cycles. In certain embodiments, a pseudo-random number generator may be used, and sampling employed only if the generated pseudo-random number falls within a certain range. The probability of taking a control action may be fixed or variable. In certain embodiments, once sampling is employed, the variable probability may be set to zero for a certain period of time or before a certain point in time to limit the maximum resampling rate to be less than a certain value. In other embodiments, when sampling is not employed, the variable probability may be gradually increased over time and reset to zero or fixed to a small value once the control action is performed to reduce the average sampling rate to and/or limit the minimum sampling rate to be greater than a certain value.

43 is a flowchart illustrating an example method 5300 for varying the point at which resampling occurs in each resampling cycle, according to certain embodiments of the invention. Method 5300 varies this point by randomly (typically with equal probability) selecting a resampling point for each resampling cycle. Method 5300 begins at step 5310 where a resampling point is randomly selected for a resampling cycle. The resampling point may be chosen randomly, for example using a pseudo-random number generator. If, for example, resampling is performed at a rate of 1/32, the randomly selected resampling point can be any of the 32 points in the resampling cycle.

At step 5320, the signal is sampled at the selected resampling point. As discussed above, sampling at a selected resampling point may include sampling a number of data bits before, after, or around the selected point. For example, in a particular embodiment, 6 bits may be sampled, and the first bit may correspond to the selected point. It should be noted that sampling at selected resampling points may or may not effect control actions. For example, a control action may be enabled if a transition occurs in the sample, and may not be enabled if the transition does not occur in the sample. As another example, in certain embodiments where filter patterns are used, no control action may be taken if no suitable filter pattern is observed in the sample. If a certain filter pattern is observed in the sampling, control action can be taken. After the signal has been sampled at the selected resampling point in the cycle, method 5300 returns to step 5310 and a new resampling point is randomly selected for the next cycle. In this way, any locking of the resampling period with the period of the (quasi) periodic signal can be avoided.

44 is a flowchart illustrating another example method 5400 for varying the point at which resampling occurs in each resampling cycle, according to certain embodiments of the invention. For the resampling cycle following the resampling cycle in which the control action was taken, method 5400 varies the resampling point by randomly selecting the resampling point, generally with equal probability. Method 5400 begins at step 5410 where a resampling point is randomly selected for a resampling cycle. The resampling point may be chosen randomly, for example using a pseudo-random number generator. If, for example, resampling is performed at a rate of 1/32, the randomly selected resampling point can be any of the 32 points in the resampling cycle.

At step 5420, the signal is sampled at the selected resampling point. As discussed above, sampling at a selected resampling point may include sampling a number of data bits before, after, or around the selected point. Sampling at selected resampling points may or may not effect control actions. For example, a control action may be enabled if a transition occurs in the sample, and may not be enabled if the transition does not occur in the sample. As another example, in certain embodiments where filter patterns are used, no control action may be taken if no suitable filter pattern is observed in the sample. If a certain filter pattern is observed in the sampling, control action can be taken.

At step 5430, a determination is made as to whether a control action has been taken. If not, method 5400 returns to step 5420 and the signal is sampled at the selected resampling point in the next cycle. If at step 5430 it is determined that a control action has been taken (in the first or subsequent resampling cycle), method 5400 returns to step 5410 and a new resampling point is randomly selected. In this way, any locking of the resampling period with the period of the (quasi) periodic signal can be avoided.

It should be noted that in certain embodiments, control actions may be taken at different times for gain control and offset cancellation. Taking control actions at different times results in different rates at which resampling points are selected for gain control and offset cancellation. In certain embodiments, selected resampling points may be reset for gain control and offset cancellation when gain or offset is adjusted.

45 is a flowchart illustrating yet another example method 5500 for varying the point at which resampling occurs in each resampling cycle, according to certain embodiments of the invention. For the resampling cycle following the resampling cycle in which the control action was taken, method 5500 changes the resampling points by sequentially cycling through the entire list of resampling points. Method 5500 begins at step 5510 where the next resampling point in the list is selected for a resampling cycle. Note that this list of resampling points is not necessarily in order. For example, if resampling is performed at a rate of 1/32 and the previous resampling point is at the 13th point in the resampling cycle, then at step 5510 at the 4th point in the resampling cycle the next A resampling point.

At step 5520, the signal is sampled at the selected resampling point. As discussed above, sampling at a selected resampling point may include the process of sampling a number of data bits before, after, or around the selected point. Sampling at selected resampling points may or may not effect control actions. For example, a control action may be enabled if a transition occurs in the sample, and may not be enabled if the transition does not occur in the sample. As another example, in certain embodiments where filter patterns are used, no control action may be taken if no suitable filter pattern is observed in the sample. If a certain filter pattern is observed in the sampling, control action can be taken.

At step 5530, a determination is made whether a control action has been taken. If not, method 5500 returns to step 5520 and the signal is sampled at the selected resampling point in the next cycle. If at step 5530 it is determined that a control action has been taken (in the first or subsequent resampling cycle), method 5500 returns to step 5510 and the next resampling point is selected. Looping over the entire list of resampled points may introduce another level of locking: locking occurs between the entire period of traversal of the list of resampled points and the period of the (quasi-)periodic signal. However, since the overall period of traversing the list is much longer than the resampling period, the probability of locking between the resampling process and the period of the (quasi) periodic signal is effectively reduced.

It should be noted that in certain embodiments, control actions may be taken at different times for gain control and offset cancellation. Taking control actions at different times results in different rates at which resampling points are selected for gain control and offset cancellation. In certain embodiments, selected resampling points may be reset for both gain control and offset cancellation when gain or offset is adjusted.

It should also be noted that method 5100 includes a specific embodiment of method 5500 in which resampling is performed at a rate of 1/2, and that method 5200 includes a specific embodiment of method 5400 in which resampling is performed at a rate of 1/2 .

It should also be noted that in particular embodiments, methods 5300, 5400, and 5500 may be combined in various forms. For example, if resampling is performed at a rate of 1/32, the 32 possible resampling points can be hierarchically divided into 8 groups (4 resampling points per group). In a particular embodiment, method 5300 may be employed to select one of 8 possible groups of resampling points, and method 5400 may be employed to select one of 4 possible resampling points in each group.

It should also be noted that, in addition to adaptive gain control actions and/or offset cancellation based on sampling boundary values and/or one or more data values as described above in connection with FIGS. In addition to control, in certain embodiments, methods 5300, 5400, and 5500 may be applied to any other suitable control system that utilizes sampler outputs to prevent or mitigate a locking relationship between resampling processes and (quasi-)periodic signals . For example, in certain embodiments, these methods can be applied to conventional adaptive Equalizer control. In certain embodiments, these methods can also be applied to clock and data recovery (CDR) systems that adjust the recovered clock for the sampler based on the output of the sampler.

Modifications, additions, or omissions may be made to the systems and methods without departing from the scope of the present invention. Components of the systems and methods may be integrated or separated according to particular needs. Additionally, the operations of the systems and methods may be performed by more, fewer or other components.

As discussed above, an equalizer may utilize two or more control loops simultaneously to equalize a signal. For example, an equalizer may utilize adaptive equalizer controls to adjust gain and reduce residual intersymbol interference. The equalizer can also use the offset canceller at the same time to adjust the offset and cancel the residual offset.

One challenge that may arise from employing multiple control loops simultaneously is the coupling that may occur between the multiple control loops. Coupling between multiple control loops may delay the convergence time or even make the control loop unstable. For example, if the gain is optimal but the residual offset is suboptimal, then the boundary values may deviate towards high or low values (e.g. high if the residual offset is positive, and if the residual offset is negative, it is a low value). Equalizer gain controls may misinterpret deviating boundary values and/or other information as an overcompensation or undercompensation condition. If the counts of high and low data values for equalizer gain control are unbalanced, then misinterpretation of an overcompensated or undercompensated condition is also unbalanced, shifting the equalizer gain from optimal to suboptimal. In a similar manner, if the gain is suboptimal, the residual bias shifts from optimal to suboptimal.

In certain embodiments, multiple control loops may be decoupled by making these loops insensitive to each other. For example, the adaptive equalizer control can be made insensitive to residual offset, and the offset canceller can be made insensitive to residual intersymbol interference. In order to make the adaptive equalizer control and the offset canceller mutually insensitive, in a particular embodiment, the adaptive equalizer control and the offset canceller may use two sets of complementary data patterns in an unbalanced manner. Complementary data patterns may, for example, include those patterns that have different values of data values (eg, "0" or "1") at particular bits in the data pattern.

For example, where the control action is based on a comparison of a boundary value between successive data values comprising a transition with a data value 1.5 bits preceding the boundary value, the adaptive equalizer control and offset canceller may cause The number of control actions taken when the data value 1.5 bits before the boundary value is high or low is balanced. In a particular embodiment, the adaptive equalizer control and offset canceller may do so by alternately using a filter pattern with either a high data value or a low data value immediately preceding the data value comprising the transition filter mode. In this way, the adaptive equalizer control can be made insensitive (or less sensitive) to the residual offset, and the offset canceller can be made insensitive (or less sensitive) to the residual intersymbol interference, thereby Decouple multiple control loops. Particular embodiments of decoupling multiple control loops are described further below in conjunction with FIGS. 46 and 47 .

FIG. 46 is a flowchart illustrating an example method 5600 for decoupling multiple control loops in accordance with certain embodiments of the invention. Method 5600 can decouple an adaptive equalization controller from an offset canceller, eg, by using two sets of complementary data patterns in a balanced manner. Method 5600 can use two sets of complementary data patterns in a balanced manner by alternating between: monitoring for one set for incoming signals and taking control actions based on that one set; and then for the other set of pairs of incoming signals The signals of the other set are monitored and control actions are taken based on this other set. Where, for example, the control action is based on comparing a boundary value between consecutive data values comprising a transition with a data value 1.5 bits before the boundary value, the first set of data patterns may comprise a 1.5 bits preceding the boundary value with a high For those data patterns of data values (i.e., those data patterns with a high data value immediately preceding the data value comprising the transition), the second set of data patterns may include data patterns with a low data value 1.5 bits before the boundary value. Values of those data schemas (and vice versa).

Method 5600 begins at step 5610 . At this step, logic (eg, receiver logic 47 ) monitors the incoming signal for a first set of data patterns. For example, the logic may monitor the incoming signal for consecutive data values that include transitions where the data value immediately preceding the consecutive data value includes a low value. In certain embodiments, the logic may use a filter pattern for this monitoring. Suitable filter patterns may include, for example, the particular patterns illustrated and described above in connection with FIGS. At step 5620, if a data pattern in the first set of data patterns is detected, method 5600 proceeds to step 5630. If no data patterns in the first set of data patterns are detected, method 5600 returns to step 5610, whereupon the logic continues to monitor incoming signals for the first set of data patterns.

At step 5630, upon detection of a data pattern in the first set of data patterns, appropriate control action is taken. In a particular embodiment, the control action may be based, for example, on a comparison of a boundary value between consecutive data values comprising a transition with a data value 1.5 bits preceding the boundary value. The control action may be an adaptive equalizer action and/or an offset cancellation action. In certain embodiments the control action may also be based on a conventional adaptive control algorithm. After the control action is taken, method 5600 proceeds to step 5640 .

At step 5640, the logic monitors the incoming signal for a second set of data patterns. For example, the logic may monitor the incoming signal for consecutive data values that include transitions where the data value immediately preceding the consecutive data value includes a high value. In certain embodiments, the logic may use a filter pattern for this monitoring. Suitable filter patterns may include, for example, the particular patterns illustrated and described above in connection with FIGS. At step 5650, if a data pattern in the second set of data patterns is detected, method 5600 proceeds to step 5660. If no data patterns in the second set of data patterns are detected, method 5600 returns to step 5640, whereupon the logic continues to monitor incoming signals for the second set of data patterns.

At step 5660, upon detection of a data pattern in the second set of data patterns, appropriate control action is taken. In a particular embodiment, the control action may be based, for example, on a comparison of a boundary value between consecutive data values comprising a transition with a data value 1.5 bits preceding the boundary value. The control action may be an adaptive equalizer action and/or an offset cancellation action. In certain embodiments the control action may also be based on a conventional adaptive control algorithm. After the control action is taken, method 5600 returns to step 5610. By using two sets of complementary data patterns in a balanced manner, Method 5600 can decouple the adaptive equalizer control from the offset canceller. It should be noted that in order to avoid locking with the period of the (quasi-)periodic signal using alternating cycles of the two sets of data patterns, a randomizing equalizer can be used simultaneously (eg see methods 5300 to 5400 above).

47 is a flowchart illustrating another example method 5700 for decoupling multiple control loops in accordance with certain embodiments of the invention. Method 5700 can decouple adaptive equalization control from an offset canceller, eg, by using two sets of complementary data patterns in a balanced manner. Method 5700 can use these two sets of complementary data patterns in a balanced manner by randomly selecting one of the two sets with equal probability, monitoring incoming signals for the selected set, based on the The selected group takes the control action, followed by random selection of one of the two groups with equal probability. Where, for example, the control action is based on a comparison of a boundary value between consecutive data values comprising a transition with a data value 1.5 bits preceding the boundary value, the first set of data patterns may comprise a boundary value 1.5 bits preceding the boundary value having For those data patterns with high data values (i.e., those data patterns with a high data value immediately preceding the data value that includes the transition), the second set of data patterns may include data patterns with low data values 1.5 bits before the boundary value of those data patterns (and vice versa).

Method 5700 begins at step 5710 where logic (eg, receiver logic 47 ) selects one of two sets of complementary data patterns, typically with equal probability. The logic may select randomly, for example by using a pseudo-random number generator and associating one of the generated numbers with one group and another of the generated numbers with another group. one of these two groups. After one of the two sets of complementary data patterns is selected, method 5700 proceeds to step 5720 .

At step 5720 , if the selected group of data patterns is the first group (eg, a data pattern that includes a low data value immediately preceding a data value that includes a transition), method 5700 proceeds to step 5730 . If the selected group of data patterns is the second group (eg, a data pattern that includes a high data value immediately preceding the data value that includes the transition), method 5700 proceeds to step 5760 .

At step 5730, the logic monitors the incoming signal for a first set of data patterns. For example, the logic may monitor the incoming signal for consecutive data values that include transitions where the data value immediately preceding the consecutive data value includes a low value. In certain embodiments, the logic may use a filter pattern for this monitoring. Suitable filter patterns may include, for example, the particular patterns illustrated and described above in connection with FIGS.

At step 5740, if a data pattern in the first set of data patterns is detected, method 5700 proceeds to step 5750. If no data patterns in the first set of data patterns are detected, method 5700 returns to step 5730, whereupon the logic continues to monitor incoming signals for the first set of data patterns. At step 5750, upon detection of a data pattern in the first set of data patterns, appropriate control action is taken. In a particular embodiment, the control action may be based, for example, on a comparison of a boundary value between consecutive data values comprising a transition with a data value 1.5 bits preceding the boundary value. The control action may be an adaptive equalizer action and/or an offset cancellation action. In certain embodiments, the control action may also be based on a conventional adaptive control algorithm. After the control action is taken, method 5700 returns to step 5710 and randomly selects one of the two sets of complementary data patterns.

If the selected set of data patterns at steps 5710 and 5720 is the second set (eg, a data pattern comprising a high data value immediately preceding the data value comprising the transition), method 5700 proceeds to step 5760 . At step 5760, the logic monitors the incoming signal for a second set of data patterns. For example, the logic may monitor the incoming signal for consecutive data values that include transitions where the data value immediately preceding the consecutive data value includes a high value. In certain embodiments, the equalizer may use a filter pattern to perform this monitoring. Suitable filter patterns may include, for example, the particular patterns illustrated and described above in connection with FIGS.

At step 5770, if a data pattern in the second set of data patterns is detected, method 5700 proceeds to step 5780. If no data patterns in the second set of data patterns are detected, method 5700 returns to step 5760 and continues monitoring for incoming signals for the second set of data patterns. At step 5780, upon detection of a data pattern in the second set of data patterns, appropriate control action is taken. In a particular embodiment, the control action may be based, for example, on a comparison of a boundary value between consecutive data values comprising a transition with a data value 1.5 bits preceding the boundary value. The control action may be an adaptive equalizer action and/or an offset cancellation action. After the control action is taken, method 5700 returns to step 5710 and randomly selects one of the two complementary data patterns. By using two sets of complementary data patterns in a balanced manner, method 5700 can decouple the adaptive equalizer control from the offset canceller.

Modifications, additions, or omissions may be made to the systems and methods without departing from the scope of the present invention. Components of the systems and methods may be integrated or separated according to specific needs. Additionally, the operations of the systems and methods may be performed by more, fewer or other components.

As discussed above, logic (eg, receiver logic 47 ) may adjust the gain and/or offset applied to the incoming signal after certain data and boundary values are detected. In certain embodiments, gains and/or offsets may be applied in a stop-start control scheme.

In a stop-start control scheme, based on a binary target variable that takes one of two states "high" or "low" (for example, the binary forms ISI degree, EQ degree, or residual offset in the above description, or A binary form of residual amplitude error in Automatic Gain Control (AGC) systems (where a "high" state of this target variable may be due to a "high" value of a control variable and may be caused by a "low" value of a control variable cause a "low" state of the target variable) to adjust a control variable (eg, gain or offset). In this case, if the target variable indicates a "high" state, the control variable can be decreased, and if the target variable indicates a "low" state, the control variable can be increased.

In a conventional stop-start control system, such as an automatic gain control (AGC) system, a controlled variable, such as amplifier gain, is updated in a symmetrical manner such that an increase in the controlled variable has the same magnitude as a decrease in the controlled variable , this is because binary target variables (such as the residual amplitude error in binary form) carry only qualitative information. Therefore, when the same amount of increase and decrease is applied to the control variable, the control variable will remain at the same level on average and the control system will reach a state of equilibrium. It should be noted that if (in the same manner as ISI levels described above in connection with FIG. 6 ) binary target variables are assigned numerical values (for example, "+1" and "- 1”), the mean value of the binary target variable will converge to zero in the equilibrium state in the conventional start-stop control system.

A binary target variable having a zero mean value at equilibrium may be desirable in certain systems (eg, AGC systems). For example, if a binary target variable (such as residual amplitude error in binary form) is derived from the output of a comparator that directly compares an analog target variable (such as amplifier output amplitude) to a control target (such as a target level of amplitude) , then the optimal mean value of the binary target variable at equilibrium may naturally be zero, since the comparator is expected to generate the same amount of "+1" and "-1" when the simulated target variable is closest to the control target " output. This situation is quite common in the application of conventional stop-start control schemes, which therefore simply utilize symmetric updates to the control variables.

On the other hand, a binary target variable with zero mean value at equilibrium may not necessarily be optimal in a particular system. For example, the optimal average value of the ISI levels described above in connection with FIG. 6 may be greater or less than zero depending on various conditions such as channel loss and the incoming signal itself. In certain embodiments, the optimal average ISI level may be high for high loss channels and low for low loss channels. Also, by way of example only, the optimal average ISI degree may vary from -0.6 to +0.5. For another example, under optimal conditions that depend on various systematic errors in the residual offset measurement (e.g., uncancelled offset in the boundary sampler rather than the data sampler), the residual offset described above in connection with Figure 25 May be statistically inclined to be positive or negative. Therefore, a non-zero mean at equilibrium for a binary target variable may be useful in specific cases.

In a particular embodiment, by introducing asymmetric updates to the control variables as exemplified in the following set of equations, the mean value of a binary target variable (eg, ISI level) in a stop-start control system at equilibrium becomes not equal to zero. It should be noted, however, that the non-zero values can be used for any suitable control variable (e.g., control for the offset if the best residual offset is not zero) and under any suitable circumstances, not just said circumstances. Symmetrical start-stop control scheme. In the following formulas, K _p and K _n are the control step values for increasing and decreasing the control variable (such as equalizer gain), respectively, and N _p and N _n are the upward and downward values of the control variable per unit time in the equilibrium state, respectively The number of downward actions, A is the mean value of the binary target variable at equilibrium. Here, it is assumed that the binary target variable takes a value of "+1" or "-1" when the control variable is "high" or "low", respectively. It should be noted that _Np and _Nn are also the number of binary target variables having "low" and "high" states per unit time, respectively. As can be observed, the product of _Kp and _Np is equal to the product of _Kn and _Nn in the long run since the control variable should not change in equilibrium. It should also be noted that A can be made not equal to zero by making _Kp different from _Kn . For example, in a particular embodiment, A may be 0.2 when _Kp is 0.3 and _Kn is 0.2. It should be noted that A may have any value from -1 (when K _p =0 and K _n >0) to +1 (when K _p >0 and K _n =0). It should also be noted that A becomes zero when _Kp = _Kn > 0 (which is the case for conventional stop-start control schemes).

K _p ×N _p -K _n ×N _n =0

N _n ÷ N _p = K _p ÷ K _n

$\mathrm{<span\; class="notranslate">\; A</span>}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; N</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; N</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}}}{{\mathrm{<span\; class="notranslate">\; N</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; N</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}}}{{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}}}$

48 is a flowchart illustrating an example method 5800 for generating a particular average of a binary target variable (eg, ISI level, EQ level, or residual offset) at equilibrium, according to certain embodiments of the invention. The method begins at step 5810 where it is checked in any suitable manner, for example using the adaptive controller 102, whether the target variable is high or low. For example, in certain embodiments, by applying an anti-correlation function (or correlation function) or an XOR (or XNOR) operation to the boundary value between consecutive data values comprising a transition and the data values 1.5 bits before the boundary value, it is possible to Check whether the ISI level is "+1" or "-1", or you can check whether the EQ level is "high" or "low". In an alternative embodiment, a filter mode, such as certain ones of the modes described above in connection with Figures 6, 8, 10, 14, and 16, may be used for checking. For another example, using the tables described above in connection with Figures 25, 27, 29, 32, 34, 36, 38 and 40, it may be checked whether the residual offset is "positive" or "negative".

A determination is made at steps 5820 and 5830 whether a control variable (eg, equalizer gain) should be increased or decreased based on the high or low value of the target variable checked at step 5810 . For example, in a particular embodiment for equalizer gain control, if at step 5810 the ISI level is "-1" or the EQ level is "low", then it is determined to increase the equalizer gain and the method proceeds to step 5840. If the ISI level is “+1” or the EQ level is “high” at step 5810 , it is determined to decrease the equalizer gain, and the method proceeds to step 5850 . In an alternative embodiment using filter patterns, the particular filter pattern detected may determine whether the equalizer gain will be decreased or increased. As another example, in a particular embodiment for equalizer offset control, if at step 5810 the residual offset is "negative", then it is determined to increase the equalizer offset and the method then proceeds to step 5840 . If at step 5810 the residual offset is "positive", then it is determined to reduce the equalizer offset and the method proceeds to step 5850. In an alternative embodiment using filter patterns, the particular filter pattern detected may determine whether the equalizer offset will be decreased or increased.

At step 5840, after determining that the controlled variable is to be increased, the controlled variable is increased by Kp. For example, in a particular embodiment for equalizer gain control, the equalizer gain is increased by Kp. As another example, in a particular embodiment for equalizer offset control, the equalizer offset is increased by Kp. Method 5800 returns to step 5810 after the control variable is incremented.

At step 5850, after determining that the controlled variable is to be decreased, the controlled variable is decreased by Kn. For example, in a particular embodiment for equalizer gain control, the equalizer gain is reduced by Kn. As another example, in a particular embodiment for equalizer offset control, the equalizer offset is decreased by Kn. After the control variable is decreased, method 5800 returns to step 5810.

Unlike conventional stop-start control systems, K _p is not necessarily equal to K _n . On the contrary, _Kp can be made different from _Kn based on the following set of formulas using the parameter T which is the control target for the binary target variable in the equilibrium state. Any suitable value from -1 to +1 (not necessarily zero) may be chosen as T, and in a particular embodiment, the value of T may depend on various conditions associated with, for example, the bit error rate and may correspond to Optimal target value under these conditions. In alternative embodiments, the value of T may be fixed. In certain embodiments T may be associated with the ratio or difference between _Kp and _Kn . For example, in certain embodiments, the control target value T may comprise a target ratio (fixed or variable) of the frequency of detection of the target variable in the second state versus the first state.

K in the following formula is a common loop constant for the increase and decrease of the control variable, and is defined as the arithmetic mean of _Kp and _Kn . As can be observed, when _Kp =K×(1+T) and _Kn =K×(1−T), the mean value A of the binary target variable will converge to T in equilibrium.

_Kp =K×(1+T)

_Kn =K×(1-T)

$\frac{{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}}}{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; K</span>}<span\; class="notranslate">\; \&times;</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; T</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; K</span>}<span\; class="notranslate">\; \&times;</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; T</span>}<span\; class="notranslate">\; )</span>}{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; <figure-callout\; id="2"\; label="K"\; filenames="H071A9830820070620E000061.png,H071A9830820070620E000081.png"\; state="\{\{state\}\}">K</figure-callout></span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; K</span>}$

$\mathrm{<span\; class="notranslate">\; A</span>}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}}}{{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; K</span>}<span\; class="notranslate">\; \&times;</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; T</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; K</span>}<span\; class="notranslate">\; \&times;</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; T</span>}<span\; class="notranslate">\; )</span>}{\mathrm{<span\; class="notranslate">\; K</span>}<span\; class="notranslate">\; \&times;</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; T</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; K</span>}<span\; class="notranslate">\; \&times;</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; T</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; KT</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; K</span>}}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; T</span>}$

By employing a control target T that is not necessarily equal to zero, method 5800 can cause the average value of a binary target variable (e.g., degree of ISI, degree of equalization, residual offset, or other suitable target variable) to converge to a value that more appropriately corresponds to a particular condition. point. As discussed above, in certain embodiments, the control target T may be fixed. In alternative embodiments, the control target T may vary dynamically as a function of specified one or more variables.

49 is a flowchart illustrating an example method 5900 for dynamically generating a control objective for an average value of a binary objective variable (eg, ISI level) at equilibrium, according to certain embodiments of the invention. As discussed above, in certain embodiments, the optimal average ISI level may be high for high loss channels and low for low loss channels. Thus, in certain embodiments, it may be advantageous to have a control target of the mean value of a binary target variable (such as the degree of ISI or other suitable equalization degree) that varies with the value of the control variable (such as the equalizer gain setting ) and change dynamically.

Method 5900 begins at step 5910 where it is checked in any suitable manner using, for example, adaptive controller 102 whether the target variable is high or low. Steps 5910 to 5950 may be the same as the above steps 5810 to 5850, so they will not be described again. After increasing the control variable by K _p at step 5940 or decreasing it by K _n at step 5950 , method 5900 proceeds to step 5960 . At step 5960, a value for a control variable (eg, equalizer gain) is identified. At step 5970, the control target T and the control step size value _Kp are adjusted for the mean value of the binary target variable (e.g., ISI degree or other suitable equalization degree) based on the identified value for the control variable (e.g., equalizer gain) and K _n .

For example, in certain embodiments, the control target T may be adjusted to vary with a control variable (eg equalizer gain) within a fixed range. Merely as an example, when the value of the control variable is relatively high, the control target T may be set to +0.4, and when the value of the control variable is relatively low, the control target T may be set to -0.4. When the value of the control variable is between a relatively high value and a relatively low value, the control target T may be an interpolated value between +0.4 and -0.4. In this way, _Kp and _Kn can be dynamically generated from a control variable (eg equalizer gain) to generate an optimal average of a binary target variable (eg ISI degree) based on bit error rate.

In a particular embodiment, the control target T can be dynamically calculated as a function of the current value of a control variable (eg equalizer gain code) using the following set of formulas:

$\mathrm{<span\; class="notranslate">\; T</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; G</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; h</span>}}<span\; class="notranslate">\; \&times;</span>\frac{\mathrm{<span\; class="notranslate">\; G</span>}}{{\mathrm{<span\; class="notranslate">\; G</span>}}_{\mathrm{<span\; class="notranslate">\; C</span>}}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; L</span>}}<span\; class="notranslate">\; \&times;</span>\frac{{\mathrm{<span\; class="notranslate">\; G</span>}}_{\mathrm{<span\; class="notranslate">\; C</span>}}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; G</span>}}{{\mathrm{<span\; class="notranslate">\; G</span>}}_{\mathrm{<span\; class="notranslate">\; C</span>}}}<span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span>\mathrm{<span\; class="notranslate">\; G</span>}<span\; class="notranslate">\; <</span>{\mathrm{<span\; class="notranslate">\; G</span>}}_{\mathrm{<span\; class="notranslate">\; C</span>}}$

T(G)＝T _H ... G≥G _C

where G (eg, 0 to 126) is the current value of a control variable (eg, equalizer gain code, which represents the amount of frequency compensation applied by the equalizer). In addition, _TH (e.g. -1.0 to +1.0) is the T value for relatively high values of the control variable, T _L (e.g. -1.0 to +1.0) is the T value for relatively low values of the control variable, G _C (e.g. 0, 1, 2, 4, 8, 16, 32, 64) are the values of G at the corners of a function that have a flat T value when G is above the corner. An adaptive controller, such as adaptive controller 102, can utilize the dynamically computed T and the loop constant K (described above) to generate updated values for _Kp and _Kn . Method 5900 returns to step 5910 after T, _Kp , and _Kn are updated.

50 is a graph 6000 illustrating the results of applying an example control objective formula in equalizer gain control according to certain embodiments of the invention to dynamically generate an example control objective for the average value of a binary objective variable at equilibrium. The example control target formula is the formula listed above for T(G). As can be observed, when the current value G of the equalizer gain code is equal to zero, the control target T is equal to a relatively low gain value _TL . When G is between 0 and _GC , the control target T can be set as an interpolation value between _TL and a relatively high gain value _TH . When G is greater than G _C , the control target T is equal to _TH . It should be noted that in alternative embodiments, different control target formulations may be used, resulting in different graphs than those illustrated in graph 6000 . It should also be noted that while this discussion describes a control target for the average ISI level, the level of equalization can be described and targeted in other suitable ways (and not necessarily tracking the average ISI level).

In certain embodiments, the high frequency gain code G may be split into two or more paths of a multidimensional equalizer (eg, paths 101A through 101C above). For example, the adaptive controller 102 may convert the high frequency gain code G into a DC path gain code and a first order path gain code. The high frequency gain code G may be converted in any suitable manner (as described below in Figures 51 and 52).

51 is a table illustrating an example scheme 6100 for converting high frequency gain codes to DC path gain codes and first order path gain codes in accordance with certain embodiments of the invention. Column 6110 of scheme 6100 includes the value of the high frequency gain code G to be converted into a DC path gain code and a first order path gain code. Column 6120 includes values for DC path gain code G ₀ and column 6130 includes values for first order path gain code G ₁ . Each row 6140 includes a high frequency gain code (or range of high frequency gain codes) and corresponding DC path and first order path gain codes. It should be noted that in scheme 6100 , G ₀ MAX is the maximum value of the DC path gain code specified in a register in adaptive controller 102 . Furthermore, the maximum value of the first order path gain code is 63 in a particular embodiment.

52A and 52B are graphs illustrating the results of applying the example scheme 6100 of FIG. 51 for converting high frequency gain codes to DC path gain codes and first order path gain codes, according to certain embodiments of the invention. FIG. 52A is a graph 6200 illustrating DC path gain code as a function of high frequency gain code. FIG. 52B is a graph 6300 illustrating first order path gain code as a function of high frequency gain code. It should be noted that in alternative embodiments, a different conversion scheme than scheme 6100 may be employed, resulting in different graphs than those illustrated in graphs 6200 and 6300 .

Modifications, additions, or omissions may be made to the systems and methods without departing from the scope of the present invention. Components of the systems and methods may be integrated or separated according to particular needs. Additionally, the operations of the systems and methods may be performed by more, fewer or other components.

Although the invention has been described in terms of several embodiments, variations, modifications, alterations, changes and modifications may be suggested by those skilled in the art, and the present invention is intended to cover such changes, modifications, changes, changes and modifications as long as they fall within the scope of the appended claims. For example, although several embodiments have been illustrated and described in the context of gain control, alternative implementations may additionally or alternatively be implemented in the context of offset control or any other suitable control parameter, as appropriate. example. Although several embodiments have been illustrated and described in the context of offset control, alternative embodiments may additionally or alternatively be implemented in the context of gain control or any other suitable control parameter, as appropriate.

This application claims priority to US Provisional Application 35 U.S.C. §119(e) filed May 30, 2006, entitled "Adaptive Equalizer" (Serial No. 60/803,451).

Claims (12)

1. method that is used for conditioning signal, this method may further comprise the steps:

To take place signal before or after the distortion apply at the compensating for loss and damage of frequency dependent distortion and in the migration of DC bias distortion at least one to generate output signal;

Use clock signal, described output signal is sampled to generate a plurality of data values and boundary value;

At first group of data pattern, the value that monitoring is sampled;

In the value of being sampled, detect the data pattern in described first group of data pattern;

Based on one or more data value of sampling and boundary value of being associated with data pattern in detected described first group of data pattern, the described compensating for loss and damage that imposes on described signal and at least one in the described migration are regulated;

After in described compensating for loss and damage and the described migration at least one having been carried out regulate, at second group of data pattern, the value that monitoring is sampled;

In the value of being sampled, detect the data pattern in described second group of data pattern; And

Based on one or more data value of sampling and boundary value of being associated with data pattern in detected described second group of data pattern, the described compensating for loss and damage that imposes on described signal and at least one in the described migration are regulated,

Wherein, data pattern is represented predefined binarization mode,

And wherein:

Each data pattern in described first group of data pattern comprises the high data value at the certain bits place that is arranged in this data pattern; And

Each data pattern in described second group of data pattern comprises the low data value at the certain bits place that is arranged in this data pattern, and the described certain bits that wherein comprises described high data value in described first group of data pattern is corresponding to the described certain bits that comprises described low data value in described second group of data pattern.

2. method according to claim 1, wherein:

Each data pattern in described first group of data pattern comprises the transformation and the high data value before 1.5 positions of the boundary value between two continuous data values of the transformation that comprises this value of value; And

Each data pattern in described second group of data pattern comprises the transformation and the low data value before 1.5 positions of the boundary value between two continuous data values of the transformation that comprises this value of value.

3. method according to claim 1, wherein, described clock signal is associated with described output signal.

4. method that is used for conditioning signal, this method may further comprise the steps:

To take place signal before or after the distortion apply at the compensating for loss and damage of frequency dependent distortion and in the migration of DC bias distortion at least one to generate output signal;

Use clock signal, described output signal is sampled to generate a plurality of data values and boundary value;

Select one of first group of data pattern and second group of data pattern with random fashion;

At selected one group of data pattern, the value that monitoring is sampled;

In the value of being sampled, detect the data pattern in selected one group of data pattern;

Based on one or more data value of sampling and boundary value of being associated with data pattern in detected selected one group of data pattern, the described compensating for loss and damage that imposes on described signal and at least one in the described migration are regulated; And

After in described compensating for loss and damage and the described migration at least one having been carried out regulate, select one of described first group of data pattern and described second group of data pattern with random fashion, and repeat the step of monitoring, detection and the adjusting of front,

Wherein, data pattern is represented predefined binarization mode,

And wherein:

Each data pattern in described first group of data pattern comprises the high data value at the certain bits place that is arranged in this data pattern; And

Each data pattern in described second group of data pattern comprises the low data value at the certain bits place that is arranged in this data pattern, and the described certain bits that wherein comprises described high data value in described first group of data pattern is corresponding to the described certain bits that comprises described low data value in described second group of data pattern.

5. method according to claim 4, wherein:

Each data pattern in described first group of data pattern comprises the transformation and the high data value before 1.5 positions of the boundary value between two continuous data values of the transformation that comprises this value of value; And

Each data pattern in described second group of data pattern comprises the transformation and the low data value before 1.5 positions of the boundary value between two continuous data values of the transformation that comprises this value of value.

6. method according to claim 4, wherein, described clock signal is associated with described output signal.

7. adaptive equalizer, this adaptive equalizer comprises:

Equalizer, its be configured to take place signal before or after the distortion apply at the compensating for loss and damage of frequency dependent distortion and in the migration of DC bias distortion at least one to generate output signal;

Sampler, it is configured to:

Receive described output signal and clock signal;

Use described clock signal, described output signal is sampled to generate a plurality of data values and boundary value; With

Controller, it is configured to:

At first group of data pattern, the value that monitoring is sampled;

In the value of being sampled, detect the data pattern in described first group of data pattern;

Based on one or more data value of sampling and boundary value of being associated with data pattern in detected described first group of data pattern, the described compensating for loss and damage that imposes on described signal and at least one in the described migration are regulated;

After in described compensating for loss and damage and the described migration at least one having been carried out regulate, at second group of data pattern, the value that monitoring is sampled;

In the value of being sampled, detect the data pattern in described second group of data pattern; And

Based on one or more data value of sampling and boundary value of being associated with data pattern in detected described second group of data pattern, the described compensating for loss and damage that imposes on described signal and at least one in the described migration are regulated,

Wherein, data pattern is represented predefined binarization mode,

And wherein:

Each data pattern in described first group of data pattern comprises the high data value at the certain bits place that is arranged in this data pattern; And

Each data pattern in described second group of data pattern comprises the low data value at the certain bits place that is arranged in this data pattern, and the described certain bits that wherein comprises described high data value in described first group of data pattern is corresponding to the described certain bits that comprises described low data value in described second group of data pattern.

8. adaptive equalizer according to claim 7, wherein:

Each data pattern in described first group of data pattern comprises the transformation and the high data value before 1.5 positions of the boundary value between two continuous data values of the transformation that comprises this value of value; And

Each data pattern in described second group of data pattern comprises the transformation and the low data value before 1.5 positions of the boundary value between two continuous data values of the transformation that comprises this value of value.

9. adaptive equalizer according to claim 7, wherein, described clock signal is associated with described output signal.

10. adaptive equalizer, this adaptive equalizer comprises:

Equalizer, its be configured to take place signal before or after the distortion apply at the compensating for loss and damage of frequency dependent distortion and in the migration of DC bias distortion at least one to generate output signal;

Sampler, it is configured to:

Receive described output signal and clock signal;

Use described clock signal, described output signal is sampled to generate a plurality of data values and boundary value; With

Controller, it is configured to:

Select one of first group of data pattern and second group of data pattern with random fashion;

At selected one group of data pattern, the value that monitoring is sampled;

In the value of being sampled, detect the data pattern in selected one group of data pattern;

Based on one or more data value of sampling and boundary value of being associated with data pattern in detected selected one group of data pattern, the described compensating for loss and damage that imposes on described signal and at least one in the described migration are regulated; And

After in described compensating for loss and damage and the described migration at least one having been carried out regulate, select one of described first group of data pattern and described second group of data pattern with random fashion, and repeat the process of monitoring, detection and the adjusting of front,

Wherein, data pattern is represented predefined binarization mode,

And wherein:

Each data pattern in described first group of data pattern comprises the high data value at the certain bits place that is arranged in this data pattern; And

Each data pattern in described second group of data pattern comprises the low data value at the certain bits place that is arranged in this data pattern, and the described certain bits that wherein comprises described high data value in described first group of data pattern is corresponding to the described certain bits that comprises described low data value in described second group of data pattern.

11. adaptive equalizer according to claim 10, wherein:

Each data pattern in described first group of data pattern comprises the transformation and the high data value before 1.5 positions of the boundary value between two continuous data values of the transformation that comprises this value of value; And

Each data pattern in described second group of data pattern comprises the transformation and the low data value before 1.5 positions of the boundary value between two continuous data values of the transformation that comprises this value of value.

12. adaptive equalizer according to claim 10, wherein, described clock signal is associated with described output signal.

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