CN101079618A

CN101079618A - MOS pipe threshold extension circuit and threshold extension method

Info

Publication number: CN101079618A
Application number: CN 200710072227
Authority: CN
Inventors: 刘莹; 方倩; 方振贤
Original assignee: Heilongjiang University
Current assignee: Heilongjiang University
Priority date: 2007-05-21
Filing date: 2007-05-21
Publication date: 2007-11-28
Anticipated expiration: 2027-05-21
Also published as: CN101079618B

Abstract

The invention discloses a MOS pipe threshold expansion circuit and threshold expanding method, which consist of threshold identifier and inverter, wherein the threshold identifier contains NMOS pipe G10, PMOS pipe G11 and threshold identifier load; the inverter consists of PMOS pipe G12 and NMOS pipe G13. The invention can improve the starting distinguishability obviously, which is fit for FPGA, CPLD, semi-locking or full-locking ASIC and memory and other digital IC technical domain.

Description

Metal-oxide-semiconductor threshold spread circuit and threshold spread method

(1) technical field

The invention belongs to the digital integrated circuit technical field, be specifically related to a kind of metal-oxide-semiconductor threshold spread technology.

(2) background technology

Along with the develop rapidly of MOS integrated circuit technique, integrated scale is increasing, and integrated level is more and more higher, and some shortcomings appear in VLSI (very lagre scale integrated circuit (VLSIC)), and at first on the VLSI substrate, wiring but takies the silicon area more than 70%; In programmable logic device (as FPGA and CPLD), also need there be a large amount of interconnectors able to programme (to comprise the switch that is connected able to programme, as fuse-type switch, anti-fuse-type switch, floating boom programmed element etc.), each logic function block or I/O are coupled together, finish the circuit of specific function, wiring (comprising that programming connects switch) has accounted for the very big cost of material.The proportion that reduces wiring cost becomes important problems.To every line transmitting digital information, binary signal is to carry minimum a kind of of amount of information, and multi-valued signal carries and contains much information in binary signal, shows from the message transmission aspect, adopts multi-valued signal can reduce the line number.From the information stores aspect, adopt multi-valued signal can improve information storage density, particularly utilize metal-oxide-semiconductor grid capacitance stored information, same capacitance stores amount of information is many-valued bigger than two-value.The development of present many-valued device is extensively carried out, and Toshiba matches by the CMOS technology of 70nm and the many-valued technology of 2bit/ unit with Sandisk company, at 146mm ²Chip on realized the memory capacity of 8Gbit; The 8Gbit product of Samsung exploitation adopts the CMOS technology of 63nm and the many-valued technology of 2bit/ unit; Succeed in developing and the commercialization of 4 value memories is important steps of many-valued research, but needs the switching threshold V of control or change pipe _Tn, changing threshold method is to use multistage ion implantation technique in semiconductor fabrication process, or controls methods such as the amount of electrons control threshold value of the grid storage of swimming.

Prior art and existing problems:

The shortcoming of prior art control metal-oxide-semiconductor threshold value: 1. control the amplitude limited (because of ion implantation concentration is limited) of threshold value, unlatching resolution is low; And control the performance that threshold amplitude regular meeting changes metal-oxide-semiconductor in the technology, and for example the sharp increase that causes cutting off electric current is returned in the reduction of threshold voltage, and the adjustment of threshold voltage is to the performance and influential, the stable V of stability of pipe _TnExtremely important.To many-valued memory, the amount of electrons of injecting the grid that swims is a continually varying, needs the control of very fine ground, and each threshold voltage level does not still reach quasi-stationary state.Therefore practical at present voltage-type multivalued circuit is not more than 4 value circuit, and more multivalued circuit is used difficulty.2. can only control the amplitude of threshold value, can not change metal-oxide-semiconductor and open character (being＜t conducting) as change 〉=t conducting, and multivalued gate must have two kinds of metal-oxide-semiconductors of opening character, just can make the combinational circuit structure the simplest, for example 7 value not gates, 7 values move to right door and the circuit structure of 7 value followers should be identical, just threshold voltage and unlatching different in kind thereof.Yet only control the technology of threshold amplitude at present, make above-mentioned multivalued gate structural difference very big, complex structure influences its practicability.3. need to increase ion and inject extra operation, and can only in semiconductor fabrication process, control threshold value, not only increase process complexity, and can not behind semiconductor fabrication process, control threshold value, or threshold users is non-programmable by the user.

(3) summary of the invention

The present invention seeks to open metal-oxide-semiconductor threshold spread circuit and threshold spread method, it is based on conventional metal-oxide-semiconductor, come the diffused mos pipe threshold with metal-oxide-semiconductor threshold spread circuit, comprise that metal-oxide-semiconductor unlatching character is amplified, dwindled, changes to threshold value and resolution is opened in raising, by reference voltage V _RefThe metal-oxide-semiconductor threshold value of regulating.

The structure of metal-oxide-semiconductor threshold spread circuit of the present invention is: be made up of threshold discriminator and inverter two parts, threshold discriminator comprises NMOS pipe G ₁₀, PMOS manages G ₁₁With the threshold discriminator load, inverter comprises PMOS pipe G ₁₂With NMOS pipe G ₁₃NMOS pipe G in the threshold discriminator ₁₀With PMOS pipe G ₁₁Source electrode join, NMOS manages G ₁₀Drain electrode meet DC power supply V _DD, NMOS manages G ₁₀Grid meet outer input In1, PMOS manages G ₁₁Grid meet outer input In2, the threshold discriminator load is connected on PMOS pipe G ₁₁Drain electrode and ground between, PMOS manages G ₁₁Drain electrode be the output V of threshold discriminator _Out1, V _Out1Be connected to and be subjected to keyholed back plate G _T1Grid and inverter input; NMOS pipe G in the inverter ₁₃Grounded drain, PMOS manages G ₁₂Drain electrode meet another DC power supply V _D, PMOS manages G ₁₂With NMOS pipe G ₁₃Two grids be connected and be the inverter input; PMOS manages G ₁₂With NMOS pipe G ₁₃Two drain electrodes be connected and be the output V of inverter _Out0, V _Out0Be connected to and be subjected to keyholed back plate G _T0Grid.

Metal-oxide-semiconductor threshold spread circuit of the present invention also has some architectural features like this:

1, described outer input In1 is input voltage V _x, importing In2 outward is reference voltage V _Ref

2, described outer input In1 is reference voltage V _Ref, importing In2 outward is input voltage V _x

3, described threshold discriminator load is a resistance R ₁₀

4, described threshold discriminator load is current source I ₁₀

Metal-oxide-semiconductor threshold spread method of the present invention is:

1, setting threshold discriminator parameter is V _Extn1=V _Ref+ V _Tn+ | V _Tp|, threshold discriminator is pressed reference voltage V _RefTo signal input V _xDifferentiate the output V of threshold discriminator _Out1Accept keyholed back plate G _T1Grid is worked as V _x〉=V _Extn1The time, V _Out1Produce positive voltage control and be subjected to keyholed back plate G _T1Conducting makes to be subjected to keyholed back plate G _T1The numerical value of expanded threshold value is V _Extn1, be subjected to keyholed back plate G _T1The openability quality guarantee is held constant; V _Out1Connect the inverter input, inverter output V _Out0Accept keyholed back plate G _T0Grid is worked as V _x＜V _Extn1The time, V _Out0Produce positive voltage control and be subjected to keyholed back plate G _T0Conducting is subjected to keyholed back plate G _T0Unlatching character changes; Regulate reference voltage V _RefChange to change and be subjected to keyholed back plate G _T1The numerical value of expanded threshold value;

2, setting threshold discriminator parameter is V _Extn0=V _Ref-V _Tn-| V _Tp|, threshold discriminator is pressed signal input V _xTo reference voltage V _RefDifferentiate the output V of threshold discriminator _Out0Accept keyholed back plate G _T0Grid is worked as V _x＜V _Extn0The time, V _Out0Produce positive voltage control and be subjected to keyholed back plate G _T0Conducting makes to be subjected to keyholed back plate G _T0The numerical value of expanded threshold value is V _Extn0, be subjected to keyholed back plate G _T0Unlatching character changes; V _Out0Connect the inverter input, inverter output V _Out1Accept keyholed back plate G _T1Grid is worked as V _x〉=V _Extn0The time, V _Out1Produce positive voltage control and be subjected to keyholed back plate G _T1Conducting is subjected to keyholed back plate G _T1The openability quality guarantee is held constant; Regulate reference voltage V _RefChange to change and be subjected to keyholed back plate G _T1The numerical value of expanded threshold value.

Extended method of the present invention also has some technical characterictics like this:

1, reference voltage V _RefSatisfy V _DD〉=V _Ref〉=0, then NMOS manages G ₁₀Grid meet input voltage V _x, PMOS manages G ₁₁Grid meet reference voltage V _RefThe threshold spread circuit satisfy V _DD+ V _Tn+ | V _Tp| 〉=V _Extn1〉=V _Tn+ | V _Tp|; NMOS manages G ₁₀Grid meet reference voltage V _Ref, PMOS manages G ₁₁Grid meet input voltage V _xThe threshold spread circuit satisfy V _DD-V _Tn-| V _Tp| 〉=V _Extn0〉=-V _Tn-| V _Tp|; The range of choice of the expanded threshold value size during two kinds of metal-oxide-semiconductor threshold spread circuit associatings expands V to _DD+ V _Tn+ | V _Tp| and-V _Tn-| V _Tp| between.

The amplification of metal-oxide-semiconductor threshold spread circuit has improved unlatching resolution among the present invention.Metal-oxide-semiconductor threshold spread circuit signal (V _xAnd V _Ref) be the grid input, the wasted work rate that has that absorbs reference voltage source is almost 0, and reference voltage source adopts a string diode (or the resistance of a string high value and diode) to press voltage divider form composition, and it is very low to choose the reference voltage source operating current; If reference voltage V _RefSatisfy V _DD〉=V _Ref〉=0, then first kind of metal-oxide-semiconductor threshold spread circuit satisfies V _DD+ V _Tn+ | V _Tp| 〉=V _Extn1〉=V _Tn+ | V _Tp|, second kind of metal-oxide-semiconductor threshold spread circuit satisfies V _DD-V _Tn-| V _Tp| 〉=V _Extn0〉=-V _Tn-| V _Tp|; The range of choice of the expanded threshold value size during two kinds of metal-oxide-semiconductor threshold spread circuit associatings expands V to _DDV _Tn+ | V _Tp| and-V _Tn-| V _Tp| between.After the inverter input is received in threshold discriminator output, the control signal that forms in inverter output is opposite with the threshold discriminator output polarity, make the NMOS pipe of inverter output control and the unlatching incompatibility of the NMOS pipe that discriminator output is controlled thus, and the numerical value of expanded threshold value the two is identical.When two kinds of metal-oxide-semiconductor threshold spread circuit use in conjunction arrived multivalued circuit, the partial circuit heavy mutually to function can merge or leave out, even can select wherein useful partial circuit reservation by the function of concrete application need, left out the partial circuit that does not need function.

The concrete description of contents with detailed is as follows:

First kind of metal-oxide-semiconductor threshold spread circuit of the present invention shows as the empty frame in Fig. 1 left side, this circuit output V _Out0And V _Out1Receive controlled NMOS pipe G respectively _T0And G _T1Grid, make G _T0And G _T1Threshold spread (amplify, dwindle, change open character and improve and open resolution); Fig. 1 right side is the pipe G that is connected to the threshold spread circuit _T0And G _T1Symbol (be called and expand threshold type NMOS pipe).If V _DD〉=V _D〉=V _Tn+ | V _Tp|, because of V _Extn1=V _Ref+ V _Tn+ | V _Tp|, NMOS pipe and PMOS pipe threshold voltage are respectively V _Tn＞0 and V _Tp＜0.Manage G in the empty frame of Fig. 1 ₁₀And G ₁₁Grid the source potential difference is respectively V _Gs10And V _Gs11, work as V _Gs10〉=V _TnThe time G ₁₀Conducting; Work as V _Gs11≤ V _TpTime pipe G ₁₁Conducting.Because G ₁₀And G ₁₁Two source electrodes join, so only work as G ₁₀Grid voltage V _G10To G ₁₁Grid voltage V _G11Poor V _G10-V _G11〉=V _Tn+ | V _Tp| the time, G ₁₀And G ₁₁Just conducting simultaneously, otherwise G ₁₀And G ₁₁End simultaneously.Because of V _G10=V _x, V _G11=V _Ref, draw thus: 1. work as V _G10-V _G11=V _x-V _Ref〉=V _Tn+ | V _Tp|, i.e. input voltage V _x〉=V _Extn1The time, G ₁₀And G ₁₁Conducting, resistance R ₁₀Last voltage V _Out1Be high level V _OH, make G _T1Conducting; V _Out1After inverter is anti-phase, produce output V _Out0=0 volt, make G _T0End.2. work as V _x＜V _Extn1The time, G ₁₀And G ₁₁End resistance R ₁₀Voltage is V _Out10Volt makes G _T1End; V _Out1After the CMOS inverter is anti-phase, produce output V _Out0=V _D, make G _T0Conducting.Show thus, originally G _T0And G _T1All be to work as V _x〉=V _TnThe time conducting, behind the threshold spread circuit in figure shown in the empty frame, make G _T1Become V _x〉=V _Extn1The time conducting, make G _T0Become V _x＜V _Extn1The time conducting, also be G _T1And G _T0The threshold voltage size expand to V _Extn1, G _T0Unlatching character changes, G _T1Unlatching character is constant, in addition, because of the threshold spread circuit has amplification, opens resolution and improves, and promptly only needs less input voltage increment Delta V _x, just make G _T1And G _T0By by the end of conducting (otherwise or).Two class method for expressing are arranged: 1. expanded threshold value voltage representation (being beneficial to circuit test).As above-mentioned 〉=V _Extn1With＜V _Extn1, unit is volt; 2. normalization expanded threshold value representation (being beneficial to circuit design and theory analysis).Calculate V earlier _Extn1Normalized threshold t=V _Extn1(t is a ratio to/Δ, no unit; Stepped-up voltage Δ=V _{K '}/ K ', to K value circuit, high logic value K '=K-1, high logic level V _{K '}Near V _DD); At the right threshold type NMOS pipe G that expands of Fig. 1 _T1And G _T0Other its normalization expanded threshold value of mark respectively is 〉=t when t (input logic value x 〉=conducting) and＜t when t (x＜conducting).

Second kind of metal-oxide-semiconductor threshold spread circuit of the present invention shows that as Fig. 2 Fig. 2 circuit structure and Fig. 1 are identical, just with the V among Fig. 1 _xAnd V _RefExchange G _T0And G _T1Exchange V _Out0And V _Out1Exchange, because of V _Extn0=V _Ref-V _Tn-| V _Tp|.The same method draws: 1. work as V _Ref-V _x〉=V _Tn+ | V _Tp|, i.e. V _x≤ V _Extn0The time, V _Out0=V _OH, make G _T0Conducting; V _Out1=0 volt, make G _T1End.2. work as V _x＜V _Extn0The time, V _Out0=0 volt, make G _T0End; V _Out1=V _D, make G _T1Conducting.As hereinbefore, G _T1And G _T0Become V respectively _x〉=V _Extn0And V _x＜V _Extn0The time conducting.Calculate t=V _Extn0/ Δ is at the right G of Fig. 2 _T1And G _T0Other mark 〉=t respectively and＜t.

Two kinds of metal-oxide-semiconductor threshold spread circuit can be united use, and can partly or entirely save inverter wherein according to actual needs.Adopt metal-oxide-semiconductor threshold spread circuit can realize that T network expands any K value of threshold type (as 7 values door) circuit, comprise K value not gate, move to right door, follower and the door that moves to left (as 7 value not gates, move to right door, follower and move to left), wherein a K value not gate, the door that moves to right, follower (as 7 value not gates, move to right, follower) is identical, the door that moves to left is almost complete in (only changing a line), circuit structure is simple, easily conversion.Yet the door that moves to right in the existing multivalued circuit, not gate, the follower and the gate structure difference that moves to left are very big, and voltage-type MOS or BiCMOS multivalued circuit can not arrive seven values.

In order to realize MOS type or BiCMOS type seven value logical circuits, the reference voltage V that metal-oxide-semiconductor threshold spread circuit Fig. 1 and 2 is used _RefBe chosen as 1.9 volts, 3.1 volts, 4.1 volts (take from one group of series diode of lightly conducting state, the conducting electric current is about 1 μ A), the V of NMOS pipe _Tn=0.95 volt, output V _Out0And V _Out1The Pspice computer simulation show as Figure 16 and 17 V among Figure 16 (a-55), V (a-45), V (a-35), V (a-25), V (a-15), corresponding 6 V of V (a-05) respectively _Out0, being followed successively by of institute's expanded threshold value＜5.9 volts,＜4.75 volts,＜3.45 volts,＜2.5 volts,＜1.5 volts,＜0.55 volt.V among Figure 17 (ap55), V (ap45), V (ap35), V (ap25), V (ap15), corresponding 6 V of V (ap05) _Out1, being followed successively by of institute's expanded threshold value 〉=6.05 volts, 〉=4.8 volts, 〉=3.5 volts, 〉=2.7 volts, 〉=1.6 volts, 〉=0.6 volt.The absolute value of above-mentioned expanded threshold value is all between 6 pairs of adjacent logic levels.Among the figure only with three V _Ref, as increasing reference voltage V _RefNumber is regulated V separately _Ref, the numerical value that can make expanded threshold value is near the adjacent logic levels mid point.

It is sinusoidal signal a that Pspice computer simulation waveform Figure 20 goes up the 1st little figure most, and a is transported to the input of preposition seven value followers, and by its shaping, just the output at it forms seven value signal x (the 2nd little figure).If change the NMOS pipe threshold with multistage ion implantation technique, and constitute multivalued gate, then sinusoidal signal a needs the shaping of secondary multivalued gate, could form multi-valued signal; Show because of the threshold spread circuit has amplification, improved unlatching resolution, only need less input voltage increment Delta V _x, just make pipe by by the end of conducting (otherwise or).

Fig. 8 is the accurate mirror current source of many outputs of the ground connection used always, utilizes this current source, with ' the resistance R of ground connection in the threshold spread circuit diagram 1 ₁₀' usefulness ' the current source I of ground connection ₁₀' replace, the third is connected to current source I to draw the present invention shown in Figure 9 ₁₀The threshold spread circuit.Fig. 2 can do above-mentioned same replacement.Fig. 7 is the another kind of commonly used V that connects _DDThe accurate mirror current source of many outputs, utilize this current source, will ' meet V among Fig. 3 _DDResistance R ' with ' meeting V _DDCurrent source I ' replace, draw the seven value not gates that are connected to current source I shown in Figure 10.By same quadrat method, will ' meet V among Fig. 4, Fig. 5, Fig. 6 _DDResistance R ' use successively and ' meet V _DDCurrent source I ' replace, draw seven values that are connected to current source I separately and move to right that door, seven values move to left, seven value followers.

(4) description of drawings

Fig. 1 is the present invention's first kind of metal-oxide-semiconductor threshold spread circuit and graphical diagram;

Fig. 2 is the present invention's second kind of metal-oxide-semiconductor threshold spread circuit and graphical diagram;

Fig. 3 expands threshold type seven value not circuit figure for first kind of T network of the present invention;

Fig. 4 expands the threshold type seven values gate circuit figure that moves to right for T network of the present invention;

Fig. 5 expands the threshold type seven values gate circuit figure that moves to left for T network of the present invention;

Fig. 6 expands threshold type seven value follower circuit figure for T network of the present invention;

Fig. 7 is existing accurate mirror current source circuit diagram of output and graphical diagram more than first kind;

Fig. 8 is existing accurate mirror current source circuit diagram of output and graphical diagram more than second kind;

Fig. 9 is the present invention the third metal-oxide-semiconductor threshold spread circuit and graphical diagram;

Figure 10 expands threshold type seven value not circuit figure for second kind of T network of the present invention;

Figure 11 expands threshold type arbitrary value not circuit figure for first kind of T network of the present invention;

Figure 12 expands the threshold type arbitrary value gate circuit figure that moves to right for T network of the present invention;

Figure 13 expands the threshold type arbitrary value gate circuit figure that moves to left for T network of the present invention;

Figure 14 expands threshold type arbitrary value follower circuit figure for T network of the present invention;

Figure 15 expands threshold type arbitrary value not circuit figure for second kind of T network of the present invention;

Figure 16 is one of computer simulation oscillogram of threshold spread circuit diagram 1 of the present invention and Fig. 2;

Figure 17 is two of the computer simulation oscillogram of threshold spread circuit diagram 1 of the present invention and Fig. 2;

Figure 18 is for using current source I among threshold spread circuit diagram 1 of the present invention and Fig. 2 ₁₀Replace resistance R ₁₀After one of computer simulation oscillogram;

Figure 19 is for using current source I among threshold spread circuit diagram 1 of the present invention and Fig. 2 ₁₀Replace resistance R ₁₀After the computer simulation oscillogram two;

Figure 20 expands one of threshold type seven value gate circuit Fig. 3, computer simulation oscillogram of 4,5 and 6 for T network of the present invention;

Figure 21 expands among threshold type seven value gate circuit Fig. 3,4,5 and 6 with two of the computer simulation oscillogram after the current source I replacement resistance R for T network of the present invention.

(5) embodiment

The present invention is further illustrated below in conjunction with the drawings and specific embodiments:

Embodiment 1:T l network expands threshold type seven value not circuits

In conjunction with Fig. 3, present embodiment adopts 6 expansion threshold type NMOS pipe G _i(i=1,2,3,4,5,6), their grid meets input x through the threshold spread circuit; Pipe G ₁Source ground, other manages G ₂～G ₆Source electrode all meet lead-in wire g, g has two connected modes: g ground connection and g take over G ₁Drain electrode, seven value not gates are chosen g ground connection; Adopt 5 diode D _i(i=1,2,3,4,5), diode D _iNegative pole and positive pole connect successively and expand threshold type NMOS pipe G _iDrain electrode and expand threshold type NMOS pipe G _I+1Drain electrode; Expand threshold type NMOS pipe G ₆Drain electrode meet power supply V through overload _DD, and expanding threshold type NMOS pipe G ₆Drain electrode form 7 value not gates output y.The expansion threshold type NMOS pipe G of 7 value not gates _iThe normalization expanded threshold value press i=1,2,3,4,5,6 the order be taken as successively 〉=0.5, 〉=1.5, 〉=2.5, 〉=3.5, 〉=4.5, 〉=5.5.

Seven value not gates require: when input x was 6,5,4,3,2,1,0, output y was followed successively by 0,1,2,3,4,5,6.Fig. 3 expands threshold type NMOS pipe G _iThe normalization expanded threshold value press i=1,2,3,4,5,6 the order be followed successively by 〉=0.5, 〉=1.5, 〉=2.5, 〉=3.5, 〉=4.5, 〉=5.5, g ground connection; Fig. 3 satisfies the not gate requirement: 1. when x=6, and x 〉=5.5 then, G ₆Conducting, output y=0 (V _y=0 Δ); 2. when x=5, x 〉=4.5 then, G ₆End G ₅And D ₅Conducting, output y=1 (V _y=1 Δ); 3. when x=4, x 〉=3.5 then, G ₅, G ₆End G ₄And D ₄, D ₅Conducting, output y=2 (V _y=2 Δs); 4. when x=3, x 〉=2.5 then, G ₄～G ₆End G ₃And D ₃～D ₅Conducting, output y=3 (V _y=3 Δs); 5. when x=2, x 〉=1.5 then, G ₃～G ₆End G ₂And D ₂～D ₅Conducting, output y=4 (V _y=4 Δs); 6. when x=1, x 〉=0.5 then, G ₂～G ₆End G ₁And D ₁～G ₅Conducting, output y=5 (V _y=5 Δs); 7. when x=0, G then ₁～G ₆Do not satisfy turn-on condition, G ₁～G ₆All end output y=6 (V _yNearly 6 Δs select V _DDNearly 6 Δs).

Embodiment 2:T l network expands the threshold type seven values gate circuit that moves to right

Fig. 4 is identical with Fig. 3 structure, the seven values G among Fig. 4 that moves to right ₁～G ₆Expansion threshold type NMOS pipe G _iThe normalization expanded threshold value press i=1,2,3,4,5,6 the order be taken as successively＜4.5,＜3.5,＜2.5,＜1.5,＜0.5, 〉=5.5.

The requirement that moves to right of seven values: when input x was 6,0,1,2,3,4,5, an output z that moves to right was followed successively by 0,1,2,3,4,5,6.Fig. 4 expands threshold type NMOS pipe G _iThe normalization expanded threshold value press i=1,2,3,4,5,6 the order be followed successively by＜4.5,＜3.5,＜2.5,＜1.5,＜0.5, 〉=5.5.Fig. 4 satisfies to move to right and requires (1.～7. each tubulose attitude and not gate Fig. 3 are identical): 1. when x=6, and x 〉=5.5 then, G ₆Conducting, output z=0.2. when x=0, x＜0.5 then, G ₆End G ₅And D ₅Conducting, output z=1; 3. when x=1, x＜1.5 then, G ₅, G ₆End G ₄And D ₄, D ₅Conducting, output z=2; 4. when x=2, x＜2.5 then, G ₄～G ₆End G ₃And D ₃～D ₅Conducting, output z=3; 5. when x=3, x＜3.5 then, G ₃～G ₆End G ₂And D ₂～D ₅Conducting, output z=4; 6. when x=4, x＜4.5 then, G ₂～G ₆End G ₁And D ₁～G ₅Conducting, output z=5; 7. when x=5, G then ₁～G ₆Do not satisfy turn-on condition, G ₁～G ₆All end output z=6

Embodiment 3:T l network expands threshold type seven value follower circuits

Fig. 6 is identical with Fig. 3 structure, G among seven value follower Fig. 6 ₁～G ₆Expansion threshold type NMOS pipe G _iThe normalization expanded threshold value press i=1,2,3,4,5,6 the order be taken as successively＜5.5,＜4.5,＜3.5,＜2.5,＜1.5,＜0.5.

Seven value followers require: when input x was 0,1,2,3,4,5,6, output u still was followed successively by 0,1,2,3,4,5,6.Fig. 6 expands threshold type NMOS pipe G _iThe normalization expanded threshold value press i=1,2,3,4,5,6 the order be taken as successively＜5.5,＜4.5,＜3.5,＜2.5,＜1.5,＜0.5, g ground connection; Fig. 6 satisfies follower requirement (1.～7. each tubulose attitude and not gate Fig. 3 also are identical): 1. when x=0, and x＜0.5 then, G ₆Conducting, output u=0; 2. when x=1, x＜1.5 then, G ₆End G ₅And D ₅Conducting, output u=1; 3. when x=2, x＜2.5 then, G ₅, G ₆End G ₄And D ₄, D ₅Conducting, output u=2; 4. when x=3, x＜3.5 then, G ₄～G ₆End G ₃And D ₃～D ₅Conducting, output u=3; 5. when x=4, x＜4.5 then, G ₃～G ₆End G ₂And D ₂～D ₅Conducting, output u=4; 6. when x=5, x＜5.5 then, G ₂～G ₆End G ₁And D ₁～G ₅Conducting, output u=5; 7. when x=6, G then ₁～G ₆Do not satisfy turn-on condition, G ₁～G ₆All end output u=6.

Embodiment 4:T l network expands the threshold type seven values circuit that moves to left

(remove g and take over G in conjunction with Fig. 5 ₁Outside the drain electrode, Fig. 5 is identical with Fig. 3), the 7 values G among Fig. 5 that moves to left ₁～G ₆Expansion threshold type NMOS pipe G _iThe normalization expanded threshold value press i=1,2,3,4,5,6 the order be taken as successively 〉=0.5,＜5.5,＜4.5,＜3.5,＜2.5,＜1.5.

The requirement that moves to left of seven values: when input x was 1,2,3,4,5,6,0, output w was followed successively by 0,1,2,3,4,5,6.Fig. 5 expands threshold type NMOS pipe G _iThe normalization expanded threshold value press i=1,2,3,4,5,6 the order be taken as successively 〉=0.5,＜5.5,＜4.5,＜3.5,＜2.5,＜1.5, g takes over G ₁Drain electrode; Fig. 5 satisfies a requirement that moves to left: 1. when x=1, and x＜1.5 then, x 〉=0.5, G ₆, G ₁Conducting, output w=0; 2. when x=2, x＜2.5 then, x 〉=0.5, G ₆End G ₅, G ₁And D ₅Conducting, output w=1; 3. when x=3, x＜3.5 then, x 〉=0.5, G ₅, G ₆End G ₄, G ₁And D ₄, D ₅Conducting, output w=2; 4. when x=4, x＜4.5 then, x 〉=0.5, G ₄～G ₆End G ₃, G ₁And D ₃～D ₅Conducting, output w=3; 5. when x=5, x＜5.5 then, x 〉=0.5, G ₃～G ₆End G ₂, G ₁And D ₂～D ₅Conducting, output w=4; 6. when x=6, x 〉=0.5 then, G ₂～G ₆End G ₁And D ₁～D ₅Conducting, output w=5.7. when x=0, then do not satisfy x 〉=0.5, G ₁End output w=6.

Above-mentioned Fig. 3～6 specify as follows:

The input of Fig. 3～6 all is x, and their threshold spread circuit can be shared (by threshold spread size and character).The Pspice computer simulation is carried out in Fig. 3～6, draw analog waveform and show that as Figure 20 Figure 20 is followed successively by a, x from top to bottom, y, z, w, u be totally 6 waveforms, going up most the 1st little figure is sinusoidal signal a, earlier a is transported to the input of preposition seven value followers, forms seven value signal x by its output, waveform shows as the 2nd little figure.Again x is transported to simultaneously seven value not gates, seven values and moves to right that door, seven values move to left and seven value followers, the output of these 4 doors is followed successively by y, z, w, u shows respectively as the 3rd, the 4th, the the 5th, the 6 little figure, found out by these 4 little figure: y, z, w and u satisfy separately that seven value not gates, seven values move to right, seven values move to left and the requirement of seven value followers.Also can find out the effect of seven value followers: 1. shaping operation, as sinusoidal signal a (non-seven value signals) once is shaped as seven value signal x, opens resolution and improve.2. driving action promptly increases the fan-out coefficient.Actual seven value signals have 6 grades of ladders, are not the desirable ladder that waits, but require every grade of stairstep signal relativity shift of each output very little.

Waveform according to Figure 20 is measured x, y, and z, w, the logic levels at different levels of u are: 1. 0 level is followed successively by 0.019 volt, and 0.004 volt, 0.004 volt, 0.020 volt, 0.019 volt; 2. 1 level is followed successively by 0.91 volt, and 0.906 volt, 0.92 volt, 0.92 volt, 0.91 volt; 3. 2 level are followed successively by 1.928 volts, and 1.928 volts, 1.93 volts, 1.943 volts, 1.928 volts; 4. 3 level are followed successively by 3.025 volts, and 3.025 volts, 3.021 volts, 3.035 volts, 3.025 volts; 5. 4 level are followed successively by 4.158 volts, and 4.158 volts, 4.158 volts, 4.165 volts, 4.158 volts; 6. 5 level are followed successively by 5.31 volts, and 5.31 volts, 5.31 volts, 5.31 volts, 5.302 volts; 7. 6 level are followed successively by 6.94 volts, and 6.936 volts, 6.935 volts, 7.2 volts, 6.94 volts; Logic level relativity shifts at different levels very little (wherein desirable 〉=6.5 volt be 6 level).

Seven values that are connected to current source I the move to left Pspice computer simulation waveform of door, seven value followers of door, seven values that moves to right shows as Figure 21, is followed successively by a from top to bottom, x, and y, z, w, u be totally 6 waveforms, and obvious Figure 21 and Figure 20 are similar.Drawn by Figure 21: y, z, w and u satisfy seven value not gates, seven values and move to right that door, seven values move to left and the requirement of seven value followers.

Measure x according to the waveform among Figure 21, y, z, w, the logic levels at different levels of u are: 1. 0 level is followed successively by 0.019 volt, and 0.004 volt, 0.004 volt, 0.019 volt, 0.019 volt; 2. 1 level is followed successively by 0.91 volt, and 0.905 volt, 0.92 volt, 0.92 volt, 0.91 volt; 3. 2 level are followed successively by 1.952 volts, and 1.952 volts, 1.955 volts, 1.972 volts, 1.952 volts; 4. 3 level are followed successively by 3.16 volts, and 3.16 volts, 3.10 volts, 3.12 volts, 3.16 volts; 5. 4 level are followed successively by 4.33 volts, and 4.33 volts, 4.33 volts, 4.34 volts, 4.33 volts; 6. 5 level are followed successively by 5.61 volts, and 5.63 volts, 5.62 volts, 5.607 volts, 5.61 volts; 7. 6 level are followed successively by 7.125 volts, and 7.125 volts, 7.125 volts, 7.125 volts, 7.125 volts; Every grade of logic level relativity shift is all very little.

Embodiment 5:T l network expands the general gate circuit of threshold type arbitrary value (comprise arbitrary value value not gate, arbitrary value value door, arbitrary value value follower and the arbitrary value value door that moves to left that moves to right, identical circuit structure is arranged)

It is as follows that T network expands the general gate circuit electricity of threshold type structure: setting arbitrary value is the K value, K=3, and 4, Adopt the individual expansion threshold of K-1=K ' type NMOS pipe G _i, i=1,2,3 ..., K '; Expand threshold type NMOS pipe G _iGrid connect input x through the threshold spread circuit; Pipe G ₁Source ground, other manages G ₂～G _{K '}Source electrode all meet lead-in wire g, g has two connected modes: g ground connection and g take over G ₁Drain electrode; Adopt K '-1 diode D _i, i=1,2,3 ..., K '-1, D _iNegative pole and positive pole be connected successively and expand threshold type NMOS pipe G _iDrain electrode and expand threshold type NMOS pipe G _I+1Drain electrode; Expand threshold type NMOS pipe G _{K '}Drain electrode meet power supply V through overload _DD, and expanding threshold type NMOS pipe G _{K '}Drain electrode form the general door output of arbitrary value;

K value not gate (referring to Figure 11), its expansion threshold type NMOS pipe G _iThe normalization expanded threshold value press i=1,2,3 ..., K '-1, K ' order is taken as successively 〉=and 0.5, 〉=1.5, 〉=2.5 ..., 〉=K '-2.5, 〉=K '-1.5, 〉=K '-0.5, g ground connection, general door is output as not gate output y;

The K value moves to right (referring to Figure 12), its expansion threshold type NMOS pipe G _iThe normalization expanded threshold value press i=1,2,3 ..., K '-1, K ' order is taken as＜K '-1.5 successively,＜K '-2.5,＜K '-3.5 ...,＜1.5,＜0.5, 〉=K '-0.5, g ground connection, general door is output as an output z that moves to right;

K value follower (referring to Figure 14), its expansion threshold type NMOS pipe G _iThe normalization expanded threshold value press i=1,2,3 ..., K '-1, K ' order is taken as＜K '-0.5 successively,＜K '-1.5,＜K '-2.5 ...,＜2.5,＜1.5,＜0.5, g ground connection, general door is output as follower output u;

The K value moves to left (referring to Figure 13), its expansion threshold type NMOS pipe G _iThe normalization expanded threshold value press i=1,2,3 ..., K '-1, K ' order is followed successively by 〉=and 0.5,＜K '-0.5,＜K '-1.5,＜K '-2.5 ...,＜3.5,＜2.5,＜1.5, g takes over G ₁Drain electrode, general door are output as an output w that moves to left.

Present embodiment concrete as follows with detailed description of contents:

(1) a K value requirement that moves to right: when input x be K ', 0,1,2 ... K '-3, K '-2, K '-1 o'clock, the output z that moves to right is followed successively by 0,1,2,3 ... K '-2, K '-1, K '.Figure 12 expands threshold type NMOS pipe G _iThe normalization expanded threshold value be followed successively by in order＜K '-1.5,＜K '-2.5,＜K '-3.5 ...,＜1.5,＜0.5, 〉=K '-0.5, g ground connection, Figure 12 satisfies a requirement that moves to right: 1. when x=K ' time, x 〉=K '-0.5 then, G _{K '}Conducting, output z=0 (V _Z=0 Δ); 2. when x=0, x＜0.5 then, G _{K '}End G _{K '-1}And D _{K '-1}Conducting, output z=1 (V _ZNearly 1 Δ); 3. when x=1, x＜1.5 then, G _{K '-1}, G _{K '}End G _{K '-2}And D _{K '-2}, D _{K '-1}Conducting, output z=2 (V _ZNearly 2 Δs); 4. when x=2, x＜2.5 then, G _{K '-2}～G _{K '}End G _{K '-3}And D _{K '-3}～D _{K '-1}Conducting, output z=3 (V _ZNearly 3 Δs); 5. when x=K '-4, x＜K '-3.5 then, G ₄～G _{K '}End G ₃And D ₃～D _{K '-1}Conducting, output z=K '-3 (V _ZNear (K '-3) Δ); 6. when x=K '-3, x＜K '-2.5 then, G ₃～G _{K '}End G ₂And D ₂～D _{K '-1}Conducting, output z=K '-2 (V _yNear (K '-2) Δ); 7. when x=K '-2, x＜K '-1.5 then, G ₂～G _{K '}End G ₁And D ₁～D _{K '-1}Conducting, output z=K '-1 (V _ZNear (K '-1) Δ); 8. when x=K '-1, G then ₁～G _{K '}Do not satisfy turn-on condition, G ₁～G _{K '}All end output z=K ' (V _ZNearly K ' Δ selects V _DDNearly K ' Δ).

(2) K value not gate requires: when input x be K ', K '-1, K '-2, K '-3 ... 3,2,1,0 o'clock, not gate output y is followed successively by 0,1,2,3 ... K '-3, K '-2, K '-1, K '.Figure 11 pipe G _iThe normalization expanded threshold value be followed successively by in order 〉=0.5, 〉=1.5, 〉=2.5 ..., 〉=K '-2.5, 〉=K '-1.5, 〉=K '-0.5, g ground connection, Figure 11 satisfies the not gate requirement: 1. when x=K ' time, x 〉=K '-0.5 then, G _{K '}Conducting, output y=0; 2. when x=K '-1, x 〉=K '-1.5 then, G _{K '}End G _{K '-1}And D _{K '-1}Conducting, output y=1; 3. when x=K '-2, x 〉=K '-2.5 then, G _{K '-1}, G _{K '}End G _{K '-2}And D _{K '-2}, D _{K '-1}Conducting, output y=2; 4. when x=K '-3, x 〉=K '-3.5 then, G _{K '-2}～G _{K '}End G _{K '-3}And D _{K '-3}～D _{K '-1}Conducting, output y=3; 5. when x=3, x 〉=2.5 then, G ₄～G _{K '}End G ₃And D ₃～D _{K '-1}Conducting, output y=K '-3; 6. when x=2, x 〉=1.5 then, G ₃～G _{K '}End G ₂And D ₂～D _{K '-1}Conducting, output y=K '-2; 7. when x=1, x 〉=0.5 then, G ₂～G _{K '}End G ₁And D ₁～G _{K '-1}Conducting, output y=K '-1; 8. when x=0, G then ₁～G _{K '}Do not satisfy turn-on condition, G ₁～G _{K '}All end output y=K '.

(3) K value follower requires: when input x be 0,1,2,3 ... K '-3, K '-2, K '-1, K ' time, follower output y is followed successively by 0,1,2,3 ... K '-3, K '-2, K '-1, K '.Figure 14 pipe G _iThe normalization expanded threshold value be followed successively by in order＜K '-0.5,＜K '-1.5,＜K '-2.5 ...,＜2.5,＜1.5,＜0.5, g ground connection, Figure 14 satisfies the follower requirement: 1. when x=0, x＜0.5 then, G _{K '}Conducting, output u=0; 2. when x=1, x＜1.5 then, G _{K '}End G _{K '-1}And D _{K '-1}Conducting, output u=1; 3. when x=2, x＜2.5 then, G _{K '}, G _{K '-1}End G _{K '-2}And D _{K '-2}, D _{K '-1}Conducting, output u=2; 4. when x=3, x＜3.5 then, G _{K '-2}～G _{K '}End G _{K '-3}And D _{K '-3}～D _{K '-1}Conducting, output u=3; 5. when x=K '-3, x＜K '-2.5 then, G ₄～G _{K '}End G ₃And D ₃～D _{K '-1}Conducting, output u=K '-3; 6. when x=K '-2, x＜K '-1.5 then, G ₃～G _{K '}End G ₂And D ₂～D _{K '-1}Conducting, output y=K '-2; 7. when x=K '-1, x＜K '-0.5 then, G ₂～G _{K '}End G ₁And D ₁～D _{K '-1}Conducting, output u=K '-1; 8. when x=K ' time, G then ₁～G _{K '}Do not satisfy turn-on condition, G ₁～G _{K '}All end output u=K '.

(4) a K value requirement that moves to left: when input x be 1,2,3,4 ... K '-2, K '-1, K ', 0 o'clock, the output w that moves to left is followed successively by 0,1,2,3 ... K '-3, K '-2, K '-1, K '.Figure 13 pipe G _iThe normalization expanded threshold value be followed successively by in order 〉=0.5,＜K '-0.5,＜K '-1.5,＜K '-2.5 ...,＜3.5,＜2.5,＜1-5, g takes over G ₁Drain electrode, Figure 13 satisfies a requirement that moves to left: 1. when x=1, x＜1.5 then, x 〉=0.5, G _{K '}And G ₁Conducting, output w=0; 2. when x=2, x＜2.5 then, x 〉=0.5, G _{K '}End G _{K '-1}, G ₁And D _{K '-1}Conducting, output w=1; 3. when x=3, x＜3.5 then, x 〉=0.5, G _{K '}, G _{K '-1}End G _{K '-2}, G ₁And D _{K '-2}, D _{K '-1}Conducting, output w=2; 4. when x=4, x＜4.5 then, x 〉=0.5, G _{K '-2}～G _{K '}End G _{K '-3}, G ₁And D _{K '-3}～D _{K '-1}Conducting, output w=3; 5. when x=K '-2, x＜K '-1.5 then, x 〉=0.5, G ₄～G _{K '}End G ₃, G ₁And D ₃～D _{K '-1}Conducting, output w=K '-3; 6. when x=K '-1, x＜K '-0.5 then, x 〉=0.5, G ₃～G _{K '}End G ₂, G ₁And D ₂～D _{K '-1}Conducting, output w=K '-2; 7. when x=K ' time, x 〉=0.5 then, G ₂～G _{K '}End G ₁And D ₁～D _{K '-1}Conducting, output w=K '-1; 8. when x=0, then do not satisfy x 〉=0.5, G ₁End output w=K '.K value gate circuit verification method and aforementioned seven value gate circuits are similar, and available mathematical induction proof satisfies: y is the non-of x, and z is moving to right of x, and u is following of x, and w is moving to left of x.The present invention extends to seven values, any K value trigger and sequence circuit.

Claims

1, a kind of metal-oxide-semiconductor threshold spread circuit is characterized in that it is made up of threshold discriminator and inverter two parts, and threshold discriminator comprises NMOS pipe G ₁₀, PMOS manages G ₁₁With the threshold discriminator load, inverter comprises PMOS pipe G ₁₂With NMOS pipe G ₁₃NMOS pipe G in the threshold discriminator ₁₀With PMOS pipe G ₁₁Source electrode join, NMOS manages G ₁₀Drain electrode meet DC power supply V _DD, NMOS manages G ₁₀Grid meet outer input In1, PMOS manages G ₁₁Grid meet outer input In2, the threshold discriminator load is connected on PMOS pipe G ₁₁Drain electrode and ground between, PMOS manages G ₁₁Drain electrode be the output V of threshold discriminator _Out1, V _Out1Be connected to and be subjected to keyholed back plate G _T1Grid and inverter input; NMOS pipe G in the inverter ₁₃Grounded drain, PMOS manages G ₁₂Drain electrode meet another DC power supply V _D, PMOS manages G ₁₂With NMOS pipe G ₁₃Two grids be connected and be the inverter input; PMOS manages G ₁₂With NMOS pipe G ₁₃Two drain electrodes be connected and be the output V of inverter _Out0, V _Out0Be connected to and be subjected to keyholed back plate G _T0Grid.

2, according to claim 1 described a kind of metal-oxide-semiconductor threshold spread circuit, it is characterized in that: described outer input In1 is input voltage V _x, importing In2 outward is reference voltage V _Ref

3, according to claim 1 described a kind of metal-oxide-semiconductor threshold spread circuit, it is characterized in that: described outer input In1 is reference voltage V _Ref, importing In2 outward is input voltage V _x

4, according to claim 1 or 2 or 3 described a kind of metal-oxide-semiconductor threshold spread circuit, it is characterized in that: described threshold discriminator load is a resistance R ₁₀

5, according to claim 1 or 2 or 3 described a kind of metal-oxide-semiconductor threshold spread circuit, it is characterized in that: described threshold discriminator load is current source I ₁₀

6, a kind of metal-oxide-semiconductor threshold spread method, it is characterized in that: setting threshold discriminator parameter is V _Extn1=V _Ref+ V _Tn+ | V _Tp|, threshold discriminator is pressed reference voltage V _RefTo signal input V _xDifferentiate the output V of threshold discriminator _Out1Accept keyholed back plate G _T1Grid is worked as V _x〉=V _Extn1The time, V _Out1Produce positive voltage control and be subjected to keyholed back plate G _T1Conducting makes to be subjected to keyholed back plate G _T1The numerical value of expanded threshold value is V _Extn1, be subjected to keyholed back plate G _T1The openability quality guarantee is held constant; V _Out1Connect the inverter input, inverter output V _Out0Accept keyholed back plate G _T0Grid is worked as V _x＜V _Extn1The time, V _Out0Produce positive voltage control and be subjected to keyholed back plate G _T0Conducting is subjected to keyholed back plate G _T0Unlatching character changes; Regulate reference voltage V _RefChange to change and be subjected to keyholed back plate G _T1The numerical value of expanded threshold value.

7, a kind of metal-oxide-semiconductor threshold spread method, it is characterized in that: setting threshold discriminator parameter is V _Extn0=V _Ref-V _Tn-| V _Tp|, threshold discriminator is pressed signal input V _xTo reference voltage V _RefDifferentiate the output V of threshold discriminator _Out0Accept keyholed back plate G _T0Grid is worked as V _x＜V _Extn0The time, V _Out0Produce positive voltage control and be subjected to keyholed back plate G _T0Conducting makes to be subjected to keyholed back plate G _T0The numerical value of expanded threshold value is V _Extn0, be subjected to keyholed back plate G _T0Unlatching character changes; V _Out0Connect the inverter input, inverter output V _Out1Accept keyholed back plate G _T1Grid is worked as V _x〉=V _Extn0The time, V _Out1Produce positive voltage control and be subjected to keyholed back plate G _T1Conducting is subjected to keyholed back plate G _T1The openability quality guarantee is held constant; Regulate reference voltage V _RefChange to change and be subjected to keyholed back plate G _T1The numerical value of expanded threshold value.

8. according to claim 6 or 7 described a kind of metal-oxide-semiconductor threshold spread methods, it is characterized in that: reference voltage V _RefSatisfy V _DD〉=V _Ref〉=0, then NMOS manages G ₁₀Grid meet input voltage V _x, PMOS manages G ₁₁Grid meet reference voltage V _RefThe threshold spread circuit satisfy V _DD+ V _Tn+ | V _Tp| 〉=V _Extn1〉=V _Tn+ | V _Tp|; NMOS manages G ₁₀Grid meet reference voltage V _Ref, PMOS manages G ₁₁Grid meet input voltage V _xThe threshold spread circuit satisfy V _DD-V _Tn-| V _Tp| 〉=V _Extn0〉=-V _Tn-| V _Tp|; The range of choice of the expanded threshold value size during two kinds of metal-oxide-semiconductor threshold spread circuit associatings expands V to _DD+ V _Tn+ | V _Tp| and-V _Tn-| V _Tp| between.