CN101076944A - Symmetrical time-voltage transfer circuit - Google Patents
Symmetrical time-voltage transfer circuit Download PDFInfo
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- CN101076944A CN101076944A CNA2005800427044A CN200580042704A CN101076944A CN 101076944 A CN101076944 A CN 101076944A CN A2005800427044 A CNA2005800427044 A CN A2005800427044A CN 200580042704 A CN200580042704 A CN 200580042704A CN 101076944 A CN101076944 A CN 101076944A
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- 101150025634 CTT1 gene Proteins 0.000 claims abstract description 11
- 230000010354 integration Effects 0.000 claims description 8
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- 239000003990 capacitor Substances 0.000 claims description 3
- 230000001276 controlling effect Effects 0.000 claims 1
- 230000002596 correlated effect Effects 0.000 claims 1
- 230000000875 corresponding effect Effects 0.000 claims 1
- 238000006243 chemical reaction Methods 0.000 abstract description 12
- 230000007704 transition Effects 0.000 description 7
- 230000003068 static effect Effects 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 4
- 229940124913 IPOL Drugs 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000007812 deficiency Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000007493 shaping process Methods 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 241000169413 Lemodes Species 0.000 description 1
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- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
Abstract
The invention relates to a time/voltage conversion circuit, comprising two simple time/voltage converters (CTT1 and CTT2), which are structurally-identical to each other, each having an input receiving a respective logic control signal (Up and Dwn) and an output providing a corresponding voltage representative of the duration of the logic control signal (Vup and Vdwn) and a differentiator block (BE2) with positive (302) and negative (304) inputs, each connected to a relevant simple converter (CTT1 et CTT2) and an output, providing a signal (Vdiff) representing the voltage difference between the two control signals (Up and Dwn). The output (Vdiff) from the differentiator block (BE2) is connected to an integrator block (BE3).
Description
The present invention relates to the conversion of time, hereinafter referred to as time-voltage transitions to voltage.
The present invention is applied to accurately to generate based on the reference clock of extremely high frequency (it is conspicuous generally to be higher than 1G) electronic circuit of phase shifted clock (horloges d é phas é es).
Therefore, the present invention is applied to phase locked loop system, be also referred to as " PLL " (Phase LockedLoop, the phase-locked loop) or " DLL " (Delay Locked Loop, lock prolongs the loop, delay locked loop), in phase locked loop system, the deviation of time accurately need be converted to the voltage that is directly proportional.
The conventional architectures of phase locked loop system is a charge pump, the English charge pump that claims.Usually, charge pump generates the voltage of the difference that is proportional to described two signal durations based on two logical signals (being also referred to as Up (increasing) or Down (subtracting)).Described difference is stored with by the time integration.
Such as, described logical signal Up and Down are the control signal that phase detectors send, and are the pictures of wishing phase difference between two clock signals of perfect synchronization.When described two clock signals were not synchronous as yet, the duration of described signal Up and Down was different.Described just duration difference then by the time integration, thereby is revised deviation by negative feedback loop for will be converted to the voltage that is directly proportional.
With reference to figure 1, the change-over circuit 2 that prior art provides comprises two switches 4 and 24.Described switch 4 comprises the control input 6 of received signal Up, the input branch road 8 that links to each other with current source 10 and output branch road 14.Described current source 10 is connected to positive power supply terminal 12.Described switch 24 comprises control input 26, the input branch road 34 of received signal Dwn and is connected to the output branch road 28 of current source 30.Described current source 30 is connected to power supply terminal 32 (the earth).The output branch road 14 of described switch 4 links to each other by node 36 with the input branch road 34 of described switch 24.The terminal 38 of electric capacity 40 links to each other with described node 36.The another terminal 42 of described electric capacity 40 links to each other with the output of described current source 30.
When the electric current I up of described two current sources 10 and 30 equates fully with Idwn, the voltage that described switch 4 and the difference of 24 duration of closing show as described electric capacity 40 two ends rises or voltage drop, because one of described switch 4 is opened between a moment, and another switch 24 cuts out (vice versa).So the pressure reduction of described electric capacity 40 records is proportional to duration poor of described signal Up and Dwn.Use this structure, therefore described time-voltage transitions and integration have been realized simply compactly, but its precision is very low.
Described low precision comes from the mismatch (desappariement) that many places exist in this structure of prior art.
Define two types mismatch.First kind becomes static mismatch (DS, d é sappariementstatique), and it is corresponding to the skew of voltage on the described electric capacity 40 when the duration of described logical signal Up and Dwn is identical.In fact it reflect poor between described electric current I up and the Idwn, and described difference comes from the mismatch of described current source 10 and 30.It is asymmetric that described difference mainly comes from described current source 10 and 30 structures, and one is realized by nmos pass transistor, and another is realized by the PMOS transistor.So obtain different output resistances and bias voltage.And because incoherent technique variation, the compensation of regulating by simulation can not guarantee the usefulness that compensates.
Second kind of mismatch is dynamic mismatch (DD, d é sappariement dynamique), and it is corresponding to the jump of the voltage that observes on the described electric capacity 40 when described logical signal Up and the Dwn conversion.Identical with described static mismatch, described error comes from described current source 10 and 30 structures different, especially, even make the transistor drain of current source Iup10 and Idwn30 and source electrode surface equate that described node 8 is also different with the electric capacity on 28.And because described transistor NMOS is different with PMOS place mobility of charge carrier rate, the recovery time at described node 8 and 28 places, (temps de recouvrement) was asymmetric.
And when this traditional structure was used for extremely high frequency, the contribution of described dynamic mismatch became big with respect to other error, because it occupies the longer duration relatively in the clock cycle.And described dynamic mismatch DD can not accurately be compensated.
The variation of the voltage of the control by reducing described node 8 and 28 places and described switch 4 and 24 can improve foregoing prior art constructions.
Can also replace described integrating capacitor 40 with active circuit, described active circuit has amplifier and electric capacity, and described amplifier and described electric capacity are installed with negative feedback type between the output of the negative input of described amplifier and described amplifier.Therefore such active circuit can keep the output potential of described current source constant and reduced described static mismatch.
Other solution is especially in document US 5,508,660 and EP 0 647 032 in provide.
In these documents, provided a kind of structure, according to this structure, the difference between described electric current I up and the Idwn is read by duplicate circuit (circuit de replique), described duplicate circuit and described main circuit are worked under same condition, so have same error.Described error obtains using in compensation circuit by putting upside down its polarity, and described loop is inserted between the bias voltage of the output of described charge pump and described current source transistor.
Such structure is only eliminating static mismatch, thereby is unsuitable for very high frequency, because described dynamic mismatch is not revised.In fact, described structure exists the structure between described current source Iup and the Idwn asymmetric in traditional charge pump always based on traditional charge pump, because described current source is made of dissimilar transistor (NMOS and PMOS).
Also know a kind of differential configuration, described as following document: " (A 500MHzMP/DLL Clock Generator for a 5Gb/s Backplane Transceiver in0.25 μ m CMOS ", ISCC 2003, author: Gu-Yeon Wei, John T.Stonick, Dan Weinlader, Jeff Sonntag and Shawn Searles.
With reference to figure 2, described circuit comprises four control switch S1 to S4, wherein the control of two control switch S1 and S2 input is respectively described signal Up and Dwn, and the control input of two other control switch S3 and S4 is respectively complementary signal Upb and the Dwnb of signal Up and Dwn.
Described circuit also comprises eight current path switch S 5 to S12.Described channel selector S5 and S6 are controlled by bias voltage Vb1.Described channel selector S7 and S8 are controlled by bias voltage Vb2.Described channel selector S9 and S10 are controlled by bias voltage Vb3.Described channel selector S11 and S12 are controlled by bias voltage Vb4.
Switch S 13 and S14 are by the module controls that is called CMFB (common feedback pattern, Commun ModeFeedBack).Described CMFB module can be controlled public output mode (lemode commun en sortie), and promptly described bias voltage Vb1 is to the average level of Vb4, and described bias voltage is determined the level of described electric current I up and Idwn.
When described signal Iup is identical with Idwn polarity, there is not electric current in loop filter FB, to flow described system equalization.
When described signal Iup was opposite with Idwn polarity, described electric current I up and Idwn flowed in described loop filter FB, generated differential voltage (Vdiff+-Vdiff-) thereby be integrated.Thereby described differential voltage converts signal control lag circuit to by transducer CDU.
When described electric current I up and Idwn resulted from the size transistor identical with type, the structure of described difference system was so-called symmetrical structure.Similarly, the oxide-semiconductor control transistors of described current path switch S 5 to S12 is identical for signal Up and Dwn.
Therefore described structure can be injected the balanced described dynamic mismatch that reduces by the electric charge when making conversion.
The deficiency of this class formation, being on the one hand needs control described public output mode (CMFB module), is that on the other hand difference arrives one pole conversion CDU Module Design.The difficult design of described two module CM FB and CDU has produced extra mismatch, has caused the increase of described static mismatch.
The present invention has remedied these deficiencies.
Target of the present invention is a kind of time-electric pressure converter, and it is suitable for generally being higher than the conspicuous high-frequency region of 1G with the poor voltage that is directly proportional that is converted to accurately of the duration of two logical signals.
According to general structure of the present invention, described time-voltage transfer circuit comprises identical basic time-electric pressure converter of two structures and difference block, each basic time-electric pressure converter all has the input and output that receive the respective logic control signal to represent the output of voltage of the duration of corresponding logic control signal, and described difference block comprises respectively the output that the signal of the voltage difference between described two control signals is represented in the positive and negative input that links to each other with the output of relevant basic transducer and output.
It is asymmetric that such structure has been eliminated the structure that exists between the generation with reference to current source Iup and Idwn in the figure 1 described structure.
Similarly, do not use and described asymmetric relevant compensation circuit such structure does not resemble in the difference processing in the structure described in conjunction with Figure 2.
In fact, the circuit that the present invention provides has provided a kind of like this structure: in the conversion of signals stage symmetry fully that generally is the reason of dynamic mismatch, in the then accurate symmetry of process segment.
Therefore, by the present invention, described dynamic and static mismatch has been eliminated from structure.
Therefore, the technology that the present invention provides has better release ability for the noise of power supply and substrate-loading, because described structure is symmetrical fully for the high-precision operation of needs.In fact, on described two passages, find out interference, and deduct by difference block.
Other features and advantages of the present invention will provide in subsequent detailed description and accompanying drawing, and accompanying drawing comprises:
The Fig. 1 that has described shows a kind of structure of time-electric pressure converter in the prior art;
The Fig. 2 that has described shows a kind of structure of differential-type time-electric pressure converter in the prior art;
Fig. 3 has schematically illustrated symmetrical time-electric pressure converter that the present invention provides;
Fig. 4 A and 4B show in detail basic time-electric pressure converter that the present invention provides;
Fig. 5 has schematically illustrated the reseting pulse generator that the present invention provides;
Fig. 6 shows the sequential chart of the reset signal of generator shown in Figure 5;
The signal timing diagram of the structure of symmetrical time-voltage transitions that Fig. 7 provides for the present invention;
Fig. 8 is the module diagram of the analog-digital conversion structure of the transducer that uses the present invention and provide.
With reference to figure 3, described time-voltage transitions and integration operation are decomposed into three basic module BE1 to BE3.
The first module BE1 is relevant with time-voltage transitions on the two independent passages.Subtracting each other of the voltage of intermediate module BE2 and described passage is relevant, and last module BE3 is relevant with the integration of difference.
Described modular converter BE1 comprises the conversion operations of signal, and described conversion operations carries out for described independent passage fully symmetrically, and this has eliminated structural dynamic mismatch fully.
Described modular converter BE1 comprises two identical basic times-electric pressure converter CTT1 and CTT2, and the parallel individually symmetry of described transducer is installed.Each basic transducer CTT1 and CTT2 comprise the voltage Vup of duration of the input of the control signal Up that receives corresponding polarity respectively or Dwn and each control signal of output expression or the output of Vdwn.
With reference to figure 4A, described basic time-electric pressure converter CTT1 comprises:
First switch (transistor) 100A, it has input branch road 102 (drain electrode), output branch road 104 (source electrode) and control input 106 (grids), described input branch road links to each other with the first positive power supply terminal Vcc, described output branch road links to each other with first intermediate node 108, and described control input receives control signal Upb.
Second switch (transistor) 110A, it has input branch road 112 (drain electrode), output branch road 114 (source electrode) and control input 116 (grids), described input branch road links to each other with second intermediate node 118, described output branch road links to each other with first intermediate node 108, and described control input receives the complementary signal Up of the control signal Upb of the described first switch 100A.
Current source Ipol (transistor) 120A, it comprises input branch road 122 (drain electrode), output branch road 124 (source) and control input 126 (grids), described input branch road links to each other with first intermediate node 108, described output branch road links to each other with second power supply terminal 128 (the earth), and described control input links to each other with the 3rd power supply terminal Vpol.
Capacitor 130A, it has the first terminal 132 and second terminal 134, and described the first terminal links to each other with second intermediate node 118, and described second terminal links to each other with second power supply terminal 128.
The 3rd switch (transistor) 140A, it has input branch road 142 (drain electrode), output branch road 144 (source electrode) and control input 146 (grids), described input branch road links to each other with the 4th power supply terminal Vref, described output branch road links to each other with second intermediate node 118, and described control input receives the reset signal Reset of described electric capacity to the value that resets to described the 4th power supply terminal Vref.
Voltage amplifier (transistor) 150A, it has control input 152 (grids) and output 154 (drain electrodes), described control input links to each other with second intermediate node 118, described output sends the voltage Vup of described control signal Up duration of expression, source electrode 156 ground connection 128 of described transistor 150A, described drain electrode 154 links to each other with described power supply terminal Vcc by resistance 160A.
With reference to figure 4B, described basic time-electric pressure converter CTT2 comprises and the identical structure of CTT1 shown in Fig. 4 A.The composed component of described transducer CTT2 uses the Reference numeral identical with transducer CTT1, but after connect letter b.Described transducer CTT2 and described control signal Dwn and complementary signal Dwnb thereof are associated.
When the control signal Upb of described switch 100A and 100B and Dwnb are effective, described current source Ipol 120A and 120B come from described power supply terminal Vcc, when the control signal Up of described switch 110A and 110B and Dwn were effective, described current source Ipol 120A and 120B came from described electric capacity 130A and 130B.Described signal Upb and Dwnb are inversion signal or the complementary signals of described signal Up and Dwn.Voltage Vup on described electric capacity 130A and the 130B terminal and Vdwn therefore and the shut-in time of described switch 110A and 110B be directly proportional, thereby and the duration of described signal Up and Dwn be directly proportional.
Described voltage Vup and Vdwn then are exaggerated device 150A and 150B and amplify and shaping (remise en forme) before being delivered to described subtraction block BE2.
Voltage before described electric capacity 130A and 130B memory is amplified, and by reseting signal reset to described voltage Vref.Described voltage is by described transistor 150A and 150B and described resistance 160A and 160B amplification.
Described voltage Vpol can fix the electric current I pol among each basic transducer CTT.Described voltage vcc is total supply power voltage.Described voltage Vref is the reference voltage that is lower than described supply power voltage Vcc.
Reseting stage has been used in the conversion of described time-voltage, and in the described stage, described electric capacity 130A and 130B are repositioned onto reference value Vref.
In the practical operation, described switch is realized by means of MOS technology transistor.Such as, the switch of all transducer CTT1 and CTT2 is made by nmos pass transistor.
Being created in the practical operation of described complementary control signal realizes by means of inverter (inverseur).
With reference to figure 5, described reseting controling signal Reset is such as being generated based on described Up or Dwn signal by a special module, this module comprises edge-triggered device (bascule à front) and delay cell (cellules à retard), described delay cell is installed in series, and each constitutes by inverter 220 and electric capacity 210, described inverter is labeled as 220A respectively to 220E, and described electric capacity is labeled as 210A respectively to 210E.
Such as, described reset signal Reset generates based on the trailing edge (frontdescendant) of described Up signal.Can generate described reset signal based on described Dwn signal equally, because the trailing edge of described Up and Dwn signal is synchronous.This character is relevant with the use of phase comparator 700.
With reference to figure 5 and Fig. 6, the trailing edge of described Up signal has triggered the clock input CKN of described edge-triggered device 200.Be positioned at 0 described output Q in advance and get current level promptly 1 on the input D.By means of described electric capacity 210A, 210B2 and 210C postpone described signal Q for many times subsequently.The current demand signal at described node 230C place becomes 0, and at time period T1 end the input RST of described edge-triggered device 200 is reset to 0, and described time period T1 is corresponding to the duration of described reset pulse.
Described pulse is repeatedly postponed by means of described electric capacity 210D and 210E subsequently once more.The summation of all time of delays is time period T2, and it is corresponding to the beginning moment of described reset pulse Reset.
Refer again to Fig. 3.Described time-voltage transitions is carried out with symmetric mode, described voltage difference Vup-Vdwn is realized continuously by described BE2 module, described module comprises subtracting amplifier 300, described subtracting amplifier has positive input 302 and negative input 304, described positive input 302 receives described voltage Vup by resistance 306, and described negative input 304 receives described voltage Vdwn by resistance 308.Described reference voltage Vref is also powered to described positive input 302 by resistance 310, and described output 330 links to each other with described negative input 304 by resistance 320.
The integration of described difference realizes continuously that by integrator BE3 described integrator comprises amplifier 400, and this amplifier 400 is the active connection (montageactif) of resistance 410 electric capacity 420 class.
With reference to figure 7, described sequential chart shows signal Up, the longer duration of the more described signal Dwn of described signal Up.After the time-voltage transitions of carrying out according to the present invention, the level of described voltage Vup and Vdwn is different, all is proportional to the duration of described signal Up and Dwn.Described voltage is reset to reference level by described reset signal Reset.
Therefore difference Vdiff=Vup-Vdwn is positive, and will increase the output voltage V int of described integrator BE3.Here, described voltage Vint changes towards the direction opposite with Vdiff, because the connected mode of described integrator is an inverter.
The present invention can be integrated into the digitizing technique of the receive path that is used for reflector, and described reflector is worked at ultra broadband (ULB or UWB).In this technology, on 1 bit be that the conspicuous UWB of 20G is signal digitalized with frequency.
With reference to figure 8, the transformational structure of UWB system comprises conspicuous analog to digital converter 500 of 1 bit 20G and delay locked loop (DLL).Described loop comprises by voltage-controlled delay line 600, phase comparator 700 and time-electric pressure converter 800 manufactured according to the present invention.
The conspicuous conversion of 1 bit 20G is implemented in low frequency more for the reason of technical limitations.Such as generating 16 1.25G hertz, be offset the clock of 50 psecs.Therefore obtained working in 1 conspicuous bit moduli transducer of 20G, it is installed in parallel by 16 and is made of the comparator of the clock control of 16 skews.
One of key point of the overall accuracy of described system is the skew of described 50 psecs.Need to use phase feedback loop (boucle à asservissement de phase) to control this delay and generate described 16 clocks.
Analog signal to be converted is Vin_uwb.It is compared by means of 16 comparators 510 in parallel and voltage Vref_uwb, and described comparator is in the conspicuous work of 1.25G and be offset 50 psecs.The result of described 16 conversions passes and is sent to the logic module that is used for shaping and operation (exploitation).
The clock of described 16 skew 50 psecs is generated by described phase feedback loop, and described loop is made of voltage-controlled delay line 600, phase comparator 700 and time-electric pressure converter 800 manufactured according to the present invention.
Provide expected accuracy under circuit that the present invention provides thereby can the 1.25G conspicuous operating frequency, described circuit is integrated into the described phase comparator 700 that generates Up and Dwn signal and by in the phase feedback loop between the voltage-controlled described delay line 600.
The technology that the present invention uses has better immunocompetence for the noise of power supply and substrate-loading, because described structure is symmetrical fully for the high-precision operation of needs.In fact, independently parasitic signal occurs on channel C TT1 and the CTT2 two, and deduct by difference block BE2.
Claims (7)
1. time-voltage transfer circuit, described circuit comprises two basic time-electric pressure converter (CTT1 and CTT2) and difference block (BE2) that structure is identical, each basic transducer all comprises input and output, described input receives logical controlling signal (Up and Dwn), described output sends the voltage (Vup and Vdwn) of the duration of the corresponding logic control signal of expression, and described difference block has just (302) and negative (304) input that links to each other with the output of the basic transducer (CTT1 and CTT2) of being correlated with respectively and the output that sends the signal (Vdiff) of voltage difference between described two control signals of expression (Up and Dwn).
2. according to the described circuit of claim 1, wherein, the output of described difference block is connected to integration module (BE3).
3. according to the described circuit of claim 1, wherein, described difference block (BE2) is subtracting amplifier (300).
4. according to claim 2 or 3 described circuit, wherein, described integration module (BE3) is the activated amplifier (400) of RC type.
5. according to the described circuit of one of claim 1 to 4, wherein, described control signal (Up and Dwn) is sent from phase comparator (700).
6. according to the described circuit of claim 1, it is characterized in that described basic time-electric pressure converter (CTT1 and CTT2) comprises:
First switch (100A, 100B), it has the output branch road (104) that the input branch road (102) that links to each other with first power supply terminal (Vcc) links to each other with first intermediate node (108) and receives control signal (Upb, control input (106) Dwnb);
Second switch (110A, 110B), it has output branch road (114) and reception and the described first switch (100A that the input branch road (112) that links to each other with second intermediate node (118) links to each other with described first intermediate node (108), control signal (Upb 100B), Dwnb) complementary signal (Up, control input (116) Dwn);
Current source (120A, 120B), it comprises output branch road (124) that the input branch road (122) that links to each other with first intermediate node (108) links to each other with second power supply terminal (128) and the control input (126) that links to each other with the 3rd power supply terminal (Vpol);
Capacitor (130A, 130B), it has the first terminal (132) that links to each other with second intermediate node (118) and second terminal (134) that links to each other with second power supply terminal (128);
The 3rd switch (140A, 140B), it has the output branch road (144) that the input branch road (142) that links to each other with the 4th power supply terminal (Vref) links to each other with second intermediate node (118) and receives the control input (146) of reset signal (Reset) that described electric capacity is reset to the value of described the 4th power supply terminal (Vref);
(150A, 150B), it has the control input (152) that links to each other with second intermediate node (118) and sends the described control signal of expression (Up, the voltage of duration Dwn) (Vup, output Vdwn) (154) voltage amplifier.
7. according to the described circuit of claim 6, wherein, described reset signal (Reset) realizes by means of edge-triggered device (200) and delay cell (210,220).
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR0412082 | 2004-11-15 | ||
| FR0412082A FR2878093B1 (en) | 2004-11-15 | 2004-11-15 | SYMMETRIC TIME-VOLTAGE CONVERSION CIRCUIT |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101076944A true CN101076944A (en) | 2007-11-21 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2005800427044A Pending CN101076944A (en) | 2004-11-15 | 2005-11-08 | Symmetrical time-voltage transfer circuit |
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| Country | Link |
|---|---|
| US (1) | US20080218228A1 (en) |
| EP (1) | EP1813018B1 (en) |
| JP (1) | JP2008520139A (en) |
| CN (1) | CN101076944A (en) |
| AT (1) | ATE445934T1 (en) |
| DE (1) | DE602005017180D1 (en) |
| FR (1) | FR2878093B1 (en) |
| WO (1) | WO2006051212A2 (en) |
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| US11038521B1 (en) | 2020-02-28 | 2021-06-15 | Silicon Laboratories Inc. | Spur and quantization noise cancellation for PLLS with non-linear phase detection |
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| GB2356751B (en) * | 1999-11-23 | 2004-04-21 | Sony Uk Ltd | Charge pump |
| KR100512937B1 (en) * | 2003-01-14 | 2005-09-07 | 삼성전자주식회사 | Differential charge pump and method, and Phase locked loop using this pump and method |
| US7184510B2 (en) * | 2003-09-26 | 2007-02-27 | Quicklogic Corporation | Differential charge pump |
| FR2878094B1 (en) * | 2004-11-15 | 2007-02-09 | Commissariat Energie Atomique | DEVICE FOR COMPENSATING THE STATIC PHASE ERROR IN A SYMMETRIC STRUCTURE PHASE LOCKING BUCKLE SYSTEM |
-
2004
- 2004-11-15 FR FR0412082A patent/FR2878093B1/en not_active Expired - Fee Related
-
2005
- 2005-11-08 US US11/719,289 patent/US20080218228A1/en not_active Abandoned
- 2005-11-08 AT AT05817343T patent/ATE445934T1/en not_active IP Right Cessation
- 2005-11-08 EP EP05817343A patent/EP1813018B1/en not_active Not-in-force
- 2005-11-08 DE DE602005017180T patent/DE602005017180D1/en not_active Expired - Fee Related
- 2005-11-08 CN CNA2005800427044A patent/CN101076944A/en active Pending
- 2005-11-08 JP JP2007540677A patent/JP2008520139A/en not_active Withdrawn
- 2005-11-08 WO PCT/FR2005/002783 patent/WO2006051212A2/en active Application Filing
Also Published As
| Publication number | Publication date |
|---|---|
| ATE445934T1 (en) | 2009-10-15 |
| EP1813018B1 (en) | 2009-10-14 |
| EP1813018A2 (en) | 2007-08-01 |
| WO2006051212A3 (en) | 2007-04-05 |
| US20080218228A1 (en) | 2008-09-11 |
| FR2878093A1 (en) | 2006-05-19 |
| WO2006051212A2 (en) | 2006-05-18 |
| DE602005017180D1 (en) | 2009-11-26 |
| JP2008520139A (en) | 2008-06-12 |
| FR2878093B1 (en) | 2007-02-09 |
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| PB01 | Publication | ||
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| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
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Open date: 20071121 |