CN1968021A - A delay phase-lock loop, voltage-controlled delay line and delay cell - Google Patents
A delay phase-lock loop, voltage-controlled delay line and delay cell Download PDFInfo
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- CN1968021A CN1968021A CN 200610062340 CN200610062340A CN1968021A CN 1968021 A CN1968021 A CN 1968021A CN 200610062340 CN200610062340 CN 200610062340 CN 200610062340 A CN200610062340 A CN 200610062340A CN 1968021 A CN1968021 A CN 1968021A
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Abstract
The invention relates to a delay phase-lock ring, voltage-control delay line and delay unit, wherein it comprises bias generator and voltage-control delay line; the bias generator generates bias voltage input into voltage-control delay line; the delay line generates time delay; the delay line comprises one or more cascade delay units; said delay unit comprises one asymmetry active load delay unit, the first controller, differential signal output select channel and second controller; only one of first and second controllers can be operated at one time. The invention can flexibly set delay output of voltage-control delay line.
Description
Technical field
The invention belongs to the communications field, relate in particular to a kind of delay phase-locked loop, voltage controlled delay line and delay unit.
Background technology
Along with the increase of volume of transmitted data, also more and more higher to the requirement of synchronised clock frequency.For the more data of transmission under lower clock frequency, begin to utilize the two of clock in design, under identical clock frequency, can singly transmit one times the data of Duoing than adopting along (rising edge or trailing edge) mode along (rising edge and trailing edge) image data.Receiving data terminal, for accurate restore data, clock accurately need be postponed the time (such as 1/4 cycle) of certain numerical value, and the basic no change of the duty ratio of clock.
Fig. 1 shows typical delays phase-locked loop (Delay Locked Loop, DLL) structure, comprise phase discriminator 101, charge pump 102, loop filter 103, biasing generator (Bias Generator) 104 and voltage controlled delay line (Voltage Controlled Delay Line, VCDL) 105.The phase place of clock signal FCLK after 101 pairs of sources of phase discriminator clock signal SCLK and the delay judges that control signal UP and DN to charge pump 102 that output is corresponding are converted into electric current by charge pump 102.Charge pump 102 carries out charge or discharge to loop filter 103 under the control of control signal UP and DN, obtain the control voltage V of voltage controlled delay line 105
Ctr, produce bias voltage V by biasing generator 104
BPAnd V
BNBe input to voltage controlled delay line 105.The bias voltage V that biasing generator 104 produces
BP, V
BNControl voltage controlled delay line 105 produces time-delay, makes the basic no change of clock duty cycle.
Fig. 2 shows the structure of biasing generator 104, controls voltage controlled delay line 105 by the mode that changes bias current and then change bias voltage and produces corresponding time-delay.
Voltage controlled delay line 105 adopts the symmetrical active load delay unit (Delay Cell) of differential configuration as shown in Figure 3, adopts N channel field-effect crystal (MOS) pipe as input pipe, and the P channel MOS tube is as the load pipe.Supply voltage VDD inserts the source electrode of metal-oxide-semiconductor T6, T7, T8, T9, the drain electrode of T6 links to each other with the drain and gate of T7, form VCR1 (Voltage Controlled Resistor, thyrite), corresponding M OS pipe T8 and T9 form VCR2, VCR1 and VCR2 constitute the active load of symmetry, bias voltage V
BPInsert the grid of T7, T8.Differential signal VINPA and VINNA are input to the grid of input difference to pipe T2 and T3, and the grid of T2 and T3 meets output VOUTN and VOUTP, the differential signal of output after metal-oxide-semiconductor T2 and T3 amplification.The drain electrode of T2, T3 is connected with the drain electrode of T7, T8 respectively, and source electrode is connected with the drain electrode of P channel MOS tube T1.T1 provides tail current, the source ground GND of T1, bias voltage V
BNInsert the grid of T1.
In application, need make voltage controlled delay line can export different time-delays according to actual conditions to the delay phase-locked loop configuration of delaying time, in the existing voltage controlled delay line since delay unit fix, can't realize the configuration of delaying time, be difficult to satisfy the needs of practical application.
Summary of the invention
The object of the present invention is to provide a kind of delay phase-locked loop, be intended to solve in the existing phase-locked loop,, can't realize the problem of delaying time and disposing because the delay unit of voltage controlled delay line is fixed.
Another object of the present invention is to provide a kind of voltage controlled delay line.
Another object of the present invention is to provide a kind of delay cell.
The present invention realizes like this, a kind of delay phase-locked loop, comprise biasing generator and voltage controlled delay line, described biasing generator produces bias voltage and is input to voltage controlled delay line, control described voltage controlled delay line and produce time-delay, described voltage controlled delay line comprises the delay unit of one or more cascade, and described delay unit comprises a symmetrical active load delay unit, and described delay unit further comprises:
First control end is serially connected in the described symmetrical active load delay unit, and the differential signal input and output path of described symmetrical active load delay unit is carried out break-make control;
Differential signal output selection path is connected with the output of described symmetrical active load delay unit, receives differential signal, the differential signal after output is amplified; And
Second control end is serially connected in the described differential signal output selection path, and the differential signal input and output path of described differential signal being exported the selection path carries out break-make control;
Described first control end and second control end can only have one to open or turn-off simultaneously.
Described delay phase-locked loop further comprises one from loop, receive the clock signal of input, clock signal after output time-delay under the identical bias voltage control of described biasing generator, describedly comprise one or more independently voltage controlled delay line from loop, described voltage controlled delay line comprises the delay unit of one or more cascade.
The voltage controlled delay line of described delay phase-locked loop is consistent with the load of described voltage controlled delay line from loop.
Opening and turn-off by coding of described first control end and second control end controlled.
Described biasing generator is the Replica circuit.
The input pipe of described delay unit is the N-channel MOS pipe, and the load pipe is the P channel MOS tube, and perhaps input pipe is the P channel MOS tube, and the load pipe is the N-channel MOS pipe.
A kind of voltage controlled delay line comprises the delay unit of one or more cascade, and described delay unit comprises a symmetrical active load delay unit, and described delay unit further comprises:
First control end is serially connected in the described symmetrical active load delay unit, and the differential signal input and output path of described symmetrical active load delay unit is carried out break-make control;
Differential signal output selection path is connected with the output of described symmetrical active load delay unit, receives differential signal, the differential signal after output is amplified; And
Second control end is serially connected in the described differential signal output selection path, and the differential signal input and output path of described differential signal being exported the selection path carries out break-make control;
Described first control end and second control end can only have one to open or turn-off simultaneously.
The input pipe of described delay unit is the N-channel MOS pipe, and the load pipe is the P channel MOS tube, and perhaps input pipe is the P channel MOS tube, and the load pipe is the N-channel MOS pipe.
A kind of delay unit, described delay unit comprise a symmetrical active load delay unit, and described delay unit further comprises:
First control end is serially connected in the described symmetrical active load delay unit, and the differential signal input and output path of described symmetrical active load delay unit is carried out break-make control;
Differential signal output selection path is connected with the output of described symmetrical active load delay unit, receives differential signal, the differential signal after output is amplified; And
Second control end is serially connected in the described differential signal output selection path, and the differential signal input and output path of described differential signal being exported the selection path carries out break-make control;
Described first control end and second control end can only have one to open or turn-off simultaneously.
The input pipe of described delay unit is the N-channel MOS pipe, and the load pipe is the P channel MOS tube, and perhaps input pipe is the P channel MOS tube, and the load pipe is the N-channel MOS pipe.
Voltage controlled delay line among the present invention adopts the delay unit with gating function to realize, by the number of delay unit in the break-make adjustment voltage controlled delay line of control delay unit, has realized the flexible configuration to voltage controlled delay line time-delay output.By principal and subordinate's loop structure, realized the concurrent working of a plurality of clock path.Simultaneously, the biasing generator adopts the Replica circuit, has avoided the nonlinear Control to time-delay, makes clock frequency change step uniformity.
Description of drawings
Fig. 1 is the exemplary block diagram of delay phase-locked loop in the prior art;
Fig. 2 is the circuit structure diagram of biasing generator in the prior art;
Fig. 3 is the circuit structure diagram of voltage controlled delay line in the prior art;
Fig. 4 is the circuit structure diagram of the delay unit that provides in the one embodiment of the invention;
Fig. 5 is the circuit structure diagram of the delay unit that provides in another embodiment of the present invention;
Fig. 6 is the exemplary circuit structure chart of voltage controlled delay line among the present invention;
Fig. 7 is the structure chart that adopts the delay phase-locked loop of principal and subordinate's loop structure among the present invention;
Fig. 8 is the exemplary circuit structure chart that adopts among the present invention from the loop voltage controlled delay line;
Fig. 9 is the circuit structure diagram of biasing generator among the present invention.
Embodiment
In order to make purpose of the present invention, technical scheme and advantage clearer,, the present invention is further elaborated below in conjunction with drawings and Examples.Should be appreciated that specific embodiment described herein only in order to explanation the present invention, and be not used in qualification the present invention.
In the present invention, voltage controlled delay line adopts the delay unit with gating function to realize, adjusts the number of delay unit in the voltage controlled delay line by the break-make of selection path in the control delay unit, thereby realizes the flexible configuration to voltage controlled delay line time-delay output.
Fig. 4 shows the structure of delay unit provided by the invention, the input difference that is serially connected in symmetrical active load delay unit constitutes first control end to pipe P channel MOS tube T4 and T5, and differential signal VINPA, the VINNA of the symmetrical active load delay unit of control input is to the break-make of output VOUTP, VOUTN.The drain electrode of T4 and T5 meets drain electrode and output VOUTP, the VOUTN of T7, T8 respectively, and source electrode connects the drain electrode of T2, T3 respectively.Break-make control signal SELA inserts the grid of T4 and T5.
T1 '～T5 ' formation is corresponding to another differential signal output selection path of T1～T5, and input difference is to pipe T4 ' and T5 ' formation second control end, and control input differential signal VINPB, VINNB are to the break-make of output VOUTP, VOUTN.The drain electrode of T4 ' and T5 ' meets output VOUTN, VOUTP respectively, and source electrode connects the drain electrode of T2 ', T3 ' respectively.Break-make control signal SELB inserts the grid of T4 ' and T5 '.Differential signal VINPB and VINNB are input to the grid of input difference to pipe T2 ' and T3 ', output after input difference is to pipe T2 ' and T3 ' amplification.The drain electrode of T2 ', T3 ' is connected with the source electrode of T4 ', T5 ' respectively, and source electrode is connected with the drain electrode of T1 '.T1 ' provides tail current, the source ground GND of T1 ', bias voltage V
BNInsert the grid of T1 '.
SELA can only have one to be logic high " 1 " (voltage identical with power vd D) simultaneously with SELB.When SELA is a logic high, when SELB is logic low " 0 " (voltage identical with ground GND), input differential signal VINPA, VINNA are transferred to output VOUTP, VOUTN, input differential signal VINPB, VINNB turn-off conductively-closed because of SELB, vice versa, selects 1 function thereby make this delay unit have 2.
Adopt the N-channel MOS pipe as input pipe among Fig. 4, the P channel MOS tube also can select the P channel MOS tube to make input pipe as the load pipe, and the N-channel MOS pipe is done the load pipe, as shown in Figure 5, realizes that principle is same as described above, repeats no more.
Fig. 6 shows the example structure of voltage controlled delay line 105, adopts 24 grades of delay unit cascades, by S1～S24 being carried out corresponding break-make control, can realize exporting as required different time-delays.For example working as S1, S25 is high level, when S2 is low level, can export 2 grades of time-delays; When S1, S2, S26 are high level, when S25 is low level, can export 3 grades of time-delays etc., specifically can be by coding control.
In order to realize clock path concurrent working for a long time, in one embodiment of the invention, delay phase-locked loop adopts principal and subordinate's loop structure, as shown in Figure 7.From loop 12 by one or morely be subjected to the same control of major loop 11 voltage-controlledly to prolong voltage-controlled slow line 12.1,12.2......12.n constitutes, wherein, CLK1......CLKN is the input clock signal with major loop 11 source clock sclk same frequencys, CKO1......CKON is the clock signal after the corresponding time-delay, and ADJ1......ADJN is a control end of adjusting delay unit number from the loop voltage controlled delay line.
If the number of the delay unit of the voltage controlled delay line in the major loop 11 is N
m, the delay unit number of each voltage controlled delay line is N from loop 12
s, be T/N the time of delay of each delay unit in the voltage controlled delay line of major loop 11 at this moment
m, because the delay unit in the voltage controlled delay line of the delay unit in each voltage controlled delay line and major loop 11 is all identical on circuit structure, load, size from loop 12, thus from loop the time of delay of each voltage controlled delay line be (T/N
m) * N
s, by changing N
sThereby numerical value can change the time-delay of each voltage controlled delay line from loop 12.Separate between each voltage controlled delay line from loop 12, can adjust time-delay respectively, the adjustment of time-delay realizes by the mode that changes the delay unit number, its step-length uniformity can the linear configurations time-delay.Simultaneously, can also guarantee that principal and subordinate's voltage-controlled delay linear load keeps strict unified, avoids major loop and inconsistent from the delay of loop.
For example at major loop voltage controlled delay line 105 with when the loop voltage controlled delay line adopts Fig. 6, structure shown in Figure 8 respectively, when the control end S3 of delay unit DC3 is a high level, when the control end S26 of DC25 also is high level, the VINPA of the VINPA of DC3, VINNA and DC25, VINNA are the loads of DC2, and such load is load one.When the control end S2 of delay unit DC2 is a high level, when the control end S25 of DC25 was low level, delay unit DC1 did not have signal to extract out, and the VINPB of the VINPA of DC2, VINNA and DC25, VINNB are the loads of DC1, and such load is load two.8 of the delay units of total load 1 in the voltage controlled delay line 105 of whole major loop 11,16 of the delay units of load 2.The delay unit number that has load one like this in the major loop 11 is 8: 16 with the delay unit number ratio with load two, satisfy principal and subordinate's loop voltage-controlled delay linear load and keep strict unified, must make the delay unit number that from each voltage controlled delay line of loop, has load one identical with major loop 11 with delay unit number ratio with load two.
In 3 grades of time-delays, from the loop voltage controlled delay line shown in the control end state following table of each delay unit:
| The control end title | S1 | ?S2 | ?S3 | ?S4 | ?S5 | ?S6 | ?S7 | ?S8 | ?S9 | ?S10 | ?S11 |
| The control end level | High | High | Low | Low | Low | High | Low | Low | Low | High | Low |
Then clock is by DC1, and DC6, DC8 obtain 3 grades of time-delays, and the delay unit with load one is DC1, and the delay unit with load two is DC6 and DC8, and ratio is 1: 2.
In 6 grades of time-delays, from the loop voltage controlled delay line shown in the control end state following table of each delay unit:
| The control end title | S1 | ?S2 | ?S3 | ?S4 | ?S5 | ?S6 | ?S7 | ?S8 | ?S9 | ?S10 | ?S11 |
| The control end level | High | High | High | High | High | High | Low | Low | High | Low | High |
Clock obtains 6 grades of time-delays by DC1, DC2, DC3, DC4, DC7, DC8.Delay unit with load one is DC1 and DC4, and the delay unit with load two is DC2, DC3, DC7 and DC8, and ratio is 2: 4.
Therefore, in principal and subordinate's loop, the delay unit with load one equates fully that with the delay unit ratio with load two (1: 2=2: 4=8: 16), load keeps strict conformance, has realized the uniformity of principal and subordinate's loop time-delay step-length well.Coding purpose to control end SEL is to realize that all the time two kinds of unequally loaded delay unit number ratios remain unchanged in the variable scope of time-delay, thereby guarantees the uniformity of time-delay step-length.Because the time-delay control of biasing generator 104 pairs of voltage controlled delay lines 105 is adopted bias current to be converted to bias voltage and arrive time-delay control again, existence controls voltage to the nonlinear problem of time-delay, makes the inhomogeneous unanimity of clock frequency change step.As one embodiment of the present of invention, biasing generator 104 adopts the Replica circuit to realize that the Replica circuit is the common name of a class circuit, and the related content of Replica circuit is referring to IEEE VOL.27, No.11, Nov, 1992,1599, Ian A.Young, Jeffrey K.Greason, and Keng L.Wong, " APLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessors ".
As shown in Figure 9, T1, T2, T3, T11, T12, T13 and T14 are the N-channel MOS pipe, and T4～T10 is the P channel MOS tube.Supply voltage VDD connects the source electrode of T1, T11, T12, T13, T14, and the drain electrode of T1 connects the source electrode of T1, T2, and bias voltage VB1 connects the grid of the drain electrode of T1.The A point voltage inserts the grid of T2, and the drain electrode of T2 connects the drain and gate of P channel MOS tube.The drain electrode of T3 connects the drain electrode of T5 and the grid of T6.The source ground of T4, T5, T6.Reference voltage V
RefConnect the grid of T3.The grid of T4 and the grid of T5 join.The drain electrode of T6 connects the source electrode of T7 and the source electrode of grid and T8, and supply voltage VDD connects the grid of T8.The source electrode of T9 connects the drain electrode of T7, and grid meets supply voltage VDD, and drain electrode connects the drain electrode of T13 and the drain and gate of T14.The grid of T10 connects the grid of T9, and drain electrode connects the drain electrode of T11 and the drain and gate of T12.The grid of T12 and T13 joins.
T1～T5 forms an error amplifier, relatively A point voltage and reference voltage V
Ref, result is relatively fed back to T6, the tail current of control T6, thus make A point voltage and V
RefEquate.The circuit that T6～T14 constitutes and the forming circuit basically identical of delay unit, when circuit working, only need one side circuit working in T7, T9, T13, T14 or T8, T10, T11, the T12 symmetry path to get final product, the present invention is connected into T7 the form of shutoff, be T7, T9, T13, the shutoff of T14 path, T8, T10, T11, T12 conducting.
For example work as V
Ctr(V
BP) when diminishing, the VCR that T11, T12 form diminishes, and causes the pressure reduction on the VCR to diminish, the A point voltage raises, and makes V by error amplifier
BNRaise, it is big that the tail current of T6 becomes, big thereby the pressure reduction on the VCR becomes, and makes the A point voltage reduce; As A point voltage and V
RefWhen equating, the A point voltage remains unchanged.
Otherwise, work as V
BPWhen becoming big, it is big that the VCR that T11, T12 form becomes, and causes the pressure reduction on the VCR to become big, and the A point voltage reduces, and makes V by error amplifier
BNReduce, the tail current of T6 diminishes, thereby the pressure reduction on the VCR diminishes, and makes the A point voltage raise; As A point voltage and V
RefWhen equating, the A point voltage remains unchanged.
The time-delay of delay unit is directly proportional with the size of VCR, is inversely proportional to the tail current of T6, works as V
BPWhen diminishing, VCR diminishes, and it is big that the T6 tail current becomes, thereby than single V
BPTime-delay during control is littler.Otherwise, work as V
BPWhen becoming big, it is big that VCR becomes, and the T6 tail current diminishes, thereby than single V
BPTime-delay during control is bigger, thereby can increase the scope of time-delay.
Because the biasing generator does not use from control voltage V
Ctr→ electric current → bias voltage V
BPAnd V
BNConversion, eliminated the non-linear time-delay nonlinear problem that causes of V → I → V, make the clock frequency change step keep uniformity.
The above only is preferred embodiment of the present invention, not in order to restriction the present invention, all any modifications of being done within the spirit and principles in the present invention, is equal to and replaces and improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1, a kind of delay phase-locked loop, comprise biasing generator and voltage controlled delay line, described biasing generator produces bias voltage and is input to voltage controlled delay line, control described voltage controlled delay line and produce time-delay, described voltage controlled delay line comprises the delay unit of one or more cascade, described delay unit comprises a symmetrical active load delay unit, it is characterized in that described delay unit further comprises:
First control end is serially connected in the described symmetrical active load delay unit, and the differential signal input and output path of described symmetrical active load delay unit is carried out break-make control;
Differential signal output selection path is connected with the output of described symmetrical active load delay unit, receives differential signal, the differential signal after output is amplified; And
Second control end is serially connected in the described differential signal output selection path, and the differential signal input and output path of described differential signal being exported the selection path carries out break-make control;
Described first control end and second control end can only have one to open or turn-off simultaneously.
2, delay phase-locked loop as claimed in claim 1, it is characterized in that, described delay phase-locked loop further comprises one from loop, receive the clock signal of input, clock signal after output time-delay under the identical bias voltage control of described biasing generator, describedly comprise one or more independently voltage controlled delay line from loop, described voltage controlled delay line comprises the delay unit of one or more cascade.
3, delay phase-locked loop as claimed in claim 2 is characterized in that, the voltage controlled delay line of described delay phase-locked loop is consistent with the load of described voltage controlled delay line from loop.
4, delay phase-locked loop as claimed in claim 1 is characterized in that, opening and turn-off by coding of described first control end and second control end controlled.
As the described delay phase-locked loop of the arbitrary claim of claim 1 to 4, it is characterized in that 5, described biasing generator is the Replica circuit.
As the described delay phase-locked loop of the arbitrary claim of claim 1 to 4, it is characterized in that 6, the input pipe of described delay unit is the N-channel MOS pipe, the load pipe is the P channel MOS tube, and perhaps input pipe is the P channel MOS tube, and the load pipe is the N-channel MOS pipe.
7, a kind of voltage controlled delay line comprises the delay unit of one or more cascade, and described delay unit comprises a symmetrical active load delay unit, it is characterized in that described delay unit further comprises:
First control end is serially connected in the described symmetrical active load delay unit, and the differential signal input and output path of described symmetrical active load delay unit is carried out break-make control;
Differential signal output selection path is connected with the output of described symmetrical active load delay unit, receives differential signal, the differential signal after output is amplified; And
Second control end is serially connected in the described differential signal output selection path, and the differential signal input and output path of described differential signal being exported the selection path carries out break-make control;
Described first control end and second control end can only have one to open or turn-off simultaneously.
8, voltage controlled delay line as claimed in claim 7 is characterized in that, the input pipe of described delay unit is the N-channel MOS pipe, and the load pipe is the P channel MOS tube, and perhaps input pipe is the P channel MOS tube, and the load pipe is the N-channel MOS pipe.
9, a kind of delay unit, described delay unit comprise a symmetrical active load delay unit, it is characterized in that described delay unit further comprises:
First control end is serially connected in the described symmetrical active load delay unit, and the differential signal input and output path of described symmetrical active load delay unit is carried out break-make control;
Differential signal output selection path is connected with the output of described symmetrical active load delay unit, receives differential signal, the differential signal after output is amplified; And
Second control end is serially connected in the described differential signal output selection path, and the differential signal input and output path of described differential signal being exported the selection path carries out break-make control;
Described first control end and second control end can only have one to open or turn-off simultaneously.
10, delay unit as claimed in claim 9 is characterized in that, the input pipe of described delay unit is the N-channel MOS pipe, and the load pipe is the P channel MOS tube, and perhaps input pipe is the P channel MOS tube, and the load pipe is the N-channel MOS pipe.
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|---|---|---|---|
| CN 200610062340 CN1968021B (en) | 2006-08-25 | 2006-08-25 | A delay phase-lock loop, voltage-controlled delay line and delay cell |
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|---|---|---|---|
| CN 200610062340 CN1968021B (en) | 2006-08-25 | 2006-08-25 | A delay phase-lock loop, voltage-controlled delay line and delay cell |
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| CN1968021B CN1968021B (en) | 2010-04-21 |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7902935B2 (en) | 2007-09-07 | 2011-03-08 | Huawei Technologies Co., Ltd. | Bias circuit and voltage-controlled oscillator |
| CN102281053A (en) * | 2010-06-04 | 2011-12-14 | 马克西姆综合产品公司 | Data interface with delay locked loop for high speed digital to analog converters and analog to digital converters |
| CN102684687B (en) * | 2010-01-08 | 2014-03-26 | 无锡中星微电子有限公司 | Delay-locked loop |
| CN104467819A (en) * | 2014-07-08 | 2015-03-25 | 北京芯诣世纪科技有限公司 | Delay-locked loop, voltage-controlled delay line and delay unit |
| CN104734694A (en) * | 2013-12-20 | 2015-06-24 | 深圳市国微电子有限公司 | Clock phase correcting circuit |
| CN112650139A (en) * | 2020-12-11 | 2021-04-13 | 北京时代民芯科技有限公司 | DDR3 storage protocol-oriented clock controller and control method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1794577A (en) * | 2006-01-09 | 2006-06-28 | 威盛电子股份有限公司 | Delay unit of pressure controlled oscillator |
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2006
- 2006-08-25 CN CN 200610062340 patent/CN1968021B/en active Active
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7902935B2 (en) | 2007-09-07 | 2011-03-08 | Huawei Technologies Co., Ltd. | Bias circuit and voltage-controlled oscillator |
| CN102684687B (en) * | 2010-01-08 | 2014-03-26 | 无锡中星微电子有限公司 | Delay-locked loop |
| CN102281053A (en) * | 2010-06-04 | 2011-12-14 | 马克西姆综合产品公司 | Data interface with delay locked loop for high speed digital to analog converters and analog to digital converters |
| CN104734694A (en) * | 2013-12-20 | 2015-06-24 | 深圳市国微电子有限公司 | Clock phase correcting circuit |
| CN104734694B (en) * | 2013-12-20 | 2017-12-08 | 深圳市国微电子有限公司 | A kind of clock phase correcting circuit |
| CN104467819A (en) * | 2014-07-08 | 2015-03-25 | 北京芯诣世纪科技有限公司 | Delay-locked loop, voltage-controlled delay line and delay unit |
| CN112650139A (en) * | 2020-12-11 | 2021-04-13 | 北京时代民芯科技有限公司 | DDR3 storage protocol-oriented clock controller and control method |
| CN112650139B (en) * | 2020-12-11 | 2022-08-02 | 北京时代民芯科技有限公司 | DDR3 storage protocol-oriented clock controller and control method |
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|---|---|
| CN1968021B (en) | 2010-04-21 |
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