CN112650139B

CN112650139B - DDR3 storage protocol-oriented clock controller and control method

Info

Publication number: CN112650139B
Application number: CN202011459833.6A
Authority: CN
Inventors: 郭琨; 陈雷; 李学武; 孙华波; 倪劼; 王文锋; 孙健爽; 刘亚泽; 赫彩; 甄淑琦; 张玉; 方鑫; 单连志
Original assignee: Beijing Microelectronic Technology Institute; Mxtronics Corp
Current assignee: Beijing Microelectronic Technology Institute; Mxtronics Corp
Priority date: 2020-12-11
Filing date: 2020-12-11
Publication date: 2022-08-02
Anticipated expiration: 2040-12-11
Also published as: CN112650139A

Abstract

A clock controller and a control method facing a DDR3 storage protocol abandon traditional clock control circuits, adopt a negative feedback structure to reduce the influence of a clock caused by process, temperature and noise, and the structure comprises a digital delay phase-locked loop, a mirror symmetry delay chain, a Gray code phase selector and a Gray code phase interpolator to realize accurate control, lower phase error and less locking time of the clock. The DDR3 storage protocol-oriented clock controller can realize accurate delay of 64-level TAP of a DDR3 clock, guarantee the central position of a sampling clock delay data effective window, improve the stability and reliability of high-frequency clock sampling, and enable the highest frequency of the clock to be as high as 800 MHz.

Description

DDR3 storage protocol-oriented clock controller and control method

Technical Field

The invention relates to a clock controller facing a DDR3 storage protocol and a control method, in particular to a clock control circuit optimally designed aiming at DDR3 application requirements through a programmable logic device, and belongs to the field of integrated circuits.

Background

DDR3 SDRAM adopts advanced production process based on DDR2 SDRAM, and its working voltage is lowered from 1.8V to 1.5V, and adopts advanced production process, and its memory data transmission rate is greatly raised, and can be up to 1600MHz, so that it can meet the requirements of high-performance server, and at the same time can implement quick, stable and reliable system operation

Data in the DDR3 SDRAM is double-transmitted, a data sampling clock can reach 800MHz at most, namely, the rising edge and the falling edge of the data clock are simultaneously sampled, so that how to quickly and accurately position the sampling clock in the DDR3 SDRAM controller is very important, and whether to correctly control accurate sampling data and sampling precision becomes important factors influencing the performance of the memory controller. Therefore, there are high demands on the performance and accuracy of the clock controller facing the DDR3 protocol, and the DDR3 controller has two clocks, one external bus clock and one internal operating clock. Ideally, the two clocks of the DDR3 controller should be synchronized, but due to various reasons, such as temperature, voltage fluctuations, etc., delays make it difficult to synchronize the two. If the internal clock of the DDR3 memory deviates from the external clock, errors due to data asynchronism are likely to result. Considering that the external clock and the internal clock are not absolutely uniform, it is necessary to dynamically correct the delay of the internal clock according to the external clock to synchronize the internal clock with the external clock, to achieve accurate control and low phase error of the clock, and to achieve accurate delay of the 64-level TAP of the DDR3 clock. And meanwhile, less locking time is needed, higher flexibility is realized, and higher clock controller performance is obtained.

Disclosure of Invention

The technical problem solved by the invention is as follows: the clock controller and the control method for the DDR3 storage protocol overcome the defects of the prior art, solve the problem that external clocks in a DDR3 memory are asynchronous due to temperature and voltage fluctuation and the like, improve the performance of a delay line, solve the problem of accurate delay of 64-level TAP of a DDR3 clock, solve the problem of poor sampling precision of the DDR3 clock controller, and solve the problems of poor anti-interference capability and long locking time of the DDR3 clock controller.

The technical solution of the invention is as follows: a clock controller facing a DDR3 storage protocol comprises a digital delay phase-locked loop, a mirror symmetry delay chain, a Gray phase selector and a Gray code phase interpolator;

the digital delay phase-locked loop receives an external common clock signal CLK _ IN, outputs a clock signal CLK _ FB feedback access input, and sends output voltage signals Vctrl _ P and Vctrl _ N to a mirror symmetry delay chain;

the mirror symmetry delay chain receives an external common clock signal CLK _ IN, receives voltage signals Vctrl _ P and Vctrl _ N of the digital delay phase-locked loop and converts the voltage signals into 8 paths of output clocks Clk45, Clk225, Clk90, Clk270, Clk135, Clk315, Clk180 and Clk0 to a Gray code phase selector;

the gray code phase selector receives external common control signals PS0, PS1 and PS2 and selects eight paths of output clocks of the mirror symmetry delay chain to the gray code phase interpolator;

the Gray code phase interpolator receives external common control signals PI0, PI1 and PI2, receives Output voltage signals Vctrl _ P and Vctrl _ N of the digital delay phase-locked loop, receives Output of the Gray code phase selector, and outputs external clock signals Output _ P and Output _ N.

Furthermore, the frequency range of the external common clock signal CLK _ IN is 400 MHz-800 MHz; the external clock signals Output _ P and Output _ N are a pair of differential Output clock signals; the external common control signals PS0, PS1 and PS2 are clock signals for controlling the Gray code phase selector to normally control the working; the external common control signals PI0, PI1, and PI2 are clock signals for controlling the gray code phase interpolator to normally control the operation.

Further, the digital delay phase-locked loop comprises an N-channel mos tube K15, a P-channel mos tube K14, a delay unit K9, a delay unit K10, a delay unit K11, a delay unit K12, a delay unit K13, a phase discriminator K5, a charge pump K6, a filter K7 and a reference circuit K8;

an external common clock input end signal CK _ IN is connected to the input end of the delay unit K9 and the input end of the phase detector K5, and the other input end of the phase detector K5 is connected with a feedback clock signal CK _ FB; the output end UP and the output end DOWN of the phase detector K5 are connected to the input end of a charge pump K6, and the output end Vctrl of the charge pump is connected to the input end of a filter K7; an output end Vctrl _ A of the filter K7 is connected to an input end of a reference circuit K8, and output ports of the reference circuit are Vctrl _ P and Vctrl _ N; the control end C24 of the delay unit K9 is connected to the drain electrode of a P-channel MOS tube, the control end C23 is connected to the drain electrode of an N-channel MOS tube, and the output end of the delay unit K3878 is connected to the input end of the next-stage delay unit K10; the control end C27 of the delay unit K10 is connected to the drain electrode of a P-channel MOS tube, the control end C26 is connected to the drain electrode of an N-channel MOS tube, and the output end of the delay unit K3878 is connected to the input end of the next-stage delay unit K11; the control end C30 of the delay unit K11 is connected to the drain electrode of a P-channel MOS tube, the control end C29 is connected to the drain electrode of an N-channel MOS tube, and the output end of the delay unit K3878 is connected to the input end of the next-stage delay unit K12; the control end C33 of the delay unit K12 is connected to the drain electrode of a P-channel MOS tube, the control end C32 is connected to the drain electrode of an N-channel MOS tube, and the output end of the delay unit K3878 is connected to the input end of the next-stage delay unit K13; the control terminal C35 of the delay unit K13 is connected to the drain of the P-channel MOS transistor, the control terminal C36 is connected to the drain of the N-channel MOS transistor, and the output terminal is connected to the feedback clock input terminal CK _ FB.

Further, the phase detector K5 includes a flip-flop K16, a flip-flop K19, an inverter K18, and a nand gate K17;

an external common clock signal CK _ IN is connected to a clock input end of a flip-flop K16, a common clock signal CK _ FB is connected to a clock input end of a flip-flop K19, a data end of the flip-flop K16 is connected with a power supply VS, a data end of the flip-flop K19 is connected with the power supply VS, an output end Q of a flip-flop K16 and an output end of a flip-flop K19 are connected to an input port of a NAND gate K17, an output end of the NAND gate K17 is connected with an input end of an inverter K18, and an output end of the inverter K18 is connected to reset ports of the flip-flop K16 and the flip-flop K19.

Further, the charge pump K6 includes a P-channel MOS transistor K24, a P-channel MOS transistor K20, a P-channel MOS transistor K22, an N-channel MOS transistor K21, an N-channel MOS transistor K23, and an N-channel MOS transistor K25;

the power supply VS is connected to the source electrode of the P-channel MOS tube K24, the grid electrode of the P-channel MOS tube K24 is connected to the input end control signal Vctrl _ P, and the drain electrode of the P-channel MOS tube K20 and the source electrode of the P-channel MOS tube K22; the grid electrode of the P-channel MOS tube K20 is connected with an input end signal UP, and the drain electrode of the P-channel MOS tube K20 is connected with the drain electrode of the N-channel MOS tube K21; the source electrode of the N-channel MOS tube K25 is connected with the ground GS, the grid electrode of the N-channel MOS tube K25 is connected with the input end control signal Vctrl _ N, and the drain electrode of the N-channel MOS tube K21 and the source electrode of the N-channel MOS tube K23; the grid electrode of the N-channel MOS tube K23 is connected with the reverse direction of the signal DOWN at the input end, and the drain electrode of the N-channel MOS tube K23 is connected with the drain electrode of the P-channel MOS tube K22; the grid electrode of the P-channel MOS tube K22 is connected with the reverse direction of the signal UP at the input end, and the drain electrode of the P-channel MOS tube K20 is connected with the output end Vctrl.

Further, the filter K7 includes a capacitor K24, a resistor K25, and a capacitor K26;

one ends of the capacitor K24 and the capacitor K26 are connected to the ground GS; the input end Vctrl is connected to the other end of the capacitor K24, connected to one end of the resistor K25 and connected to the output end Vctrl _ A; the other end of the resistor K25 is connected to the other end of the capacitor K26;

the reference circuit K8 comprises a P-channel MOS tube K26, a P-channel MOS tube K27, a P-channel MOS tube K32, a P-channel MOS tube K33, a P-channel MOS tube K34, a P-channel MOS tube K35, an N-channel MOS tube K28, an N-channel MOS tube K29, an N-channel MOS tube K30, an N-channel MOS tube K31, an N-channel MOS tube K39, an N-channel MOS tube K36, an N-channel MOS tube K37 and a resistor K38;

a power supply VS is connected to the source electrode of a P-channel MOS tube K26, the gate electrode of a P-channel MOS tube K26 is connected to the output end of a resistor K38, the drain electrode of the P-channel MOS tube K26 is connected to the source electrode of a P-channel MOS tube K27, the gate electrode of a P-channel MOS tube K27 is connected to the ground GS, the drain electrode of the P-channel MOS tube K26 is connected to the drain electrode and the gate electrode of an N-channel MOS tube K28, the gate electrode of the N-channel MOS tube K28 is connected to the gate electrode of an N-channel MOS tube K30, the source electrode of the N-channel MOS tube K28 is connected to the drain electrode of an N-channel MOS tube K29 and the source electrode of an N-channel MOS tube K30, the gate electrode of the N-channel MOS tube K29 is connected to a control signal ctrl, and the source electrode of the N-channel MOS tube K29 is connected to the ground GS; the source of the N-channel MOS transistor K30 is connected to the sources of the N-channel MOS transistor K31 and the N-channel MOS transistor K39, the gate of the N-channel MOS transistor K31 is connected to the input control signal Vctrl _ a, the drain of the N-channel MOS transistor K31 is connected to the input of the resistor K38 and the drain of the P-channel MOS transistor K33, the gate of the N-channel MOS transistor K39 is connected to the gate of the N-channel MOS transistor K37, the drain of the N-channel MOS transistor K39 is connected to the gate and the drain of the P-channel MOS transistor K32, the source of the P-channel MOS transistor K32 is connected to the power supply VS and the source of the P-channel MOS transistor K33, the drain of the P-channel MOS transistor K33 is connected to the input of the resistor K38, and the output of the resistor K38 is connected to the gate of the P-channel MOS transistor K34 and the output Vctrl _ P; the source electrode of the P-channel MOS tube K34 is connected to a power supply VS, the drain electrode is connected to the source electrode of the P-channel MOS tube K35, the grid electrode of the P-channel MOS tube K35 is connected to the GS, the drain electrode of the P-channel MOS tube K35 is connected to the drain electrode of the N-channel MOS tube K37, the grid electrode of the N-channel MOS tube K37 is connected to the output end Vctrl _ N and the drain electrode of the N-channel MOS tube K36, the grid electrode of the N-channel MOS tube K36 is connected to a control signal ctrl, and the source electrode is connected to the GS.

Further, the mirror symmetry delay chain comprises a delay unit K40, a delay unit K41, a delay unit K42, a delay unit K43, a delay unit K44, a P-channel MOS transistor K39, an N-channel MOS transistor K45, an inverter K46, an inverter K47, an inverter K48 and an inverter K49;

a signal CK _ IN at a common clock input end is connected to an input end of a delay unit K40, a control end C40 of the delay unit K40 is connected to a control end C40 of a delay unit K40, a control end C40 of the delay unit K40, a grid electrode of a P-channel MOS tube K40 is connected to an input end Vctrl _ P, a source electrode of the P-channel MOS tube K40 is connected to a power supply VS, a control end C40 of the delay unit K40 is connected to a control end C40 of the delay unit K40, a source electrode of the N-channel MOS tube K40, a grid electrode of the N-channel MOS tube K40 is connected to a ground, a C40 of the output end of the delay unit K40 is connected to a next stage C40 of the delay unit K40, a drain electrode of the delay unit K40 is connected to a next stage C40, a drain electrode of the delay unit K40, a drain of the delay unit K40 is connected to a lower stage C40, a drain of the delay unit K40, a delay unit K40 is connected to a lower stage C40, a drain of the delay unit K40 is connected to a delay unit K40, a lower stage of the delay unit K40 is connected to a delay unit K40, a drain of the delay unit K40 is connected to a lower stage, a delay unit K40 is connected to a drain of the delay unit K40, a drain of the delay unit K40 is connected to a drain, a drain of the delay unit K40 is connected to a lower stage, a drain, a delay unit K40 is connected to a drain of the delay unit K40 is connected to a delay unit K40, a drain of the delay unit K40 is connected to a delay unit K40, a delay unit K40 is connected to a ground, a delay unit K40 is connected to a delay unit K40, a delay unit K40 is connected to a delay unit K40, a lower stage, a delay unit K40 is connected to a delay unit K40, a delay unit K685, The output end Clk90 and the input end of the inverter K47 are connected, the output end C60 of the delay unit K42 is connected with the input end of the next-stage delay unit K43, the output end Clk _135 and the input end of the inverter K48, the output end C63 of the delay unit K43 is connected with the input end of the next-stage delay unit K44, the output end Clk180 and the input end of the inverter K49, the output end of the inverter K46 is connected with the output end Clk _225, the output end of the inverter K47 is connected with the output end Clk _270, the output end of the inverter K48 is connected with the output end Clk _315, and the output end of the inverter K49 is connected with the output end Clk _ 0.

Further, the gray code phase selector is connected to the input terminals Clk _45, Clk _225, Clk _90, Clk _270, Clk _135, Clk _315, Clk _180, Clk _0, to the external input terminals PS0, PS1, PS2, to the output terminal Out1_ P, Out1_ N, Out2_ P, Out2_ N.

Further, the gray code phase interpolator includes a gray code decoding circuit K51, a P-channel MOS tube K611, a P-channel MOS tube K51, a P-channel N channel K51, a P-channel K51, and N channel K51, and N channel K51, a P-channel K51, N channel MOS channel K51, and N channel K51;

gray code decoding circuit is connected with input terminals PI0, PI1 and PI2, outputs 16 control signals I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15 and I16, a power supply VS is connected with the source of a P-channel MOS tube K52, the grid of the P-channel MOS tube K52 is connected with an input terminal Vctrl _ P, the drain of the P-channel MOS tube K52 is connected with the source of the P-channel MOS tube K61 and the source of the P-channel MOS tube K611, the grid of the P-channel MOS tube K61 is connected with a ground GS, the grid of the P-channel MOS tube K611 is connected with a control signal I0, the drain of the P-channel MOS tube K0 is connected with the drain of the P-channel MOS tube K0, the drain of the P-channel MOS tube K0, the drain of the MOS tube K0 of the MOS tube 0, the drain electrode of the P-channel MOS tube K611 is connected with the drain electrode of the P-channel MOS tube K63, the drain electrode of the P-channel MOS tube K65, the drain electrode of the P-channel MOS tube K67, the drain electrode of the P-channel MOS tube K69, the drain electrode of the P-channel MOS tube K71, the drain electrode of the P-channel MOS tube K73, the drain electrode of the P-channel MOS tube K75, the drain electrode of the P-channel MOS tube K77, the source electrode of the P-channel MOS tube K79 and the source electrode of the P-channel MOS tube K81, the power supply VS is connected with the source electrode of the P-channel MOS tube K53, the grid electrode of the P-channel MOS tube K53 is connected with the input terminal Vctrl _ P, the drain electrode of the P-channel MOS tube K53 is connected with the source electrode of the P-channel MOS tube K62 and the source electrode of the P-channel MOS tube K63, the grid electrode of the P-channel MOS tube K62 is connected with the control signal I1, the grid electrode of the P-channel MOS tube K63, the power supply VS is connected with the source electrode of the P-channel MOS tube K54, the drain electrode of the P-channel MOS tube K46K 386 and the drain electrode of the P-channel MOS tube K463, the grid of the P-channel MOS tube K64 is connected with a control signal I3, the grid of the P-channel MOS tube K65 is connected with a control signal I4, the power supply VS is connected with the source of the P-channel MOS tube K55, the grid of the P-channel MOS tube K55 is connected with an input end Vctrl _ P, the drain of the P-channel MOS tube K55 is connected with the source of the P-channel MOS tube K66 and the source of the P-channel MOS tube K67, the grid of the P-channel MOS tube K66 is connected with a control signal I5, the grid of the P-channel MOS tube K67 is connected with a control signal I6, the power supply VS is connected with the source of the P-channel MOS tube K56, the grid of the P-channel MOS tube K56 is connected with the input end Vctrl _ P, the drain of the P-channel MOS tube K56 is connected with the source of the P-channel MOS tube K68 and the source of the P-channel MOS tube K69, the grid of the P-channel MOS tube K68 is connected with a control signal I7, the grid of the P-channel MOS tube K69, the source of the P-channel MOS tube K387 is connected with the input end Vctrl-channel MOS tube K57, the drain of a P-channel MOS tube K57 is connected with the source of a P-channel MOS tube K70 and the source of a P-channel MOS tube K71, the gate of a P-channel MOS tube K70 is connected with a control signal I9, the gate of a P-channel MOS tube K71 is connected with a control signal I10, a power supply VS is connected with the source of a P-channel MOS tube K58, the gate of a P-channel MOS tube K58 is connected with an input end Vctrl _ P, the drain of a P-channel MOS tube K58 is connected with the source of a P-channel MOS tube K72 and the source of a P-channel MOS tube K73, the gate of a P-channel MOS tube K72 is connected with a control signal I11, the gate of a P-channel MOS tube K73 is connected with a control signal I12, the power supply VS is connected with the source of a P-channel MOS tube K59, the gate of a P-channel MOS tube K59 is connected with an input end Vctrl _ P, the drain of a P-channel MOS tube K59 is connected with the source of a P-channel MOS tube K6852 and the source of a P-channel MOS tube K5475, the gate of a power supply K74 is connected with the source of a power supply control signal I74, the gate of a power supply VS 74, the control signal VS channel MOS tube K74 is connected with the gate of a P-channel MOS tube K74, the grid electrode of the P-channel MOS tube K60 is connected with an input end Vctrl _ P, the drain electrode of the P-channel MOS tube K60 is connected with the source electrode of the P-channel MOS tube K76 and the source electrode of the P-channel MOS tube K77, the grid electrode of the P-channel MOS tube K76 is connected with a control signal I15, the grid electrode of the P-channel MOS tube K77 is connected with a power supply VS, and the source electrode of the P-channel MOS tube K78, the source electrode of the P-channel MOS tube K79 and the source electrode of the P-channel MOS tube K80 are connected with a power supply Vdd input end K88; the drain electrode of the P-channel mos tube K78, the drain electrode of the P-channel mos tube K79 and the drain electrode of the P-channel mos tube K80 are connected to the drain electrode of the N-channel mos tube K81; the source of an N-channel mos tube K81 is connected to the drain of an N-channel mos tube K82, the source of the N-channel mos tube K82 is connected to the drain of the N-channel mos tube K83, the source of the N-channel mos tube K83 is connected to the ground, the gate of a P-channel mos tube K78 is connected to the input end Out1_ P, the gate of a P-channel mos tube K79 is connected to the input end Out2_ P, the gate of the P-channel mos tube K80 is connected to the input end Out1_ N, the gate of the P-channel mos tube K81 is connected to the input end Out2_ N, the drain of the P-channel mos tube K78 is connected to the drain of the N-channel mos tube K82, the drain of the P-channel mos tube K79 and the Output end Output _ N, the drain of the P-channel mos tube K80 is connected to the N-channel mos tube K81, the drain of the P-channel mos tube K83 and the Output end P-channel mos 78, the gate of the N-channel mos tube K82 is connected to the input end Vcgsl, the source is connected to the ground, the source of the input end GS tube K83 and the input end Vcgs.

The clock control method realized by the clock controller facing the DDR3 storage protocol comprises the following steps:

1) the digital delay phase-locked loop receives an external common clock signal CLK _ IN, outputs a clock signal CLK _ FB feedback access input, and controls an output voltage signal Vctrl _ P and Vctrl _ N to be a mirror symmetry delay chain;

2) the mirror symmetry delay chain receives an external common clock signal CLK _ IN, converts the input external common clock signal into 8 paths of output clocks Clk45, Clk225, Clk90, Clk270, Clk135, Clk315, Clk180, Clk0 to Gray code phase selectors with different phases under the control of a digital delay phase-locked loop voltage signal Vctrl _ P and Vctrl _ N;

3) the gray code phase selector receives external common control signals PS0, PS1 and PS2, and selects 8 paths of output clocks with different phases of the mirror symmetry delay chain to the gray code phase interpolator to perform phase interpolation;

4) the gray code phase interpolator receives external common control signals PI0, PI1 and PI2, receives Output voltage signals Vctrl _ P and Vctrl _ N of the digital delay phase-locked loop, receives Output of the gray code phase selector, and outputs external clock signals Output _ P and Output _ N, so that 64-level TAP interpolation can be performed on an external input clock through six control signals PS0, PS1, PS2, PI0, PI1 and PI2, and accurate phase interpolation and accurate clock delay are achieved.

Compared with the prior art, the invention has the advantages that:

(1) the invention realizes the accurate time delay of the clock by adopting the digital time delay phase-locked loop structure, can improve the flexibility of the clock controller, reduces the influence of the clock caused by process, temperature and noise by adopting the negative feedback structure, and provides the anti-interference capability of the clock controller.

(2) By adopting the mirror symmetry delay chain structure, the invention can ensure that the mirror symmetry delay chain and the digital delay phase-locked loop with the negative feedback structure have accurate and consistent phases, improve the stability and the reliability of high-frequency clock sampling, simultaneously realize the same quick locking with the digital delay phase-locked loop, and meet the requirements of DDR3 on sampling stability and high performance.

(3) By using the Gray code phase selector structure, the phase jitter brought by the traditional phase selection technology can be reduced, the phase selection can be rapidly and accurately carried out, the error of the phase selection is reduced, and the accurate phase precision and range of the DDR3 are realized.

(4) By adopting a Gray code phase interpolator structure, the invention can realize the accurate interpolation of 64-level TAP in the selected phase, ensure that the clock can be delayed to the central position of a data effective window, improve the sampling precision, ensure the correctness of DDR3 data acquisition and the balance of establishing holding time, ensure that a DDR3 storage interface can execute the correct read-write operation, and ensure the synchronization of internal and external clocks.

Drawings

FIG. 1 is a schematic diagram of a DDR3 memory protocol oriented clock controller of the present invention;

FIG. 2 is a schematic diagram of a digital delay locked loop circuit according to the present invention;

fig. 3 is a circuit schematic diagram of the phase detector K5 of the present invention;

FIG. 4 is a schematic diagram of a charge pump circuit of the present invention;

FIG. 5 is a schematic circuit diagram of the filter K7 of the present invention;

FIG. 6 is a schematic diagram of a reference circuit of the present invention;

FIG. 7 is a schematic diagram of a mirror symmetric delay chain circuit of the present invention;

FIG. 8 is a schematic diagram of the Gray code phase selector of the present invention;

fig. 9 is a schematic diagram of the gray code phase interpolator of the present invention.

Detailed Description

In order to better understand the technical solutions, the technical solutions of the present application are described in detail below with reference to the drawings and specific embodiments, and it should be understood that the specific features in the embodiments and examples of the present application are detailed descriptions of the technical solutions of the present application, and are not limitations of the technical solutions of the present application, and the technical features in the embodiments and examples of the present application may be combined with each other without conflict.

The DDR3 storage protocol oriented clock controller provided in the embodiments of the present application is described in further detail below with reference to the drawings in the specification, and specific implementations may include (as shown in fig. 1): the digital delay phase-locked loop K1, the mirror symmetry delay chain K2, the Gray code phase selector K3 and the Gray code phase interpolator K4.

IN the solution provided by the embodiment of the present application, as shown IN fig. 1, the digital delay locked loop input is connected to the external common clock signal input CLK _ IN, and the other input (C0) is connected to the digital delay locked loop output CLK _ FB (C1). The two outputs Vctrl _ P and Vctrl _ N are connected to a mirror symmetric delay chain.

The mirror symmetry delay chain inputs are connected to an external common clock signal input CLK _ IN, the other two inputs are connected to digital delay locked loop outputs Vctrl _ P and Vctrl _ N, and the outputs are connected to gray code phase selectors CLK45(C5), CLK225(C6), CLK90(C7), CLK270(C8), CLK135(C12), CLK315(C11), CLK180(C10), and CLK0 (C9).

The gray code phase selector is connected with external common control signals PS0(C15), PS1(C14) and PS2(C13) at input ends, connected with mirror symmetry delay chain input ends Clk45(C5), Clk225(C6), Clk90(C7), Clk270(C8), Clk135(C12), Clk315(C11), Clk180(C10) and Clk0(C9) at input ends, and connected with a gray code phase interpolator at output ends.

The input of the gray code phase interpolator receives external common control signals PI0(C16), PI1(C17) and PI2(C18), the input of the gray code phase interpolator is connected with the Output of the gray code phase selector, the input of the gray code phase interpolator is also connected with digital delay phase-locked loop outputs Vctrl _ P and Vctrl _ N, and the Output of the gray code phase interpolator is connected with external clock signals Output _ P (C20) and Output _ N (C21).

A digital delay locked loop, as shown in fig. 2, includes: the circuit comprises an N-channel mos tube K15, a P-channel mos tube K14, a delay unit K9, a delay unit K10, a delay unit K11, a delay unit K12, a delay unit K13, a phase discriminator K5, a charge pump K6, a filter K7 and a reference circuit K8.

An external common clock input terminal signal CK _ IN (C37) is connected to an input terminal of the delay unit K9 and an input terminal of the phase detector K5, and the other input terminal of the phase detector K5 is connected to a feedback clock signal CK _ FB (C38). The output UP (C39) and DOWN (C40) of the phase detector K5 are connected to the input of the charge pump (K6), and the output Vctrl (C41) of the charge pump is connected to the input of the filter K7. The filter K7 output Vctrl _ a (C42) is connected to the reference circuit (K8) input, the reference circuit output ports Vctrl _ P (C43) and Vctrl _ N (C44). The control end C24 of the delay unit K9 is connected to the drain of the P-channel MOS tube, the control end C23 is connected to the drain of the N-channel MOS tube, and the output end is connected to the input end of the next-stage delay unit K10. The control end C27 of the delay unit K10 is connected to the drain of the P-channel MOS tube, the control end C26 is connected to the drain of the N-channel MOS tube, and the output end is connected to the input end of the next-stage delay unit K11. The control end C30 of the delay unit K11 is connected to the drain of the P-channel MOS tube, the control end C29 is connected to the drain of the N-channel MOS tube, and the output end is connected to the input end of the next-stage delay unit K12. The control end C33 of the delay unit K12 is connected to the drain of the P-channel MOS tube, the control end C32 is connected to the drain of the N-channel MOS tube, and the output end is connected to the input end of the next-stage delay unit K13. The control terminal C35 of the delay unit K13 is connected to the drain of the P-channel MOS transistor, the control terminal C36 is connected to the drain of the N-channel MOS transistor, and the output terminal is connected to the feedback clock input CK _ FB (C38).

The phase detector K5, as shown in fig. 3, includes: flip-flop K16, flip-flop K19, inverter K18, nand gate K17.

An external common clock signal CK _ IN (C45) is connected to a clock input end of a flip-flop K16, a common clock signal CK _ FB (C46) is connected to a clock input end of a flip-flop K19, a data end of the flip-flop K16 is connected with a power supply VS, a data end of the flip-flop K19 is connected with the power supply VS, an output end Q of the flip-flop K16 and an output end Q of the flip-flop K19 are connected to an input port of a NAND gate K17, an output end of the NAND gate K17 is connected with an input end of an inverter K18, and an output end of the inverter K18 is connected to reset ports of the flip-flop K16 and the flip-flop K19.

The charge pump, as shown in fig. 4, includes: p-channel MOS pipe K24, P-channel MOS pipe K20, P-channel MOS pipe K22, N-channel MOS pipe K21, N-channel MOS pipe K23 and N-channel MOS pipe K25.

The power source VS is connected to the source of the P-channel MOS transistor K24, the gate of the P-channel MOS transistor K24 is connected to the input terminal control signal Vctrl _ P, and the drain is connected to the sources of the P-channel MOS transistor K20 and the P-channel MOS transistor K22. The grid electrode of the P-channel MOS tube K20 is connected with the input end signal UP, and the drain electrode is connected with the drain electrode of the N-channel MOS tube K21. The source of the N-channel MOS tube K25 is connected to the ground GS, the gate is connected to the input end control signal Vctrl _ N, and the drain is connected to the sources of the N-channel MOS tube K21 and the N-channel MOS tube K23. The gate of the N-channel MOS transistor K23 is connected to the inverse of the input signal DOWN, and the drain is connected to the drain of the P-channel MOS transistor K22. The grid electrode of the P-channel MOS tube K22 is connected with the reverse direction of the signal UP at the input end, and the drain electrode of the P-channel MOS tube K20 is connected with the output end Vctrl.

The filter K7, as shown in fig. 5, includes: capacitor K24, resistor K25, and capacitor K26.

One end of the capacitor K24 and one end of the capacitor K26 are connected to the ground GS. The input terminal Vctrl (C49) is connected to the other end of the capacitor K24, to one end of the resistor K25, and to the output terminal Vctrl _ a. The other end of the resistor K25 is connected to the other end of the capacitor K26.

The reference circuit, as shown in fig. 6, includes: p channel MOS pipe K26, P channel MOS pipe K27, P channel MOS pipe K32, P channel MOS pipe K33, P channel MOS pipe K34, P channel MOS pipe K35, N channel MOS pipe K28, N channel MOS pipe K29, N channel MOS pipe K30, N channel MOS pipe K31, N channel MOS pipe K39, N channel MOS pipe K36, N channel MOS pipe K37, resistance K38.

The power source VS is connected to the source electrode of the P-channel MOS tube K26, the grid electrode of the P-channel MOS tube K26 is connected to the output end of the resistor K38, the drain electrode of the P-channel MOS tube K26 is connected to the source electrode of the P-channel MOS tube K27, the grid electrode of the P-channel MOS tube K27 is connected to the ground GS, the drain electrode of the P-channel MOS tube K26 is connected to the drain electrode and the grid electrode of the N-channel MOS tube K28, the grid electrode of the N-channel MOS tube K28 is connected to the grid electrode of the N-channel MOS tube K30, the source electrode of the N-channel MOS tube K28 is connected to the drain electrode of the N-channel MOS tube K29 and the source electrode of the N-channel MOS tube K30, the grid electrode of the N-channel MOS tube K29 is connected to the control signal ctrl, and the source electrode of the N-channel MOS tube K29 is connected to the ground GS. The source of the N-channel MOS transistor K30 is connected to the sources of the N-channel MOS transistor K31 and the N-channel MOS transistor K39, the gate of the N-channel MOS transistor K31 is connected to the input control signal Vctrl _ a, the drain of the N-channel MOS transistor K31 is connected to the input of the resistor K38 and the drain of the P-channel MOS transistor K33, the gate of the N-channel MOS transistor K39 is connected to the gate of the N-channel MOS transistor K37, the drain of the N-channel MOS transistor K39 is connected to the gate and the drain of the P-channel MOS transistor K32, the source of the P-channel MOS transistor K32 is connected to the power source VS and the source of the P-channel MOS transistor K33, the drain of the P-channel MOS transistor K33 is connected to the input of the resistor K38, and the output of the resistor K38 is connected to the gate of the P-channel MOS transistor K34 and the output Vctrl _ P. The source electrode of the P-channel MOS tube K34 is connected to a power supply VS, the drain electrode is connected to the source electrode of the P-channel MOS tube K35, the grid electrode of the P-channel MOS tube K35 is connected to the GS, the drain electrode of the P-channel MOS tube K35 is connected to the drain electrode of the N-channel MOS tube K37, the grid electrode of the N-channel MOS tube K37 is connected to the output end Vctrl _ N and the drain electrode of the N-channel MOS tube K36, the grid electrode of the N-channel MOS tube K36 is connected to a control signal ctrl, and the source electrode is connected to the GS.

The mirror symmetry delay chain, as shown in fig. 7, includes a delay unit K40, a delay unit K41, a delay unit K42, a delay unit K43, a delay unit K44, a P-channel MOS transistor K39, an N-channel MOS transistor K45, an inverter K46, an inverter K47, an inverter K48, and an inverter K49.

A common clock input end signal CK _ IN (C) is connected to an input end of a delay unit K, a control end C of the delay unit K is connected to a control end C of the delay unit K, a grid electrode of a P-channel MOS tube K is connected with an input end Vctrl _ P, a source electrode of the P-channel MOS tube K is connected with a power supply VS, a control end C of the delay unit K is connected to a control end C of the delay unit K, a drain electrode of an N-channel MOS tube K, a grid electrode of the N-channel MOS tube K is connected with an input end Vctrl _ N, a source electrode of the N-channel MOS tube K is connected with a ground GS, an output end C of the delay unit K is connected with an input end of a next-stage delay unit K, an output end Clk _45 and an input end of an inverter K, an output end C of the delay unit K is connected with an input end of a next-stage delay unit K, and a control end C of the delay unit K is connected with an input end of the next-stage, The output end Clk90 and the input end of the inverter K47 are connected, the output end C60 of the delay unit K42 is connected with the input end of the next-stage delay unit K43, the output end Clk _135 and the input end of the inverter K48, the output end C63 of the delay unit K43 is connected with the input end of the next-stage delay unit K44, the output end Clk180 and the input end of the inverter K49, the output end of the inverter K46 is connected with the output end Clk _225, the output end of the inverter K47 is connected with the output end Clk _270, the output end of the inverter K48 is connected with the output end Clk _315, and the output end of the inverter K49 is connected with the output end Clk _ 0.

The gray code phase selector, as shown in fig. 8, includes: gray code phase selector K50

The gray code phase selector is connected with the input terminals Clk _45, Clk _225, Clk _90, Clk _270, Clk _135, Clk _315, Clk _180 and Clk _0, the external input terminals PS0, PS1 and PS2 and the output terminal Out1_ P, Out1_ N, Out2_ P, Out2_ N.

The gray code phase interpolator, as shown in fig. 9, includes a gray code decoding circuit K51, a P-channel MOS transistor K611, a P-channel MOS transistor K51, a P-channel MOS transistor K51, a P-channel MOS transistor K51, a P-channel K51, a P-channel K51, and a P-channel K51, a P-channel MOS transistor K51, a P-channel MOS transistor K51, a P-channel P-channel K51, a P-channel K51, and a P-channel K51.

The whole circuit can work under the frequency clock of 400 MHz-800 MHz, can use in the DRAM memory interface towards DDR3 storage protocol. Under normal working conditions, the circuit adopts a 28-nanometer process device of a central core international company, and can also select a proper device type according to the requirements of users, so that the accurate delay of 64-level TAP of a DDR3 clock is realized, and the clock can be delayed to the central position of a data effective window. Particularly, under the frequency clock of 800MHz, the highest delay precision of each TAP can reach 19.53ps, and the high-frequency performance of the DRAM of the DDR3 protocol is met.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.

Those skilled in the art will appreciate that those matters not described in detail in the present specification are well known in the art.

Claims

1. A DDR3 storage protocol oriented clock controller, comprising: the digital delay phase-locked loop, the mirror symmetry delay chain, the Gray code phase selector and the Gray code phase interpolator;

the gray code phase interpolator receives external common control signals PI0, PI1 and PI2, receives Output voltage Vctrl _ P and Vctrl _ N of the digital delay phase-locked loop, receives Output of the gray code phase selector, and outputs external clock signals Output _ P and Output _ N;

the digital delay phase-locked loop comprises an N-channel mos tube K15, a P-channel mos tube K14, a delay unit K9, a delay unit K10, a delay unit K11, a delay unit K12, a delay unit K13, a phase discriminator K5, a charge pump K6, a filter K7 and a reference circuit K8;

2. The clock controller for DDR3 storage protocol-oriented memory controller of claim 1, wherein: the frequency range of the external common clock signal CLK _ IN is 400 MHz-800 MHz; the external clock signals Output _ P and Output _ N are a pair of differential Output clock signals; the external common control signals PS0, PS1 and PS2 are clock signals for controlling the gray code phase selector to normally control the working; the external common control signals PI0, PI1, and PI2 are clock signals for controlling the gray code phase interpolator to normally control the operation.

3. The clock controller for DDR3 storage protocol-oriented memory controller of claim 1, wherein: the phase detector K5 comprises a flip-flop K16, a flip-flop K19, an inverter K18 and a NAND gate K17;

4. The clock controller for DDR3 storage protocol-oriented memory controller of claim 1, wherein: the charge pump K6 comprises a P-channel MOS tube K24, a P-channel MOS tube K20, a P-channel MOS tube K22, an N-channel MOS tube K21, an N-channel MOS tube K23 and an N-channel MOS tube K25;

5. A DDR3 storage protocol oriented clock controller in accordance with claim 1, wherein: the filter K7 comprises a capacitor K24, a resistor K25 and a capacitor K26;

6. The clock controller for DDR3 storage protocol-oriented memory controller of claim 1, wherein: the mirror symmetry delay chain comprises a delay unit K40, a delay unit K41, a delay unit K42, a delay unit K43, a delay unit K44, a P-channel MOS tube K39, an N-channel MOS tube K45, an inverter K46, an inverter K47, an inverter K48 and an inverter K49;

7. The clock controller for DDR3 storage protocol-oriented memory controller of claim 1, wherein: the gray code phase selector is connected with the input terminals Clk _45, Clk _225, Clk _90, Clk _270, Clk _135, Clk _315, Clk _180 and Clk _0, the external input terminals PS0, PS1 and PS2 and the output terminal Out1_ P, Out1_ N, Out2_ P, Out2_ N.

8. The clock controller for DDR3 storage protocol-oriented memory controller of claim 1, wherein: a gray code phase interpolator, including a gray code decoding circuit K51, a P-channel MOS tube K611, a P-channel MOS tube K51, a P-channel K51, a P-channel K51, and a P-channel K51;

9. The clock control method implemented by the clock controller facing the DDR3 storage protocol as claimed in claim 1, wherein the method comprises the following steps: