CN101056097A - Time impulse generator and shift buffer - Google Patents
Time impulse generator and shift buffer Download PDFInfo
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- CN101056097A CN101056097A CN 200610060284 CN200610060284A CN101056097A CN 101056097 A CN101056097 A CN 101056097A CN 200610060284 CN200610060284 CN 200610060284 CN 200610060284 A CN200610060284 A CN 200610060284A CN 101056097 A CN101056097 A CN 101056097A
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Abstract
The present invention relates to a time pulse generator including an input end, and output end, a logic brake and a plurality of inverters. The logic brake includes two input ends and one output end. Odd number of converters are connected in series between the input end of the logic brake and the input end of the time pulse generator, while even number of converters are connected in series between the other input end of the logic brake and the output end of the time pulse generator. The present invention also provides a displacement buffer using said time pulse generator.
Description
[technical field]
The present invention relates to a kind of clock pulse generator (Clock-pulse Generator) and use the bit shift register (Shift Register) of this clock pulse generator, refer in particular to a kind of clock pulse generator and bit shift register that is applied to LCD.
[background technology]
Bit shift register is Thin Film Transistor-LCD (Thin Film TransistorLiquid Crystal Display, TFT-LCD) drive integrated circult (IntegratedCircuit, IC) core, it provides each scan line of LCD pulse signal in proper order, and then control thin-film transistor (Thin Film Transistor, switch TFT) on this scan line.
A kind of bit shift register of prior art as shown in Figure 1, this bit shift register 2 comprises that a clock pulse generator 20, mixes latched flip flop (Modified Hybrid LatchFlip-Flop, MHLFF) 25 and one buffer 29.This clock pulse generator 20 comprises an input 23 and an output 24, and this mixing latched flip flop 25 comprises a pulse input end 26, a data input pin 27 and a signal output part 28.The output 24 of this clock pulse generator 20 is connected with the pulse input end 26 of this mixing latched flip flop 25, and the signal output part 28 of this buffer 29 and this mixing latched flip flop 25 is connected.
This clock pulse generator 20 produces a series of positive pulse signals and offers this mixing latched flip flop 25 according to the clock signal that this input 23 receives, this mixing latched flip flop 25 reaches from the data-signal of these data input pin 27 inputs according to this positive pulse signal and produces a plurality of control signals, offers follow-up circuit after this buffer 29 postpones to amplify.
See also Fig. 2, it is the functional block diagram of this clock pulse generator 20.This clock pulse generator 20 further comprises a NAND gate 201, one first inverter 205, one second inverter 206, one the 3rd inverter 207, one the 4th inverter 208.The first input end 202 of this NAND gate 201 directly connects this input 23, this second, third, the 4th inverter 206,207,208 is serially connected between second input 203 and this input 23 of this NAND gate 201 successively.This first inverter 205 is serially connected between the output 204 and this output 24 of this NAND gate 201.
See also Fig. 3, it is the working waveform figure of this clock pulse generator 20.The voltage clock signal waveform of these input 23 inputs is shown in Fig. 3 (A), through this second, third, reach the voltage waveform of these NAND gate 201 second inputs 203 shown in Fig. 3 (B) after 206,207,208 3 inverse delayed of the 4th inverter, wherein, transistorized breadth length ratio (W/L) realizes the carryover effects of this voltage waveform in the inverter by regulating.The voltage of 201 pairs of these first, second input 202,203 inputs of this NAND gate is handled, when being all 1, the voltage of these first, second input 202,203 inputs produces a undersuing, signal promptly forms the undersuing sequence shown in Fig. 3 (C) continuously, after these first inverter, 205 inverse delayed form the positive pulse signal sequence shown in Fig. 3 (D) and pass to this mixing latched flip flop 25 and further handle.
This positive pulse signal width is relevant with the mutual retardation of voltage of this NAND gate 201 2 inputs input.The signal delay of second input 203 of this NAND gate 201 can by this second, third, the 4th inverter 206,207,208 or more a plurality of inverters are set control, this first input end 202 is owing to directly be connected the retardation of uncontrollable its signal with this input 23.Only can control under the condition of retardation of an input at this, the width of the pulse signal that this NAND gate 201 produces will be difficult to control, if the width of this pulse signal is too short, the phenomenon of this mixing latched flip flop 25 will occur triggering.So, the less stable of this bit shift register 2.
[summary of the invention]
In order to solve the problem that clock pulse generator in the prior art is difficult to control the pulse duration of output, the invention provides a kind of clock pulse generator that can better control the pulse duration of output.
The bit shift register that provides a kind of stability higher is provided simultaneously.
A kind of clock pulse generator, it comprises: an input, one output, a plurality of inverters, one produces the logic lock of pulse signal, and it comprises two inputs and an output, serial connection one inverter between the output of this logic lock and the output of this clock pulse generator, serial connection odd number inverter is connected in series even number of inverters between the input of its another input and this clock pulse generator between one input of this logic lock and the input of this clock pulse generator.
A kind of bit shift register, it comprises that a clock pulse generator, of serial connection mixes a latched flip flop and a buffer successively, this clock pulse generator is aforesaid clock pulse generator.
Compared to prior art, first, second input of the logic lock of this clock pulse generator is connected by odd number, even number inverter and this input respectively, the quantity of the inverter that change links to each other with first, second input, can control the retardation of the clock signal of this first, second input input simultaneously, thereby better control the width of the pulse of its output, so that adopt the stability of the bit shift register of this clock pulse generator to improve.
[description of drawings]
Fig. 1 is a kind of functional block diagram of prior art bit shift register.
Fig. 2 is the circuit diagram of clock pulse generator shown in Figure 1.
Fig. 3 is the operating voltage oscillogram of clock pulse generator shown in Figure 2.
Fig. 4 is the circuit diagram of clock pulse generator first execution mode of the present invention.
Fig. 5 is the operating voltage oscillogram of clock pulse generator shown in Figure 4.
Fig. 6 is the functional block diagram that adopts the bit shift register of clock pulse generator shown in Figure 4.
Fig. 7 is the circuit diagram of clock pulse generator second execution mode of the present invention.
Fig. 8 is the operating voltage oscillogram of clock pulse generator shown in Figure 7.
Fig. 9 is the circuit diagram of clock pulse generator the 3rd execution mode of the present invention.
Figure 10 is the operating voltage oscillogram of clock pulse generator shown in Figure 9.
[embodiment]
See also Fig. 4, it is the circuit diagram of clock pulse generator first execution mode of the present invention.This clock pulse generator 60 comprises an input 63, an output 64, a NAND gate 601, one first inverter 605, one second inverter 606, one the 3rd inverter 607 and one the 4th inverter 608.This second inverter 606 of 63 serial connections of the first input end 602 of this NAND gate 601 and this input, second input 603 of this NAND gate 601 and 63 of this inputs are connected in series the 3rd, the 4th inverter 607,608 successively.This first inverter 605 of 64 serial connections of the output 604 of this NAND gate 601 and this output.
See also Fig. 5, it is the operating voltage oscillogram of this clock pulse generator 60.The voltage clock signal waveform of these input 63 inputs is shown in Fig. 5 (A), the voltage waveform that reaches these NAND gate 601 first input ends 602 after these second inverter, 606 inverse delayed reaches the voltage waveform of these NAND gate 601 second inputs 603 shown in Fig. 5 (C) after the 3rd, the 4th inverter 607,608 secondary inverse delayed shown in Fig. 5 (B).Wherein, transistorized breadth length ratio (W/L) realizes the carryover effects of this voltage waveform in the inverter by regulating, and for example, when transistorized breadth length ratio is 10 in second inverter 606, does not then postpone basically through the waveform behind this second inverter 606; When transistorized breadth length ratio is 0.1 in the 3rd, the 4th inverter 607,608, then apparent in view delay has just been arranged through the waveform behind the 3rd, the 4th inverter 607,608.The clock signal of 601 pairs of these first, second input 602,603 inputs of this NAND gate is handled, be all 1 place at it and form a undersuing, signal promptly forms the undersuing sequence shown in Fig. 5 (D) continuously, after these first inverter, 605 inverse delayed form the positive pulse signal sequence shown in Fig. 5 (E) and pass to subsequent conditioning circuit and further handle.
First, second input 602,603 of this NAND gate 601 is not limited to be connected with this input 63 by one, two inverters, but the width of the positive pulse that can produce is as required selected the inverter of other suitable number, for example can be respectively three, four etc., an end is an odd number only to need to satisfy wherein, and the other end is that even number gets final product.What of inverter quantity by controlling these first, second input 602,603 correspondences can be controlled simultaneously from the retardation of the clock signal of these first, second input 602,603 inputs, thereby better control the width of the positive pulse signal of its generation.
See also Fig. 6, it is the functional block diagram of bit shift register of the present invention.This bit shift register 6 uses this clock pulse generator 60 and comprises that further one mixes a latched flip flop 65 and a buffer 69.This mixing latched flip flop 65 comprises a pulse input end 66, a data input pin 67 and a signal output part 68.The output 64 of this clock pulse generator 60 is connected with the pulse input end 66 of this mixing latched flip flop 65, and the signal output part 68 of this buffer 69 and this mixing latched flip flop 65 is connected.
This clock pulse generator 60 produces a series of positive pulse signals and offers this mixing latched flip flop 65, this mixing latched flip flop 65 reaches from the data-signal of these data input pin 67 inputs according to this positive pulse signal and produces a plurality of control signals, offers follow-up circuit after this buffer 69 postpones to amplify.
This bit shift register 6 is because the width of the positive pulse signal that this clock pulse generator 60 of employing and this clock pulse generator 60 produce can be better controlled, and its stability is higher.
See also Fig. 7, it is the circuit diagram of clock pulse generator second execution mode of the present invention.This clock pulse generator 70 comprises an input 73, an output 74, a NOR gate 701, one first inverter 705, one second inverter 706, one the 3rd inverter 707 and one the 4th inverter 708.This second inverter 706 of 73 serial connections of the first input end 702 of this NOR gate 701 and this input, second input 703 of this NOR gate 701 and 73 of this inputs are connected in series the 3rd, the 4th inverter 707,708 successively, this first inverter 705 of 74 serial connections of the output 704 of this NOR gate 701 and this output.
See also Fig. 8, it is the operating voltage oscillogram of this clock pulse generator 70.Wherein, Fig. 8 (A) is the voltage clock signal oscillogram of these input 73 inputs, Fig. 8 (B) is the voltage oscillogram of the first input end 702 of this NOR gate 701, Fig. 8 (C) is the voltage oscillogram of second input 703 of this NOR gate 701, Fig. 8 (D) is the oscillogram of positive pulse signal sequence of output 704 output of this NOR gate 701, and Fig. 8 (E) is the oscillogram of the undersuing sequence that produces of this clock pulse generator 70.The difference of this clock pulse generator 70 and this clock pulse generator 60 is: it is to be all at the voltage that this first, second input 702,703 is imported to produce a series of positive pulse signals at 0 o'clock.
First, second input 702,703 of this NOR gate 701 is not limited to link to each other with this input 73 by one, two inverters, but the width of the positive pulse signal that can produce is as required selected the inverter of other suitable number, for example can be respectively three, four etc., an end is an odd number only to need to satisfy wherein, and the other end is that even number gets final product.Because first, second input 702,703 of this NOR gate 701 all links to each other with this input 73 by at least one inverter, the positive pulse width of its output also can better be controlled.
See also Fig. 9, it is the circuit diagram of clock pulse generator the 3rd execution mode of the present invention.This clock pulse generator 80 comprises an input 83, an output 84, a mutual exclusion or door 801,1 first inverter 805, one second inverter 806, one the 3rd inverter 807 and one the 4th inverter 808.This second inverter 806 of 83 serial connections of the first input end 802 of this mutual exclusion or door 801 and this input, second input 803 and 83 of this inputs of this mutual exclusion or door 801 are connected in series the 3rd, the 4th inverter 807,808 successively.This first inverter 805 of 84 serial connections of the output 804 of this mutual exclusion or door 801 and this output.
See also Figure 10, it is the operating voltage oscillogram of this clock pulse generator 80.Wherein, Figure 10 (A) is the voltage clock signal oscillogram of these input 83 inputs, Figure 10 (B) is the voltage oscillogram of the first input end 802 of this mutual exclusion or door 801, Figure 10 (C) is the voltage oscillogram of second input 803 of this mutual exclusion or door 801, Figure 10 (D) is the oscillogram of the undersuing sequence of this mutual exclusion or 804 outputs of door 801 output, and Figure 10 (E) is the oscillogram of the positive pulse signal sequence that produces of this clock pulse generator 80.The difference of this clock pulse generator 80 and this clock pulse generator 60 is: it is different at the voltage of these first, second input 802,803 inputs, and promptly one is 0, one to be to produce a positive pulse signal at 1 o'clock.
The width of the positive pulse that first, second input 802,803 of this mutual exclusion or door 801 also can produce as required selects the inverter of other suitable number to link to each other with this input 83, for example can be respectively three, four etc., an end is an odd number only to need to satisfy wherein, and the other end is that even number gets final product.Because first, second input 802,803 of this mutual exclusion or door 801 all links to each other with this input 83 by at least one inverter, the positive pulse width of its output also can better be controlled.
This bit shift register 6 also can adopt this clock pulse generator 70,80, also has the higher characteristics of stability.
Claims (9)
1. clock pulse generator, it comprises: an input, an output, a plurality of inverters, one produces the logic lock of pulse signal, and it comprises two inputs and an output, serial connection one inverter between the output of this logic lock and the output of this clock pulse generator; It is characterized in that: serial connection odd number inverter between an input of this logic lock and the input of this clock pulse generator is connected in series even number of inverters between the input of its another input and this clock pulse generator.
2. clock pulse generator as claimed in claim 1 is characterized in that: this logic lock is a NAND gate.
3. clock pulse generator as claimed in claim 1 is characterized in that: this logic lock is a NOR gate.
4. clock pulse generator as claimed in claim 1 is characterized in that: this logic lock is mutual exclusion or door.
5. as any described clock pulse generator in the claim 1 to 4, it is characterized in that: this odd number is one.
6. clock pulse generator as claimed in claim 5 is characterized in that: this even number is two.
7. as any described clock pulse generator in the claim 1 to 4, it is characterized in that: this odd number is three.
8. clock pulse generator as claimed in claim 7 is characterized in that: this even number is four.
9. bit shift register, it comprises that a clock pulse generator, of serial connection mixes a latched flip flop and a buffer successively, it is characterized in that: this clock pulse generator is the described clock pulse generator of claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200610060284 CN101056097A (en) | 2006-04-12 | 2006-04-12 | Time impulse generator and shift buffer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200610060284 CN101056097A (en) | 2006-04-12 | 2006-04-12 | Time impulse generator and shift buffer |
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| Publication Number | Publication Date |
|---|---|
| CN101056097A true CN101056097A (en) | 2007-10-17 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200610060284 Pending CN101056097A (en) | 2006-04-12 | 2006-04-12 | Time impulse generator and shift buffer |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102148614A (en) * | 2010-02-10 | 2011-08-10 | 上海宏力半导体制造有限公司 | Pulse generating circuit and method, reference voltage generating circuit and method as well as reference voltage driving circuit and method |
| US8487862B2 (en) | 2009-12-14 | 2013-07-16 | Chimei Innolux Corporation | Shift register and driving circuit for liquid crystal display |
| CN104539272A (en) * | 2014-11-27 | 2015-04-22 | 英业达科技有限公司 | Computer system provided with wake-up circuit |
| CN104849889A (en) * | 2015-05-12 | 2015-08-19 | 深圳市华星光电技术有限公司 | Liquid crystal display panel and liquid crystal display device |
| CN106057117A (en) * | 2016-06-28 | 2016-10-26 | 厦门天马微电子有限公司 | Shift register unit, shift register, and display panel |
-
2006
- 2006-04-12 CN CN 200610060284 patent/CN101056097A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8487862B2 (en) | 2009-12-14 | 2013-07-16 | Chimei Innolux Corporation | Shift register and driving circuit for liquid crystal display |
| CN102148614A (en) * | 2010-02-10 | 2011-08-10 | 上海宏力半导体制造有限公司 | Pulse generating circuit and method, reference voltage generating circuit and method as well as reference voltage driving circuit and method |
| CN102148614B (en) * | 2010-02-10 | 2015-11-11 | 上海华虹宏力半导体制造有限公司 | Pulse-generating circuit and method, reference voltage produce and promote circuit and method |
| CN104539272A (en) * | 2014-11-27 | 2015-04-22 | 英业达科技有限公司 | Computer system provided with wake-up circuit |
| CN104849889A (en) * | 2015-05-12 | 2015-08-19 | 深圳市华星光电技术有限公司 | Liquid crystal display panel and liquid crystal display device |
| CN104849889B (en) * | 2015-05-12 | 2018-05-18 | 深圳市华星光电技术有限公司 | Liquid crystal display panel and liquid crystal display device |
| CN106057117A (en) * | 2016-06-28 | 2016-10-26 | 厦门天马微电子有限公司 | Shift register unit, shift register, and display panel |
| CN106057117B (en) * | 2016-06-28 | 2019-11-12 | 厦门天马微电子有限公司 | Shifting deposit unit, shift register and display panel |
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