CN101339338B - Electric charge sharing mode LCD device, source drive device and electric charge sharing method - Google Patents
Electric charge sharing mode LCD device, source drive device and electric charge sharing method Download PDFInfo
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- CN101339338B CN101339338B CN2007100763027A CN200710076302A CN101339338B CN 101339338 B CN101339338 B CN 101339338B CN 2007100763027 A CN2007100763027 A CN 2007100763027A CN 200710076302 A CN200710076302 A CN 200710076302A CN 101339338 B CN101339338 B CN 101339338B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3685—Details of drivers for data electrodes
- G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/027—Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
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Abstract
The invention discloses a liquid crystal display having charge sharing mode, comprising a liquid crystal display screen, a grayscale generating circuit, a first switch circuit, a source driver, a gate driver and a logic control sequence circuit, the source driver comprising a source driving latch, a digital/analog converter, a source driving buffer and a source output control circuit which are sequentially connected, also comprising a second switch circuit, wherein the first switch circuit is serially connected between the grayscale generating circuit and the digital/analog converter, the second switch circuit is connected between the input terminal and the output terminal of the source driving buffer, the source output control circuit is a third switch circuit, and the logic control sequence circuit controls that the switch-on time of the second switch circuit and the third switch circuit at least has a coincident switch-on time arrange for synchronously switching on the second switch circuit and the third switch circuit, and controls the first switch circuit on a switch-off condition in at least a coincident switch-on time arrange. The liquid crystal display having charge sharing mode implements the charge sharing and reduces the power consumption of the source driver.
Description
[technical field]
The present invention relates to thin film transistor (TFT)-LCD (TFT-LCD), be particularly related under the prerequisite that does not reduce the Source drive driving force, use Thin Film Transistor-LCD and electric charge sharing method thereof that electric charge sharing mode reduces TFT-LCD driver (Thin Film Transistor-LCD chip for driving/driver) power consumption.
[background technology]
Along with the TFT LCD develops towards directions such as high integration, high resolving power, many gray scales, the power consumption and the area of corresponding chip for driving become increasing, and cost is more and more higher.As how less chip area and lower power consumption realize that TFT-LCD driver Source drive becomes the problem that the designer must consider.
[summary of the invention]
Fundamental purpose of the present invention solves the problems of the prior art exactly, a kind of LCD and electric charge sharing method thereof with electric charge sharing mode is provided, this LCD is used the power consumption that electric charge sharing mode reduces TFT-LCD driver under the prerequisite that does not reduce the Source drive driving force.
For achieving the above object, the invention provides a kind of LCD with electric charge sharing mode, comprise LCDs, GTG produces circuit, first on-off circuit, Source drive, gate driver, the logic control sequential circuit, be manufactured with a plurality of thin film transistor (TFT)s on the described LCDs, described GTG produces circuit output gray scale voltage to Source drive, the output terminal of described Source drive and gate driver is coupled respectively to the source electrode and the grid of thin film transistor (TFT), described Source drive comprises that the source that is linked in sequence drives latch, D/A, the source drives buffer and source output control circuit, described Source drive also comprises the second switch circuit, described first on-off circuit is serially connected in described GTG and produces between circuit and the D/A, the described second switch circuit source that is connected drives between the input end and output terminal of buffer, described source output control circuit is the 3rd on-off circuit, the output terminal of described the 3rd on-off circuit is coupled to the source electrode of thin film transistor (TFT), described logic control sequential circuit is exported first control timing to the first on-off circuit, export second control timing to the second switch circuit, export the 3rd control timing to the three on-off circuits, described logic control sequential circuit is controlled in the ON time of the ON time of second switch circuit and the 3rd on-off circuit and has a coincidence ON time section that makes second switch circuit and the conducting simultaneously of the 3rd on-off circuit at least, and described logic control sequential circuit is controlled first on-off circuit be in off-state at least one is overlapped ON time section.Wherein coupling refers in a different manner signal is delivered to that purpose parts, coupling scheme comprise indirect connection (for example carrying out the signal coupling by electric capacity or resistance) and direct connected mode.
Described first control timing, second control timing and the 3rd control timing are preferably synperiodic cyclical signal, in each cycle, described logic control sequential circuit control second switch circuit and the 3rd on-off circuit have one at least and overlap the ON time section, and described logic control sequential circuit is controlled first on-off circuit be in off-state at least one is overlapped ON time section.
Further improvement of the present invention is: described gate driver output film transistor controls sequential is in conducting state with control TFT when the conducting simultaneously of second switch circuit and the 3rd on-off circuit and first on-off circuit disconnect.
For achieving the above object, the present invention also provides a kind of LCD to carry out the method that electric charge is shared simultaneously, the electric charge sharing mode that is used for Thin Film Transistor-LCD, wherein, described LCD comprises LCDs, GTG produces circuit, Source drive, gate driver and logic control sequential circuit, be manufactured with a plurality of thin film transistor (TFT)s on the described LCDs, described GTG produces circuit output gray scale voltage to Source drive, the output terminal of described Source drive and gate driver is coupled respectively to the source electrode and the grid of thin film transistor (TFT), described LCD also comprises first on-off circuit, described Source drive comprises that the source that is linked in sequence drives latch, D/A, the source drives buffer and source output control circuit, described Source drive also comprises the second switch circuit, described first on-off circuit is serially connected in described GTG and produces between circuit and the D/A, the described second switch circuit source that is connected drives between the input end and output terminal of buffer, described source output control circuit is the 3rd on-off circuit, the output terminal of described the 3rd on-off circuit is coupled to the source electrode of thin film transistor (TFT), for electric charge can be shared, described electric charge sharing method may further comprise the steps:
A1, described logic control sequential circuit are exported control timing to the first on-off circuit, second switch circuit and the 3rd on-off circuit respectively, described control timing makes the coincidence ON time section that exists to make second switch circuit and the conducting simultaneously of the 3rd on-off circuit at least in the ON time of the ON time of second switch circuit and the 3rd on-off circuit, and first on-off circuit is in off-state at least one overlaps the ON time section;
A2, current line show finish after, before Source drive is to the charging of next line pixel, with all select the passage of same gray level voltage to be shorted to together in the next line, make the current line stored charge between the passage of all selection same gray level voltages, realize reallocation.
Wherein said steps A 2 may further comprise the steps:
A21, when the current line on the LCDs show finish after, the path that GTG produces between circuit and the source driving circuit is turned off, and the source drives data in the latch through decoding, and a certain passage in the control D/A is opened, and is the gray scale voltage of this channel selecting correspondence of next line;
A22, in overlapping the ON time section, by the second switch circuit source is driven the buffer short circuit, make LCDs form path between the D/A, make at least that the electric charge on the current line storage capacitors feeds back to D/A on the LCDs;
A23, simultaneously by D/A with all select the passage of same gray level voltages to be shorted to together in the next line, the electric charge on the current line storage capacitors is reallocated at described interchannel.
Wherein, in steps A 1, second switch circuit and the 3rd on-off circuit have a coincidence ON time section at least in each cycle of control timing, and first on-off circuit is in off-state at least one overlaps ON time section.
The present invention provides a kind of source drive device of LCD simultaneously, comprise that GTG produces circuit, Source drive and logic control sequential circuit, described GTG produces circuit output gray scale voltage to Source drive, described Source drive comprises that the source that is linked in sequence drives latch, D/A, the source drives buffer and source output control circuit, also comprise first on-off circuit, described Source drive also comprises the second switch circuit, described first on-off circuit is serially connected in described GTG and produces between circuit and the D/A, the described second switch circuit source that is connected drives between the input end and output terminal of buffer, described source output control circuit is the 3rd on-off circuit, the output terminal of described the 3rd on-off circuit is used to be coupled to LCDs, described logic control sequential circuit is exported first control timing to the first on-off circuit, export second control timing to the second switch circuit, export the 3rd control timing to the three on-off circuits, described logic control sequential circuit is controlled in the ON time of the ON time of second switch circuit and the 3rd on-off circuit and has a coincidence ON time section that makes second switch circuit and the conducting simultaneously of the 3rd on-off circuit at least, and described logic control sequential circuit is controlled first on-off circuit be in off-state at least one is overlapped ON time section.
Further improvement of the present invention is: described gate driver output film transistor controls sequential is in conducting state with control TFT when the conducting simultaneously of second switch circuit and the 3rd on-off circuit and first on-off circuit disconnect, make in steps A 22 that the electric charge on the current line storage capacitors and bus stray capacitance feeds back on the D/A on the LCDs, the electric charge on the current line storage capacitors and bus stray capacitance is reallocated at described interchannel.
The invention has the beneficial effects as follows: 1) the present invention produces circuit and on-off circuit of D/A increase at GTG, driving between the input end of buffer and the output terminal in the source increases an on-off circuit, by special control timing, stray capacitance on the bus is fed back, carry out the electric charge reallocation, the realization electric charge is shared, and has the advantage of existing charge shared model, has especially reduced the power consumption of TFT-LCDdriver.2) the present invention is by control timing, and the electric charge in the memory capacitance of current line is also fed back, and reallocates, and further reduced the power consumption of TFT-LCD driver.3) the present invention has only increased less transmission gate, on less chip area, can finish, and simple to the control timing of these transmission gates.
[description of drawings]
Fig. 1 is the structural drawing of TFT-LCD;
Fig. 2 is a functional-block diagram of the present invention;
Fig. 3 is the wherein circuit structure diagram of a branch road of an embodiment of the present invention;
Fig. 4 is the circuit structure diagram of an embodiment of the present invention;
Fig. 5 is the control timing figure of an embodiment of the present invention;
Fig. 6 is the preferred control timing figure of an embodiment of the present invention;
Fig. 7 is the control timing figure of the another kind of embodiment of the present invention.
[embodiment]
Feature of the present invention and advantage will be elaborated in conjunction with the accompanying drawings by embodiment.
Embodiment one:
LCD according to the present invention comprises that LCDs, GTG produce circuit, Source drive, gate driver and logic control sequential circuit, the structure of described LCDs as shown in Figure 1, be manufactured with many select lines G1, G2 and many data line S1, S2 of a plurality of thin film transistor (TFT) N1, mutually insulated on the panel, the grid of each thin film transistor (TFT) N1, source electrode and drain electrode are connected contiguous select lines, data line and pixel electrode (not marking among the figure) respectively, select lines is connected to the output terminal of gate driver, and data line is connected to the output terminal of Source drive.Described GTG produces circuit output gray scale voltage to Source drive.
As shown in Figure 2, described Source drive comprises that the source that is linked in sequence drives latch, D/A, the source drives buffer and source output control circuit, described first on-off circuit is serially connected in described GTG and produces between circuit and the D/A, the described second switch circuit source that is connected drives between the input end and output terminal of buffer, described source output control circuit is the 3rd on-off circuit, the output terminal of described the 3rd on-off circuit is coupled to the source electrode of the thin film transistor (TFT) of LCDs, described logic control sequential circuit is exported first control timing C1 to the first on-off circuit, export the second control timing C2 to the second switch circuit, export the 3rd control timing C3 to the three on-off circuits, to control first on-off circuit respectively, the conducting of second switch circuit and the 3rd on-off circuit and disconnection.
Please refer to Fig. 3,4, be illustrated in figure 3 as the circuit diagram of Source drive, be illustrated in figure 4 as the circuit diagram that Source drive outputs to many data lines for a data line.GTG produces circuit and comprises divider resistance and buffer, by electric resistance partial pressure, produces 64 grades of grayscale voltages, and just the voltage that reduces successively of 64 grades of sizes offers Source drive by buffer, finally shows 262,144 looks on liquid crystal display.First on-off circuit connects the output terminal that GTG produces the buffer of circuit, first on-off circuit is a cmos transmission gate, D/A (DAC) also connection source drives latch (LATCH), it is a follower that the source drives buffer, the second switch circuit is a cmos transmission gate, the source that is connected across drives the input end and the output terminal of buffer, and the 3rd on-off circuit is a cmos transmission gate, and the transmission gate T3 source that is connected drives between the source electrode of the output terminal of buffer and thin film transistor (TFT) N1.Transmission gate T3 is at transition status in conducting and between disconnecting under the control of the 3rd control timing C3, and when certain transmission gate T3 conducting, data-signal outputs on the data line that is connected with this transmission gate T3.And gate driver output film transistor controls sequential C4 is with conducting and the disconnection of control TFT N1.In order to make the storage capacitors C of LCD
sAnd the stray capacitance C on the bus (BUS)
aCan reallocate to reach the purpose that electric charge is shared, the sequential of the first control timing C1, the second control timing C2, the 3rd control timing C3 and thin film transistor (TFT) control timing C4 is set, make in the ON time of the ON time of ON time, transmission gate T3 of transmission gate T2 and thin film transistor (TFT) N1 to have a coincidence ON time section M who makes transmission gate T2, transmission gate T3 and thin film transistor (TFT) N1 conducting simultaneously at least, and overlap ON time section M at least one in transmission gate T1 be in off-state.A kind of embodiment of its control timing as shown in Figure 5, the first control timing C1, the second control timing C2, the 3rd control timing C3 and thin film transistor (TFT) control timing C4 are the cyclical signals with same period, high level makes the transmission gate conducting, in each cycle, have one and overlap ON time section M, transmission gate T2, transmission gate T3 and thin film transistor (TFT) N1 conducting simultaneously in this overlaps ON time section M, and transmission gate T1 disconnects.
Below to make transistor turns with high level be that example illustrates principle of the present invention and effect.
Under common mode of operation, because of there not being first on-off circuit, it is normally on that GTG produces between circuit and the D/A, and GTG produces the voltage that circuit generates, and selects to output on the TFT LCDs through DAC.Supposing has the voltage of two data channel selecting to be respectively V in the current line on the LCDs (for example X is capable)
mAnd V
n(V
m≠ V
n), and these two passages are all selected voltage V at next line (being that X+1 is capable), then power consumed is with regard to these two data passages: P
1=kcf[(V-V
m)
2+ (V-V
n)
2], wherein k is a coefficient, and c is a load capacitance, and f is a switching frequency.
Under the electric charge sharing mode of present embodiment, on the LCDs, after the current line demonstration is finished, the path that GTG produces between circuit and the source driving circuit is turned off, and the source drives the data process decoding in the latch, a certain passage among the control DAC is opened, to select corresponding gray scale voltage.Path between source driving circuit and the TFT-LCD display screen is opened simultaneously, is stored in LCDs current line (X is capable) storage capacitors C like this
sAnd BUS stray capacitance C
aOn electric charge will feed back.So next line (X+1 is capable) will select the passage of voltage V all to connect together by above-mentioned control.Because GTG produces circuit and turn-offs to the output that the source drives, and the path between source driving circuit and the TFT-LCD display screen is opened, so current line (X is capable) charge stored on the LCDs will be reallocated at these interchannels.Thereby reduce the power consumption of chip.
As shown in Figure 5, when the first control timing C1 is low level, when transmission gate T1 is turned off, the voltage that GTG produces the circuit generation no longer is output to source driving circuit, in the time of in entering this coincidence ON time section M, the second control timing C2, the 3rd control timing C3 and thin film transistor (TFT) control timing C4 are high level, and when transmission gate T2, T3 and thin film transistor (TFT) N1 were open mode, the source drove buffer OPA2 by short circuit.And the source that is latched in drives the decoding of data by DAC among the latch LATCH, selects the voltage of next line (X+1 is capable).Suppose that next line (X+1 is capable) will have two channel selecting voltage V, and the voltage that these two passage current lines (X is capable) are selected is respectively V
mAnd V
n, voltage V like this
mAnd V
nBe stored in LCDs storage capacitors C
sAnd BUS stray capacitance C
aOn electric charge, with respectively by thin film transistor (TFT) N1, transmission gate T3 and the T2 of passage feed back to DAC separately.Because these two passages are all selected voltage V through decoding at next line, this moment, transmission gate T1 turn-offed, and such two passages will be shorted to together by DAC, and charge stored will be reallocated on the electric capacity, and final two passage stored voltage are approximately respectively
Power consumed like this
Dissolve P respectively
1And P
2Have:
Because:
2(V
m 2+V
n 2)-(V
m+V
n)
2＝2V
m 2+2V
n 2-V
m 2-2V
mV
n-V
n 2
＝V
m 2-2V
mV
n+V
n 2＝(V
m-V
n)
2>0
So: P
1P
2
Therefore this electric charge sharing mode possesses the ability of province's power consumption.
Wherein, the first control timing C1, the second control timing C2, the 3rd control timing C3 and thin film transistor (TFT) control timing C4 preferred arrangement are to be provided with according to system clock, and as shown in Figure 6, wherein sys_clk is the system clock in the chip.In typical case, the time of scanning liquid crystal display delegation is 16 sys_clk, and just the cycle of the first control timing C1, the second control timing C2, the 3rd control timing C3 and thin film transistor (TFT) control timing C4 also is 16 clock length.In the one-period of the first control timing C1, high level is 13.5 clocks, and low level is 2.5 clocks.In the one-period of the second control timing C2,6 clocks of high level, 10 clocks of low level.In the one-period of the 3rd control timing C3, high level is 15 clocks, and low level is 1 clock.In the one-period of thin film transistor (TFT) control timing C4, high level is 14 clocks, and low level is 2 clocks.Identical under the sequential of the 3rd control timing C3 and thin film transistor (TFT) control timing C4 and the normal operation mode, the negative edge of thin film transistor (TFT) control timing C4 is carried previous clock than the negative edge of the 3rd control timing C3, the negative edge of the second control timing C2 is delayed a clock than the negative edge of the 3rd control timing C3, and the negative edge of the first control timing C1 is than leading half clock of the negative edge of the 3rd control timing C3.In each cycle, have one and overlap ON time section M.
As required, can also in one-period, design two or three and overlap ON time section M, the sequential chart shown in Fig. 5 for example as long as the dutycycle of the first control timing C1 is increased, just can be implemented in and has two in the one-period (or more than two) overlap ON time section M.
On-off circuit in the present embodiment also can be a triode, selects different transistors, has different concrete connecting circuit, and this belongs to prior art, no longer describes in detail.
Embodiment two:
What present embodiment and embodiment one were different is to only require that logic control sequential circuit control second switch circuit and the 3rd on-off circuit exist at least one to make the coincidence ON time section M of second switch circuit and the while conducting of the 3rd on-off circuit in its ON time, and described logic control sequential circuit is controlled first on-off circuit and be in off-state at least one is overlapped the ON time section, as shown in Figure 7, the first control timing C1, the second control timing C2 and the 3rd control timing C3 are the cyclical signals with same period, high level makes transistor turns, in each cycle, have one and overlap ON time section M, transmission gate T2 in this overlaps ON time section M, transmission gate T3 conducting simultaneously, and transmission gate T1 disconnects, and the conducting of thin film transistor (TFT) and disconnection and transmission gate T1, transmission gate T2, transmission gate T3 is irrelevant.In this case, when overlapping transmission gate T2, transmission gate T3 conducting in ON time section M at this, transmission gate T1 disconnects and thin film transistor (TFT) N1 also during conducting, has same effect with embodiment one.When overlap transmission gate T2, transmission gate T3 conducting in the ON time section M at this, when transmission gate T1 disconnection and thin film transistor (TFT) N1 disconnect, be stored in liquid crystal panel storage capacitors C
sOn electric charge can't feed back to D/A and reallocate, have only BUS stray capacitance C
aReallocate, embodiment one is poor for reducing power consumption energy force rate.Above content be in conjunction with concrete preferred implementation to further describing that the present invention did, can not assert that concrete enforcement of the present invention is confined to these explanations.For the general technical staff of the technical field of the invention, without departing from the inventive concept of the premise, can also make some simple deduction or replace, all should be considered as belonging to protection scope of the present invention.
Claims (11)
1. LCD with electric charge sharing mode, comprise LCDs, GTG produces circuit, Source drive, gate driver and logic control sequential circuit, be manufactured with a plurality of thin film transistor (TFT)s on the described LCDs, described GTG produces circuit output gray scale voltage to Source drive, the output terminal of described Source drive and gate driver is coupled respectively to the source electrode and the grid of thin film transistor (TFT), described Source drive comprises that the source that is linked in sequence drives latch, D/A, the source drives buffer and source output control circuit, it is characterized in that: also comprise first on-off circuit, described Source drive also comprises the second switch circuit, described first on-off circuit is serially connected in described GTG and produces between circuit and the D/A, the described second switch circuit source that is connected drives between the input end and output terminal of buffer, described source output control circuit is the 3rd on-off circuit, the output terminal of described the 3rd on-off circuit is coupled to the source electrode of thin film transistor (TFT), described logic control sequential circuit is exported first control timing to the first on-off circuit, export second control timing to the second switch circuit, export the 3rd control timing to the three on-off circuits, described logic control sequential circuit is controlled in the ON time of the ON time of second switch circuit and the 3rd on-off circuit and has a coincidence ON time section that makes second switch circuit and the conducting simultaneously of the 3rd on-off circuit at least, and described logic control sequential circuit is controlled first on-off circuit be in off-state at least one is overlapped ON time section.
2. the LCD with electric charge sharing mode as claimed in claim 1, it is characterized in that: described first control timing, second control timing and the 3rd control timing are synperiodic cyclical signal, in each cycle, described logic control sequential circuit control second switch circuit and the 3rd on-off circuit have one at least and overlap the ON time section, and described logic control sequential circuit is controlled first on-off circuit be in off-state at least one is overlapped ON time section.
3. the LCD with electric charge sharing mode as claimed in claim 2 is characterized in that: described gate driver output film transistor controls sequential is in conducting state with control TFT when the conducting simultaneously of second switch circuit and the 3rd on-off circuit and first on-off circuit disconnect.
4. the LCD with electric charge sharing mode as claimed in claim 3, it is characterized in that: described first control timing, second control timing, the 3rd control timing and thin film transistor (TFT) control timing are synperiodic cyclical signal, in each cycle, described coincidence ON time Duan Weiyi.
5. as each described LCD with electric charge sharing mode in the claim 1 to 4, it is characterized in that: described first on-off circuit, second switch circuit and the 3rd on-off circuit all are a cmos transmission gate.
6. a LCD is carried out the method that electric charge is shared, the electric charge sharing mode that is used for Thin Film Transistor-LCD, wherein, described LCD comprises LCDs, GTG produces circuit, Source drive, gate driver and logic control sequential circuit, be manufactured with a plurality of thin film transistor (TFT)s on the described LCDs, described GTG produces circuit output gray scale voltage to Source drive, the output terminal of described Source drive and gate driver is coupled respectively to the source electrode and the grid of thin film transistor (TFT), described LCD also comprises first on-off circuit, described Source drive comprises that the source that is linked in sequence drives latch, D/A, the source drives buffer and source output control circuit, described Source drive also comprises the second switch circuit, described first on-off circuit is serially connected in described GTG and produces between circuit and the D/A, the described second switch circuit source that is connected drives between the input end and output terminal of buffer, described source output control circuit is the 3rd on-off circuit, the output terminal of described the 3rd on-off circuit is coupled to the source electrode of thin film transistor (TFT), it is characterized in that: described electric charge sharing method may further comprise the steps:
A1, described logic control sequential circuit are exported control timing to the first on-off circuit, second switch circuit and the 3rd on-off circuit respectively, described control timing makes the coincidence ON time section that exists to make second switch circuit and the conducting simultaneously of the 3rd on-off circuit at least in the ON time of the ON time of second switch circuit and the 3rd on-off circuit, and first on-off circuit is in off-state at least one overlaps the ON time section;
A2, current line show finish after, before Source drive is to the charging of next line pixel, with all select the passage of same gray level voltage to be shorted to together in the next line, make the current line stored charge between the passage of all selection same gray level voltages, realize reallocation.
7. the method that electric charge as claimed in claim 6 is shared, it is characterized in that: wherein said steps A 1 may further comprise the steps:
A21, when the current line on the LCDs show finish after, the path that GTG produces between circuit and the source driving circuit is turned off, and the source drives data in the latch through decoding, and a certain passage in the control D/A is opened, and is the gray scale voltage of this channel selecting correspondence of next line;
A22, in overlapping the ON time section, by the second switch circuit source is driven the buffer short circuit, make LCDs form path between the D/A, make at least that the electric charge on the current line storage capacitors feeds back to D/A on the LCDs;
A23, simultaneously by D/A with all select the passage of same gray level voltages to be shorted to together in the next line, the electric charge on the current line storage capacitors is reallocated at described interchannel.
8. the method that electric charge as claimed in claim 6 is shared, it is characterized in that: in steps A 1, second switch circuit and the 3rd on-off circuit have a coincidence ON time section at least in each cycle of control timing, and first on-off circuit is in off-state at least one overlaps ON time section.
9. the method that electric charge as claimed in claim 8 is shared, it is characterized in that: described gate driver output film transistor controls sequential is in conducting state with control TFT when the conducting simultaneously of second switch circuit and the 3rd on-off circuit and first on-off circuit disconnect, make in steps A 22 that the electric charge on the current line storage capacitors and bus stray capacitance feeds back on the D/A on the LCDs, the electric charge on the current line storage capacitors and bus stray capacitance is reallocated at described interchannel.
10. the source drive device of a LCD, comprise that GTG produces circuit, Source drive and logic control sequential circuit, described GTG produces circuit output gray scale voltage to Source drive, described Source drive comprises that the source that is linked in sequence drives latch, D/A, the source drives buffer and source output control circuit, it is characterized in that: also comprise first on-off circuit, described Source drive also comprises the second switch circuit, described first on-off circuit is serially connected in described GTG and produces between circuit and the D/A, the described second switch circuit source that is connected drives between the input end and output terminal of buffer, described source output control circuit is the 3rd on-off circuit, the output terminal of described the 3rd on-off circuit is used to be coupled to LCDs, described logic control sequential circuit is exported first control timing to the first on-off circuit, export second control timing to the second switch circuit, export the 3rd control timing to the three on-off circuits, described logic control sequential circuit is controlled in the ON time of the ON time of second switch circuit and the 3rd on-off circuit and has a coincidence ON time section that makes second switch circuit and the conducting simultaneously of the 3rd on-off circuit at least, and described logic control sequential circuit is controlled first on-off circuit be in off-state at least one is overlapped ON time section.
11. source drive device as claimed in claim 10, it is characterized in that: described first control timing, second control timing and the 3rd control timing are synperiodic cyclical signal, in each cycle, described logic control sequential circuit control second switch circuit and the 3rd on-off circuit have one at least and overlap the ON time section, and described logic control sequential circuit is controlled first on-off circuit be in off-state at least one is overlapped ON time section.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007100763027A CN101339338B (en) | 2007-07-02 | 2007-07-02 | Electric charge sharing mode LCD device, source drive device and electric charge sharing method |
| PCT/CN2008/071529 WO2009003418A1 (en) | 2007-07-02 | 2008-07-02 | Source drive device, lcd and driving method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007100763027A CN101339338B (en) | 2007-07-02 | 2007-07-02 | Electric charge sharing mode LCD device, source drive device and electric charge sharing method |
Publications (2)
| Publication Number | Publication Date |
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| CN101339338A CN101339338A (en) | 2009-01-07 |
| CN101339338B true CN101339338B (en) | 2011-05-18 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2007100763027A Expired - Fee Related CN101339338B (en) | 2007-07-02 | 2007-07-02 | Electric charge sharing mode LCD device, source drive device and electric charge sharing method |
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| CN (1) | CN101339338B (en) |
| WO (1) | WO2009003418A1 (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI406260B (en) * | 2010-12-29 | 2013-08-21 | Au Optronics Corp | Control circuit with voltage charge sharing function of display panel and control method of same |
| TWI436248B (en) * | 2011-01-04 | 2014-05-01 | Raydium Semiconductor Corp | Touch sensing apparatus |
| CN103543567B (en) | 2013-11-11 | 2016-03-30 | 北京京东方光电科技有限公司 | A kind of array base palte and driving method, display device |
| CN108737604B (en) * | 2018-06-26 | 2020-07-28 | Oppo广东移动通信有限公司 | Mobile terminal |
| CN114023255A (en) * | 2021-11-22 | 2022-02-08 | 惠州视维新技术有限公司 | Drive circuit, drive device, and display device |
| CN115472131B (en) * | 2022-08-26 | 2024-03-22 | 苇创微电子(上海)有限公司 | Electric balance method of display device source electrode driving circuit and source electrode driving circuit thereof |
| CN115457915B (en) * | 2022-10-18 | 2024-06-04 | 硅谷数模(苏州)半导体股份有限公司 | Control method and control device of source driver and display system |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1372241A (en) * | 2001-02-26 | 2002-10-02 | 三星电子株式会社 | LCD and driving method thereof |
| CN1444201A (en) * | 2002-03-13 | 2003-09-24 | 松下电器产业株式会社 | Liquid crystal panel driver |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100604918B1 (en) * | 2004-11-15 | 2006-07-28 | 삼성전자주식회사 | Driving method and source driver of the flat panel display for digital charge share control |
| US7663594B2 (en) * | 2005-05-17 | 2010-02-16 | Lg Display Co., Ltd. | Liquid crystal display device with charge sharing function and driving method thereof |
| KR101167407B1 (en) * | 2005-06-28 | 2012-07-19 | 엘지디스플레이 주식회사 | Liquid Crystal Display and Driving Method thereof |
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2007
- 2007-07-02 CN CN2007100763027A patent/CN101339338B/en not_active Expired - Fee Related
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1372241A (en) * | 2001-02-26 | 2002-10-02 | 三星电子株式会社 | LCD and driving method thereof |
| CN1444201A (en) * | 2002-03-13 | 2003-09-24 | 松下电器产业株式会社 | Liquid crystal panel driver |
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| CN101339338A (en) | 2009-01-07 |
| WO2009003418A1 (en) | 2009-01-08 |
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Assignee: SHENZHEN BYD MICROELECTRONICS Co.,Ltd. Assignor: BYD Co.,Ltd. Contract fulfillment period: 2008.4.25 to 2015.8.16 Contract record no.: 2008440000068 Denomination of invention: Electric charge sharing mode LCD device, source drive device and electric charge sharing method License type: General permission Record date: 20080504 |
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