CN101022551A - Motion compensating module pixel prefetching device in AVS video hardware decoder - Google Patents
Motion compensating module pixel prefetching device in AVS video hardware decoder Download PDFInfo
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Abstract
A pixel pre-fetching device of movement compensation module in AVS video hardware decoder consists of decision control module, write buffer storage unit, read buffer storage unit, gating unit, forward pre-fetching buffer storage, backward pre-fetching buffer storage and reread buffer storage. The method utilizing said device to pre-fetch pixel is also disclosed.
Description
Technical field
What the present invention relates to is a kind of device of electronic information technical field, specifically a kind of pixel prefetching device based on motion compensating module in the AVS hardware video decoder of digital audio/video encoding and decoding technique standard.
Background technology
Digital audio/video encoding and decoding technique standard (AVS) is the audio frequency and video source encoding standard of being taken the lead and being formulated by Chinese digital audio/video encoding and decoding technique standard operation group (AVS working group), is the general character basic standard of digital audio/video industrial colonies such as Digital Television, broadband network Streaming Media, mobile multimedia communication, videodisc.In the design and realization of AVS hardware video decoder, the required bandwidth of memory interface is one of key factor of system for restricting performance and cost.And memory is carried out in the module of read-write operation, motion compensating module is to take the maximum module of memory interface bandwidth, also the bottleneck of whole decode system often.Reduce motion compensating module to memory interface bus time that takies and the data volume that reads, have great important for reducing the memory interface bandwidth and improving systematic function.With MEPG-2 or H.264 similar, AVS is divided into many macro blocks (macroblock) to every frame, and the size of each macro block is 16 * 16 pixels.Each macro block among the AVS is divided into four 8 * 8 again, and they are base units of decoding.The size of the inter prediction piece of AVS can be 16 * 16,16 * 8,8 * 16 or 8 * 8, and accordingly, the number of the motion vector that this macro block has is 1,2,2 or 4.In the design of hardware decoder, unify piece based on 8 * 8, if promptly the infra-frame prediction block size is 16 * 16, then each motion vector of 8 * 8 all is identical, 16 * 8 and 8 * 16 situation is similar.Four 8 * 8 motion vector in macro block is close, and the position of the piece in the reference frame that their point to also is close, and this is the basis of thought of looking ahead.The statistics of actual video sequence also proves this point.
In the process of motion compensation, each 8 * 8 have two reference blocks, are referred to as forward direction reference block and back respectively to reference block, and each reference block comprises brightness and colourity two parts again, is referred to as brightness reference block and chroma reference piece.AVS supports the motion compensation of 1/4 luminance pixel precision and 1/8 colourity precision, obtain the non-integer pixel of a piece for interpolation, the brightness reference block size that need read is all more than or equal to 8 * 8, be 12 * 11 or 11 * 12 to the maximum, the size of the chroma reference piece that need read is 5 * 5 (under the 4:2:0 chroma formats).In order to calculate a non-integer point pixel, often need much more integral point pixel to carry out interpolation, and these pixels all are stored among the chip external memory SDRAM, motion compensating module need be visited memory interface, send read request, wait for the request of the moderator responsive movement compensating module of memory interface inside then, wait for the data that SDRAM sends back again.Motion compensating module can take the longest memory interface bus time and maximum memory interface data throughout/bandwidth.Calculating shows, for the high definition TV of 1920 * 1080 pixels, 4:2:0 chroma format, all must carry out under the worst case of motion compensation at each piece, and motion compensating module will take the bandwidth of about 390 megabyte per seconds to the operation of reading reference block of memory.And other module, display module for example, the bandwidth that takies only is 90 megabyte per seconds.So,, the present invention proposes the pixel prefetching device of motion compensating module in the AVS hardware video decoder in order to reduce motion compensating module to memory interface bus time that takies and the data volume that reads.
Find by prior art documents, Egbert G.T.Jaspers, people such as Peter H.N.de With are published in " IEEE Transactions on Consumer Electronics ", Vol.47, No.4, propose to be devoted to reduce the handle up method of bandwidth of video decoder memory device interface data in " Bandwidth Reduction for VideoProcessing in Consumer Systems " (how the reducing the bandwidth of Video processing in the consumer electronics) of November 2001 (the consumer electronics journal of IEEE), it relates to the pixel data how technical scheme mainly concentrate on image space and carries out map addresses, and how to select suitable data unit length (bus bit wide).How to be connected between motion compensating module and memory interface that further to reduce bandwidth effectively then be the technical problem that needs most solution in the prior art to reach.
Summary of the invention
The present invention is directed to the deficiencies in the prior art and defective, the pixel prefetching device of motion compensating module in a kind of AVS hardware video decoder between motion compensating module (hereinafter to be referred as the MC module) and memory interface (hereinafter to be referred as the MIU module) is provided, make it reduce the demand of motion compensating module effectively, reduce the design difficulty of whole system and storage control the memory interface bandwidth.
In current 8 * 8 motion compensation, need read reference block from external memory storage.The present invention reads than bigger one of current required reference block scope from external memory storage in advance, is referred to as prefetched chunks.Reference block is divided into forward direction reference block and back to reference block, and correspondingly prefetched chunks also is divided into forward direction prefetched chunks and back to prefetched chunks, leaves in respectively in " forward direction look ahead buffer memory ", " back is to the buffer memory of looking ahead ".When the motion compensation of handling next 8 * 8, if required reference block drops in the prefetched chunks, the MC module just directly from " forward direction look ahead buffer memory ", " back is to the buffer memory of looking ahead " reading of data, does not need to propose read request to memory, promptly hits; The required reference block of next else if 8 * 8 motion compensation all not or some is not in " forward direction look ahead buffer memory ", " back is to the buffer memory of looking ahead ", then propose to read again the request of reference block to memory, promptly hit failure, the reference block of reading this moment is referred to as to read again piece, be filled in " reading buffer memory again " lining, the MC module is fetched data from reading cache read again.
The present invention is achieved by the following technical solutions, the present invention includes: the judgement control unit, write buffer unit, read buffer unit, gating unit, forward direction look ahead buffer memory, back to buffer memory and the stressed buffer memory of looking ahead, the judgement control unit is accepted the outside system configuration information and request, origin coordinates, scope, reference frame sign, the piece sequence number of MC module; The judgement control unit can select signal to give gating unit by output buffers; Gating unit is selected signal according to buffer memory, forward direction look ahead buffer memory, back to the buffer memory of looking ahead, read again between the buffer memory three and select one, address, read data and write data are connected on the port of the above-mentioned buffer memory of selecting; Origin coordinates of exporting after the judgement control unit is adjudicated and write cache mode, write the buffer memory enabling signal, correspondence being write cache mode and scope are given and are write buffer unit, and receive the state of writing buffer unit; Write the request of buffer unit dateout, coordinate to memory interface, wait for and receive the data and the data useful signal of memory interface output; Write buffer unit then the address and the write data of certain buffer memory that will write are exported to gating unit; The output of judgement control unit is read cache mode and is read enabling signal to reading buffer unit; Read buffer unit and send the address to gating unit and obtain reading data cached from gating unit; Read buffer unit then the data of reading in certain buffer memory are exported to the MC module, send the data useful signal simultaneously; After the data of whole reference block send and finish, read buffer unit and finish signal to the output of MC module.
Described judgement control unit, it with the MC module interface, write buffer unit and read buffer unit and link to each other, it receives MC module interface signal and comprises request, origin coordinates, scope, reference frame sign and the piece sequence number of reading reference block, with origin coordinates, scope, write and start and the WriteMode signal sends to and writes buffer unit, and etc. buffer unit to be written return to write and finish signal; To read to start and the reading mode signal sends to and reads buffer unit.Described judgement control unit, the reference block that internal judgment need be read whether hit forward direction look ahead buffer memory or the back in the buffer memory of looking ahead, and select signal for the correct buffer memory of gating unit according to judged result, it is to select one at look ahead buffer memory, back of forward direction in look ahead buffer memory and stressed buffer memory that this buffer memory is selected the effect of signal.
The described buffer unit of writing, it links to each other with outside MIU interface with judgement control unit, gating unit, and it is finished from the MIU request msg and writes the function of certain buffer memory.Read the signal that buffer unit receives the judgement control unit, comprise origin coordinates, scope, WriteMode, write startup,,, ask read data to MIU with a definite sequence according to origin coordinates that receives and scope in case it is effective to write enabling signal; Writing buffer unit inside, pixel coordinate is carried out address mapping, the pixel coordinate of two dimension is transformed into the buffer address of one dimension, and this address sent to gating unit, wait for that simultaneously MIU sends active data back to, these data and address synchronization send to gating unit, write buffer unit and write behind prefetched chunks or the stressed piece to write and finish signal to judgement control unit feedback.
The described buffer unit of reading, it links to each other with the MC module interface with judgement control unit, gating unit, and it is finished from certain cache read data and sends back to the function of MC module.The signal of reading buffer unit reception judgement control unit comprises reading mode and reads startup, in case it is effective to read enabling signal, requirement according to the MC module, send the address to gating unit sequentially, and receive the data from certain buffer memory, read from gating unit, these data and data in synchronization useful signal are returned to the MC module interface, read buffer unit and run through behind the whole reference block to send and finish signal to the MC module interface.
Described gating unit, it with the judgement control unit, write buffer unit, read buffer unit, forward direction is looked ahead buffer memory, the back to the buffer memory of looking ahead, read buffer memory again and link to each other, it finishes the function of certain buffer memory of gating.Gating unit is accepted buffer memory from the judgement control unit and is selected signal, this signal indication select forward direction look ahead buffer memory, back to the buffer memory of looking ahead, read in the buffer memory which again; If buffer memory is selected signal to indicate to choose is the forward direction buffer memory of looking ahead, gating unit can write buffer unit send to the address of gating unit and read address that buffer unit sends to gating unit carry out or operate after send to the forward direction buffer memory of looking ahead, send to the forward direction buffer memory of looking ahead writing write data that buffer unit sends to gating unit, look ahead read data that buffer memory sends of forward direction is sent to and reads buffer unit; If buffer memory is selected signal to indicate to choose be the back to buffer memory or the stressed buffer memory of looking ahead, adopt and carry out the gating operation in a like fashion.
The described forward direction buffer memory of looking ahead, it links to each other with gating unit, is used for depositing the forward direction prefetched chunks.The forward direction buffer memory of looking ahead is accepted address and write data signal from gating unit, and the forward direction buffer memory of looking ahead returns read data and gives gating unit; The forward direction buffer memory of looking ahead is deposited the forward direction prefetched chunks, and it has enlarged scope than required forward direction reference block, and the required reference block of next 8 * 8 block motion compensations has very big possibility to hit in this forward direction prefetched chunks.
Described back is to the buffer memory of looking ahead, and it links to each other with gating unit, is used for depositing the back to prefetched chunks.The back is accepted address and write data signal to the buffer memory of looking ahead from gating unit, and the back is returned read data to the buffer memory of looking ahead and given gating unit; The back is deposited to prefetched chunks to the buffer memory of looking ahead in the back, and it has afterwards enlarged scope to reference block than required, and the required reference block of next 8 * 8 block motion compensations has very big possibility to hit in this back in prefetched chunks.
Described stressed buffer memory, it links to each other with gating unit, is used for depositing stressed piece.Read buffer memory again and accept address and write data signal from gating unit, stressed buffer memory returns read data and gives gating unit; Stressed buffer memory is deposited stressed piece, and it is to hit the current required reference block that failure the time is read, do not distinguish forward direction still the back to.
Characteristics of the present invention are: the prefetching device of motion compensation reference pixel reads current decoding block from external memory storage in advance in the AVS hardware decode system does not need, but the reference pixel that next decoding block needs leaves in " forward direction is looked ahead buffer memory, back to the buffer memory of looking ahead ".Experiment statistics shows, the probability (hit rate) that the reference block of 1,2, No. 3 piece in macro block hits in prefetched chunks can reach average 93.3%, can reduce simultaneously by average about 24.4% memory interface bandwidth demand, promptly can estimate that high bandwidth reduces to about 295MB/s by 390MB/s to the motion compensating module theory, the design difficulty that reduces storage control also improves the stability of a system.Meanwhile, it is very little to introduce the on-chip memory that the buffer memory of looking ahead need increase, about 2K byte.The algorithm that this prefetching device all adopts the judgement of choosing and whether hitting of prefetched chunks is all simpler, is easy to hardware and realizes.
In sum, the present invention is by excavating the operating characteristics of motion compensating module in the AVS video decode algorithm, proposing this prefetching device is cost with look ahead buffer memory and simple control logic of increase, reduce the demand of motion compensating module effectively to the memory interface bandwidth, and motion compensating module is a module maximum to the bandwidth of memory request in the whole decode system, account for the nearly 2/3rds of whole bandwidth request, the bandwidth bottleneck problem that solves memory interface is had very big meaning.
Description of drawings
Sub-piece when macro block of Figure 1A VS video carries out motion compensation is divided schematic diagram;
The schematic diagram of the motion vector of four pieces of an interior macroblocks of Fig. 2;
The schematic diagram of Fig. 3 prefetching device position in decode system;
The internal structure schematic diagram of Fig. 4 prefetching device;
The position of Fig. 5 prefetched chunks and reference block and the schematic diagram of scope.
Embodiment
Below in conjunction with accompanying drawing embodiments of the invention are elaborated: present embodiment has provided detailed execution mode and process being to implement under the prerequisite with the technical solution of the present invention, but protection scope of the present invention is not limited to following embodiment.
Present embodiment defines in each macro block four 8 * 8 from left to right, called after No. 0, No. 1, No. 2 and No. 3 pieces respectively from top to bottom, and specific implementation process is as follows:
When 1) handling No. 0 piece of a macro block, the MC module is sent request to prefetching device, and prefetching device request MIU fills the buffer memory of looking ahead;
When handling No. 0 piece, the reference frame sign that the judgement control unit can provide according to the MC module selects signal for buffer memory of gating unit, and the gating forward direction is looked ahead buffer memory or back to the buffer memory of looking ahead.If the origin coordinates that the MC module provides be (x0, y0), scope be (rx0, ry0).Then adjudicating control unit then is that (x0, y0), scope is that (rx0+ex, ry0+ey), WriteMode is " writing the buffer memory of looking ahead ", sends and writes enabling signal to the origin coordinates of writing buffer unit.Write buffer unit receive from the judgement control unit write enabling signal after, to MIU read request and coordinate reading are proposed, this coordinate is from (x0, y0) be incremented to always that (x0+rx0+ex y0+ry0+ey), covers this with (x0, y0) be starting point, wide is rx0+ex, and height is the prefetched chunks of ry0+ey; Simultaneously this coordinate is carried out address mapping, the pixel coordinate of two dimension is transformed into the address of the buffer memory of looking ahead of one dimension.Wait for that MIU sends the data useful signal, the data that MIU is returned are by gating unit, write forward direction and look ahead buffer memory or back to the buffer memory of looking ahead.If No. 0 piece has two-way reference block, then look ahead and also will fill the back behind the buffer memory having filled forward direction to the buffer memory of looking ahead.After prefetched chunks (forward direction and/or after to) is written into the buffer memory of looking ahead, writes buffer unit and return one for the judgement control unit to write and finish signal.
2) the MC module obtains the required reference block of piece No. 0 from the buffer memory of looking ahead;
The judgement control unit receives " reference block is finished " signal of writing buffer unit, sends and reads enabling signal and reading mode reading buffer unit immediately, and reading mode is " reading the buffer memory of looking ahead ".The address that the pixel order that reading buffer unit needs according to the MC module produces the buffer memory of looking ahead, and this address exported to forward direction or back to the buffer memory of looking ahead by gating unit; Again the data of reading from the buffer memory of looking ahead are returned to the MC module, provide the data useful signal simultaneously.If No. 0 piece has two-way reference block, look ahead and also will read the back behind the buffer memory running through forward direction to the buffer memory of looking ahead.After reference block (forward direction and/or after to) is all exported to the MC module, read buffer unit sends the signal that runs through from No. 0 piece to the MC module.
When 3) handling No. 1 piece, the MC module is sent request to prefetching device, and prefetching device judges whether required reference block hits in the buffer memory of looking ahead;
The if block sequence number is 1, and the judgement control unit in the prefetching device judges at first whether Already in whether required reference block in the prefetched chunks, promptly " hit ".The condition of hitting is: at first, if current reference block direction is " forward direction ", forward direction is looked ahead must have data in the buffer memory, and reference frame must be identical; If current reference block direction is " back to ", must there be data the back in the buffer memory of looking ahead, and reference frame must be identical.Hit failure otherwise directly be judged to be.Secondly, if there are the data of same reference frame in the buffer memory of looking ahead really, judge the required scope of reference block whether in prefetched chunks, that is, the origin coordinates of establishing required reference block is that (x1, y1), scope is that (rx1 ry1), satisfy
If satisfy following formula, promptly hit; Otherwise, hit failure.
4) if hit, the MC module obtains the required reference block of piece No. 1 from the buffer memory of looking ahead;
After the judgement control unit obtains the result of " hitting ", do not start and write buffer unit, directly start and read buffer unit, reading mode is " reading the buffer memory of looking ahead ".The address that the pixel order that reading buffer unit needs according to the MC module produces the buffer memory of looking ahead, and this address exported to forward direction or back to the buffer memory of looking ahead by gating unit; Again the data of reading from the buffer memory of looking ahead are returned to the MC module, provide the data useful signal simultaneously.If No. 1 piece has two reference blocks, get back to step (c), handle the reference block of another direction of No. 1 piece.When reference block (forward direction and/or after to) all export finish after, read buffer unit and send to the MC module and run through signal.
5) if miss, prefetching device request MIU fills and reads buffer memory again, and the MC module obtains the required reference block of piece No. 1 from read buffer memory again;
After the judgement control unit obtains the result of " hitting failure ", start and write buffer unit, WriteMode is " writing stressed buffer memory ".Write buffer unit receive from the judgement control unit write enabling signal after, to MIU read request and coordinate reading are proposed, this coordinate from (x1, y1) be incremented to always (x1+rx1, y1+ry1); Simultaneously this coordinate is carried out address mapping, the pixel coordinate of two dimension is transformed into the address of the stressed buffer memory of one dimension.Wait for that MIU sends the data useful signal, the data that MIU returns are passed through gating unit, write stressed buffer memory.After whole stressed piece has been write, write buffer unit and return the status signal of " read again and finish " for the judgement control unit.After the judgement control unit receives this " read again finish " signal, send and read enabling signal and reading mode reading buffer unit immediately, reading mode is " reading to read again buffer memory ".The address that the pixel order that reading buffer unit needs according to the MC module produces the buffer memory of looking ahead, and this address exported to stressed buffer memory by gating unit; Again the data of reading from stressed buffer memory are returned to the MC module, provide the data useful signal simultaneously.If No. 1 piece has two reference blocks, get back to step (c), handle the reference block of another direction of No. 1 piece.When reference block (forward direction and/or after to) all export finish after, read buffer unit and send to the MC module and run through signal.
6) set by step (3) are to No. 2 pieces and No. 3 pieces of described this macro block of processing of step (5);
When reading the reference block of No. 2 pieces and No. 3 pieces, adopt and No. 1 identical method of piece: promptly whether the required reference pixel scope of judgement hits in the buffer memory of looking ahead earlier; If hit, the MC module reads required reference block from the buffer memory of looking ahead; If miss, prefetching device request MIU fills and reads buffer memory again, and the MC module reads required reference block from read buffer memory again.
7) set by step (1) finishes the motion compensation of all macro blocks to step (6).
For each macro block, all when reading the reference block of No. 0 piece, upgrade the buffer memory of looking ahead, No. 0 required reference block of piece reads from the buffer memory of looking ahead then; Whether at first adjudicate required reference block when reading the reference block of 1,2, No. 3 piece hits in the buffer memory of looking ahead; If hit, directly from the cache read reference block of looking ahead, do not need to visit MIU, if hit failure, visit MIU fills and reads buffer memory again, reads reference block from read buffer memory again.
Four kinds of division methods when Fig. 1 has illustrated that AVS carries out motion compensation to a macro block.Can carry out motion compensation by 16 * 16,16 * 8,8 * 16 or 8 * 8 block size, correspondence has 1,2,2 or 4 motion vector.In the design of hardware decoder, the motion compensation unification is based on 8 * 8 piece.There are 48 * 8 in the macro block, are masked as respectively No. 0 to No. 3.Because the interpolation algorithm in the AVS video motion compensation,, need carry out filtering to a plurality of pixels on every side for interpolation goes out half-pix or 1/4 pixel; Again because the restriction of bus bit wide and mapping mode, (for example, usually the bus bit wide of this class Video Decoder is 64 bits, promptly an internal storage access can be read 8 pixels, even having only 1 pixel is real needs, also must read 8 pixels), have a lot of repetitions between the reference block of adjacent block.If repeat to read these data, be huge waste to the bandwidth of memory interface from external memory storage.The described prefetching device of present embodiment can reduce this waste effectively.
Fig. 2 is the schematic diagram of motion vector of four pieces of an interior macroblocks, and 4 of certain macro block 8 * 8 have each self-corresponding motion vector in the present frame, have pointed to reference block separately respectively at reference frame.Process is to the statistics of the AVS code stream of multiple character, because the big or small direction of these four motion vectors is very approaching, four reference blocks all drop in the scope.Through statistics, on average surpass the identical reference frame of motion vector points of four pieces of 90% interior macroblocks to the AVS code stream of a large amount of various sizes and characteristic.And the mean difference of these four motion vectors is very little, is respectively: 0.13 pixel of x direction, 0.08 pixel of y direction.This " locality " make according to motion vector of No. 0 piece, take out a prefetched chunks in advance after, the reference block that No. 1, No. 2, No. 3 pieces need has very big probability to hit in reference block.
Fig. 3 is the schematic diagram of prefetching device position in decode system, and prefetching device has no effect to motion compensating module between motion compensating module and memory interface module.
Fig. 4 is the internal structure schematic diagram of prefetching device, and wherein adjudicating control unit is the core of prefetching device, and when handling No. 0 piece, it is responsible for starting and writes buffer unit, and prefetched chunks is write the buffer memory of looking ahead accordingly, and WriteMode is " writing the buffer memory of looking ahead "; Start then and read buffer unit, the reference block of No. 0 piece needs is read from the buffer memory of looking ahead, give MC module, reading mode is " reading the buffer memory of looking ahead ".When handling 1,2, No. 3 piece, judge at first whether required reference block hits in the buffer memory of looking ahead.If hit, then start and read buffer unit, reading mode is " reading the buffer memory of looking ahead "; If do not hit, then start earlier and write buffer unit, WriteMode be " writing stressed buffer memory ", and required reference block is write stressed buffer memory, and then starts and read buffer unit, reading mode is " reading stressed buffer memory ", gives MC module required reference block.
Writing buffer unit finishes from the MIU request msg and writes the function of certain buffer memory.Reading buffer unit finishes from certain cache read data and sends back to the function of MC module.Gating unit is selected Information Selection according to the buffer memory that sends of judgement control unit, the address of some buffer memorys, read data, write data, write the enable port and the corresponding port writing buffer unit or read buffer unit couples together.
Fig. 5 is the position of prefetched chunks and reference block and the schematic diagram of scope, shows that the starting point of prefetched chunks is identical with the starting point of the reference block of No. 0 piece, but bigger than the reference block scope of No. 0 piece.The scope of the reference block of No. 0 piece be (rx0, ry0), and the scope of prefetched chunks be (rx0+ex, ry0+ey).Ex and dy increase, and hit rate can increase, but the data volume that reads to MIU also can increase.Experiment shows, Duoing respectively on x direction and the y direction than reference block under the situation of 8 pixels when the scope of prefetched chunks is made as, and (is ex=8, ey=8), can reaches hit rate (average 93.3%) and reduce the optimum balance of reading of data amount (average 24.4%).
It is such that the size of buffer memory and stressed buffer memory of looking ahead is set: establishing the bus bit wide is 64 bits, and the data cell of each 64 bit is horizontal 8 continuous luminance pixels, or horizontal continuous 4 pairs of chroma pixels (Cb and Cr).Then one 8 * 8 luminance block is carried out motion compensation, motion compensation is carried out to one 4 * 4 chrominance block in the zone of maximum demand 24*12, the zone of maximum demand 8*5.Prefetched chunks enlarges to some extent than reference block, promptly concerning brightness, expands 32*20 to, concerning colourity, expands 12*9 to.The size that buffer memory need be stored so forward direction is looked ahead is the 32*20+2*12*9=856 byte.The back is identical with forward direction to the size of the buffer memory of looking ahead.The size of reading buffer memory again is the 24*12+2*8*5=368 byte.Amount to 2080 bytes.
Claims (8)
1, the pixel prefetching device of motion compensating module in a kind of AVS hardware video decoder is characterized in that, comprising: the judgement control unit, write buffer unit, read buffer unit, gating unit, forward direction look ahead buffer memory, back to buffer memory and the stressed buffer memory of looking ahead; The judgement control unit is accepted the outside system configuration information and request, origin coordinates, scope, reference frame sign, the piece sequence number of motion compensating module, and the judgement control unit can select signal to give gating unit by output buffers; Gating unit is selected signal according to buffer memory, forward direction look ahead buffer memory, back to the buffer memory of looking ahead, read again between the buffer memory three and select one, address, read data and write data are connected on the port of the above-mentioned buffer memory of selecting; Origin coordinates of exporting after the judgement control unit is adjudicated and write cache mode, write the buffer memory enabling signal, correspondence being write cache mode and scope are given and are write buffer unit, and receive the state of writing buffer unit; Write the request of buffer unit dateout, coordinate to memory interface, wait for and receive the data and the data useful signal of memory interface output, write buffer unit then the address and the write data of certain buffer memory that will write are exported to gating unit; The output of judgement control unit is read cache mode and is read enabling signal to reading buffer unit, read buffer unit and send the address to gating unit and obtain reading data cached from gating unit, read buffer unit then the data of reading in certain buffer memory are exported to motion compensating module, send the data useful signal simultaneously; After the data of whole reference block send and finish, read buffer unit and finish signal to motion compensating module output.
2, the pixel prefetching device of motion compensating module in the AVS hardware video decoder according to claim 1, it is characterized in that, described judgement control unit, it with the motion compensating module interface, write buffer unit and read buffer unit and link to each other, it receives the motion compensating module interface signal and comprises request, origin coordinates, scope, reference frame sign and the piece sequence number of reading reference block, with origin coordinates, scope, write and start and the WriteMode signal sends to and writes buffer unit, and etc. buffer unit to be written return to write and finish signal; To read to start and the reading mode signal sends to and reads buffer unit.Described judgement control unit, whether the reference block that internal judgment need be read hits in the buffer memory of looking ahead, and select signal for the correct buffer memory of gating unit according to judged result, it is to select one at look ahead buffer memory, back of forward direction in look ahead buffer memory and stressed buffer memory that this buffer memory is selected the effect of signal.
3, the pixel prefetching device of motion compensating module in the AVS hardware video decoder according to claim 1, it is characterized in that, the described buffer unit of writing, it links to each other with external memory interface with judgement control unit, gating unit, read the signal that buffer unit receives the judgement control unit, comprise origin coordinates, scope, WriteMode, write startup, in case it is effective to write enabling signal, according to the origin coordinates that receives and scope to the memory requests read data; Writing buffer unit inside, pixel coordinate is carried out address mapping, the pixel coordinate of two dimension is transformed into the buffer address of one dimension, and this address sent to gating unit, wait for that simultaneously memory interface sends active data back to, these data and address synchronization send to gating unit, write buffer unit and write behind prefetched chunks or the stressed piece to write and finish signal to judgement control unit feedback.
4, the pixel prefetching device of motion compensating module in the AVS hardware video decoder according to claim 1, it is characterized in that, the described buffer unit of reading, it and judgement control unit, gating unit links to each other with the motion compensating module interface, the signal of reading buffer unit reception judgement control unit comprises reading mode and reads startup, in case it is effective to read enabling signal, requirement according to motion compensating module, send the address to gating unit sequentially, and receive the data from certain buffer memory, read from gating unit, these data and data in synchronization useful signal are returned to the motion compensating module interface, read buffer unit and run through whole reference block reverse compensating module interface and send and finish signal.
5, the pixel prefetching device of motion compensating module in the AVS hardware video decoder according to claim 1, it is characterized in that, described gating unit, it with the judgement control unit, write buffer unit, read buffer unit, forward direction is looked ahead buffer memory, the back to the buffer memory of looking ahead, read buffer memory again and link to each other, gating unit is accepted buffer memory from the judgement control unit and is selected signal, this signal indication select forward direction look ahead buffer memory, back to the buffer memory of looking ahead, read in the buffer memory which again; If buffer memory is selected signal to indicate to choose is the forward direction buffer memory of looking ahead, gating unit can write buffer unit send to the address of gating unit and read address that buffer unit sends to gating unit carry out or operate after send to the forward direction buffer memory of looking ahead, send to the forward direction buffer memory of looking ahead writing write data that buffer unit sends to gating unit, look ahead read data that buffer memory sends of forward direction is sent to and reads buffer unit; If buffer memory is selected signal to indicate to choose be the back to buffer memory or the stressed buffer memory of looking ahead, adopt and carry out the gating operation in a like fashion.
6, the pixel prefetching device of motion compensating module in the AVS hardware video decoder according to claim 1 is characterized in that, the described forward direction buffer memory of looking ahead, and it links to each other with gating unit, is used for depositing the forward direction prefetched chunks; The forward direction buffer memory of looking ahead is accepted address and write data signal from gating unit, and the forward direction buffer memory of looking ahead returns read data and gives gating unit; The forward direction buffer memory of looking ahead is deposited the forward direction prefetched chunks, and it has enlarged scope than required forward direction reference block, and the follow-up reference block that will read has very big possibility to hit in this forward direction prefetched chunks.
7, the pixel prefetching device of motion compensating module in the AVS hardware video decoder according to claim 1, it is characterized in that, described back is to the buffer memory of looking ahead, it links to each other with gating unit, the back is accepted address and write data signal to the buffer memory of looking ahead from gating unit, and the back is returned read data to the buffer memory of looking ahead and given gating unit; The back is deposited to prefetched chunks to the buffer memory of looking ahead in the back, and it has afterwards enlarged scope to reference block than required, and the required reference block of next 8x8 block motion compensation has very big possibility to hit in this back in prefetched chunks.
8, the pixel prefetching device of motion compensating module in the AVS hardware video decoder according to claim 1, it is characterized in that, described stressed buffer memory, it links to each other with gating unit, read buffer memory again and accept address and write data signal from gating unit, stressed buffer memory returns read data and gives gating unit; Stressed buffer memory is deposited stressed piece, and it is to hit the current required reference block that failure the time is read, do not distinguish forward direction still the back to.
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