CN101022275A - Counter capable of setting value and testing method thereof - Google Patents
Counter capable of setting value and testing method thereof Download PDFInfo
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- CN101022275A CN101022275A CN 200610008803 CN200610008803A CN101022275A CN 101022275 A CN101022275 A CN 101022275A CN 200610008803 CN200610008803 CN 200610008803 CN 200610008803 A CN200610008803 A CN 200610008803A CN 101022275 A CN101022275 A CN 101022275A
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Abstract
A method fro test counter being able to set value includes setting lowest k numbers of bits on the secondary counter circuit to be at different initial values, inputting (2 m) numbers of time pulse to detect counter being able set value, setting m bits of the secondary counter, inputting two counting time pulse one by one and detecting counter being able to set value step by step.
Description
(1) technical field
The present invention is a kind of method of testing of counter capable of setting value, refers to the low testing cost of a kind of tool especially but the counter capable of setting value method of testing of high test coverage rate is arranged.
(2) background technology
If want the general counter of complete test, for example the counter with sixteen bit unit length under the situation that can't set its value, needs two the individual clock signal of 16 powers (65536), causes the tediously long of testing time and does not have efficient; But add test circuit, though can shorten the testing time, on the method for testing if there is not a perfect planning, test condition the circuit mistake that can find out may produce blind spot.
Secondary counter is the mode of least cost with the framework of pulsed counter (ripple counter), each secondary counter with the pulsation carry (carry-ripple) the mode carry to next secondary counter, but the counting bit of each secondary counter can not be oversize, because if pulsation counting bit is oversize, relatively can cause carry transmission delay (carry propagation delay) to influence usefulness too greatly.Can work as the carry bit with reference to the count value of previous stage at each secondary counter, so the delay of the counting and the carry bit of the secondary counter of previous stage is only arranged when every group of secondary counter, and do not have the effect of accumulated delay, and can keep counter in certain usefulness, can take into account the area cost again.Consider when more high-effect when need, secondary counter also can adopt the framework of carry look ahead (carry-lookahead), but the area cost is higher, can consider decision counting bit length according to cost.But add test circuit at each secondary counter,, can't judge this class error analysis that the short circuit of count value data wire is joined, make the test coverage rate therefore limited though can shorten the testing time.
(3) summary of the invention
First purpose of the present invention is to provide a kind of method of testing of counter capable of setting value, be applied to a counter capable of setting value that comprises n secondary counter circuit, wherein these secondary counter circuits comprise n carry digit meta-logic, (n-1) individual test signal circuit and m * n output count data line, and connect with series system, this method of testing comprises that step is as follows: minimum k bit (a) setting these secondary counter circuits is the combinations of one of different initial values, and enters a test pattern; (b) input 2
mIndividual counting clock pulse, and judge one by one whether the individual counts value of these secondary counter circuits all meets corresponding desired value; (c1) be as the comparative result of step (b) and meet, then these secondary counter circuits of decidable and these output count data lines are correct, and whole bits of setting these counter circuits are 1, make it enter a count mode, continued access step (d); (c2) the arbitrary comparative result as step (b) does not meet, and carries out the debug analysis and the end of a correspondence; (d) to set each bit initial value be 1 and enter count mode, continues a counting of input clock pulse, and judge whether a count value of this counter capable of setting value is 0; (e1) comparative result as step (d) is 0, stay at this count mode, and continued access step (f); (e2) non-as the comparative result of step (d) is 0, and then the decidable mistake results from these carry digit meta-logics or these test signal circuit and finishes; (f) continue a counting of input clock pulse, and judge whether one of this counter capable of setting value count value is 1; (g1) comparative result as step (f) is 1, and then this counter capable of setting value of decidable is correct; And (g2) non-as the comparative result of step (f) be 1, then the decidable mistake results from these test signal circuit.
According to the present invention's conception, n is a positive integer, and these secondary counter circuits all have the m bit, and m is a positive integer and is not less than log
2N, this counter capable of setting value cording has mxn bit, and k is for being not less than log
2The minimum positive integer of n.
According to purpose of the present invention, these secondary counter circuits have (m) individual replacement input to receive (m) individual reset signal.
According to purpose of the present invention, these secondary counter circuits have (m) individual set input to receive (m) individual setting signal.
According to purpose of the present invention, in these secondary counter circuits except that headed by this secondary counter circuit, between between each secondary counter circuit and the secondary counter circuit of a previous stage, all have one the test module, this test module has two inputs and an output, these inputs are a counting overflow signal and test signals that are used for receiving respectively the secondary counter circuit of this previous stage, this output be according to one of this counting overflow signal and this test signal " or " (OR) logical operation to be to export a carry bit signal.
According to purpose of the present invention, the one-period of finishing this method of testing needs 2
m+ 2 counting clock pulses.
According to purpose of the present invention, these secondary counter circuits have the framework of a pulsed counter (ripple counter) or a carry look ahead (carry-look ahead).
According to purpose of the present invention, these secondary counter circuits have a clock pulse input, receive a counting clock pulse with parallel way.
Second purpose of the present invention is to provide a kind of method of testing of counter capable of setting value, be applied to one and comprise n a counter capable of setting value with secondary counter circuit of m bit, wherein these secondary counter circuits are that string connects with series system, and this method of testing comprises that step is as follows: minimum k bit setting these secondary counter circuits is different initial values; Enter a test pattern, and import 2
mIndividual counting clock pulse is to detect this counter capable of setting value; Set the m bit of these secondary counter circuits; And enter a count mode, import 2 counting clock pulses successively and detect this counter capable of setting value one by one.
According to purpose of the present invention, n is a positive integer, and m is a positive integer and is not less than log
2N, this counter capable of setting value have mxn bit, and k one is not less than log
2The minimum positive integer of n.
According to purpose of the present invention, these secondary counter circuits have the framework of a pulsed counter (ripple counter) or a carry look ahead (carry-look ahead).
The 3rd purpose of the present invention is to provide a kind of counter capable of setting value, comprises n secondary counter circuit; These secondary counter circuits comprise n carry digit meta-logic, (n-1) individual test signal circuit and n output count data line; Wherein these secondary counter circuits connect with series system, and minimum k bit of these secondary counter circuits can be set to different initial values, and imports 2 under a test pattern
mIndividual counting clock pulse and under a count mode input 2 the counting clock pulses to detect these secondary counter circuits respectively.
According to purpose of the present invention, n is a positive integer, and these secondary counter circuits all have the m bit, and m is a positive integer and is not less than log
2N, this counter capable of setting value have mxn bit, and k one is not less than log
2The minimum positive integer of n.
According to purpose of the present invention, these secondary counter circuits have m replacement input to receive m reset signal.
According to purpose of the present invention, these secondary counter circuits have m set input to receive m setting signal.
According to purpose of the present invention, in these secondary counter circuits except that headed by this secondary counter circuit, between between each secondary counter circuit and the secondary counter circuit of a previous stage, all have one the test module, this test module has two inputs and an output, these inputs are used for receiving respectively a counting overflow signal and a test signal of the secondary counter circuit of this previous stage, this output be according to one of this counting overflow signal and this test signal " or " (OR) logical operation to be to export a carry bit signal.
According to purpose of the present invention, these secondary counter circuits have the framework of a pulsed counter (ripple counter) or a carry look ahead (carry-look ahead).
According to purpose of the present invention, these secondary counter circuits have a clock pulse input, receive a counting clock pulse with parallel way.
Effect of the present invention and purpose can and illustrate by the following example, and more deep understanding is arranged.
(4) description of drawings
Fig. 1 is the flow chart of the method for testing of counter capable of setting value in the embodiment of the invention; And
Fig. 2 is the schematic diagram of counter capable of setting value in the embodiment of the invention.
(5) embodiment
The present invention is the method for testing of counter capable of setting value, this counter inside structure can be divided the secondary counter of different sum of series frameworks according to different usefulness requirements, and purpose is to average out a little between usefulness and manufacturing cost, and, improve the test coverage rate by the mode of setting initial count value.
The present invention has n secondary circuit, but and each secondary circuit be that (m must be more than or equal to log for the definite value test counter of m bit
2N) all applicable; When entering test pattern, set the minimum log of each secondary counter initial value
2The n bit is a different value, Once you begin the counting then each secondary counter count parasynchronously, amount to several 2
mIndividual counting clock pulse, when count results meets desired value, then decidable count value data wire line and each secondary counter circuit be correct, otherwise will do the debug analysis to confirm the circuit blocks of mistake.
The selection of the above initialization must be followed above rule: " the minimum log of each secondary counter initial value
2The n bit is a different value "; Be higher than log
2The secondary counter bit of n can be arbitrary value.Because at counting 2
mBetween individual counting clock pulse, each bit of each secondary counter all experiences the variation combination of all situations, if counting output data line wrong or short circuit are arranged, can therefore check.
See also Fig. 1, it is the flow chart of the method for testing of counter capable of setting value in the embodiment of the invention; Its execution in step is carried out as follows: (a) at first sets specific initial value, and enters test pattern, and input counting clock pulse, whether the count value variation of observing each counting clock pulse simultaneously is desired value; (b) if correct, to set once more then that initial value is 1 at the beginning of all counting bits, and under general modfel, import 1 counting clock pulse again, this moment, count value should be 0; (c) if correct, import 1 counting clock pulse again, this moment, count value should be 1.
Divide according to circuit function, four circuit blocks that may make a mistake are arranged, be respectively (I) secondary counter circuit; (II) carry digit meta-logic; (III) test signal circuit; And (IV) output count value data wire; As find mistake in step (a), then above circuit all might be for producing wrong block, and whether can be analyzed by the combination of setting different initial values is the mistake of (IV) output count value data wire again; If step (a) is errorless, but step (b) is found mistake, then may be (II) carry digit meta-logic or (III) the test signal circuit is wrong; If step (a) and (b) all correct, but in step (c), find mistake, then may be (III) test signal circuit wrong (for example, carry is 1 forever).
See also Fig. 2, it is the schematic diagram of counter capable of setting value in the embodiment of the invention, wherein secondary counter (SC0, SC1, SC2, SC3) is to be serially connected, each secondary counter (SC0, SC1, SC2, SC3) is according to performance requirements, (this example is four bits for counter with certain bit length, the framework of a pulsed counter or a carry look ahead), so be that the secondary counter of four (n) individual four (m) bit is concatenated into the counter of sixteen bit unit (m is more than or equal to log
2N), and each the counting bit all have setting (SET) and the replacement (RESET) signal.It is count results (mode of pulsation carry (Carry-Ripple)) with reference to previous stage that counting mode in the present embodiment is adopted carry bit (CA0, CA1, CA2, CA3) between each secondary counter (SC0, SC1, SC2, SC3), and CA is fixed as 1.When the secondary counter of previous stage (SC0, SC1, SC2) overflow, the carry bit of setting the secondary counter of next stage (SC1, SC2, SC3) is 1, and when next one counting clock pulse (CLK) input, the secondary counter of next stage (SC1, SC2, SC3) adds one.
Test mode as for present embodiment, for considering Easy Test, then can be with reference to No. the 00176735th, Taiwan patent announcement " the high speed digit counter of Easy Test ", when setting test mode signal TM is 1 when entering a test pattern, forcing the carry bit (CA0, CA1, CA2, CA3) of each secondary counter (SC0, SC1, SC2, SC3) is 1, so parallelizable the carrying out of (SC0, SC1, SC2, the SC3) of each secondary counter test.
Under test pattern, if the bit number of each secondary counter (SC0, SC1, SC2, SC3) is identical, and when initial set value is also consistent, the result of calculation of each secondary counter, count cycle in each test should be able to be identical, but also the mistake that might therefore can't observe out counting output data line (D0, D1, D2, D3) wrong or short circuit is for example worked as the D1 of SC1 and the D2 short circuit of SC2 and is connected together, and above mode is just checked not come out.
The present invention utilizes the characteristic of counter capable of setting value, can overcome above disappearance.Above example explains, because four secondary counter (SC0 are arranged, SC1, SC2, SC3), so each secondary counter (SC0, SC1, SC2, SC3) minimum two bits of initial value must be different value, for example set SC0=0000/B, SC1=0001/B, SC2=0010/B, SC3=0011/B, so just can guarantee each secondary counter (SC0, SC1, SC2, SC3) Nei count value is in the different time points carry, as each secondary counter (SC0, SC1, SC2, SC3) can both count in regular turn correctly, can get rid of and to observe enumeration data line (D0, D1, D2, D3) problem of wrong is arranged between mutually.In like manner, if five secondary counters (SC0, SC1, SC2, SC3, SC4) are arranged, minimum three bits of initial value that then will set each secondary counter (SC0, SC1, SC2, SC3, SC4) are different value.
The testing process of counter capable of setting value 1 is as follows:
(a) initial value of at first setting 16 bits of counter capable of setting value 1 is 3210H, and set test mode signal TM and be 1 to enter test pattern, then import 16 counting clock pulses (CLK) again, whether the count value of observing simultaneously after each counting clock pulse number (CLK) is imported changes as predetermined value;
(b) if correct, then setting 16 bit initial values once more is FFFFH, and to set test mode signal TM be 0 to recover count mode, then imports 1 counting clock pulse (CLK) again, and count value should be 0000H at this moment;
(c) if correct, then import 1 counting clock pulse (CLK) again, this moment, count value should be 0001H.
As previously mentioned, divide, four circuit blocks that may make a mistake are arranged, be respectively (1) secondary counter circuit (SC0, SC1, SC2, the counting circuit of SC3) according to circuit function; (2) carry digit meta-logic (CA0, CA1, CA2, CA3); (3) test signal circuit (comprising test block 3 and test signal line TM), test block system according to the overflow signal 2 of test signal and secondary counter circuit " or " (OR) logical operation to be to export a carry bit signal (CA0, CA1, CA2, CA3); And (4) output count value data wire (D0, D1, D2, D3).
If find mistake in step (a), whether all possible mistake of then above circuit can be the mistake of output count data line (D0, D1, D2, D3) by the combinatory analysis of setting different initial values again; If step (a) is correct, but step (b) is found mistake, then may be that carry digit meta-logic (CA0, CA1, CA2, CA3) or test signal circuit are wrong; If the step (a) and (b) are correct, but step (c) is found mistake, then may be test signal circuit wrong (for example, carry is 1 forever).
So test the counter capable of setting value 1 of above sixteen bit unit according to this mode, must can finish by (2 4 powers+2) individual counting clock pulse (CLK), and can check out the wiring error of enumeration data line (D0, D1, D2, D3), improve the coverage rate of test.
In sum, the method of testing of counter capable of setting value of the present invention, because of setting the initial value of its secondary counter, tradition can not shorten the required time of test by the set point counter significantly, also can not have simultaneously and omit the place (wiring error that comprises the enumeration data line) that the area is separated out wrong circuit, promote the coverage rate of test.
Though the present invention describes with reference to current specific embodiment, but those of ordinary skill in the art will be appreciated that, above embodiment is used for illustrating the present invention, under the situation that does not break away from spirit of the present invention, also can make the variation or the replacement of various equivalences, therefore, as long as in connotation scope of the present invention in the scope to the variation of the foregoing description, claims that modification all will drop on the application.
Claims (11)
1. the method for testing of a counter capable of setting value, be applied to one and comprise one of n secondary counter circuit counter capable of setting value, wherein these secondary counter circuits are to comprise n carry digit meta-logic, (n-1) individual test signal circuit and m * n output count data line, and with the series system connection, this method of testing comprises that step is as follows:
(a) minimum k bit setting these secondary counter circuits is a combination of different initial values, and enters a test pattern;
(b) input 2
mIndividual counting clock pulse, and judge one by one whether the individual counts value of these secondary counter circuits all meets corresponding desired value;
(c1) be as the comparative result of step (b) and meet, then these secondary counter circuits of decidable and these output count data lines are correct, and whole bits of setting these counter circuits are 1, make it enter a count mode, continued access step (d);
(c2) the arbitrary comparative result as step (b) does not meet, and carries out the debug analysis and the end of a correspondence;
(d) continue a counting of input clock pulse, and judge whether a count value of this counter capable of setting value is 0;
(e1) comparative result as step (d) is 0, stay at this count mode, and continued access step (f);
(e2) non-as the comparative result of step (d) is 0, and then the decidable mistake results from these carry digit meta-logics or these test signal circuit and finishes;
(f) continue a counting of input clock pulse, and judge whether a count value of this counter capable of setting value is 1;
(g1) comparative result as step (f) is 1, and then this counter capable of setting value of decidable is correct; And
(g2) non-as the comparative result of step (f) is 1, and then the decidable mistake results from these test signal circuit.
2. the method for testing of counter capable of setting value as claimed in claim 1, it is characterized in that: n is a positive integer, and these secondary counter circuits all have the m bit, and m is a positive integer and is not less than log
2N, this counter capable of setting value have a m * n bit, and k one is not less than log
2The minimum positive integer of n.
3. the method for testing of counter capable of setting value as claimed in claim 2 is characterized in that: these secondary counter circuits have m replacement input to receive m reset signal.
4. the method for testing of counter capable of setting value as claimed in claim 2 is characterized in that: these secondary counter circuits have m set input to receive m setting signal.
5. the method for testing of counter capable of setting value as claimed in claim 2, in these secondary counter circuits except that headed by this secondary counter circuit, between between each secondary counter circuit and the secondary counter circuit of a previous stage, all has a test module, this test module is to have two inputs and an output, these inputs are to be used for receiving respectively one of the secondary counter circuit of this previous stage to count an overflow signal and a test signal, and this output is to export a carry bit signal according to the computing of one of this counting overflow signal and this test signal OR else logic.
6. the method for testing of counter capable of setting value as claimed in claim 2 is characterized in that: the one-period of finishing this method of testing needs 2
m+ 2 counting clock pulses.
7. the method for testing of counter capable of setting value as claimed in claim 1, it is characterized in that: these secondary counter circuits have the framework of a pulsed counter (ripple counter) or a carry look ahead (carry-look ahead).
8. the method for testing of counter capable of setting value as claimed in claim 1, it is characterized in that: these secondary counter circuits have a clock pulse to be exported into end, receives a counting clock pulse with parallel way.
9. the method for testing of a counter capable of setting value is applied to one and comprises n the counter capable of setting value with secondary counter circuit of m bit, and wherein these secondary counter circuits are to connect with series system, and this method of testing comprises that step is as follows:
Minimum k bit setting these secondary counter circuits is different initial values;
Enter a test pattern, and import 2
mIndividual counting clock pulse is to detect this counter capable of setting value;
Set the m bit of these secondary counter circuits; And
Enter a count mode, import 2 counting clock pulses successively and detect this counter capable of setting value one by one.
10. the method for testing of counter capable of setting value as claimed in claim 9, wherein n is a positive integer, m is a positive integer and is not less than log
2N, this counter capable of setting value have m * n bit, and k one is not less than log
2The minimum positive integer of n.
11. a counter capable of setting value comprises n secondary counter circuit; These secondary counter circuits comprise:
N carry digit meta-logic;
(n-1) individual test signal circuit; And
N * m output count data line;
Wherein these secondary counter circuits are to connect with series system, and minimum k bit of these secondary counter circuits can be set to different initial values, and imports 2 under a test pattern
mIndividual counting clock pulse and under a count mode input 2 the counting clock pulses to detect these secondary counter circuits respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100088037A CN100525108C (en) | 2006-02-15 | 2006-02-15 | Counter capable of setting value and testing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100088037A CN100525108C (en) | 2006-02-15 | 2006-02-15 | Counter capable of setting value and testing method thereof |
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| Publication Number | Publication Date |
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| CN101022275A true CN101022275A (en) | 2007-08-22 |
| CN100525108C CN100525108C (en) | 2009-08-05 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB2006100088037A Expired - Fee Related CN100525108C (en) | 2006-02-15 | 2006-02-15 | Counter capable of setting value and testing method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109981099A (en) * | 2019-04-17 | 2019-07-05 | 成都微光集电科技有限公司 | A kind of counter circuit with overflow protection function |
-
2006
- 2006-02-15 CN CNB2006100088037A patent/CN100525108C/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109981099A (en) * | 2019-04-17 | 2019-07-05 | 成都微光集电科技有限公司 | A kind of counter circuit with overflow protection function |
| CN109981099B (en) * | 2019-04-17 | 2021-07-06 | 成都微光集电科技有限公司 | Counter circuit with overflow protection function |
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| Publication number | Publication date |
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| CN100525108C (en) | 2009-08-05 |
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