CN101018452A - Multilayer printed wiring board - Google Patents

Multilayer printed wiring board Download PDF

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Publication number
CN101018452A
CN101018452A CN 200610100689 CN200610100689A CN101018452A CN 101018452 A CN101018452 A CN 101018452A CN 200610100689 CN200610100689 CN 200610100689 CN 200610100689 A CN200610100689 A CN 200610100689A CN 101018452 A CN101018452 A CN 101018452A
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CN
China
Prior art keywords
via hole
wiring board
multilayer printed
insulating layers
resin insulating
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CN 200610100689
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CN100584150C (en
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白井诚二
岛田宪一
浅井元雄
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Ibiden Co Ltd
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Ibiden Co Ltd
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Abstract

A multilayer printed wiring board having a filled-via structure which provides excellent reliability of connection between via-holes. Apertures (42) formed in a lower-layer interlayer resin insulating layer (40) are filled with plating material (48) to form lower-layer via-holes (50) having flat surfaces. Apertures (62) are formed in an upper-layer interlayer resin insulating layer (60) on the lower-layer via-holes (50) to form upper-layer via-holes (70). Since the surfaces of the lower-layer via-holes (50) are flat and no resin is left on the surfaces, the reliability of connection between the lower-layer via-hole (50) and the upper-layer via-hole (70) can be secured. Further, since the surfaces of the lower-layer via-holes (50) are flat, even when the upper-layer via-holes (70) are formed on the lower-layer via-holes (50), the surface smoothness of the multilayer printed wiring board is not deteriorated.

Description

Multilayer printed-wiring board
The application is that the priority date of applicant Ibiden Co., Ltd. is denomination of invention the dividing an application for the Chinese patent application No.200410100636X of " multilayer printed-wiring board " on December 29th, 1997.
Technical field
What the present invention relates to directly over lower via hole to form the upper strata via hole has a filling vias structure multilayer printed wiring board.
Background technology
Shown in Figure 20 (A), in so-called combination multilayer printed-wiring board, utilize via hole 650 conductivity ground to connect lower floor's conductor circuit 634 and top conductor circuit 652.By on the inner surface of the peristome 642 of break-through setting on the interlayer resin insulating layers 640, electroplating film 648 being set, form this via hole 650.In the inboard of the electrodeposited coating 648 that forms this via hole 650, fill the resin 660a of the interlayer resin insulating layers 660 that forms the upper strata.Therefore, shown in the dotted line among the figure, if form via hole, then because the influence of the resin 660a that fills in the inboard of electrodeposited coating 648 is difficult to realize two connections between the via hole on the upper strata of this via hole 650.
Therefore, when on via hole, forming via hole, promptly, in order to seek densification, when directly not being connected to via hole on the via hole, shown in Figure 21 (I), with the peristome 542 on the electronplate 548 filling interlayer resin insulating layers 540 by wiring, utilize this so-called filling vias structure, form multilayer printed-wiring board.The spy that relevant technology is published the applicant opens flat 2-188992 number, spy and opens flat 3-3298 number, spy and open in flat 7-34048 number.
With reference to Figure 20 (B)～Figure 21 (I), the method that forms via hole on this via hole is described.
Formed at first, from the teeth outwards that coating forms the resin 540 (with reference to Figure 20 (B)) that lower interlayer resin insulating layers is used on the upper and lower surface of substrate 530 of conductor circuit 534.Then, on this interlayer resin insulating layers 540, form the peristome 542 (with reference to Figure 20 (C)) that is used for forming via hole.Then, after separating out electroless plating film 544 equably on the surface of substrate 530, form resist layer 566 (with reference to Figure 20 (D)).Then, in the non-formation portion of this resist layer 546, separate out metallide film 548, form via hole 550 and conductor circuit 552 (with reference to Figure 20 (E)).Then, after lower floor's electroless plating film 544 of resist layer 546 and resist layer peeled off, coating constituted the resin 560 (with reference to Figure 21 (F)) of upper strata interlayer resin insulating layers on the surface of substrate 530.Then, adopt photoetching process on this interlayer resin insulating layers 560, to form the peristome 562 (with reference to Figure 21 (G)) that is used for forming via hole.Then, on the surface of substrate 530, separate out equably after the electroless plating film 564, form resist layer 566, in the non-formation portion of this resist layer 566, separate out metallide film 568 (with reference to Figure 21 (H)).At last, lower floor's electroless plating film 564 of resist layer 566 and resist layer is peeled off, made upper strata via hole 570 and conductor circuit 572 (with reference to Figure 21 (I)).
, in the multilayer printed-wiring board relevant with above-mentioned manufacture method, lower via hole 550 is low with the reliability that upper strata via hole 570 is connected.The present inventor has studied its reason, shown in Figure 20 (E), when separating out metallide thing 548 on the peristome 542 that forms on interlayer resin insulating layers 540, can see that pit 550a appears in the central portion at via hole 550.Promptly, when the resin 560 that will constitute the upper strata interlayer resin insulating layers is coated on this via hole 550 shown in Figure 21 (F), because the thickness h 1 of the resin 560 on this pit 550a is different with the thickness h 2 at this pit 550a position in addition, so shown in Figure 21 (G), on this interlayer resin insulating layers 560, formed when being used for forming the peristome 562 of via hole with photoetching process, in pit 550a, stayed a little resin 560a.That is, shown in Figure 21 (I), owing to the effect of this resin 560a is insulated, visible lower via hole 550 is low with the reliability that upper strata via hole 570 is connected.
In addition, also know the resin 560a in above-mentioned pit 550a, also since oxidation by the effect of overlay film, lower via hole 550 is low with the reliability that upper strata via hole 570 is connected.That is, shown in Figure 20 (E), when utilizing metallide layer 548 to form lower via hole 550, on the surface of this lower via hole 550, form oxidation by overlay film.At this moment, shown in Figure 21 (J), when upper strata interlayer resin insulating layers 560 is carried out thermal contraction repeatedly, along the direction stress application that this lower via hole 550 and upper strata via hole 570 are drawn back.At this moment, if on the interface of lower via hole 550 and upper strata via hole 570, promptly on the surface of lower via hole 550, form oxidation by overlay film, then the lower surface of the surface of this lower via hole 550 and upper strata via hole 570 is separated, and the conductivity of lower via hole 550 and upper strata via hole 570 is connected and is disconnected as can be known.
In the filling vias structure multilayer printed wiring board, also has problem.With reference to Figure 21 (J), in the via hole 550,570 of above-mentioned filling vias structure, owing on the upper surface, form pit 550a, 570a,, when being installed, IC chip etc. can reduce the reliability of installing so damaged the flatness of substrate surface.Corresponding to such problem, in order to improve the flatness of substrate, the applicant has proposed to make the level and smooth scheme in upper surface of via hole.That is, shown in Figure 22 (D), tested by the upper surface that makes lower via hole 550 and upper strata via hole 570 smoothly, made substrate level and smooth.Here, Figure 22 (E) expression promptly, is illustrated in the conductor layer that forms on the interlayer resin insulating layers 540 along the cross section of the E-E line among Figure 22 (D), and Figure 22 (D) expression is along the vertical section of the D-D line among Figure 22 (E).
; even make the upper surface of this via hole smooth; but shown in Figure 22 (E); in the multilayer printed-wiring board of the conductor layer that has conductor fig 552 and plane layer 553 and deposit; shown in Figure 22 (D); concluded because upside interlayer resin insulating layers 560 protuberances of plane layer 553 still can not make substrate surface smooth.
With reference to Figure 22 (A), Figure 22 (B), Figure 22 (C), Figure 22 (D) of the manufacturing process that represents this multilayer printed-wiring board, the reason of the upper strata protuberance of this plane layer 553 is described.Shown in Figure 22 (A), and, on the upper surface of lower interlayer resin insulating layers 540, form conductor fig 552 and plane layer 553 as mentioned above simultaneously with reference to Figure 22 (E).Here, shown in Figure 22 (B), in order to form the upper strata interlayer resin insulating layers, coating on substrate surface such as usefulness roller coating device constitutes the resin 560 of interlayer resin insulating layers.At this moment, the thickness that promptly enables resin 560 is even, but the upside thickness of plane layer 553 thickening.Can think as above-mentioned reason: around the via hole 550A that is connecting conductor fig 552 and conductor fig 552 (with reference to Figure 22 (E)), owing to resin 560 enters between this conductor fig 552 and the via hole 550A, so this part can be level and smooth.In contrast, on plane layer 553, can not run away, so resin (interlayer resin insulating layers) expands owing to resin 560.
Then, shown in Figure 22 (C), on resin 560, form the peristome 562 that is used for forming the upper strata via hole.Then, shown in Figure 22 (D),, form upper strata via hole 570 by electronplate 568 being filled in this peristome 542.
In addition, the problem that in the multilayer printed-wiring board shown in level and smooth Figure 22 in the upper surface that makes via hole (D), exists interlayer resin insulating layers 560 to peel off easily.That is, the cementability height of the interlayer resin insulating layers 540 that 560 pairs of interlayer resin insulating layers that is made of resin are made of resin, otherwise, low to the cementability of the conductor fig 552 that constitutes by metal, via hole 550A, plane layer 533.Here, around conductor fig 552 and via hole 550B, owing to this upper strata interlayer resin insulating layers 560 directly contacts with lower interlayer resin insulating layers 540, so bond together securely.Different therewith, because this upper strata interlayer resin insulating layers 560 can not contact lower interlayer resin insulating layers 540, so go wrong on cementability, this becomes the reason that interlayer resin insulating layers 560 is peeled off in plane layer 553.In addition, with reference to Figure 21 (J), such problem of peeling off does not take place in above-mentioned multilayer printed-wiring board.Can think that this is that this pit plays fixation for interlayer resin insulating layers because also form pit on the via hole that forms on the plane layer.
On the other hand, on the surface of the printed wiring board of module board etc., the scolding tin salient point is set, is connected so that obtain conductivity with the electronic components of being installed such as IC chip.This scolding tin salient point, directly forms on via hole for purposes such as raising integrated levels sometimes except forming on the conductor circuit on the substrate surface.On this printed wiring board, form the method for scolding tin salient point with reference to Figure 23 explanation.
The section of the multilayer printed-wiring board 510 of Figure 23 (A) expression prior art.This multilayer printed-wiring board makes a plurality of interlayer resin insulating layers 540,560 form conductor circuit 534,552,572 between the centre in the upper strata of core 530 and lower floor.Break-through is provided with the peristome 562 that via hole is used on outermost interlayer resin insulating layers 560, forms the via hole 570 that is made of copper coating on this peristome 562.Then, utilize this via hole 570, obtain and being connected of the conductor circuit 552 of the lower floor of interlayer resin insulating layers 560.On outermost interlayer resin insulating layers 560, form the platedresist 580 that break-through is provided with the opening 581 of specified diameter.
Here, when on this multilayer printed-wiring board 510, forming the scolding tin salient point, shown in Figure 23 (B), metal mask 598 is placed on the multilayer printed-wiring board 510, on each opening 581,581,581 of platedresist 580, print soldering paste.Here, each position with the opening 581 of platedresist 580 forms opening 598a, 598b accordingly on this metal mask 598.Here, 570 corresponding opening 598b form relatively large diameter with via hole, and on the contrary, 572 corresponding opening 598a form relative less diameter with conductor circuit.Therefore, can be to the more soldering paste of via hole 570 1 side printings.
Behind the printing soldering paste, make multilayer printed-wiring board 510, make that soldering paste is counter to flow, shown in Figure 23 (C), form scolding tin salient point 588 by heating furnace.The solder flux that flows out from scolding tin when then, cleaning anti-stream.Then, shown in Figure 23 (D), IC chip 590 is placed on the multilayer printed-wiring board 510, make the scolding tin district 592 of this IC chip 590 corresponding with the scolding tin salient point 588 of multilayer printed-wiring board 510 1 sides, make it pass through heating furnace, make this scolding tin district 588 fusions, the conductivity that obtains multilayer printed-wiring board 510 and IC chip 590 is connected.The solder flux that flows out from scolding tin when then, cleaning anti-stream.
, in above-mentioned multilayer printed-wiring board, can not suitably obtain sometimes and being connected of IC chip.Promptly, shown in Figure 23 (C), be difficult to make at the height h3 of the scolding tin salient point 588 that forms on the via hole 570 of concavity identical with the height h4 of the scolding tin salient point 588 that on flat conductor circuit 572, forms, so shown in Figure 23 (D), some in the scolding tin district 588 of multilayer printed-wiring board 510 1 sides can not suitably be connected with the scolding tin district 592 of IC chip 590 1 sides sometimes.
In addition, with reference to Figure 23 (B), as mentioned above,, be difficult to adjust owing to need diameter different opening 598a, 598b be set with each position break-through accordingly of the opening 581 of platedresist 580.In addition, as mentioned above, in order to form the scolding tin salient point, after making that scolding tin is counter and flowing the back and carrying out being connected of scolding tin district on this scolding tin salient point and the IC chip by anti-stream, need to clean solvent from scolding tin., because scolding tin is filled in the via hole 570, so soldering tin amount increases, the amount of the solder flux that oozes out is also many, is difficult to clean fully.Therefore, also also have solder flux remnants after cleaning, become the reason of short-circuit etc.In addition, during above-mentioned anti-stream, multilayer printed-wiring board 510 bends, often reduced and IC chip 190 between the reliability of installing.
The present invention finishes in order to solve above-mentioned problem, and what its purpose was to provide good reliability of connection between a kind of via hole and the via hole has a filling vias structure multilayer printed wiring board.
The object of the present invention is to provide a kind of substrate surface that can make to form smoothly, the multilayer printed-wiring board of crackle (デ ラ ネ-シ ョ Application) does not take place in interlayer resin insulating layers.
The object of the present invention is to provide a kind of multilayer printed-wiring board of scolding tin salient point good reliability of connection.
Disclosure of an invention
In order to achieve the above object, the present invention is that a kind of interlayer resin insulating layers and conductor circuit replace overlapping multilayer printed-wiring board, and its technical characterictic is:
Be provided with peristome on lower interlayer resin insulating layers, electrodeposited coating is filled in this peristome, forms the lower via hole that has an even surface, and forms the upper strata via hole in the upper strata of this lower via hole one side.
In the present invention, on the interlayer resin insulating layers of the upper strata of lower via hole one side, form when being used for forming the opening of upper strata via hole, because the surface of lower via hole is smooth, so cull not.Therefore, can guarantee the reliability that lower via hole is connected with the upper strata via hole.In addition, because the having an even surface of lower via hole, so even form the upper strata via hole overlappingly, also without detriment to the flatness on multilayer printed-wiring board surface.
In preferred configuration of the present invention, because roughened has been carried out on the surface of lower via hole, so, also can guarantee the reliability that lower via hole is connected with the upper strata via hole even on this surface, form oxidation by overlay film.
In preferred configuration of the present invention, because roughened has been carried out in the side of the peristome of lower interlayer resin insulating layers, so can improve tight contact with the via hole of the interior formation of this peristome.
In preferred configuration of the present invention, because roughened has been carried out on the surface of upper strata via hole and conductor circuit, so can improve and this upper strata via hole and the tight contact between scolding tin district that forms on the conductor circuit or interlayer resin insulating layers.
In preferred configuration of the present invention, constitute or mainly constitute owing to hearing the complex of resin insulating barrier down layer by layer by thermoplastic resin by thermoplastic resin and thermosetting resin, toughness is big, even so the electronplate that via hole is used is filled in the peristome of this interlayer resin insulating layers, crackle can not take place yet on interlayer resin insulating layers.
In preferred configuration of the present invention, the ratio of via hole diameter and the thickness of interlayer resin insulating layers is greater than 1.That is,,,, can effectively form via hole by electroplating so electroplate liquid can enter in this peristome fully because the degree of depth of the peristome of formation via hole is not too dark with respect to opening diameter by electroplating in the operation that forms via hole.On the other hand, the ratio of via hole diameter with the thickness of interlayer resin insulating layers is set at below 4.That is,,,, can make the surface of via hole form smoothly by adjusting electroplating time because the opening diameter of the peristome of formation via hole is not too big with respect to the degree of depth by electroplating in the operation that forms via hole.
In order to achieve the above object, the present invention is that a kind of interlayer resin insulating layers and conductor circuit replace overlapping multilayer printed-wiring board, and its technical characterictic is:
Be provided with peristome on lower interlayer resin insulating layers, electrodeposited coating is filled in this peristome, forms lower via hole, makes the matte layer of this lower via hole form the upper strata via hole between the centre.
In the present invention, lower via hole and upper strata via hole are owing to make the rough layer that forms on the surface of lower via hole couple together between the centre, even, also can guarantee the reliability that lower via hole is connected with the upper strata via hole so on this surface, form oxidation by overlay film.
In preferred configuration of the present invention, owing to form pit at the central portion of lower via hole, so rough layer vertically is set with this pit.Therefore, securely lower via hole and upper strata via hole are coupled together, can guarantee the reliability that lower via hole is connected with the upper strata via hole.
In preferred configuration of the present invention, because roughened has been carried out in the side of the peristome of lower interlayer resin insulating layers, so can improve tight contact with the via hole of the interior formation of this peristome.
In preferred configuration of the present invention, because roughened has been carried out on the surface of upper strata via hole and conductor circuit, so can improve and this upper strata via hole and the tight contact between scolding tin salient point that forms on the conductor circuit or interlayer resin insulating layers.
In preferred configuration of the present invention, constitute or mainly constitute owing to hearing the complex of resin insulating barrier down layer by layer by thermoplastic resin by thermoplastic resin and thermosetting resin, toughness is big, even so the electronplate that via hole is used is filled in the peristome of this interlayer resin insulating layers, crackle can not take place yet on interlayer resin insulating layers.
In preferred configuration of the present invention, the ratio of via hole diameter and the thickness of interlayer resin insulating layers is greater than 1.That is,,,, can effectively form via hole by electroplating so electroplate liquid can enter in this peristome fully because the degree of depth of the peristome of formation via hole is not too dark with respect to opening diameter by electroplating in the operation that forms via hole.
In order to achieve the above object, the present invention is that a kind of interlayer resin insulating layers and conductor layer replace overlapping multilayer printed-wiring board, and its technical characterictic is:
One deck at least in the above-mentioned conductor layer has plane layer, and there is conductor fig and the via hole that is connected on the via hole this plane layer inside,
The via hole that is connected on the above-mentioned conductor fig is filled by electrodeposited coating, and the surface forms smoothly, and the via hole that has in the above-mentioned plane layer is filled by electrodeposited coating, forms pit from the teeth outwards.
In the present invention, owing to form pit on the via hole that has in plane layer, this pit becomes fixture, has improved the tight contact of plane layer and upper strata interlayer resin insulating layers, so this interlayer resin insulating layers is not easy to peel off.In addition, in manufacturing process, when coating forms the resin of upper strata interlayer resin insulating layers of plane layer, resin is entered in the pit on the via hole of plane layer, can make this interlayer resin insulating layers is that the surface of multilayer printed-wiring board forms smoothly.Can improve the reliability of installing when therefore, the IC chip being installed.In addition, owing to be connected having an even surface of via hole on the conductor fig, so even form via hole overlappingly, also without detriment to the flatness on multilayer printed-wiring board surface on the upper strata of this via hole.
In preferred configuration of the present invention, because hearing the side of the peristome of resin insulating barrier, layer carried out roughened, so can improve the tight contact with the via hole of the interior formation of this peristome.
In preferred configuration of the present invention, owing to inner have the surface of the plane layer of via hole to carry out roughened, so can improve and the tight contact of upper strata interlayer resin insulating layers.
In preferred configuration of the present invention, because the pit depth on the via hole that has in the plane layer is more than 5 microns, so have sufficient fixed effect, can improve the tight contact of plane layer and upper strata interlayer resin insulating layers, so this interlayer resin insulating layers is not easy to peel off.In addition, in manufacturing process, coating form plane layer on when hearing the resin of resin insulating barrier layer by layer, resin is entered in the pit on the via hole of this plane layer, can make this interlayer resin insulating layers form smoothly.On the other hand, since in the plane layer pit depth on the via hole that has below 50 microns, so can make having an even surface of the via hole that is connected on the conductor fig.
In preferred configuration of the present invention, because the area of plane layer is 0.01～10dm 2So, forming pit on the electronplate surface that the via hole that can have is filled in this plane layer, can make simultaneously to be connected the electronplate surface that the via hole on the conductor fig is filled and to form smoothly.
In order to achieve the above object, the present invention is that a kind of layer of news resin insulating barrier and conductor layer replace overlapping multilayer printed-wiring board, and its technical characterictic is to have:
The scolding tin salient point that on the conductor circuit that is arranged on the outermost interlayer resin insulating layers, forms; And
Be arranged on the scolding tin salient point that forms on the via hole that the filling electrodeposited coating constitutes in this outermost layer of peristome of hearing on resin insulating barrier in break-through.
In the present invention, by in peristome, filling electronplate, the apparent height of via hole is equated with the height of the conductor circuit that forms the scolding tin salient point.Therefore, the soldering paste of printing equivalent amount on via hole and conductor circuit can make the height of scolding tin salient point that forms on this via hole and the scolding tin salient point that forms on conductor circuit equate.Therefore, can improve the reliability that the scolding tin salient point connects.
In preferred configuration of the present invention,,, can improve the reliability that the scolding tin salient point connects so via hole and scolding tin salient point can be coupled together securely owing to form pit at the central portion of via hole.
In preferred configuration of the present invention, because roughened has been carried out in the side of the peristome of outermost interlayer resin insulating layers, so can improve tight contact with the via hole of the interior formation of this peristome.
In preferred configuration of the present invention, because roughened has been carried out on the surface of via hole and conductor circuit, so can improve and this via hole and the tight contact between the scolding tin salient point that forms on the conductor circuit.
In preferred configuration of the present invention, owing on the via hole surface of filling the electronplate formation, make precious metal form the scolding tin salient point between the centre, so between via hole surface that constitutes by copper etc. and scolding tin salient point, can not form oxidation, can improve the tight contact of via hole and scolding tin salient point by overlay film.
The simple declaration of accompanying drawing
Fig. 1 is the profile of the multilayer printed-wiring board of expression first example of the present invention.
Fig. 2～Fig. 6 is the figure of manufacturing process of multilayer printed-wiring board of first example of expression invention.
Fig. 7 is the profile of the multilayer printed-wiring board of expression second example of the present invention.
Fig. 8～Figure 10 is the figure of manufacturing process of multilayer printed-wiring board of second example of expression invention.
Figure 11 is the profile of the multilayer printed-wiring board of expression the 3rd example of the present invention.
Figure 12 is the cross-sectional profile of expression along the B-B line among Figure 11.
Figure 13～Figure 16 is the figure of manufacturing process of the multilayer printed-wiring board of expression the 3rd example of the present invention.
Figure 17 is the profile of the multilayer printed-wiring board of expression the 4th example of the present invention.
Figure 18 is the figure of manufacturing process of multilayer printed-wiring board of the 4th example of expression invention.
Figure 19 is the profile of multilayer printed-wiring board of the Change Example of expression the 4th example of the present invention.
Figure 20 (A) is the profile of the multilayer printed-wiring board relevant with prior art, and Figure 20 (B), Figure 20 (C), Figure 20 (D), Figure 20 (E) are the figure of the manufacturing process of the expression multilayer printed-wiring board relevant with prior art.
Figure 21 (F), Figure 21 (G), Figure 21 (H), Figure 21 (I), Figure 21 (J) are the figure of the manufacturing process of the expression multilayer printed-wiring board relevant with prior art.
Figure 22 (A), Figure 22 (B), Figure 22 (C), Figure 22 (D) are the figure of the manufacturing process of the expression multilayer printed-wiring board relevant with prior art.Figure 22 (E) is the profile of expression along the E-E line among Figure 22 (D).
Figure 23 (A), Figure 23 (B), Figure 23 (C), Figure 23 (D) are the figure of the manufacturing process of the expression multilayer printed-wiring board relevant with prior art.
The optimal morphology of the usefulness that carries out an invention
With reference to Fig. 1 of the section of representing multilayer printed-wiring board, the structure of the multilayer printed-wiring board of first example of the present invention is described.Multilayer printed-wiring board 10 shown in figure surface thereon is provided with the scolding tin salient point 88U that is connected week with the salient point side on the not shown IC chip, a side is disposing the scolding tin salient point 88D that is connected usefulness with the salient point on the not shown motherboard in its lower section, constituent components substrate, this module board play a part the signal between this IC chip-motherboard of transmitting-receiving etc.
A side upper strata (here below a side upper strata reached on the core 30 of multilayer printed-wiring board 10, so-called upper strata is meant that with substrate 30 be the center, just be meant upside above, the following downside that just is meant of substrate) the last internal layer copper figure 34,34 that becomes ground plane.In addition, make lower interlayer resin insulating layers 40 between the centre, form the conductor circuit 52 that constitutes holding wire, perhaps, connect this interlayer resin insulating layers 40 and form lower via hole 50 on the upper strata of internal layer copper figure 34.Make on the upper strata of lower via hole 50 and conductor circuit 52 and to hear resin insulating barrier 60 layer by layer between the centre, the upper strata via hole 70 that forms outermost conductor circuit 72 and connect this upper strata interlayer resin insulating layers 60.
Form the scolding tin district 86U that supports scolding tin salient point 88U in the above on this conductor circuit 72 of a side, the upper strata via hole 70.Here the diameter of the scolding tin district 86U of IC chip one side is 133 microns.On the other hand, below this conductor circuit 72 of a side, on the via hole (not shown) of upper strata, form to support the scolding tin district 86D of scolding tin salient point 88D.Here the diameter of the scolding tin district 86D of motherboard one side is 600 microns.
In this multilayer printed-wiring board 10, because the surface of lower via hole 50 is smooth, thus can guarantee the reliability that lower via hole 50 is connected with upper strata via hole 70, without detriment to the flatness on multilayer printed-wiring board surface.Promptly, with reference to Figure 21 (I), in the filling vias structure multilayer printed wiring board of above-mentioned prior art, owing to pit 150a on lower via hole 150, occurs, so the resin 160a as insulator remains among this pit 150a, reduced the reliability that lower via hole 150 is connected with upper strata via hole 170.Different therewith, as shown in Figure 1, in the multilayer printed-wiring board 10 of this example,,, can guarantee the reliability that connects so between lower via hole 50 and upper strata via hole 70, do not have resin because the surface of lower via hole 50 is smooth.In addition, in the multilayer printed-wiring board of the prior art shown in Figure 21 (I), because pit 170a is arranged on upper strata via hole 170, so damaged the flatness of substrate, but in the multilayer printed-wiring board 10 of this example, owing to can make substrate surface form smoothly, so can improve the installation reliability that is installed in the IC chip on this multilayer printed-wiring board (module board).
At the via hole 50 that constitutes by copper with between the interlayer resin insulating layers that constitutes by resin 40 that forms on this via hole 50, because both coefficient of thermal expansion difference, so apply big stress during thermal contraction.Here, with reference to Figure 20 (A), above-mentioned prior art in the via hole 250 that inboard potting resin 260a constitutes, can make the stress that is taken place go to resin 260a one side of electro-coppering 248 inside.Different therewith, in the multilayer printed-wiring board 10 of this example, owing to the metallide copper 48,68 that via hole is used is filled in the peristome 42,62 of interlayer resin insulating layers 40,60, so can not make stress go to the inboard.Therefore, in this multilayer printed-wiring board 10, the complex by thermoplastic resin that toughness is big and thermosetting resin is used for lower interlayer resin insulating layers 40 and upper strata interlayer resin insulating layers 60, can prevent the generation of the crackle that caused by this stress.Here, though use the complex of thermoplastic resin and thermosetting resin, also can mainly use the big thermoplastic resins such as fluororesin of toughness to replace above-mentioned complex to come cambium layer to hear resin insulating barrier 40,60.
In addition, as shown in Figure 1, owing to the surface of lower via hole 50, be that the interface of lower via hole 50 and upper strata via hole 70 forms the rough layer 58 that roughened is crossed, so both combine securely.Therefore, on the surface of this lower via hole 50, form oxidation by overlay film, even because the thermal contraction of interlayer resin insulating layers 60 along the direction stress application that lower via hole 50 and upper strata via hole 70 are drawn back, also can be guaranteed the reliability that lower via hole 50 is connected with upper strata via hole 70.And, as shown in the figure, because side 42a, the 62a of the peristome 42,62 of lower interlayer resin insulating layers 40 and upper strata interlayer resin insulating layers 60 have carried out roughened, so can improve tight contact with the via holes 50,70 of this peristome 42,62 interior formation.In addition, because roughened has been carried out on the surface of upper strata via hole 70 and conductor circuit 72,52, formed rough layer 78,58, so the tight contact of the scolding tin district 86U that can improve and on this upper strata via hole 70, conductor circuit 72, form, and and the tight contact between the interlayer resin insulating layers 60 that forms on the conductor circuit 52.
The manufacturing process of module board shown in Figure 1 then, is described with reference to Fig. 2～Fig. 6.
(1) is overlapping 18 microns Copper Foil 32 on the two sides of the core 30 that constitutes by BT (PVC ス マ レ ィ ミ De ト リ ァ ジ Application) resin or glass epoxy of 1mm at thickness, covers copper overlapping plates 30A as raw material (with reference to the operation among Fig. 2 (A)) what constitute like this.At first, carry out pattern etching, on the two sides of substrate 30, form internal layer copper figure (conductor circuit) 34 (with reference to the operation among Fig. 2 (B)) by this being covered copper overlapping plates 30A.
In addition, the substrate 30 that has formed internal layer copper figure 34 is washed, after the drying, be immersed in the electroless plating liquid of the pH=9 that constitutes by copper sulphate 8g/l, nickelous sulfate 0.6g/l, citric acid 15g/l, sodium hypophosphite 29g/l, boric acid 31g/l, surfactant 0.1g/l, on the surface of this internal layer copper figure 34, form thickness and be 3 microns the rough layer 38 (with reference to the operation among Fig. 2 (C)) that constitutes by copper-nickel-phosphorus.This substrate 30 is washed, and dipping is 1 hour in 50 ℃ the no electrolytic tin displacement plating liquid that is made of 0.1mol/l boron tin fluoride-1.0mol/l thiocarbamide liquid, and 0.3 micron tin layer (not shown) is set on the rough layer surface.
In addition, resin is coated on the surface of substrate 30, also can seeks the smoothing of substrate.In the case, the substrate 30 (operation (B)) that has formed internal layer copper figure 34 is washed, after the drying, by using NaOH (10g/l), NaClO 2(40g/l), Na 3PO 4(6g/l) as oxidation liquid (blackening liquid), with NaOH (10g/l), NaBH 4(6g/l) handle, on the surface of internal layer copper figure 34, rough layer is set as the OR of reducing solution.
The feedstock composition of following resin filler modulation usefulness is mixed stirring, obtain the resin filler.
[resin combination 1.]
Following substances is mixed stirring: (YL983U) weight ratio is 100 to the bisphenol f type epoxy resin monomer for oiling シ エ Le system, molecular weight 310; The SiO of 1.6 microns of average grain diameters of silane coupling agent has been covered on the surface 2Spheroidal particle (here, the size of maximum particulate is following for the thickness (15 microns) of hereinafter described internal layer copper figure for ア De マ テ Star Network system, CRS1101-CE) weight ratio is 170; Levelling agent (サ Application ノ プ コ system, ペ レ ノ-Le S4) weight ratio is 1.5, under 23 ± 1 ℃ temperature, the viscosity of this mixture is adjusted into 45000～49000cps.
[the curing agent constituent 2.]
(four countries change into system to imidazole hardeners, and 2E4MZ-CN) weight ratio is 6.5.
In back 24 hours of modulation, by the resin filler that is obtained being coated on the two sides of substrate 30, be filled between conductor circuit (internal layer copper figure) 34 and the conductor circuit 34 with the roller coating device, heat drying is 20 minutes under 70 ℃ temperature.
Utilize belt sand-blasting machine (it uses No. 600 belt pouncing paper (three are total to the physics and chemistry length of schooling)) to grinding through the one side of the substrate 30 after the above-mentioned processing, resin filler 40 residual on the surface with internal layer copper figure 34 grinds away, secondly, polish grinding, so that the scar that produces will utilize above-mentioned belt sand-blasting machine to grind the time is removed.Secondly, carry out heat treated under the following conditions: 100 ℃ were heated 1 hour, and 120 ℃ were heated 3 hours, and 150 ℃ were heated 1 hour, and 180 ℃ were heated 74 hours, made the sclerosis of resin filler.
After the substrate that has formed conductor circuit carried out alkali degreasing, carry out soft etching again, secondly, use the catalyst solution that constitutes by palladium bichloride and organic acid to handle, supply with the Pd catalyst, after this catalyst is activated, be immersed in the electroless plating liquid of following formation: copper sulphate 3.2 * 10 -2Mol/l, nickelous sulfate 3.9 * 10 -3Mol/l, complexing agent 5.4 * 10 -2Mol/l, hypophosphorous acid receive 3.3 * 10 -1Mol/l, boric acid 5.0 * 10 -1Mol/l, surfactant (day letter chemical industry system, サ-Off ィ-Le 465) 0.1g/l, PH=9, flood after 1 minute, in per vibration in 4 seconds ratio once, carry out extensional vibration and transverse vibration, acicular alloy coating and the rough layer that is made of Cu-Ni-P is set on the surface of conductor circuit.
In addition, under the condition of tin fluoborate 0.1mol/l, thiocarbamide 1.0mol/l, 35 ℃ of temperature, PH=1.2, carry out the Cu-Sn displacement reaction, the Sn layer of 0.3 micron of thickness is set on the surface of rough layer.Therefore, can make substrate surface level and smooth.
Next, go on to say manufacturing process.
(2) here, the feedstock composition of the interlayer insulation resin agent in the following B item being modulated usefulness mixes, and viscosity is adjusted into 1.5pas, obtains interlayer insulation resin agent (lower floor uses).
Secondly, the feedstock composition of the electroless plating in the following A item with bonding agent modulation usefulness mixed, viscosity is adjusted into 7pas, obtain electroless plating adhesive solution (upper strata is used).
A. electroless plating is modulated the feedstock composition (upper strata bonding agent) of usefulness with bonding agent
[resin combination 1.]
Following material is mixed: 25% propen compounds of cresol-novolak type epoxy resin (Japanese chemical drug system, molecular weight 2500) is dissolved among the DMDG that concentration is 80wt%, and the resin liquid weight ratio of getting after this dissolving is 35; Photo-sensitive monomer (the synthetic system in East Asia, ア ロ ニ Star Network ス M315) weight ratio is 3.15; Defoamer (サ Application ノ プ コ system, S-65) weight ratio is 0.5; The NMP weight ratio is 3.6, obtains resin combination 1.
[resin combination 2.]
Following material is mixed: polyether sulphur (PES) weight ratio is 12; Average grain diameter is that 1.0 microns epoxy resin particulate (Sanyo changes into system, Port リ マ-Port-Le) weight ratio is 7.2; Average grain diameter is that 0.5 micron epoxy resin particulate (Sanyo changes into system, Port リ マ-Port-Le) weight ratio is 3.09, adds weight ratio after the mixing again and be 30 NMP, mixes with porose particle grinder (PVC-ズ ミ Le), obtains resin combination 2..
[the curing agent constituent 3.]
Following material is mixed: (four countries change into system to imidazole hardeners, and 2E4MZ-CN) weight ratio is 2; Light trigger (チ バ ガ ィ ギ-system, ィ Le ガ キ ュ ア I-907) weight ratio is 2; Light sensitizer (Japanese chemical drug system, DETX-S) weight ratio is 0.2; The NMP weight ratio is 1.5, has obtained the curing agent constituent 3..
B. the feedstock composition (lower floor's bonding agent) of usefulness is modulated in the agent of interlayer insulation resin
[resin combination 1.]
Following material is mixed: 25% propen compounds of cresol-novolak type epoxy resin (Japanese chemical drug system, molecular weight 2500) is dissolved among the DMDG that concentration is 80wt%, and the resin liquid weight ratio of getting after this dissolving is 35; Photo-sensitive monomer (the synthetic system in East Asia, ア ロ ニ Star Network ス M315) weight ratio is 4; Defoamer (サ Application ノ プ コ system, S-65) weight ratio is 0.5; The NMP weight ratio is 3.6, obtains resin combination 1.
[resin combination 2.]
With polyether sulphur (PES) weight ratio is 12; Average grain diameter is that 0.5 micron epoxy resin particulate (Sanyo changes into system, Port リ マ-Port-Le) weight ratio is 14.49, adds weight ratio after the mixing again and be 30 NMP, mixes with porose particle grinder (PVC-ズ ミ Le), obtains resin combination 2..
[the curing agent constituent 3.]
Following material is mixed: (four countries change into system to imidazole hardeners, and 2E4MZ-CN) weight ratio is 2; Light trigger (チ バ ガ ィ ギ-system, イ Le ガ キ ュ ア I-907) weight ratio is 2; Light sensitizer (Japanese chemical drug system, DETX-S) weight ratio is 0.2; The NMP weight ratio is 1.5, has obtained the curing agent constituent 3..
(3) in back 24 hours of modulation, the viscosity that will obtain in above-mentioned (2) with the roller coating device is the two sides that the interlayer insulation resin agent (lower floor with) of 1.5pas is coated in aforesaid substrate, under level, place after 20 minutes, drying (preliminary drying) is 30 minutes under 60 ℃ temperature, secondly, in back 24 hours of modulation, be coated in the photosensitive adhesive solution that the viscosity that obtains in above-mentioned (2) is 7pas (upper strata is used), under level, placed 20 minutes, under 60 ℃ temperature dry (preliminary drying) 30 minutes then forms thickness and is 35 microns interlayer resin insulating layers 40 (with reference to the operation among Fig. 2 (D)).
With the photomask film applying of black circle that printed specified diameter on the two sides of the substrate 30 that has formed lower interlayer resin insulating layers 40, with extra-high-pressure mercury vapour lamp at 500mJ/cm 2Condition under carry out exposure.To its video picture of spraying, use extra-high-pressure mercury vapour lamp with DMDG solution again at 3000mJ/cm 2Condition under, this substrate is carried out exposure, heat treated is 1 hour under 100 ℃ temperature, heat treated (main baking) 5 hours under 150 ℃ temperature then, formation thickness is 20 microns interlayer resin insulating layers 40, it has the opening (via hole forms with peristome 42: 61 microns of bottoms, 67 microns on top) (with reference to the operation among Fig. 3 (E)) of 60 micron pore size better than the dimensional accuracy suitable with the photomask film.In addition, make and constitute opening of via hole and 42 expose the tin coating (not shown) partly.
(4) substrate 30 that has formed peristome 42 was flooded 2 minutes in chromic acid, the lip-deep epoxy resin particle dissolution of interlayer resin insulating layers 40 is removed, the formation degree of depth is 4 microns a matsurface on the surface of this interlayer resin insulating layers 40.Equally also can make the side 42a of peristome 42 inside form this matsurface (with reference to the operation among Fig. 2 (F)).Then, wash again after being immersed in the neutralization solution (シ プ レ ィ society system).
In addition, palladium catalyst (ア ト テ Star Network system) is supplied with the surface of this substrate carried out roughened, catalyst core is added in the surface of interlayer resin insulating layers 40 and via hole with on the internal face of peristome 42.
(5) substrate is immersed in the electroplating liquor without electrolytic copper of following composition, formation thickness is 0.6 micron electrolytic copper free electroplating film 44 (with reference to the operation among Fig. 2 (G)) on whole matsurfaces.
[electroless plating liquid]
EDTA 150g/l
Copper sulphate 20g/l
HCHO 30ml/l
NaOH 40g/l
α, α '-bipyridine 80mg/l
PEG 0.1g/l
(6) commercially available photosensitive dry film is posted on the electrolytic copper free electroplating film 44 that in above-mentioned (5), forms, places mask, at 100mJ/cm 2Condition under carry out exposure, carry out video picture with 0.8% sodium carbonate and handle, thickness be set be 20 microns, the platedresist 46 (with reference to the operation among Fig. 2 (H)) of L/S=25/25 micron.
(7) secondly, under the following conditions, non-the formations part of resist is carried out the cathode copper plating, separate out thickness and be 20 microns cathode copper electroplating film 48, with these electroplating film filling opening portion 42 inside (with reference to the operation among Fig. 4 (I)).
Solution condition: copper sulphate 5 hydrate 60g/l
Sulfuric acid 190g/l
Chloride ion 40ppm
Levelling agent (ア ト テ Star Network system HL) 40ml/l
Polishing material (ア ト テ シ Network system UV) 0.5ml/l
Operating condition: bubbled 3.001/ fen
Current density 0.5A/dm 2
Set current value 0.18A
Electroplating time 130 minutes
(8) with 5% KOH with platedresist 46 peel off remove after, mixed liquor with sulfuric acid and hydrogen peroxide carries out etching processing, dissolves and remove the electroless plating film 44 below this platedresist 46, forms the thickness that is made of electroless plating film 44 and cathode copper electroplating film 48 and is about 20 microns conductor circuit 52 and via hole 50 (with reference to the operation among Fig. 4 (J)).In the manufacture method of first example, compare with the cathode copper plating of carrying out according to a conventional method, the component of the levelling agent of the level and smooth usefulness of the plating face of making increases, make and electroplate the component minimizing of wearing glossiness polishing material, reduce to set current value, increase electroplating time, promptly, by with little electric current, carry out metallide for a long time, make the surface smoothing of via hole 50.
In addition, in this example, the ratio of the thickness (20 microns) of via hole diameter (opening diameter of peristome 42: 67 microns) and interlayer resin insulating layers 40 is set at 3.35.Here, the ratio of the thickness of via hole diameter and interlayer resin insulating layers is below 1, and in above-mentioned electroplating work procedure, if the degree of depth is dark excessively with respect to the opening diameter of peristome 42, then electroplate liquid can not flow in this peristome 42 fully, can not electroplate effectively.On the other hand, if the via hole diameter surpasses 4 with the ratio of the thickness of interlayer resin insulating layers, then because the opening diameter of the peristome of formation via hole is excessive with respect to the degree of depth, so not only electroplating time is very long, and, can not make the surface smoothing of via hole at central authorities' generation pit.Therefore, the ratio that preferably makes via hole diameter and the thickness of interlayer resin insulating layers greater than 1 less than 4.
In addition, the thickness of conductor circuit 52 below 20 microns for well, be preferably in below 40 microns.Though this be because the thickness of conductor circuit by the thickness decision of above-mentioned platedresist 46, if the thickness of this platedresist that forms optically above 40 microns, then resolution is low, is difficult to constitute desirable shape.
(9) then, the same with above-mentioned (2), to the conductor circuit 52 and the via hole 50 formation rough layers 58 (with reference to the operation among Fig. 4 (K)) of substrate 30.
(10) by carrying out the operation of above-mentioned (2)～(8) repeatedly, form the top conductor circuit again.Promptly, electroless plating is used the two sides of adhesive applicating at substrate 30, place with level, carry out drying, paste the photomask film then, carry out the exposure video picture, form and to have via hole to form thickness with opening 62 be 20 microns interlayer resin insulating layers 60 (with reference to the operation among Fig. 4 (L)).Secondly, after the surface that makes this interlayer resin insulating layers 60 becomes matsurface, form electrolytic copper free electroplating film 64 (with reference to the operation among Fig. 5 (M)) on the surface of this substrate 30 after this surface roughening is handled.Then, be arranged on platedresist 66 on the electrolytic copper free electroplating film 64 after, form cathode copper electroplating film 68 (with reference to the operation among Fig. 5 (N)) in the non-formation of resist part.Then, with platedresist 66 peel off remove after, electroless plating films 64 dissolvings below this platedresist 66 are removed, form upper strata via hole 70 and conductor circuit 72 (with reference to the operation among Fig. 5 (O)).On the surface of this upper strata via hole 70 and conductor circuit 72, form rough layer 78 again, make module board (with reference to the operation among Fig. 5 (P)).
(11) then, on the said modules substrate, form the scolding tin salient point.The method of adjustment of the scolder resist constituent that the scolding tin salient point is used at first, is described.Here, following material is mixed: make the photosensitive oligomer (molecular weight 4000) that has after epoxy radicals 50% propyleneization of the cresol-novolak type epoxy resin (Japanese chemical drug system) that is dissolved in 60% weight among the DMDG get 46.67g; Be dissolved in bisphenol A type epoxy resin (oiling シ ェ Le system, the エ ピ コ-ト 1001) 15.0g of 80 weight % in the butanone; (four countries change into system to imidazole hardeners, 2E4MZ-CN) 1.6g; High price propylene monomer (Japanese chemical drug system, R604) 3g as photo-sensitive monomer; Identical high price propylene monomer (common prosperity society chemistry system, DPE6A) 1.5g, disperse defoamer (サ Application ノ プ コ system, S-65) 0.71g, interpolation is as benzophenone (the chemical system in the Northeast) 2g of light trigger, as rice phase Le Shi ketone (the Northeast chemistry is made) 0.2g of light sensitizer in this mixture again, and acquisition its viscosity in the time of 25 ℃ is adjusted to the scolder resist constituent of 2.0Pas.
(12) above-mentioned scolder resist constituent is coated in above-mentioned (10) two sides of the substrate 30 that obtains, its thickness is 45 microns.Secondly, carry out under 70 ℃ the temperature dry 20 minutes, under 70 ℃ temperature dry 30 minutes dried, be placed in intimate contact the photomask film (not shown) that the thickness of having described circle diagram shape (mask graph) is 5mm then, use 1000mJ/cm 2Ultraviolet exposure, carry out the DMTG video picture and handle.And then under 80 ℃ 1 hour, 100 ℃ 1 hour, 120 ℃ 1 hour, 150 ℃ conditions of 3 hours, carry out heat treated, formed the scolder resist layer (thickness is 20 microns) 80 (with reference to the operation among Fig. 6 (Q)) of opening is arranged (bore is 200 microns) 81 in scolding tin district part (comprising via hole and contact zone part thereof).A side is 133 microns above the bore of welding zone portion (opening) 81, below a side be 600 microns.
(13) secondly, this substrate is immersed in the no electrolytic nickel electroplate liquid of pH=4.5 and continues 20 minutes, the following formation of this electroplate liquid: nickel chloride 2.31 * 10 -1Mol/l, sodium hypophosphite 2.8 * 10 -1Mol/l, citric acid receive 1.85 * 10 -1Mol/l has formed thickness and is 5 microns nickel coating 82 on peristome 81.Under 80 ℃ condition, this substrate is immersed in the electroless gold plating liquid for forming gold plating film for wire bonding again and continues 7 minutes and 20 seconds, the following formation of this electroless gold plating liquid for forming gold plating film for wire bonding: potassium auricyanide 4.1 * 10 -2Mol/l, ammonium chloride 1.87 * 10 -1Mol/l, citric acid receive 1.16 * 10 -1Mol/l, sodium hypophosphite 1.7 * 10 -1Mol/l forms thickness and is 0.03 micron Gold plated Layer 84 on nickel coating 81, form diameter in the above and be 133 microns scolding tin district 86U, forms diameter below and be 600 microns scolding tin district 86D (with reference to the operation among Fig. 6 (R)).
(14) place that to have thickness be 40 microns, diameter is the metal mask (not shown) of 160 microns peristome, above in the peristome 81 of scolder resist layer 80 on the scolding tin district 86U of a side printing average grain diameter be 20 microns soldering paste, after the scolding tin district 86D of a side goes up the printing soldering paste equally below, the anti-stream of heating under 200 ℃ temperature, thereby with diameter is that 133 microns scolding tin salient point 88U is arranged on the scolding tin district 86U of a top side, and be that 600 microns scolding tin salient point 88D is arranged on the scolding tin district 86D of a following side with diameter, the formation of scolding tin salient point finishes (with reference to Fig. 1).
As mentioned above, in the multilayer printed board of first example, via hole directly is connected on the via hole, owing to do not connect by wiring, so can realize densification.When carrying out being connected of this lower via hole and upper strata via hole, because having an even surface of lower via hole do not have residual resin on this surface, so can guarantee the reliability that the via hole of levels connects.In addition, because the having an even surface of lower via hole, so even form the upper strata via hole overlappingly, also without detriment to the flatness on multilayer printed-wiring board surface.
Then, with reference to Fig. 7 of the section of representing multilayer printed-wiring board, the structure of the multilayer printed-wiring board of second example of the present invention is described.Multilayer printed-wiring board 200 constituent components substrates shown in the figure.
Become the internal layer copper figure 34,34 of ground plane below a side upper strata reaches on the core 30 of multilayer printed-wiring board 200 on the side upper strata.In addition, make lower interlayer resin insulating layers 40 between the centre, form the conductor circuit 52 that constitutes holding wire, in addition, connect this interlayer resin insulating layers 40 and form lower via hole 50 on the upper strata of internal layer copper figure 34.Make upper strata interlayer resin insulating layers 60 between the centre on the upper strata of lower via hole 50 and conductor circuit 52, the upper strata via hole 70 that forms outermost conductor circuit 72 and connect this upper strata interlayer resin insulating layers 60.
Form the scolding tin district 86U that supports scolding tin salient point 88U in the above on this conductor circuit 72 of a side, the upper strata via hole 70.Here, the diameter of the scolding tin district 86U of IC chip one side is 133 microns.On the other hand, form the scolding tin district 86D that supports scolding tin salient point 88D on this conductor circuit 72 of a side, the upper strata via hole (not shown) below.Here, the diameter of the scolding tin district 86D of motherboard one side is 600 microns.
In the multilayer printed-wiring board of second example, owing to the surface of lower via hole 50, be that the interface of lower via hole 50 and upper strata via hole 70 forms the rough layer 58 that roughened is crossed, so both combine securely.Therefore, on the surface of this lower via hole 50, form oxidation by overlay film, even because the thermal contraction of interlayer resin insulating layers 60, along the direction stress application that draws back, also can guarantee the reliability that lower via hole 50 is connected with upper strata via hole 70 to lower via hole 50 and upper strata via hole 70.In addition, form pit 50a, vertically be provided with rough layer 58 with respect to the curved surface of this pit 50a at the central portion of lower via hole 50.Therefore, the stress corresponding to the above-below direction in the figure that is added between lower via hole 50 and the upper strata via hole 70 is peeled off both can link together both securely, can keep being connected of lower via hole 50 and upper strata via hole 70.And, as shown in FIG., because side 42a, the 62a of the peristome 42,62 of lower interlayer resin insulating layers 40 and upper strata interlayer resin insulating layers 60 have carried out roughened, so can improve tight contact with the via holes 50,70 of this peristome 42,62 interior formation.Here, the degree of depth of pit 50a does not reach on the peristome 62 that break-through is provided with on the upper strata interlayer resin insulating layers 60, is the thickness range of conductor circuit 72.Therefore, the degree of depth is in 0.5～30 micron scope.
At the via hole 50 that constitutes by copper with between the interlayer resin insulating layers that constitutes by resin 40 that forms on this via hole 50, because both hot account coefficient difference, so apply big stress during thermal contraction.Here, with reference to Figure 20 (A), above-mentioned prior art in the via hole 250 that inboard potting resin 260a constitutes, can make the stress that is taken place go to resin 260a one side of electro-coppering 248 inside.Different therewith, in the multilayer printed-wiring board 200 of this example, owing to the metallide copper 48,68 that via hole is used is filled in the peristome 42,62 of interlayer resin insulating layers 40,60, so can not make stress go to the inboard.Therefore, in this multilayer printed-wiring board 200, the complex by thermoplastic resin that toughness is big and thermosetting resin is used for lower interlayer resin insulating layers 40 and upper strata interlayer resin insulating layers 60, can prevent the generation of the crackle that caused by this stress.Here, though use the complex of thermoplastic resin and thermosetting resin, also can mainly use the big thermoplastic resins such as fluororesin of toughness to replace above-mentioned complex to form interlayer resin insulating layers 40,60.
In addition, because roughened has been carried out on the surface of upper strata via hole 70 and conductor circuit 72,52, formed rough layer 78,58, so the tight contact of the scolding tin district 86U that can improve and on this upper strata via hole 70, conductor circuit 72, form, and and the tight contact between the layer news resin insulating barrier 60 that forms on the conductor circuit 52.
The manufacturing process of multilayer printed-wiring board shown in Figure 7 then, is described with reference to Fig. 8～Figure 10.In addition, (1) in the manufacturing process of the multilayer printed-wiring board of this second example～(6) are with identical with reference to first example of Fig. 2, Fig. 3 explanation, so omit explanation and diagram.
(7) in above-mentioned operation (H) shown in Figure 3, concerning having formed the substrate 30 of resist 46, under the following conditions the non-formation part of resist being carried out cathode copper electroplates, separate out thickness and be 20 microns cathode copper electroplating film 58, with these electroplating film filling opening portion 42 inside (with reference to the operation among Fig. 8 (I)).
Solution condition: copper sulphate 5 hydrate 60g/l
Sulfuric acid 190g/l
Chloride ion 40ppm
Levelling agent (ア ト テ Star Network system HL) 40ml/l
Polishing material (ア ト テ Star Network system UV) 0.5ml/l
Operating condition: bubbled 3.001/ fen
Current density 0.5A/dm 2
Set current value 0.18A
Electroplating time 100 minutes
In the manufacture method of this example, carry out metallide, so that form pit 50a at the central portion of the cathode copper electrodeposited coating 48 at the position that forms via hole 50.
(8) with 5% KOH with platedresist 46 peel off remove after, mixed liquor with sulfuric acid and hydrogen peroxide carries out etching processing, dissolves and remove the electroless plating film 44 below this platedresist 46, forms the thickness that is made of electroless plating film 44 and cathode copper electroplating film 48 and is about 15 microns conductor circuit 52 and via hole 50 (with reference to the operation among Fig. 8 (J)).In this example, the ratio of the thickness (20 microns) of via hole diameter (opening diameter of peristome 42: 67 microns) and interlayer resin insulating layers 40 is set at 3.35.Here, the ratio of the thickness of via hole diameter and interlayer resin insulating layers is below 1, and in above-mentioned electroplating work procedure, if the degree of depth is dark excessively with respect to the opening diameter of peristome 42, then electroplate liquid can not flow in this peristome 42 fully, can not electroplate effectively.On the other hand, if the ratio of via hole diameter and the thickness of interlayer resin insulating layers surpasses 4, then because to form the opening diameter of peristome of via hole excessive with respect to the degree of depth.Therefore, the ratio that preferably makes via hole diameter and the thickness of interlayer resin insulating layers greater than 1 less than 4.
In addition, the thickness of conductor circuit 52 below 20 microns for well, be preferably in below 40 microns.Though this be because the thickness of conductor circuit by the thickness decision of above-mentioned platedresist 46, if the thickness of this platedresist that forms optically above 40 microns, then resolution is low, is difficult to constitute desirable shape.
(9) then, the same with above-mentioned (2), to the conductor circuit 52 and the via hole 50 formation rough layers 58 (with reference to the operation among Fig. 8 (K)) of substrate 30.This rough layer 58 is vertically formed on this curved surface with respect to the curved surface of the pit 50a of the central authorities of via hole 50.
(10) by carrying out the operation of above-mentioned (2)～(8) repeatedly, form the top conductor circuit again.Promptly, electroless plating is used the two sides of adhesive applicating at substrate 30, place with level, carry out drying, paste the photomask film then, carry out the exposure video picture, form and to have via hole to form thickness with opening 62 be 20 microns interlayer resin insulating layers 60 (with reference to the operation among Fig. 8 (L)).Secondly, after the surface that makes this interlayer resin insulating layers 60 becomes matsurface, form electrolytic copper free electroplating film 64 (with reference to the operation among Fig. 9 (M)) on the surface of this substrate 30 after this surface roughening is handled.Then, be arranged on platedresist 66 on the electrolytic copper free electroplating film 64 after, form cathode copper electroplating film 68 (with reference to the operation among Fig. 9 (N)) in the non-formation of resist part.Then, with platedresist 66 peel off remove after, electroless plating films 64 dissolvings below this platedresist 66 are removed, form upper strata via hole 70 and conductor circuit 72 (with reference to the operation among Fig. 9 (O)).On the surface of this upper strata via hole 70 and conductor circuit 72, form rough layer 78 again, make module board (with reference to the operation among Figure 10 (P)).
(11) then, identical with first example, on above-mentioned module board, form scolding tin salient point (with reference to the operation among Figure 10 (Q), operation (R)).
Here, illustrate that the present inventor carries out the result of heat run and thermal cycling test to structure multilayer printed wiring board shown in Figure 7.In heating under 128 ℃ the temperature after 48 hours, with observation by light microscope section, look between lower via hole 50 and upper strata via hole 70, to have or not and peel off, the result shows to produce and does not peel off.Equally, carried out 1000 thermal cycles repeatedly with-55～125 ℃ temperature after, observe with light microscope, the result shows to produce between lower via hole 50 and upper strata via hole 70 and peels off.According to above-mentioned result of the test, as can be known in the multilayer printed-wiring board of this example, owing to making rough layer 58, so lower via hole 50 and upper strata via hole 70 can be combined securely between the centre.
As mentioned above, in the multilayer printed board of second example, via hole directly is connected on the via hole, owing to do not connect by wiring, so can realize densification.When carrying out being connected of this lower via hole and upper strata via hole,, can guarantee the reliability that the levels via hole connects because the rough layer that forms on the surface of lower via hole is connected between the centre.
Then, with reference to Figure 11 and Figure 12, the structure of the multilayer printed-wiring board of the 3rd example of the present invention is described.Figure 11 represents the section of the multilayer printed-wiring board 300 of the 3rd example.Multilayer printed-wiring board 300 constituent components substrates shown in the figure.
A side upper strata becomes the internal layer copper figure 34 of ground plane on the core 30 of multilayer printed-wiring board 300.The plane graph of the upper strata interlayer resin insulating layers 40 of internal layer copper figure 34 has been shown among Figure 12, promptly along the cross section of the B-B line among Figure 11.Here, vertical section and the Figure 11 along the A-A line among Figure 12 is suitable.As the top conductor layer of this interlayer resin insulating layers 40, as shown in figure 12, form to constitute holding wire conductor fig 52, be connected via hole 50B, the plane layer 53 on the conductor fig 52 and be arranged on via hole 50A in this plane layer 53.As shown in figure 11, via hole 50A, 50B connect interlayer resin insulating layers 40, are connected on the internal layer copper figure 34 of lower floor.Here, the surface (upper surface) that is connected the via hole 50B on the conductor fig 52 forms smoothly, on the other hand, forms pit 50a on the surface of the via hole 50A that forms in plane layer 53.On the upper strata of this conductor fig 50 and plane layer 53, make upper strata interlayer resin insulating layers 60 between the centre, the upper strata via hole 70 that forms outermost conductor fig 72 and connect this upper strata interlayer resin insulating layers 60.Here, directly over lower via hole 50B, form upper strata via hole 70.Form the scolding tin district 86U that supports scolding tin salient point 88U in the above on this conductor fig 72 of a side, the upper strata via hole 70.Here, the diameter of the scolding tin district 86U of IC chip one side is 133 microns.
The internal layer copper figure 34 that becomes ground plane is gone up on a side upper strata below the core 30 of multilayer printed-wiring board 300 (here, so-called upper strata is meant that with substrate 30 be the center, just is meant upside above, the following downside that just is meant of substrate).On the upper strata of the interlayer resin insulating layers 40 that forms on the upper strata of this internal layer copper figure 34, form the conductor circuit 52 that constitutes holding wire, be connected the via hole 50B on the conductor circuit 52.On the upper strata of this conductor fig 52, make upper strata interlayer resin insulating layers 620 between the centre, form outermost conductor fig 72 and upper strata via hole (not shown).Form the scolding tin district 86D that supports scolding tin salient point 88D below on this conductor circuit 72 of a side, the upper strata via hole (not shown).Here the diameter of the scolding tin district 86D of motherboard one side is 600 microns.
In this multilayer printed-wiring board 300, because the surface of lower via hole 50 is smooth, so even connect upper strata via hole 70, also without detriment to the flatness on multilayer printed-wiring board surface.Promptly, with reference to Figure 21 (I), in the filling vias structure multilayer printed wiring board of above-mentioned prior art, owing to pit 150a on lower via hole 150, occurs, in addition, pit 170a on upper strata via hole 170, occurs, so damaged the flatness of substrate, but in the multilayer printed-wiring board 300 of this example, owing to can make substrate surface form smoothly, so can improve the installation reliability that is installed in the IC chip on this multilayer printed-wiring board (module board).
In addition, in the described later manufacturing process, when the resin that forms interlayer resin insulating layers 60 is coated in the upper strata of plane layer 53, resin is gone in the pit 50a of via hole 50A of plane layer 53.Therefore, with reference to Figure 22 (P), different with the multilayer printed-wiring board of above-mentioned prior art, in this example, because at the upside of conductor fig 52 and at the upside of plane layer 53, can both make the thickness of interlayer resin insulating layers 60 even, so can be formed flatly the surface of multilayer printed-wiring board.
In addition, owing on the via hole 50A that is configured on the plane layer 53, form pit 50a, this pit 50a becomes fixture, has improved plane layer 53 and the last tight contact of hearing resin insulating barrier 60 layer by layer, so be not easy to make this interlayer resin insulating layers 60 to peel off (デ ラ ネ-シ ョ Application).The surface process roughened of the plane layer 53 of this via hole is particularly arranged in inside, form rough layer 58, improved and the last tight contact of hearing resin insulating barrier 60 layer by layer.
And, as shown in FIG., because side 42a, the 62a of the peristome 42,62 of lower interlayer resin insulating layers 40 and upper strata interlayer resin insulating layers 60 have carried out roughened, so can improve tight contact with the via holes 50,70 of this peristome 42,62 interior formation.
In the multilayer printed-wiring board of this example, the degree of depth of the pit 50a on the via hole 50A that has in the plane layer 53 is preferably in more than 5 microns.This is because if the degree of depth more than 5 microns, then can be brought into play the effect of fixture fully, improves plane layer and the last tight contact of hearing resin insulating barrier layer by layer, and this interlayer resin insulating layers 60 is peeled off.In addition, in the described later manufacturing process, when applying the resin of the upper strata interlayer resin insulating layers 60 that forms this plane layer 53, the resin of sufficient amount is gone in the pit 50a of the via hole 50A on this plane layer 53, can make this interlayer resin insulating layers form smoothly.On the other hand, the degree of depth of this pit 50a is preferably in below 50 microns.This is because if below 50 microns, then can make having an even surface of the via hole 50B that connects conductive pattern 52 1 sides.
The manufacturing process of module board shown in Figure 11 (multilayer printed-wiring board) 300 then, is described with reference to Figure 13～Figure 16.Here, for the purpose of illustrated convenience, Figure 13～Figure 16 only represents the position that with dashed lines C surrounds among Figure 11.In addition, (1) in the manufacturing process of the multilayer printed-wiring board of the 3rd example～(6) are with identical with reference to first example of Fig. 2, Fig. 3 explanation, so omit explanation and diagram.
(7) in above-mentioned operation (H) shown in Figure 3, concerning having formed the substrate 30 of resist 46, under the following conditions the non-formation part of resist being carried out cathode copper electroplates, separate out thickness and be 15 microns cathode copper electroplating film 48, with in this electroplating film filling opening portion 42 (with reference to the operation among Figure 13 (I)).
Solution condition: copper sulphate 5 hydrate 60g/l
Sulfuric acid 190g/l
Chloride ion 40ppm
Levelling agent (ア ト テ Star Network system HL) 40ml/l
Polishing material (ア ト テ Star Network system UV) 0.5ml/l
Operating condition: bubbled 3.001/ fen
Current density 0.5A/dm 2
Set current value 0.18A
Electroplating time 100 minutes
(8) with 5% KOH with platedresist 46 peel off remove after, mixed liquor with sulfuric acid and hydrogen peroxide carries out etching processing, dissolves and remove the electroless plating film 44 below this platedresist 46, forms the thickness that is made of electroless plating film 44 and cathode copper electroplating film 48 and is about 15 microns conductive pattern 52 (with reference to Figure 11), plane layer 53 and via hole 50A, 50B (with reference to the operation among Figure 13 (J)).In the manufacture method of this example, compare with the cathode copper plating of carrying out according to a conventional method, the component of the levelling agent of the level and smooth usefulness of the plating face of making increases, make and electroplate the component minimizing of wearing glossiness polishing material, reduce to set current value, increase electroplating time, promptly, by with little electric current, carry out metallide for a long time, make the surface smoothing of the via hole 50B (with reference to Figure 12) that is connected on the conductive pattern 52, form pit 50a on the surperficial central portion of the via hole 50A that in plane layer 53, forms simultaneously.In addition, in the 3rd example, the area of plane layer 53 is preferably 0.01～10dm 2This is because form pit on the plate surface that is filled of the via hole that has in this plane layer, can make the plate surface that is filled of the via hole that is connected on the conductor fig form smoothly simultaneously.
In addition, in this example, the ratio of the thickness (20 microns) of via hole diameter (opening diameter of peristome 42: 67 microns) and interlayer resin insulating layers 40 is set at 3.35.Here, the ratio of the thickness of via hole diameter and interlayer resin insulating layers is below 1, and in above-mentioned electroplating work procedure, if the degree of depth is dark excessively with respect to the opening diameter of peristome 42, then electroplate liquid can not flow in this peristome 42 fully, can not electroplate effectively.On the other hand, if the ratio of via hole diameter and the thickness of interlayer resin insulating layers surpasses 4, then,, can not make the surface of via hole form smoothly so pit occurs in central authorities because to form the opening diameter of peristome of via hole excessive with respect to the degree of depth.Therefore, the ratio that preferably makes via hole diameter and the thickness of interlayer resin insulating layers greater than 1 less than 4.
In addition, the thickness of conductive pattern 52 and plane layer 53 below 20 microns for well, be preferably in below 60 microns.Though this be because the thickness of conductive pattern and plane layer by the thickness decision of above-mentioned platedresist 46, if the thickness of this platedresist that forms optically above 60 microns, then resolution is low, is difficult to constitute desirable shape.
(9) then, the same with above-mentioned (2), the same to conductor fig 52, plane layer 53 and the via hole 50 of substrate 30 with above-mentioned (2), form rough layer 58 (with reference to the operation among Figure 13 (K)).
(10) by carrying out the operation of above-mentioned (2)～(8) repeatedly, form the top conductor figure again.That is, electroless plating is coated in the two sides of substrate 30 with bonding agent 60, places, carry out drying (with reference to the operation among Figure 14 (L1)) with level.At this moment, as mentioned above, when resin is coated in the upper strata of plane layer 53, resin is gone in the pit 50a of via hole 50A of plane layer 53.Therefore, around resin is gone to and the upside of the conductor fig 52 that obtains and can not go to around the upside of plane layer 53 can both make the thickness of resin 60 even.
Paste the photomask film then, carry out the exposure video picture, form and to have via hole to form thickness with opening 62 be 20 microns interlayer resin insulating layers 60 (with reference to the operation among Figure 14 (L2)).Next, the formation degree of depth is 4 microns a rough layer (with reference to the operation among Figure 14 (L3)) on the surface of this layer news resin insulating barrier 60.Side 62a to peristome 62 inside also forms this matsurface equally.Form electrolytic copper free electroplating film 64 (with reference to the operation among Figure 15 (M)) on the surface of this substrate 30 after this surface roughening is handled.Then, be arranged on platedresist 66 on the electrolytic copper free electroplating film 64 after, form cathode copper electroplating film 68 (with reference to the operation among Figure 15 (N)) in the non-formation of resist part.Then, with platedresist 66 peel off remove after, electroless plating films 64 dissolvings below this platedresist 66 are removed, form upper strata via hole 70 and conductor fig 72 (with reference to the operation among Figure 15 (O)).On the surface of this upper strata via hole 70 and conductor fig 72, form rough layer 78 again, make module board (with reference to the operation among Figure 16 (P)).
(11) then, identical with first example, to form diameter be 133 microns scolding tin salient point 88U to a side on above-mentioned module board, and a side is provided with scolding tin salient point 88D (with reference to the operation among Figure 16 (Q), operation (R) and Figure 11) below.
Here, the result who the multilayer printed-wiring board of the 3rd example is carried out PCT test and thermal cycling test is described.Be to place 200 hours under 100% the environment at two air pressure, 121 ℃, humidity, carried out the PCT test, its result does not observe the phenomenon of peeling off of interlayer resin insulating layers.In addition, after the temperature that usefulness is-55～125 ℃ has been carried out 200 thermal cycles repeatedly, peeling off of interlayer resin insulating layers do not taken place yet.Promptly, in the multilayer printed-wiring board of this example, as mentioned above, on the via hole 50A that is configured on the plane layer 53, form pit 50a, in addition, the surface of plane layer 53 has been carried out roughened and has been formed rough layer 58, has improved the tight contact of plane layer 53 and interlayer resin insulating layers 60.Therefore, be not easy to make interlayer resin insulating layers 60 to peel off (デ ラ ネ-シ ョ Application).
As mentioned above, in the module board of the 3rd example, owing to form pit on the via hole that has in plane layer, this pit becomes fixture, improved the tight contact of plane layer and upper strata interlayer resin insulating layers, so on this interlayer resin insulating layers, be not easy to peel off.In addition, in manufacturing process, when coating forms the resin of upper strata interlayer resin insulating layers of plane layer, resin is gone in the pit of the via hole on the plane layer, can be made this interlayer resin insulating layers, be that the surface of multilayer printed-wiring board forms smoothly.Can improve the reliability of installation when therefore, IC chip etc. being installed.On the other hand, owing to be connected having an even surface of via hole on the conductor fig, so even the upper strata that via hole is overlapped this via hole forms, also without detriment to the flatness on multilayer printed-wiring board surface.
Then, with reference to Figure 18 (U) and Figure 17, the structure of the multilayer printed-wiring board of the 4th example of the present invention is described.Figure 17 represents the section of multilayer printed-wiring board, and Figure 18 (U) expression is installed in IC chip 90 on this multilayer printed-wiring board 400 and places the state of motherboard 95 1 sides.Multilayer printed-wiring board 400 shown in Figure 18 (U) is provided with the scolding tin salient point 88U that is connected usefulness with salient point 92 1 sides on the IC chip 90 at upper surface, be provided with the scolding tin salient point 88D that is connected usefulness with the salient point 96 on the motherboard 95 in lower surface one side, constituent components substrate, this module board play a part the signal between reception and this IC chip of the transmission 90-motherboard 95 etc.
As shown in figure 17, a side upper strata (here below a side upper strata reached on the core 30 of multilayer printed-wiring board 400, so-called upper strata is meant that with substrate 30 be the center, just is meant upside above, the following downside that just is meant of substrate) the last internal layer copper figure 34,34 that becomes ground plane.In addition, make to descend to hear resin insulating barrier 40 layer by layer, form the conductor circuit 52 that constitutes holding wire, perhaps, connect this interlayer resin insulating layers 40 and form lower via hole 50 between the centre on the upper strata of internal layer copper figure 34.Make outermost layer interlayer resin insulating layers 60 between the centre on the upper strata of lower via hole 50 and conductor circuit 52, the upper strata via hole 70 that forms outermost conductor circuit 72 and electro-coppering is filled in peristome 62 formations that form on this outermost layer interlayer resin insulating layers 60.
Form the scolding tin district 86U that supports scolding tin salient point 88U in the above on this conductor circuit 72 of a side, the upper strata via hole 70.Here the diameter of the scolding tin district 863U of IC chip one side is 133 microns.On the other hand, below this conductor circuit 72 of a side, on the via hole (not shown) of upper strata, form to support the scolding tin district 86D of scolding tin salient point 88D.Here the diameter of the scolding tin district 86D of motherboard one side is 600 microns.On the opening (welding zone) 81 of scolder resist 80, form this scolding tin salient point 88U, 88D.
In the multilayer printed-wiring board of the 4th example, fill electronplate at the peristome 62 of outermost interlayer resin insulating layers 60, form via hole 70.Therefore the concavity via hole 170 on the multilayer printed-wiring board of via hole 70 and the prior art that illustrates with reference to Figure 23 (A) is different, and apparent height equates with the height of the conductor circuit 72 of formation scolding tin salient point.Therefore, as described later,, the height of scolding tin salient point 88U that forms on this via hole 70 and the scolding tin salient point 88U that forms on conductor circuit 72 is equated by the soldering paste of printing same amount on via hole 70 and conductor circuit 72.Therefore, shown in Figure 18 (U), when placing IC chip 90, can improve the reliability that the scolding tin district 92 of this IC chip is connected with scolding tin salient point 88U on the multilayer printed-wiring board 400.
In addition, owing to form pit 70a at the central portion of via hole 70, so can improve the reliability that via hole 70 is connected with scolding tin salient point 88U.Particularly owing to the curved surface with respect to this pit 70a vertically is provided with rough layer 78, so follow the rising of the temperature of IC chip 90, corresponding to the stress that is added between via hole 70 and the scolding tin salient point 88, both can be linked together securely, can improve the reliability that via hole 70 is connected with scolding tin salient point 88U.And, as shown in FIG., because the side 62a of the peristome 62 of outermost layer interlayer resin insulating layers 60 has carried out roughened as shown in FIG., so can improve tight contact with the via holes 70 of this peristome 62 interior formation.
At the via hole 70 that constitutes by copper with between the outermost layer interlayer resin insulating layers 60 that constitutes by resin that forms on this via hole 70, because both hot account coefficient difference, so apply big stress during thermal contraction.Therefore, in this multilayer printed-wiring board 400, the complex by thermoplastic resin that toughness is big and thermosetting resin is used for outermost layer interlayer resin insulating layers 60, can prevent the generation of the crackle that caused by this stress.Here, though use the complex of thermoplastic resin and thermosetting resin, also can mainly use the big thermoplastic resins such as fluororesin of toughness to replace above-mentioned complex to form interlayer resin insulating layers 60.
In addition,, formed rough layer 78, so the tight contact of the scolding tin salient point 88U that can improve and on this conductor circuit 72, form because roughened has been carried out on the surface of conductor circuit 72.In addition, owing to forming nickel coating 82 and Gold plated Layer (layer of precious metal) 84 on the surface that reaches the conductor circuit 72 that constitutes by electro-coppering at the via hole 70 of filling electro-coppering, make this Gold plated Layer 84 between the centre, form scolding tin salient point 88U, so between the surface of the via hole 70 that constitutes by copper etc., conductor circuit 72 and scolding tin salient point 88U, do not form oxidation, can improve the tight contact of via hole and conductor circuit and scolding tin salient point by overlay film.In addition, because except scolding tin district 86U, scolder resist 80 is covered with via hole 70 and conductor circuit 72, so this scolder resist 80 is being protected via hole 70 and conductor circuit 72, can improve the bulk strength of substrate.In addition, in the above description, although understand the scolding tin salient point 88U of a top side of multilayer printed-wiring board 400, but also can similarly form the scolding tin salient point 88D of downside.
The manufacturing process of multilayer printed-wiring board shown in Figure 17 then, is described with reference to Figure 18.In addition, (1) in the manufacturing process of the multilayer printed-wiring board of the 4th example～(6) are with identical with reference to first example of Fig. 2, Fig. 3 explanation, (7)～(10) with identical, so omit explanation and diagram with reference to second example of Fig. 8～Figure 10 explanation.
In addition, identical with second example in the manufacture method of the 4th example, shown in the operation among Figure 10 (Q), carry out metallide, so that produce pit 70a at the central portion of the metallide copper 68 at the position that forms via hole 70.On the surface of this upper strata via hole 70 and conductor circuit 72, form rough layer 78 in addition, make module board.Here, as mentioned above, rough layer 78 is vertically formed with respect to the curved surface of the pit 70a of via hole 70 central authorities.
In the 4th example, the ratio that via hole diameter (opening diameter of peristome 62: 67 microns) and outermost layer are heard the thickness (20 microns) of resin insulating barrier 60 is set at 3.35.Here, the ratio of the thickness of via hole diameter and interlayer resin insulating layers is below 1, and in above-mentioned electroplating work procedure, if the degree of depth is dark excessively with respect to the opening diameter of peristome 62, electroplate liquid can not flow in this peristome 62 fully, can not electroplate effectively.On the other hand, if the ratio of via hole diameter and the thickness of interlayer resin insulating layers surpasses 4, the opening diameter of peristome that then forms via hole is excessive with respect to the degree of depth.Therefore, the ratio that preferably makes via hole diameter and the thickness of interlayer resin insulating layers greater than 1 less than 4.
In addition, the thickness of conductor circuit 72 below 20 microns for well, be preferably in below 40 microns.Though this be because the thickness of conductor circuit by the thickness decision of above-mentioned platedresist 66, if the thickness of this platedresist that forms optically above 40 microns, then resolution is low, is difficult to constitute desirable shape.
(11) shown in the operation among Figure 10 of second example (R), form diameter at substrate 30 upper surfaces and be 133 microns scolding tin district 86U, form after diameter is 600 microns scolding tin district 86D, shown in the operation among Figure 18 (S), form the scolding tin salient point at lower surface.Here, to place thickness be 40 microns, have the metal mask 98 that diameter is 160 microns opening 98a, above in the peristome 81 of scolder resist layer 80 on the scolding tin district 86U of a side printing average grain diameter be 20 microns soldering paste, the scolding tin district 86D of a side goes up the printing soldering paste equally below.In the printing process of this soldering paste, because the also printing and the soldering paste of conductor circuit 72 equal numbers on via hole 70, so can make the diameter of the opening 98a of metal mask 98 form equally fully.Therefore, the metal mask 198 of the opening 198a, the 198b that have the multiple diameter that forms multilayer printed wiring board-use of the prior art that illustrates with reference Figure 23 (B) is compared, and can easily form the metal mask 98 of this example.
After the printing of soldering paste, under 200 ℃ temperature, substrate 30 is heated anti-stream, with diameter is that 133 microns scolding tin salient point 88U is arranged on the scolding tin district 86U of a top side, with diameter is that 600 microns scolding tin salient point 88D is arranged on the scolding tin district 86D of a following side, and the formation of scolding tin salient point finishes (with reference to the operation among Figure 18 (T)).After this, clean the surface of multilayer printed-wiring board 400 with surface active material solution, the solder flux that oozes out from soldering paste during with above-mentioned anti-stream rinses out.
With reference to Figure 23 (C), when cleaning solder flux, in the multilayer printed-wiring board 110 of above-mentioned prior art,,, be difficult to fully solder flux be cleaned so the solder flux amount that the scolding tin salient point that forms from via hole 170 flows out is many because a plurality of soldering paste are inserted in the via hole 170.Different therewith, in the multilayer printed-wiring board 400 of this example, because equally also only having printed a spot of soldering paste on the via hole 70 with on the conductor circuit 72, so can solder flux is clean fully.
In addition, when instead flowing under 200 ℃ temperature, very big bending takes place in the multilayer printed-wiring board 510 of prior art, has reduced the installation accuracy of IC chip.Different therewith, crooked little during the anti-stream of the multilayer printed-wiring board of this example 400.Infer that its reason is: the multilayer printed-wiring board 510 of prior art is because via hole 570 is hollow state, so this via hole distortion itself is different therewith, in this example, because via hole 70 has been filled electro-coppering 68, and is indeformable so via hole 70 itself is heated.
At last, IC chip 90 is placed on this multilayer printed-wiring board 400, make the scolding tin district 92 of IC chip 90 corresponding with the scolding tin salient point 88U of multilayer printed-wiring board one side, anti-stream in heating furnace, thus IC chip 90 is installed in (with reference to Figure 18 (U)) on the multilayer printed-wiring board 400.After this, surface active material solution is injected between multilayer printed-wiring board 400 and the IC chip 90, the solder flux that oozes out from soldering paste during with above-mentioned anti-stream is washed off.
When cleaning solder flux, with reference to Figure 23 (D), owing to surfactant solution must be injected the narrow space of the news of multilayer printed-wiring board 400 and IC chip, so in the multilayer printed-wiring board 510 of above-mentioned prior art, the solder flux that is difficult to the scolding tin salient point that will be on via hole 170 forms is clean fully.Different therewith, in the multilayer printed-wiring board 400 of this example, because also all only having printed a spot of soldering paste on the via hole 70, so can solder flux is clean fully with identical on conductor circuit 72.
After this anti-stream operation, resin is injected space between this multilayer printed-wiring board 400 and the IC chip, all with resin-sealed this space with resin covering IC chip 90, carry out resin molded (not shown).After this, the multilayer printed-wiring board of having placed IC chip 90 is installed in (with reference to Figure 18 (U)) on the motherboard 95.
Figure 19 represents the multilayer printed-wiring board 401 of the Change Example of the 4th example of the present invention.In the multilayer printed-wiring board of the 4th example of reference Figure 17 explanation, not only formed the upper strata via hole 70 of scolding tin salient point but also the lower via hole 40 that forms is also filled with electro-coppering on lower interlayer resin insulating layers 40.Different therewith, in the multilayer printed-wiring board of Change Example, lower via hole 50 is the same with the prior art that illustrates with reference to Figure 23, inner potting resin.In addition, on the upper strata of the 4th example via hole 70, form pit 70a in central authorities, different therewith, the surface of the upper strata via hole 70 of Change Example is flat condition.In addition, in the 4th example, as layer of precious metal Gold plated Layer 84 is set at the upper surface of upper strata via hole 70 and conductor circuit 72, different therewith, in Change Example, form and electroplate platinum layer 84.Also the same in this Change Example with the 4th example, can improve the reliability that scolding tin salient point 88U, 88D connect.
As mentioned above, in the multilayer printed-wiring board of the 4th example,, the apparent height of via hole is equated with the height of the conductor circuit that has formed the scolding tin salient point by electronplate is filled in peristome.Therefore, by with the printing with paste of same quantity on via hole and conductor circuit, the height of the scolding tin salient point that forms on the scolding tin salient point that forms on this via hole and the conductor circuit is equated, so can improve the reliability that the scolding tin salient point connects.
In addition, in first to fourth above-mentioned example, though show the module board that utilizes semi-additive process to form for example, structure of the present invention also can be applied to utilize the module board of full additive method formation.In addition, in above-mentioned example, enumerated the example of module board as multilayer printed-wiring board, but self-evident, structure of the present invention also can be applied to the multilayer printed-wiring board beyond the module board.
In addition, in this example,, also can replace electroplating by the filled conductive paste though fill by plating.As the conductivity paste, can use Star electric wire system DD paste (AE16001).

Claims (2)

1. multilayer printed-wiring board, it is alternately overlapped by interlayer resin insulating layers and conductor layer, it is characterized in that:
One deck at least in the above-mentioned conductor layer has conductor fig and the inner plane layer that via hole is arranged that is connected on the via hole,
Be connected via hole on the above-mentioned conductor fig by metal filled, the surface forms smoothly, and the via hole that has in the above-mentioned plane layer is formed pit from the teeth outwards by metal filled.
2. multilayer printed-wiring board according to claim 1 is characterized in that: above-mentioned inside has the surface of the plane layer of via hole to carry out roughened.
CN200610100689A 1997-12-29 1998-12-24 Multilayer printed wiring board Expired - Lifetime CN100584150C (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP369242/1997 1997-12-29
JP369244/1997 1997-12-29
JP369245/1997 1997-12-29
JP36924297 1997-12-29
JP369243/1997 1997-12-29

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109315069A (en) * 2016-07-07 2019-02-05 名幸电子有限公司 Three-dimensional wiring substrate, the manufacturing method of three-dimensional wiring substrate and three-dimensional wiring substrate substrate

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105103245B (en) * 2013-04-04 2019-02-19 罗姆股份有限公司 Compound chip component, circuit unit and electronic equipment
CN105826295B (en) * 2015-01-07 2019-01-29 中芯国际集成电路制造(上海)有限公司 Interconnection structure and forming method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109315069A (en) * 2016-07-07 2019-02-05 名幸电子有限公司 Three-dimensional wiring substrate, the manufacturing method of three-dimensional wiring substrate and three-dimensional wiring substrate substrate
CN109315069B (en) * 2016-07-07 2021-01-08 名幸电子有限公司 Three-dimensional wiring board, method for manufacturing three-dimensional wiring board, and substrate for three-dimensional wiring board

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