CN101017798A - Method of manufacturing a flash memeory device - Google Patents
Method of manufacturing a flash memeory device Download PDFInfo
- Publication number
- CN101017798A CN101017798A CNA2006100988276A CN200610098827A CN101017798A CN 101017798 A CN101017798 A CN 101017798A CN A2006100988276 A CNA2006100988276 A CN A2006100988276A CN 200610098827 A CN200610098827 A CN 200610098827A CN 101017798 A CN101017798 A CN 101017798A
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- Prior art keywords
- etching
- isolation structure
- polysilicon layer
- semiconductor substrate
- isolation
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Links
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 238000005530 etching Methods 0.000 claims abstract description 72
- 238000000034 method Methods 0.000 claims abstract description 36
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 238000007667 floating Methods 0.000 claims abstract description 11
- 239000004020 conductor Substances 0.000 claims abstract description 3
- 239000011810 insulating material Substances 0.000 claims abstract description 3
- 238000002955 isolation Methods 0.000 claims description 67
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 64
- 229920005591 polysilicon Polymers 0.000 claims description 64
- 239000004065 semiconductor Substances 0.000 claims description 23
- 239000007789 gas Substances 0.000 claims description 14
- 229920000642 polymer Polymers 0.000 claims description 8
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 229910052786 argon Inorganic materials 0.000 claims description 3
- 239000003595 mist Substances 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 description 9
- 238000007254 oxidation reaction Methods 0.000 description 9
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 210000004027 cell Anatomy 0.000 description 4
- 238000000059 patterning Methods 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 101100107923 Vitis labrusca AMAT gene Proteins 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 210000000352 storage cell Anatomy 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
Abstract
Provided is a method of forming nonvolatile memory, comprising forming the first and second channels by etching substrate. The first and second channels are filled with insulating material to form the first and second isolating structure. The conducting layer is formed on the top of the first and second isolating structure and between the first and second isolating structure to form floating grid. The etching conducting layer and the first isolating structure forms the third channel with top and bottom. The top has a vertical side wall and the bottom has an inclined side wall. The third channel is filled with the conductive material to form control grid.
Description
Technical field
The manufacture method of relate generally to semiconductor storage unit of the present invention, the manufacture method that more specifically relates to flash memory (flashmemory device), this method relate to by adopting autoregistration shallow trench isolation (SA-STI) method to reduce interference between the NAND flash memory unit.
Background technology
In the NAND flash memory, a plurality of data storage cells are connected in series a string to form.Between unit strings and drain electrode and unit strings and source electrode, form drain electrode respectively and select transistor and drain selection transistor.NAND flash memory unit forms by forming grid, and wherein tunnel oxide film, floating grid, dielectric layer and control grid sequence stack form linkage unit on Semiconductor substrate and in the both sides of this grid.
In the NAND flash memory, location mode is influenced by the operation of adjacent cells.Therefore, holding unit is in stable condition extremely important.When location mode owing to adjacent cells operation (especially procedure operation) when changing, this phenomenon is known as " interference ".More specifically, term " interference " is meant when carrying out second program of first module after being read, because the electric charge of the floating grid of Unit second changes and causes the electric capacity operation when reading first module, causes reading the phenomenon of the threshold voltage that is higher than first module.
In other words, do not change even interference is meant the electric charge of the floating grid of institute's reading unit, the state of actual cell seems because the change of adjacent cells state and the phenomenon of distortion.Location mode is owing to interference changes.This just causes failure rate to increase and yields descends.Therefore, effectively in stable condition the so that interference of holding unit minimizes.
Simultaneously, in the manufacture process of General N AND flash memory, isolation structure and floating grid partly form by the SA-STI method.Below the SA-STI method will be described simply.
After tunnel oxide film and first polysilicon layer are formed on the Semiconductor substrate, the presumptive area of etching tunnel oxide film and first polysilicon layer.Semiconductor substrate is etched to desired depth, forms raceway groove.In raceway groove, fill insulating barrier, and carry out polishing process to form isolation structure.
On total, form second polysilicon layer.With second polysilicon layer patternization, itself and isolation structure are partly overlapped, so just form the floating grid of wherein stacked first and second polysilicon layers.In order to remove the etch residue of second polysilicon layer fully, over etching second polysilicon layer.Thereby isolation structure is etched to desired depth.Therefore, be necessary to carry out abundant over etching so that remove the etch residue of second polysilicon layer fully.The amount of removing of isolation structure is about 100 .After dielectric layer is formed on the total, be formed for controlling the 3rd polysilicon layer of grid.
If utilize above-mentioned SA-STI method to make flash memory, then between as first polysilicon layer of floating grid and adjacent first polysilicon layer, form isolation structure.Therefore, interference may appear between first polysilicon layer.
In addition, because the etching isolation structure is to desired depth, thereby the Semiconductor substrate of active region and the distance of controlling between the grid are narrowed down.Therefore, because the influence of the controlled grid of Semiconductor substrate makes that circulation may take place lost efficacy.
Summary of the invention
An embodiment of the present invention provides a kind of method of making flash memory, and purpose is that the interference between first polysilicon layer that takes place when making the over etching isolation structure minimizes when carrying out the SA-STI process.
Another embodiment of the present invention provides a kind of method of making flash memory, thereby purpose is to prevent the circulation inefficacy that makes the distance between the control grid of Semiconductor substrate and active region narrow down and produce owing to over etching isolation structure when carrying out the SA-STI process.
According to an embodiment of the present invention, the manufacture method of flash memory may further comprise the steps: (a) the presumptive area place on Semiconductor substrate forms the tunnel oxide film and first polysilicon layer in proper order, and the presumptive area place on Semiconductor substrate forms isolation structure; (b) above first polysilicon layer and isolation structure, form second polysilicon layer, and make second polysilicon layer patternization, make second polysilicon layer and isolation structure partly overlap, thus the partial etching isolation structure; (c) under the condition that produces polymer, isolation structure is etched to desired depth; (d) above the isolation structure and second polysilicon layer, form dielectric layer and the 3rd polysilicon layer, and make dielectric layer and the 3rd polysilicon layer patternization.
Step (c) can utilize the oxidation film etching chamber to carry out, and condition is that the etch rate of second polysilicon layer is low, but the etch rate height of isolation structure.
In step (c), isolation structure can be etched to V-arrangement.
Step (c) can be used CF
4, CHF
3, CF
8And CH
2F
2Mist carry out.
In addition, step (c) can be by introducing the CF of the about 200sccm of about 50-in the oxidation film etching chamber
4, the about 200sccm of about 20-CHF
3, the about 30sccm of about 5-CF
8CH with the about 50sccm of about 10-
2F
2, and then introduce about 100sccm or argon still less (Ar) gas, and apply about 200W or lower bias voltage and carry out.
Execution in step (c) makes isolation structure be etched to the height identical with the semiconductor substrate surface height.
According to an embodiment of the present invention, the manufacture method of flash memory comprises: the presumptive area on Semiconductor substrate forms the tunnel oxide film and first polysilicon layer in proper order, and the presumptive area on Semiconductor substrate forms isolation structure; On total, form second polysilicon layer, thereby and second polysilicon layer patternization is partly overlapped at indoor second polysilicon layer and the isolation structure of making of etching polysilicon, partial etching isolation structure thus; Producing under the condition of polymer, is the V-arrangement of desired depth with the isolation structure etching in the oxidation film etching chamber; With formation dielectric layer and the 3rd polysilicon layer on total, and make dielectric layer and the 3rd polysilicon layer patternization.
According to another embodiment, a kind of method that forms nonvolatile semiconductor memory member comprises that etched substrate is to form first and second raceway grooves.First and second raceway grooves are filled with insulating material to form first and second layers of isolation structure.Forming conductive layer above first and second isolation structures and between first and second isolation structures, to form floating grid.The etching conductive layer and first isolation structure have the triple channel of upper and lower with formation, and described top has vertical sidewall, and described bottom has sloped sidewall.Triple channel is filled with electric conducting material to form the control grid.
Triple channel utilizes first and second etch step and forms, and wherein first etch step is used to form the top of triple channel, and second etch step is used to form the bottom of triple channel.Second etch step is used the etching gas that produces polymer in etching process.The etching gas of second etch step comprises CF
4, CHF
3, CF
8Or CH
2F
2The etching gas of second etch step comprises and is selected from CF
4, CHF
3, CF
8And CH
2F
2Combination.
Description of drawings
Figure 1A-1C illustrates the sectional view of flash memory manufacture method according to embodiments of the present invention.
Embodiment
Figure 1A-1C illustrates the sectional view of flash memory manufacture method according to embodiments of the present invention.
With reference to Figure 1A, tunnel oxide film 12 and first polysilicon layer, 13 orders are formed on the Semiconductor substrate 11.On first polysilicon layer 13, form the hard mask film (not shown).This hard mask film (not shown) is patterning by the photoetching method that adopts isolation mask.The hard mask film (not shown) that utilizes this patterning is as mask, and etching first polysilicon layer 13, tunnel oxide film 12 and Semiconductor substrate 11 are to desired depth, thus the formation raceway groove.
Form the insulating barrier of filling raceway groove, thereby then its polishing is exposed described hard mask film (not shown).Divest this hard mask film (not shown) and form isolation structure 14.On total, form second polysilicon layer 15.On second polysilicon layer 15, form photoresist film 16.Utilize mask with this photoresist film patternization, so that itself and isolation structure 14 parts overlap.
With reference to Figure 1B, after divesting photoresist film 16, the etched portions isolation structure 14 once more.In this implementation, this etch step is carried out in second etching chamber.Second etching chamber that is used for etched portions isolation structure 14 can be oxidation film etching chamber (for example, available from the e-MAX device of AMAT or available from the SCCM device of TEL).If isolation structure 14 carries out etching in the oxidation film chamber of for example e-MAX or SCCM equipment, then the etch rate of oxidation film can improve, but the etch rate of polysilicon layer descends.
In some embodiments, etching isolation structure 14 makes the bottom 22 of raceway groove 20 have angled side walls.The width of the bottom 22 of raceway groove 20 reduces along with the increase of the degree of depth.For example, the bottom after the etching 22 is similar to V-arrangement (Figure 1B).
Use produces polymer in etching process etching gas comes etching top 22.In this implementation, use CF
4, CHF
3, CF
8And CH
2F
2Mist.In other implementation, can adopt the combination of above-mentioned gas and/or other gas.If isolation structure 14 uses described gas to carry out etching, then cause the presumptive area of isolation structure 14 forming V-shape that can be etched owing to produce polymer.Below will describe the condition of described gas of using in detail with the presumptive area etching forming V-shape of isolation structure 14.
Etching process is by introducing the CF of the about 200sccm of about 50sccm-in such as the oxidation film etching chamber of SCCM device
4, the about 200sccm of about 20sccm-CHF
3, the about 30sccm of about 5sccm-CF
8CH with the about 50sccm of about 10sccm-
2F
2, and then introduce about 100sccm or argon still less (Ar) gas, and apply about 200W or lower bias voltage and carry out.The degree of depth that is etched into the isolation structure 14 of above-mentioned V-arrangement can have the height identical with the apparent height of Semiconductor substrate 11 (for example, about 500 of about 100-).
Simultaneously, to use the oxidation film etching chambers to carry out the cause description of etching as follows for isolation structure 14.If utilize the photoresist film 16 that remains on second polysilicon layer 15 to come over etching second polysilicon layer 15, then isolation structure 14 can be etched to about 100 or littler thickness.Yet, owing to do not have the nargin of photoresist film 16, so isolation structure 14 can not be etched to about 100 or the bigger degree of depth.
With reference to figure 1C, after dielectric layer 17 is formed on the total, be formed for controlling the 3rd polysilicon layer 18 of grid.Therefore the forming V-shape because the predetermined portions of isolation structure 14 is etched forms dielectric layer 17 and the 3rd polysilicon layer 18 at this part place.Afterwards, the 3rd polysilicon layer 18 comes etching by the photoetching process that adopts the control gate mask.Etching lower floor is to form the grid of wherein stacked floating grid and control grid subsequently.
As mentioned above, according to the present invention, utilized the oxidation film etching chamber to carry out the strange land etching by the isolation structure of partial etching during the etching second polysilicon layer etching, so that it has V-arrangement.Form dielectric layer and the 3rd polysilicon layer at this V-arrangement etched portions place.
Therefore, can reduce interference between first polysilicon layer.The threshold voltage that is distributed between the unit can improve by minimizing of interference.In addition, because the distance between Semiconductor substrate and the control grid increases, make the circulation threshold voltage to improve.
Though the present invention is described in conjunction with the embodiment that is regarded as embodiment at present, should be appreciated that to the invention is not restricted to disclosed embodiment.On the contrary, the invention is intended to cover various changes and equivalent arrangements within the spirit and scope that are included in claims.
Claims (14)
1. method of making flash memory comprises:
Presumptive area place on Semiconductor substrate forms the tunnel oxide film and first polysilicon layer in proper order, and the presumptive area place on Semiconductor substrate forms isolation structure;
Form second polysilicon layer above first polysilicon layer and isolation structure, and make second polysilicon layer patternization, make second polysilicon layer and isolation structure partly overlap, wherein said isolation structure is by partial etching;
Under the condition that produces polymer, the etching isolation structure is to desired depth; With
Above the isolation structure and second polysilicon layer, form dielectric layer and the 3rd polysilicon layer, and make described dielectric layer and the 3rd polysilicon layer patternization.
2. as the desired method of claim 1, wherein the step of etching isolation structure utilizes etching chamber to carry out.Described etching chamber is designed at the etch rate of second polysilicon layer low, and etching oxide under the high condition of the etch rate of isolation structure.
3. as the desired method of claim 1, wherein in the step of etching isolation structure, the isolation structure forming V-shape that is etched.
4. as the desired method of claim 1, wherein step (c) utilization comprises CF
4, CHF
3, CF
8And CH
2F
2Mist carry out.
5. as the desired method of claim 1, wherein the step of etching isolation structure is by introducing the CF of the about 200sccm of about 50-in the oxide-film etching chamber
4, the about 200sccm of about 20-CHF
3, the about 30sccm of about 5-CF
8CH with the about 50sccm of about 10-
2F
2, and then introduce about 100sccm or argon still less (Ar) gas, and apply about 200W or lower bias voltage and carry out.
6. as the desired method of claim 1, wherein carry out the step of etching isolation structure, make isolation structure be etched to and have the height identical with the semiconductor substrate surface height.
7. method of making flash memory comprises:
Presumptive area place on Semiconductor substrate forms the tunnel oxide film and first polysilicon layer in proper order, and the presumptive area place on Semiconductor substrate forms isolation structure;
On total, form second polysilicon layer, thereby and second polysilicon layer patternization is partly overlapped at indoor second polysilicon layer and the isolation structure of making of etching polysilicon, partial etching isolation structure thus;
Producing under the condition of polymer, is the V-arrangement of desired depth with the isolation structure etching in the oxide-film etching chamber; With
On overall structure, form dielectric layer and the 3rd polysilicon layer, and make described dielectric layer and the 3rd polysilicon layer patternization.
8. as the desired method of claim 7, wherein when etching second polysilicon layer, utilized the oxide-film etching chamber to carry out the strange land etching by the isolation structure of partial etching, to form the V-arrangement etched portions.
9. method that forms nonvolatile semiconductor memory member comprises:
Etched substrate is to form first and second raceway grooves;
With filling insulating material first and second raceway grooves, to form first and second isolation structures;
Forming conductive layer above first and second isolation structures and between first and second isolation structures, to form floating grid;
The etching conductive layer and first isolation structure have the triple channel of upper and lower with formation, and described top has vertical sidewall, and described bottom has sloped sidewall; With
Fill triple channel with electric conducting material, to form the control grid.
10. the method for claim 9, wherein said triple channel adopt first and second etch step to form.
11. the method for claim 10, wherein first etch step is used to form the top of triple channel, and second etch step is used to form the bottom of triple channel.
12. the method for claim 11, wherein second etch step adopts the etching gas that produces polymer in etching process.
13. the method for claim 12, wherein the etching gas of second etch step comprises CF
4, CHF
3, CF
8Or CH
2F
2
14. the method for claim 13, wherein the etching gas of second etch step comprises and is selected from CF
4, CHF
3, CF
8And CH
2F
2Combination.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020060011551 | 2006-02-07 | ||
| KR1020060011549 | 2006-02-07 | ||
| KR1020060011549A KR100854875B1 (en) | 2006-02-07 | 2006-02-07 | Method of manufacturing a flash memeory device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101017798A true CN101017798A (en) | 2007-08-15 |
| CN100552922C CN100552922C (en) | 2009-10-21 |
Family
ID=38600729
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006100988276A Expired - Fee Related CN100552922C (en) | 2006-02-07 | 2006-07-13 | The manufacture method of flash memory |
Country Status (2)
| Country | Link |
|---|---|
| KR (1) | KR100854875B1 (en) |
| CN (1) | CN100552922C (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101894804A (en) * | 2009-05-21 | 2010-11-24 | 海力士半导体有限公司 | Method of manufacturing nonvolatile memory device |
| CN102768979A (en) * | 2011-05-04 | 2012-11-07 | 海力士半导体有限公司 | Method for fabricating nonvolatile memory device |
| CN104952806A (en) * | 2014-03-26 | 2015-09-30 | 华邦电子股份有限公司 | Memory element and method for manufacturing the same |
| CN107623002A (en) * | 2016-07-13 | 2018-01-23 | 新加坡商格罗方德半导体私人有限公司 | Integrated circuit and its manufacture method with programmable storage |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101034950B1 (en) * | 2007-09-10 | 2011-05-17 | 주식회사 하이닉스반도체 | Method of fabricating the trench isolation layer for semiconductor device |
| KR100960449B1 (en) * | 2008-01-10 | 2010-05-28 | 주식회사 하이닉스반도체 | Method of forming an isolation layer in semiconductor device |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11163304A (en) | 1997-11-28 | 1999-06-18 | Toshiba Corp | Nonvolatile semiconductor storage device and manufacture thereof |
| KR100297736B1 (en) * | 1999-08-13 | 2001-11-01 | 윤종용 | Trench isolation method |
| KR100537276B1 (en) * | 2002-11-18 | 2005-12-19 | 주식회사 하이닉스반도체 | Method of manufacturing a semiconductor device |
| KR20040054146A (en) * | 2002-12-17 | 2004-06-25 | 주식회사 하이닉스반도체 | Method for forming a tunnel oxide and method for forming floating gate in flash memory device using the same |
-
2006
- 2006-02-07 KR KR1020060011549A patent/KR100854875B1/en not_active IP Right Cessation
- 2006-07-13 CN CNB2006100988276A patent/CN100552922C/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101894804A (en) * | 2009-05-21 | 2010-11-24 | 海力士半导体有限公司 | Method of manufacturing nonvolatile memory device |
| CN102768979A (en) * | 2011-05-04 | 2012-11-07 | 海力士半导体有限公司 | Method for fabricating nonvolatile memory device |
| CN102768979B (en) * | 2011-05-04 | 2016-04-20 | 海力士半导体有限公司 | Manufacture the method for nonvolatile semiconductor memory member |
| CN104952806A (en) * | 2014-03-26 | 2015-09-30 | 华邦电子股份有限公司 | Memory element and method for manufacturing the same |
| CN104952806B (en) * | 2014-03-26 | 2018-01-05 | 华邦电子股份有限公司 | Memory element and method for manufacturing the same |
| CN107623002A (en) * | 2016-07-13 | 2018-01-23 | 新加坡商格罗方德半导体私人有限公司 | Integrated circuit and its manufacture method with programmable storage |
| CN107623002B (en) * | 2016-07-13 | 2019-06-11 | 新加坡商格罗方德半导体私人有限公司 | Integrated circuit and its manufacturing method with programmable storage |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20070080333A (en) | 2007-08-10 |
| KR100854875B1 (en) | 2008-08-28 |
| CN100552922C (en) | 2009-10-21 |
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Granted publication date: 20091021 Termination date: 20130713 |