CN101013235A - Optoelectronic device, element driving device and electronic equipment - Google Patents

Abstract

An electro-optic device comprises a plurality of electronic components; a plurality of IC chips used for driving a plurality of circuits of the electronic components; a control circuit for choosing respectively more than one unit circuit for driving the electronic components and meanwhile carrying out the driving operation; and a choosing circuit for choosing respectively more than one IC chip and meanwhile making the control circuit which has chosen the IC chip carry out the choosing and controlling.

Description

Electro-optical device, cell driving device and electronic equipment

The application is that application number is " 03801726.1 ", and denomination of invention is " electro-optical device and manufacture method thereof, cell driving device and manufacture method thereof, device substrate and an electronic equipment ", and the applying date is the dividing an application of application on May 29th, 2003.

Technical field

The present invention relates to be used to drive cell driving device and its manufacture method of a plurality of driven elements, particularly electrooptic element is used as electro-optical device and its manufacture method of driven element, this electrooptic element is used for electro ultrafiltration is transformed into light action.The present invention relates to be applicable to the device substrate of cell driving device and electro-optical device, and the electronic equipment that comprises this electro-optical device and cell driving device.

Background technology

As the display device of pocket telephone and PDA various electronic equipments such as (personal digital assistants), proposed to utilize the electrooptic element that electro ultrafiltration is transformed into light action.The exemplary of this display device is to adopt the organic EL display of organic EL and liquid crystal is used as the liquid crystal indicator of electrooptic element as electrooptic element.

These display device comprise constituting the pixel circuit of each pixel that shows least unit.This pixel circuit is to be used to control the electric current that offers electrooptic element or the circuit of voltage.Each pixel circuit is included in the driving element that forms on the silicon substrate, as disclosed in patent documentation 1 (spy opens 0013 and 0014 section of flat 9-146477 communique).

In order to improve the demonstration grade of this display device, the electrical characteristics of wishing pixel circuit are uniform in whole pixel.But low temperature polycrystalline silicon occurs in the unordered difference on the characteristic easily when recrystallization, and the situation that crystal defect takes place is also arranged.Therefore, in the display device of using the thin film transistor (TFT) that is made of low temperature polycrystalline silicon, the electrical characteristics that make pixel circuit evenly are extremely difficult in whole pixel.Particularly, owing to the possibility that the height for display image becomes more meticulous and big picture increases number of pixels and produces the unordered difference of each pixel circuit on characteristic becomes higher, show that the problem that grade descends becomes more remarkable.

Summary of the invention

The present invention proposes in view of the above problems, its objective is at the circuit that is used for driving such as the driven element of electrooptic element, suppresses the unordered difference of active component on characteristic, improves the performance and the function of sort circuit and improves integrated level.

In order to address the above problem, electro-optical device of the present invention has: element layer, and it comprises a plurality of electrooptic elements; The electronic unit layer, it comprises the element drives IC chip with a plurality of unit circuits that are used to drive electrooptic element; With the wiring cambium layer, it comprises in the wiring that contained constituent parts circuit is connected with electrooptic element corresponding to this unit circuit in the IC chip of described element drives between described element layer and described electronic unit layer.

In this structure, be used to drive a plurality of unit circuits of electrooptic element as the IC chip configuration.The contained active component of IC chip is compared with the thin film transistor (TFT) that is made of low temperature polycrystalline silicon etc., and the unordered difference on its characteristic is few.Therefore, even for the height of display image becomes more meticulous and big picture and increased number of pixels, the characteristic that also can suppress to be used to drive the unit circuit of electrooptic element produces the possibility of unordered difference, has improved the yield rate of electro-optical device thus.And, compare with the thin film transistor (TFT) that constitutes by low temperature polycrystalline silicon etc., owing to, therefore can reduce the power consumption of electro-optical device with the contained active component of low voltage drive IC chip.

Electrooptic element of the present invention will provide electric current and the electro ultrafiltration that applies voltage to be transformed into the light action of brightness and transmitance variation, perhaps light action will be transformed into electro ultrafiltration.The exemplary of this electrooptic element is organic EL luminous according to the electric current of supplying with from unit circuit and in brightness and the liquid crystal that makes orientation (being the transmitance of light) variation according to the voltage that is applied by unit circuit.But the present invention also is applicable to the device of use electrooptic element in addition.

In optimal way, each of a plurality of electrooptic elements is configured on the planar different positions.For example, a plurality of electrooptic elements are configured to the matrix state at line direction and column direction.

In more preferably mode, the electronic unit layer has a plurality of element drives IC chip that comprises a plurality of unit circuits respectively; The wiring cambium layer has the wiring that each electrooptic element corresponding with this unit circuit at each element drives contained unit circuit in the IC chip is connected.

In more preferably mode, the electronic unit layer comprises the selection IC chip of IC chip that is used for selecting to carry out with the IC chip in a plurality of element drives the driving of electrooptic element; Select to be connected with the IC chip with each element drives through contained wiring in the wiring cambium layer with the IC chip.Therefore, be used to select element drives to compare with the structure that forms by thin film transistor (TFT), sought to be used to select the operating stably of element drives with the IC chip with the circuit of IC chip.Therefore, when the yield rate of electro-optical device improves, reduced power consumption.

In another way, the electronic unit layer comprises data supply IC chip, and it is used for indicating data-signal of electric current that should provide electrooptic element or the voltage that should apply to output to the unit circuit of each element drives with the IC chip; Data are supplied with the IC chip through being connected with the IC chip with each element drives in the contained wiring of wiring cambium layer.Constitute according to this, the circuit that data-signal is outputed to unit circuit is compared with the structure that is formed by thin film transistor (TFT), has also sought to be used for data-signal is offered action stability and the high speed of element drives with the IC chip.Therefore, when the yield rate of electro-optical device improves, reduced power consumption.

Further in another way, the electronic unit layer comprises: select to use the IC chip, it is used for should carrying out with the selection of IC chip in a plurality of element drives the IC chip of the driving of electrooptic element; Data are supplied with and use the IC chip, and its data-signal that is used for should providing electric current with indication to each electrooptic element or should applies voltage outputs to the unit circuit of each element drives usefulness IC chip; With control IC chip, it is used to control selects to supply with the action of using the IC chip with IC chip and data; Select to be connected with the IC chip with each element drives in the contained wiring of cambium layer of connecting up with IC chip process with IC chip and data supply, control is supplied with IC chip and data with selection in the contained wiring of the cambium layer that connects up with IC chip process and is connected with the IC chip.According to this structure, also can when improving the electro-optical device yield rate, reduce power consumption.

In optimal way of the present invention, a plurality of element drives each of IC chip is configured on the position relative with a plurality of electrooptic elements of using the contained a plurality of unit circuits of IC chip corresponding to this element drives.According to this structure,, for example,, can obtain arranging the driving of the different electrooptic element of pitch (pitch) by using element drives of the same race IC chip owing to can use the form of the irrelevant selected electrooptic element of allocation position of IC chip with element drives.

In optimal way, relevant electro-optical device of the present invention has light shield layer, observes with the IC chip from a plurality of element drives, and it is set at an opposite side with the cambium layer that connects up, and is used for shield light.According to this form, the light from the observation of electronic unit layer from the cambial opposition side incident of distribution is interdicted by light shield layer.Therefore, can prevent the element drives that causes because of the rayed misoperation of IC chip.

In another optimal way, relevant electro-optical device of the present invention has the packed layer that is filled between each element drives usefulness IC chip.According to this structure, be flattened by packed layer with the relative face of wiring cambium layer in the electronic unit layer or strengthened.Therefore, the broken string and the short circuit of contained wiring in the cambium layer that prevents to connect up, and form wiring with superperformance by simple procedures.In more preferably mode, packed layer is by forming with the close material of the thermal expansivity of IC chip with element drives.According to this mode, suppressed because of the generation of element drives with the different thermal stress that cause of the thermal expansivity of IC chip and packed layer.And packed layer is to be formed by the strong material of thermal diffusivity.According to this mode,, suppressed the up-set condition that causes because of heat owing to improved the thermal uniformity of whole electro-optical device.

Element drives has first splicing ear and second splicing ear with the IC chip, use in the IC chip in this element drives, this first splicing ear is set on the terminal formation face relative with the cambium layer that connects up and is connected to electrooptic element, and second splicing ear is set on the terminal formation face and is connected to power lead; Under this mode, in first splicing ear with area that terminal forms the parallel face of face be in second splicing ear with terminal form the parallel face of face area 1/6 or below.According to this mode, check the action of element drives with the IC chip by probe being contacted second splicing ear.On the other hand,, compare with whole splicing ear being assumed to be, reduced element drives forms face with the terminal of IC chip area with the situation of the identical size of first splicing ear because first splicing ear is below 1/6 of area of second splicing ear.Therefore, in an electro-optical device, obtain the more element drives of configuration IC chip.Particularly, the flat shape of second splicing ear for long and wide be the rectangle of 100 μ m～70 μ m sizes, the flat shape of first splicing ear for grow and wide be the rectangle of 30 μ m～10 μ m sizes.In more preferably mode, be made as more than 1/50 of area that forms the parallel face of face in second splicing ear with terminal with area that terminal forms the parallel face of face in first splicing ear.

Relevant electronic equipment of the present invention comprises the electro-optical device of above-mentioned each mode.In this electronic equipment, suppressed to be used to drive the unordered difference of unit circuit on characteristic of electrooptic element.Particularly, electro-optical device is being used as in the electronic equipment of display device, display quality is maintained at very high level.

As preferably, electronic equipment comprises: first display part with light emitting-type electro-optical device; With second display part with non-light emitting-type electro-optical device.Wherein the light emitting-type electro-optical device has himself luminous electrooptic element.The exemplary of light emitting-type electro-optical device is the organic EL display that luminous organic EL according to supplying electric current and in brightness is used as electrooptic element.On the other hand, non-light emitting-type electro-optical device has himself non-luminous electrooptic element.The exemplary of non-light emitting-type electro-optical device is with according to applying the liquid crystal indicator that liquid crystal that voltage changes transmitance is used as electrooptic element.In this electronic equipment, show from offering image after the light of light emitting-type electro-optical device outgoing arrives non-light emitting-type electro-optical device.Therefore.There is no need to be provided with in addition lighting device guarantees to produce the visuality that shows by non-light emitting-type electro-optical device.Perhaps, even lighting device is set, the outgoing light quantity by this lighting device also can reduce.In the optimal way of this electronic equipment, for the display surface that makes each electro-optical device constitutes the posture of special angle, first display part is connected in mutual removable mode with second display part.According to this mode,, adjust the relative position relation between first display part and second display part in order to make luminous second display part that arrives effectively of first display part.

The device that is suitable for invention is not limited to the electro-optical device that comprises electrooptic element.That is, the present invention is applicable in the various devices that comprise a plurality of driven elements.Cell driving device of the present invention has: element layer, and it comprises a plurality of driven elements; The electronic unit layer, it comprises the IC chip of the element drives with a plurality of unit circuits that driven element is driven; With the wiring cambium layer, it comprises the wiring that element drives is connected with driven element corresponding to this unit circuit with constituent parts circuit contained on the IC chip between element layer and electronic unit layer.By this cell driving device, also can obtain the effect same with electro-optical device of the present invention.

The present invention is also specific for the used substrate of cell driving device.That is, device substrate of the present invention comprises: the electronic unit layer, and it comprises a plurality of electronic units with the terminal formation face that is formed with splicing ear; With the wiring cambium layer, its be laminated into the electronic unit layer in terminal to form face relative, and have a plurality of wirings that are connected with the splicing ear of each electronic unit; A plurality of electronic units are configured to make each terminal formation face to be positioned at approximately identical face.According to this structure, identical face disposes each electronic unit owing to be positioned at approximately according to the terminal formation face that makes a plurality of electronic units, can unify to form with the wiring that is connected on the splicing ear of each electronic unit.

Relevant electro-optical device of the present invention can obtain by following first to the 3rd manufacture method.

Promptly, first manufacture method has: the element drives that will have a plurality of unit circuits that are used to drive electrooptic element becomes to make the terminal with splicing ear to form face towards a side with the IC chip configuration, and forms and comprise the operation of this element drives with the electronic unit layer of IC chip; In the electronic unit layer element drives with the splicing ear institute of IC chip towards face on form the cambial operation of wiring, this wiring cambium layer comprises the wiring that the constituent parts circuit that element drives usefulness IC chip is contained is connected with electrooptic element corresponding to this unit circuit; With the operation that comprises the element layer of a plurality of electrooptic elements in the opposite side formation of the electronic unit layer of observing from the wiring cambium layer.According to by the electro-optical device that this method obtained, can suppress to be used for driving the unordered difference of unit circuit on characteristic of electrooptic element.

Second manufacture method has: on the one side of substrate, dispose element drives IC chip so that have the state that it is right that the terminal of splicing ear forms face and real estate, and formation comprises the operation of the electronic unit layer of this element drives usefulness IC chip with a plurality of unit circuits that drive electro-optical device; Peel off the operation of substrate from the electronic unit layer; On the face that substrate in the electronic unit layer is stripped from, form the cambial operation of wiring, this wiring cambium layer comprises and is used for the wiring that the constituent parts circuit that element drives usefulness IC chip is contained is connected with electrooptic element corresponding to this unit circuit; With the operation that comprises the element layer of a plurality of electrooptic elements in the opposite side formation of the electronic unit layer of observing from the wiring cambium layer.

According to this manufacture method, element drives is made in in the one side by substrate with the terminal formation face of IC chip.In other words, should be flattened by the face relative in the electronic unit layer with wiring formation face.Therefore, the cambial formation of connecting up becomes easily, has effectively prevented the broken string and the short circuit of wiring.For example, the homogeneity that constitutes the thickness of the cambial wiring layer of wiring has improved, and the error relevant with the shape of these wiring layers reduced.Thus, the yield rate of electro-optical device has improved.And, since element drives with the IC chip so that terminal forms the state configuration of the relative substrate of face, this has been avoided the damage of splicing ear in operation after this.

In the optimal way of second manufacture method, on the one side that is implemented in substrate before the operation that forms the electronic unit layer, form the operation of peel ply; In the operation that forms the electronic unit layer, at the opposite side formation electronic unit layer of the substrate of observing from peel ply; In peeling off the operation of substrate, be that substrate is peeled off from the electronic unit layer by the boundary on the other hand with the peel ply.According to this mode, make substrate be stripped from easily by getting involved peel ply.

In more preferably mode, peel off energy and peel off substrate by peel ply is provided.Particularly, peel off energy by providing to peel ply such as the electromagnetic wave irradiation of light and electromagnetic induction etc.According to this mode, owing to reliably being provided again in short time, peel ply peels off energy, and the throughput rate and the yield rate of electro-optical device have improved.As the substrate that has formed peel ply, see through the material of peeling off energy if use, then peel off energy and can offer peel ply through substrate.

In the optimal way of second manufacture method, on the one side that is implemented in substrate before the operation that forms the electronic unit layer, form the operation of tack coat; In the operation that forms the electronic unit layer, element drives is glued to tack coat with the terminal formation face of IC chip.According to this mode, impulsive force and the stress to substrate the time has been relaxed by tack coat because element drives is with the IC chip configuration, has prevented that element drives is bad with generation on the IC chip in the manufacture process of electro-optical device.

Under this mode, when removing tack coat before the wiring cambium layer forms when, tack coat wishes by gas and liquid that element drives is not exerted an influence with the splicing ear of IC chip or passes through the removable material of light to form.If like this, element drives makes splicing ear and the cambial wiring of wiring conducting reliably with the damage of IC chip splicing ear in the manufacture process owing to having avoided.

But, in alternate manner, tack coat do not remove and be used as the wiring cambial substrate.That is, in this mode, tack coat forms by insulating material, on the other hand, in forming the cambial operation of wiring, formation wiring cambium layer on the tack coat of overlay electronic component layer.Under the independent situation that forms insulation course between each IC chip of electronic unit layer and cambial each wiring of wiring,, worry that therefore the cambial flatness of wiring is damaged because each IC chip sinks to insulation course or found cementing agent near the IC chip.According to this mode,, solved this problem owing on the tack coat of overlay electronic component layer, formed the wiring cambium layer.And, owing to omitted the connect up operation of cambial insulation course of independent formation, realized the simplification of manufacturing process and the reduction of manufacturing cost.

The 3rd manufacture method has: the one side that will be used for the electrode that electrooptic element provides electric current or applies voltage is formed on substrate, and forming the cambial operation of wiring, this wiring cambium layer comprises each wiring that is connected that is used for this electrode and a plurality of unit circuits; Form the operation of electronic unit layer in an opposite side of the substrate of observing from the wiring cambium layer, this electronic unit layer comprises the element drives IC chip with a plurality of unit circuits that drive electrooptic element; Peel off the operation of substrate from the wiring cambium layer; Form electrooptic element that contacts with electrode and the operation that forms the element layer that comprises a plurality of electrooptic elements with an opposite side at the electronic unit layer of observing from the wiring cambium layer.

In this manufacture method, because electrode is formed on the substrate, electrode surface is smooth, the influence of do not connected up cambium layer and electronic unit layer.Therefore, it is homogenized to be configured to contact the characteristic of electrooptic element of this electrode.

In the optimal way of the 3rd manufacture method, on the one side that is implemented in substrate before the operation that forms the electronic unit layer, form the operation of peel ply; In forming the cambial operation of wiring, at the opposite side formation wiring cambium layer of the substrate of observing from peel ply; In peeling off the operation of substrate, be that substrate is peeled off from the wiring cambium layer by the boundary on the other hand with the peel ply.According to this mode, by getting involved peel ply, can be reliably and easily peel off substrate.

In the optimal way of the second or the 3rd manufacture method, before peeling off substrate, implement support substrate is fixed on operation on the opposite side of the substrate of observing from the electronic unit layer.According to this mode, because the electronic unit layer is by the support substrate support, it is easy that the processing in the manufacture process becomes.

In another optimal way of the second or the 3rd manufacture method, in forming the cambial operation of wiring, be formed for connecting the wiring of unit circuit and electrooptic element, form to cover this wiring and with the insulation course of a part of corresponding opening of this wiring, form electrode part at the opening part of this insulation course; In the operation that forms the electronic unit layer, the projected electrode that will be provided with on the splicing ear of element drives with the IC chip is bonded to electrode part on the other hand.According to this mode, with element drives with the IC chip configuration operation to the wiring cambium layer in, splicing ear and wiring are with reliably and easily conducting.

In the optimal way of above-mentioned first to the 3rd manufacture method, form the operation of electronic unit layer, comprise a plurality of element drives that configuration comprises a plurality of unit circuits respectively with the operation of IC chips with between each element drives is with IC chip, form the operation of packed layer.According to this mode, because each element drives is fixed by packed layer with the IC chip, in the operation of configuration element drives,, can prevent that also the IC chip from departing from the position of expectation even the IC chip is not soldered (bonding) and just be configured to simply on the substrate with the IC chip.Therefore, the configuration of each IC chip can be finished in the extremely short time.And, preferably at that time in, packed layer is formed by thermal expansivity and each IC chip approximate material or the strong material of thermal diffusivity.

In another way, form the operation of electronic unit layer, be included in the operation of a plurality of element drives with formation basalis between IC chip and the packed layer.According to this mode owing between each IC chip and packed layer, got involved basalis, even on the electronic unit layer, produce stress because of packed layer distortion etc. causes, also can by basalis slow down because of this stress cause crooked.Therefore, on not crooked tabular surface, form the wiring cambium layer.And, being provided with by conductive material as described later under the situation of light shield layer, basalis is born the effect of electrical isolation wiring cambium layer and light shield layer.

Further, in another way, form the operation of electronic unit layer, be included in from the electronic unit layer and observe the operation that forms the light shield layer of blocking light with the opposite side of wiring cambium layer.According to this mode, interdicted to come since the cambial opposition side of wiring of electronic unit layer observation or the light towards each IC chip of side by light shield layer.Therefore, prevented the element drives that causes because of the rayed misoperation of IC chip.In optimal way, light shield layer is formed by the material with electric conductivity.According to this mode, light shield layer can be used as ground wire and uses.Therefore, having reduced the brightness that causes because of source impedance effectively descends and crosstalks.And, according to the form that forms light shield layer by the high-cooling property material, can suppress the unordered difference of electrooptic element on characteristic that the heating because of electrooptic element causes.

In the optimal way of above-mentioned first to the 3rd manufacture method, in the operation that forms the electronic unit layer, use the IC chip configuration on position that should be relative with a plurality of electrooptic elements a plurality of element drives that comprise a plurality of unit circuits respectively, these a plurality of electrooptic elements are corresponding with the contained a plurality of unit circuits of IC chip with each element drives.

Above-mentioned first to the 3rd manufacture method is applicable to the cell driving device that comprises a plurality of driven elements too.

Promptly, be used to obtain first manufacture method of cell driving device, have: the element drives that will have a plurality of unit circuits that are used to drive driven element becomes to make the terminal with splicing ear to form face towards a side with the IC chip configuration, and forms and comprise the operation of this element drives with the electronic unit layer of IC chip; In the electronic unit layer element drives with the splicing ear institute of IC chip towards face on form the cambial operation of wiring, this wiring cambium layer comprises the wiring that the constituent parts circuit that element drives usefulness IC chip is contained is connected with driven element corresponding to this unit circuit; With the operation that comprises the element layer of a plurality of driven elements in the opposite side formation of the electronic unit layer of observing from the wiring cambium layer.

Be used to obtain second manufacture method of cell driving device, have: on the one side of substrate, dispose element drives and comprise the operation that this element drives is used the electronic unit layer of IC chip with IC chip and formation with a plurality of unit circuits that drive driven element so that have the state that it is right that the terminal of splicing ear forms face and real estate; Peel off the operation of substrate from the electronic unit layer; On the face that substrate in the electronic unit layer is stripped from, form the cambial operation of wiring, this wiring cambium layer comprises and is used for the wiring of element drives with the driven element connection corresponding with this unit circuit of the contained constituent parts circuit of IC chip; With the operation that comprises the element layer of a plurality of driven elements in the opposite side formation of the electronic unit layer of observing from the wiring cambium layer.

Further, be used to obtain the 3rd manufacture method of cell driving device, have: will be used for the electrode that driven element provides electric current or applies voltage is formed on the one side of substrate and forms the cambial operation of wiring, this wiring cambium layer comprises each wiring that is connected that is used for this electrode and a plurality of unit circuits; The electronic unit layer is formed on the operation on the opposite side of the substrate of observing from wiring layer, this electronic unit layer comprises the element drives IC chip with a plurality of unit circuits that are used to drive driven element; Peel off the operation of substrate from the wiring cambium layer; Form driven element that contacts with electrode and the operation that forms the element layer that comprises a plurality of driven elements with an opposite side at the electronic unit layer of observing from the wiring cambium layer.

Relevant electro-optical device of the present invention is characterised in that to have: a plurality of electrooptic elements; A plurality of element drives IC chip, it has a plurality of unit circuits that are used to drive electrooptic element respectively; And select the control circuit controlled, and select to be controlled to select 1 or above unit circuit in these a plurality of unit circuits successively, allow selected 1 or above unit circuit be used to drive the action of electrooptic element simultaneously; With select circuit, it selects 1 or above IC chip in a plurality of element drives in the IC chip successively, allows the control circuit of selected IC chip select to control simultaneously.

In this structure, the unit circuit that is used for driving electrooptic element is included in the IC chip.The active component that the IC chip comprises is compared with the thin film transistor (TFT) that is made of low temperature polycrystalline silicon, and the unordered difference on characteristic is little.Therefore, even for the height of display image becomes more meticulous and big picture has increased the number of electrooptic element, the unit circuit that has also suppressed to be used to drive it produces the possibility of unordered difference on characteristic, improved the yield rate of electro-optical device thus.And, because the active component that the IC chip comprises is compared available low voltage drive with the thin film transistor (TFT) that is made of low temperature polycrystalline silicon, sought the reduction of electro-optical device power consumption.

But, selecting circuit directly to select under the prior art structure of constituent parts circuit, need be from selecting each the many wirings (sweep trace) of circuit to a plurality of unit circuits.On the other hand, in the present invention, a plurality of pixel driving comprise a plurality of unit circuits with each of IC chip, and these pixel driving are selected as the IC chip that should drive electrooptic element successively with the IC chip.Therefore, there is no need wiring that each unit circuit is provided for selecting, constitute with prior art and compare, the radical of wiring reduces.For example, become in the minimum structure, to each pixel driving IC chip, if select circuit to be provided for selecting this pixel driving just enough with a wiring of IC chip at the wiring number.According to this structure, and all be that necessary prior art structure is compared to each wiring of a plurality of unit circuits from selecting circuit, the wiring number reduces significantly.

Electrooptic element of the present invention will provide electric current and the electro ultrafiltration that applies voltage and so on to be transformed into the light action of brightness and transmitance variation and so on, perhaps light action will be transformed into electro ultrafiltration.The exemplary of this electrooptic element is organic EL luminous in the brightness corresponding with the electric current of supplying with from unit circuit and changes the liquid crystal of orientation (being the transmitance of light) with the voltage that applies according to unit circuit.But the present invention also is applicable to the device of use electrooptic element in addition.In optimal way, each of a plurality of electrooptic elements all disposes on the planar different positions.For example, a plurality of electrooptic elements are configured to the matrix state with line direction and column direction.

" being used to drive the action of electrooptic element " of the present invention means except electrooptic element being provided the operation of electric current and voltage, also is included in the actual notion that provides this electric current and voltage also to hold it in the action in the capacity cell before of electrooptic element.

In mode more specifically, each element drives has particular electrical circuit with the IC chip, and its specific successively this element drives is with 1 contained or above unit circuit of IC chip; Control circuit will be selected control as object by particular electrical circuit specific 1 or above unit circuit.According to this mode, although can reliably drive the electrooptic element of expectation with few wiring number by control circuit.

In optimal way, select circuit that clock signal is outputed to selected element drives with on the IC chip; Each element drives is with the particular electrical circuit of IC chip and by specific successively synchronously this element drives 1 contained or the above unit circuit of IC chip of the clock signal of selecting circuit to provide.According to this structure,, make the drive actions unanimity of the electrooptic element that carries out with the IC chip by each element drives easily because clock signal is provided for selected element drives IC chip.

In more preferably mode, the constituent parts circuit has: holding circuit, and it keeps and drive current or the corresponding electric charge of driving voltage of being used to drive electrooptic element; And holding circuit, it keeps the electric charge that is kept by holding circuit.According to this structure, the constant electric charge that keeps by holding circuit of having kept.For example using under the situation of capacitor as holding circuit, the electric charge that is kept is owing to reveal and might lose.According to aforesaid way,, prevented that electric current or the voltage different with expectation drive current or driving voltage are provided for electrooptic element owing to kept by constant by the electric charge of holding circuit maintenance.

, each element drives can be carried out action checking by probe being contacted its splicing ear with the IC chip.But, in this case, need allow each splicing ear reach enough sizes that probe can contact.Therefore, in optimal way of the present invention, each element drives will be used to check that with the control circuit of IC chip the test signal of constituent parts circuit operation outputs to this element drives contained unit circuit of IC chip.According to this mode,, test signal checks the action of constituent parts circuit by being provided.Therefore, for the splicing ear of the circuit of checking by this test signal, there is no need to reach the size that needs the probe contact.That is, because element drives is littler than the size that contact probe needs with one one of the IC chip or whole splicing ear, so reduced the size of element drives with the IC chip.

Be suitable for device of the present invention and be not limited to the electro-optical device that comprises electrooptic element.That is, the present invention is applicable to the various devices that comprise a plurality of driven elements.Cell driving device of the present invention has: a plurality of driven elements; A plurality of element drives IC chip, it has respectively: a plurality of unit circuits that are used to drive driven element; With the control circuit of selecting to control, select to be controlled at and selects 1 or above unit circuit in these a plurality of unit circuits successively, allow selected 1 or above unit circuit be used to drive the action of driven element simultaneously; Select circuit, it selects 1 or above IC chip in a plurality of element drives in the IC chip successively, allows the control circuit of selected IC chip select to control simultaneously.According to this cell driving device, also can obtain the effect identical with the electro-optical device of the invention described above.

Second of the electronic circuit of electro-optical device of the present invention is characterised in that to have: a plurality of electrooptic elements, and it is driven by the drive current by the data-signal appointment respectively; With a plurality of data supply circuits, its by one or more electrooptic element each and be provided with and comprise the first data supply circuit and the second data supply circuit, comprise the reference current supply circuit that generates reference current based on reference current respectively, export the data-signal output circuit of the current value corresponding based on the reference current that generates by the reference current supply circuit with data-signal; The reference current that the first data supply circuit will use for the reference current supply circuit generation reference current of this first data supply circuit outputs to the second data supply circuit; The reference current supply circuit of the second data supply circuit generates reference current based on the reference current of first data supply circuit supply on the other hand.

Usually, at the electro-optical device that comprises a plurality of data supply circuits that are used for the difference outputting data signals, generate data-signal based on the reference current that generates at each data supply circuit.But under this structure, when the active component that constitutes each data supply circuit etc. had unordered difference on characteristic, it was different situations that the current value of reference current can produce each data supply circuit.In this case, because the current value based on the data-signal that reference current generated has produced unordered difference, even suppose to give each electrooptic element that equal drive current is provided, still having actual drive current is different problems to each data supply circuit.For example, electro-optical device is being used as under the situation of display device, is producing color spot because of the variation of drive current makes display image.

In order to address this problem, in electro-optical device of the present invention, employed reference current is output to the second data supply circuit in the reference current supply circuit of the first data supply circuit, and the reference current supply circuit of the second data supply circuit generates reference current based on the reference current of supplying with from the first data supply circuit.That is, in the first data supply circuit and the second data supply circuit, generate data-signal based on common reference current.Therefore, reduced about from the data-signal of first data supply circuit output with from the error of the current value of the data-signal of second data supply circuit output.

In optimal way of the present invention, the reference current of first data supply circuit output is with time division way each supply to a plurality of second data supply circuits.According to this mode, the reference current that uses in the reference current that uses in a plurality of second data supply circuits and the first data supply circuit becomes and equates.

In this mode, the reference current of first data supply circuit output is supplied with to each second data supply circuit through electric current supplying wire, and this electric current supplying wire has for the common part of a plurality of second data supply circuits.According to this structure, because the common wiring of use in a plurality of second data supply circuits compared with each structure that all are connected individually of the first data supply circuit and a plurality of second data supply circuits, the wiring number has reduced.

In another way, each of a plurality of data supply circuits has control circuit, is used to switch whether supply with reference current to the reference current supply circuit of this data supply circuit.According to this mode,, can provide reference current in any time by the control circuit regulation to the reference current supply circuit of each data supply circuit.And, in this form, the control circuit that also adopts each second data supply circuit the enable signal of being supplied with the control circuit of level data supply circuit in the past be the basis change could provide reference current to the reference current supply circuit in, enable signal is outputed to the structure of the control circuit of subordinate's data supply circuit.For example, the control circuit of each second data supply circuit becomes cascade connection (vertically connecting).According to this structure,, can provide reference current successively according to enable signal to the reference current supply circuit of each second data supply circuit.

In optimal way of the present invention, each data supply circuit comprises the holding circuit that keeps reference current; The reference current supply circuit of each data supply circuit generates reference current according to the reference current that holding circuit kept.Because each data supply circuit comprises holding circuit in this mode, the reference current supply circuit can generate the reference current corresponding with this reference current at any time and output to the data-signal output circuit.

, between the data-signal period of output and reference current be provided for the reference current supply circuit during when overlapping, be accompanied by the output of data-signal, the influence of power supply noise is provided for reference current, thereby produces error on the current value of reference current.Therefore, in optimal way of the present invention, to the supply of the reference current of the reference current supply circuit of each data supply circuit be beyond during the data-signal output circuit outputting data signals of this data supply circuit during on carry out.In view of the above, avoided on the current value of reference current, producing error.

In optimal way, the formation of the first data supply circuit is identical with the formation of the second data supply circuit.According to this mode, when the configuration data supply circuit, there is no need to distinguish the first data supply circuit and the second data supply circuit.Therefore, and the first data supply circuit is compared as the situation of different formations with the second data supply circuit, when enhancing productivity, also reduced manufacturing cost.

Further, in optimal way of the present invention, be provided with the IC chip of the element drives with a plurality of unit circuits, it offers electrooptic element with the drive current corresponding with data-signal; The data-signal output circuit of each data supply circuit outputs to the unit circuit of element drives with the IC chip with the data-signal that generates.According to this mode, be comprised in the IC chip owing to be used for driving the unit circuit of electrooptic element, suppressed the unordered difference of unit circuit on characteristic.

A feature of the present invention is to be applicable to the various devices that comprise a plurality of driven elements.That is, electro-optical device of the present invention has: a plurality of driven elements, and it is driven by the drive current by the data-signal appointment respectively; With a plurality of data supply circuits, its by one or more driven element each and be provided with and comprise the first data supply circuit and the second data supply circuit, comprise the reference current supply circuit that generates reference current based on reference current respectively, export the data-signal output circuit of the current value corresponding based on the reference current that generates by the reference current supply circuit with data-signal; The reference current that the first data supply circuit will use for the reference current supply circuit generation reference current of this first data supply circuit outputs to the second data supply circuit beyond the first data supply circuit; The reference current supply circuit of the second data supply circuit generates reference current according to the reference current of being supplied with by the first data supply circuit on the other hand.According to this cell driving device, also can obtain the effect identical with electro-optical device of the present invention.

Relevant electronic equipment of the present invention comprises the electro-optical device with above-mentioned feature.According to this electronic equipment, suppressed the unordered difference of active component on characteristic in the electro-optical device.Particularly, be used as in the electronic equipment of display device, display quality can be maintained high level at electro-optical device.

As preferably, electronic equipment comprises first display part with light emitting-type electro-optical device and second display part with non-light emitting-type electro-optical device.Wherein the light emitting-type electro-optical device has himself luminous electrooptic element.The exemplary of light emitting-type electro-optical device is the organic EL display that luminous organic EL according to supplying electric current and in brightness is used as electrooptic element.On the other hand, non-light emitting-type electro-optical device has himself non-luminous electrooptic element.The exemplary of non-light emitting-type electro-optical device is with according to applying the liquid crystal indicator that liquid crystal that voltage changes transmitance is used as electrooptic element.In this electronic equipment, show from offering image after the light of light emitting-type electro-optical device outgoing arrives non-light emitting-type electro-optical device.Therefore.There is no need to be provided with lighting device guarantees to produce the visuality that shows by non-light emitting-type electro-optical device.Perhaps, even lighting device is set, the outgoing light quantity by this lighting device also can reduce.In the optimal way of this electronic equipment, first display part is connected with mutual rotation mode by getting involved each limit end parts with second display part.According to this mode,, adjust the relative position relation between first display part and second display part in order to make luminous second display part that arrives effectively of first display part.

Description of drawings

Fig. 1 is the oblique view of the electro-optical device structure of expression embodiment of the present invention.

Fig. 2 is the planimetric map of expression electronic unit layer structure.

Fig. 3 is the corresponding relation synoptic diagram of expression pixel driving between IC chip and the organic EL.

Fig. 4 is the block scheme of expression pixel driving with the structure of IC chip.

Fig. 5 is expression scanning with IC chip and pixel driving with the block scheme that concerns between the IC chip.

Fig. 6 is used to illustrate the sequential chart of scanning with the IC chip operation.

Fig. 7 is the circuit diagram of the structure of expression pixel circuit.

Fig. 8 is the sequential chart that is used to illustrate the scanning of pixel circuit.

Fig. 9 is the block scheme of expression column data conversion with the structure of IC chip.

Figure 10 is the circuit diagram of the structure of expression reference current supply circuit.

Figure 11 is the sequential chart of the operation in during expression is set.

Figure 12 is the block scheme of the structure of expression D/A translation circuit.

Figure 13 is the circuit diagram of the structure of expression D/A transformation component.

Figure 14 is the sectional view of the structure of the electro-optical device that obtains by first manufacture method of expression.

Figure 15 is the expression pixel driving forms face with the IC bonding pads a structural representation.

Figure 16 is the planimetric map of the structure of expression electro-optical device.

Figure 17 is the synoptic diagram that basalis and metal level form operation in expression first manufacture method.

Figure 18 is the synoptic diagram of expression with IC chip configuration operation in the method.

Figure 19 is expression forms operation with packed layer in the method a synoptic diagram.

Figure 20 is expression forms operation with first insulation course in the method a synoptic diagram.

Figure 21 is expression forms operation with first wiring layer in the method a synoptic diagram.

Figure 22 is expression forms operation with second insulation course in the method a synoptic diagram.

Figure 23 is expression forms operation with metal film in the method and anode material film a synoptic diagram.

Figure 24 is expression forms operation with second wiring layer and anode layer in the method a synoptic diagram.

Figure 25 is expression forms operation with the 3rd insulation course in the method a synoptic diagram.

Figure 26 is expression forms operation with resin bed in the method a synoptic diagram.

Figure 27 is operation is removed in expression with the part of anode layer in the method a synoptic diagram.

Figure 28 is expression forms operation with conductive layer in the method and restraining barrier a synoptic diagram.

Figure 29 is expression forms operation with conductive layer in the method and restraining barrier a synoptic diagram.

Figure 30 is expression forms operation with restraining barrier in the method a synoptic diagram.

Figure 31 is expression forms operation with EL layer in the method a synoptic diagram.

Figure 32 is expression forms operation with anode layer in the method a synoptic diagram.

Figure 33 is the sectional view of the structure of the electro-optical device that obtains by second manufacture method of expression.

Figure 34 is expression forms operation with substrate glazing peel ply in the method a synoptic diagram.

Figure 35 is expression forms operation with metal level in the method and tack coat a synoptic diagram.

Figure 36 is the synoptic diagram of expression with IC chip configuration operation in the method.

Figure 37 is expression forms operation with basalis in the method and light shield layer a synoptic diagram.

Figure 38 is operation is pasted in expression with support substrate in the method a synoptic diagram.

Figure 39 is the synoptic diagram of expression with strippable substrate state in the method.

Figure 40 is expression forms operation with power lead in other example of method a synoptic diagram.

Figure 41 is that the structural section figure with the electro-optical device of other example acquisition of method is passed through in expression.

Figure 42 is the structural section figure of expression by the electro-optical device of the 3rd manufacture method acquisition.

Figure 43 is expression forms operation with photospallation layer in the method a synoptic diagram.

Figure 44 is expression forms operation with insulation course in the method and conductive layer a synoptic diagram.

Figure 45 is expression forms operation with second wiring layer and anode layer in the method a synoptic diagram.

Figure 46 is expression forms operation with second insulation course in the method a synoptic diagram.

Figure 47 is expression forms operation with first wiring layer in the method a synoptic diagram.

Figure 48 is expression forms operation with first insulation course in the method a synoptic diagram.

Figure 49 is expression forms operation with projection in the method a synoptic diagram.

Figure 50 is the synoptic diagram of expression with IC chip configuration operation in the method.

Figure 51 is operation is pasted in expression with support substrate in the method a synoptic diagram.

Figure 52 is the synoptic diagram of expression with strippable substrate state in the method.

Figure 53 is the oblique view of expression as the personal computer formation of electronic equipment one example.

Figure 54 is the oblique view of expression as the e-book formation of electronic equipment one example.

Among the figure: D-electro-optical device, 1-organic EL layer (element layer), 10-organic EL (electrooptic element, driven element), 13-EL layer, 15-sealant, the 2-cambium layer that connects up, 3-electronic unit layer, the 30-IC chip, 31-control IC chip, 33-scanning IC chip (selecting to use the IC chip), 35-column data conversion IC chip (data are supplied with and used the IC chip), 37-pixel driving IC chip (element drives IC chip), 371-pixel decoder device, 374-pixel counter, 377-pixel circuit (unit circuit), the CO-capacitor, 301, the 307-basalis, the 302-metal level, the 302a-installation portion, 302b-telltale mark, 304, the 305-packed layer, 306 light shield layers, 42, the 308-projection, the 6-support substrate, 41-first insulation course, 43-first wiring layer, 45-second insulation course, 47-second wiring layer, the 49-anode layer, 50-the 3rd insulation course, 52-storage lattice cofferdam layer, the 54-conductive layer, the 56-restraining barrier, 58-cathode layer, 701,707,708, the 730-metal film, 702-anode material film, the 705-resin molding, 710, the 720-substrate, 712,724-photospallation layer, the 716-resin molding, the 726-dielectric film, P1-first pad (the-splicing ear), P2-second pad (second splicing ear), YLk-scan control line group, LXD-Data Control line.

Embodiment

Below, with reference to the accompanying drawings, embodiments of the present invention are described, below shown in mode just represent a mode of the present invention, it does not limit the present invention, can change arbitrarily within the scope of the present invention.And, below shown among each figure, in order to allow each inscape become recognizable size on drawing, so the suitable difference to some extent of the size of each inscape and ratio and actual size and ratio.

＜A: the structure of electro-optical device 〉

At first, as the device that is used for display image, the mode that is applicable to electro-optical device of the present invention is described.Fig. 1 is the oblique view of expression embodiment of the present invention electro-optical device structure.As shown in FIG., electro-optical device D has support substrate 6, organic EL layer 1, wiring cambium layer 2 and electronic unit layer 3.This support substrate 6 is parts of the tabular or film like that is made of glass, plastics, metal, pottery etc.Electronic unit layer 3 is set on the one side of support substrate.Wiring cambium layer 2 is set at the opposite side of the support substrate of seeing from electronic unit layer 36, and organic EL layer 1 is set at the opposite side of the support substrate of seeing from wiring cambium layer 26.

Organic EL layer 1 comprises a plurality of organic EL 10 as electrooptic element.These organic ELs 10 are configured to matrix form according to line direction (directions X) and column direction (Y direction).Each organic EL 10 is driven by supplying electric current, is to carry out luminous element (driven element) in view of the above.The last direction of the light that each organic EL 10 sends in Fig. 1 reverse direction of support substrate 6 (promptly with) penetrates.In the present embodiment, imagination has disposed m organic EL 10 at column direction, has disposed the situation of n organic EL 10 at line direction.Therefore, number of picture elements is that " m * n " is individual altogether.

Electronic unit layer 3 comprises a plurality of electronic units that are used to drive each organic EL 10.Particularly, on electronic unit layer 3, comprise various electronic units, as adopting CMOS (Complementary Metal-Oxide Semiconductor: complementary metal oxide semiconductor (CMOS)) passive elements such as the SIC (semiconductor integrated circuit) of type or bipolar transistor (IC chip), resistance or capacitor, TFT chip or tabular paper (paper) battery etc.As shown in Figure 1, the electronic unit layer 3 in the present embodiment comprises control IC chip 31, a plurality of scanning uses IC chip 37 as electronic unit with IC chip 33, a plurality of column data conversion with IC chip 35 and a plurality of pixel driving.

On the other hand, wiring cambium layer 2 is between electronic unit layer 3 and organic EL layer 1.This wiring cambium layer 2 comprises a plurality of wirings.Particularly, wiring cambium layer 2 has and is used to connect the wiring between the contained electronic unit on the electronic unit layer 3.As shown in Figure 1, wiring cambium layer 2 comprises a plurality of scan control line group YL and a plurality of data line DL.Each scan control line group YL is the wiring that each scanning is electrically connected with IC chip 37 with IC chip 33 and a plurality of pixel driving.On the other hand, each data line is the wiring that each column data conversion is electrically connected with IC chip 37 with IC chip 35 and a plurality of pixel driving.Wiring cambium layer 2 comprises the wiring that contained electronic unit on the electronic unit layer 3 is connected with contained organic EL 10 on the organic EL layer.For example, wiring cambium layer 2 comprises the wiring (having omitted diagram among Fig. 1) that a pixel driving is electrically connected with a plurality of organic ELs 10 with IC chip 37.

Below, with reference to figure 2, the concrete formation of electronic unit layer 3 is described.As shown in FIG., a plurality of pixel driving are configured to matrix form with IC chip 37 according to line direction (directions X) and column direction (Y direction).On organic EL layer 1 in contained a plurality of organic ELs 10, each organic EL 10 of predetermined number is provided with each pixel driving with IC chip 37.Corresponding relation between pixel driving usefulness IC chip 37 and the organic EL 10 such as following.

In the present embodiment, contained " m * n " individual organic EL 10 that amounts on the organic EL layer 1 is divided into a plurality of groups (being called " element group " later on).Particularly, as shown in Figure 3, n organic EL 10 is divided in every group of q side by side on line direction, with on the column direction side by side m organic EL 10 to be divided into every group of p individual, by there being " p * q " individual organic EL 10 to constitute an element group on the zone.Then, distribute a pixel driving with IC chip 37 to each of each element group.That is, as shown in Figure 3, each pixel driving with IC chip 37 according to the task of having " p * q " individual organic EL 10 to be configured and to bear to drive these organic ELs 10 with respect to an element group.

As shown in Figure 2, a plurality of scannings are pressed column direction and row arrangement with IC chip 33 along one or two edges of support substrate 6.Each scanning has the selection circuit with the IC chip, is used for selecting in turn among with IC chip 37 to carry out in a plurality of pixel driving the IC chip of the driving of organic EL 10.On the other hand, a plurality of column data conversion are pressed line direction and row arrangement with IC chip 35 along other edge of support substrate 6.Each column data conversion is controlled the electric current that flows in each organic EL 10 with IC chip 35 based on data (being called " view data " later on) Xd of presentation video.View data Xd is the data of specifying the brightness (grade) of each organic EL 10.

On the other hand, control is configured on the part (being the angle part of support substrate 6) that a plurality of scannings intersect with the row of IC chip 35 with the row of IC chip 33 and a plurality of column data conversion with IC chip 31.This control IC chip 31 unified each scanning IC chip 33 and each column data conversion IC chips 35 controlled.Particularly, control is connected to external device (ED)s such as computer system (diagram is omitted) with IC chip 31, receives view data Xd and is used for regulation display operation time sequence control signal (for example clock signal) from this external device (ED).Control has display-memory 31a with IC chip 31.This display-memory 31a is used for the device of interim storage by the view data Xd of external device (ED) supply.

Control generates based on the control signal of supplying with from external device (ED) with IC chip 31 and is used at a plurality of scannings average signal (reset signal RSET described later that selects on the IC chip 33, clock signal YSCL, select clock signal YECL with chip), these signals are offered each scanning IC chip (with reference to figure 5).Control offers each column data conversion IC chip 35 (with reference to figure 9) with IC chip 31 with the view data Xd that stores among the display-memory 31a.And control is used to force to stop the pressure cut-off signals Doff of each pixel driving with 37 work of IC chip with 31 generations of IC chip, and this signal is outputed to each pixel driving IC chip 37 by getting involved in the 2 contained wirings of wiring cambium layer.

Below, relevant pixel driving IC chip 37 is described, scans formation and operation with each of IC chip 33 and column data conversion chip 35.And, below, after having illustrated that pixel driving is used the formation and operation of IC chip 33 with IC chip 37 and scanning, the formation and the operation of putting off until some time later bright column data conversion chip 35.

＜pixel driving the formation of IC chip 37 〉

Each pixel driving comprises the circuit that is used to drive to a plurality of organic ELs 10 of its distribution with IC chip 37.More specifically, as shown in Figure 4, each pixel driving has pixel decoder device 371, pixel counter 374 and a plurality of pixel circuit 377 with IC chip 37.Each of each pixel circuit 377 and the affiliated a plurality of organic ELs 10 of element group is configured to matrix form with 1 pair 1 corresponding form.Therefore, each pixel driving comprises " p * q " individual pixel circuit 377 altogether with IC chip 37.Each pixel circuit 377 is the circuit that are used to drive an organic EL 10.Therefore, with IC chip 37, can drive contained in the organic EL layer 1 " p * q " individual organic EL 10 by a pixel driving.

As shown in Figure 4, a line direction q side by side pixel circuit 377 interconnects by getting involved a word line WLi (i is the integer that satisfies 1≤i≤m), a retentive control signal wire HLi and a led control signal line GCLi.The end of each word line WLi, each retentive control signal wire HLi and each led control signal line GCLi is connected to pixel decoder device 371.Under this constitutes, respectively from pixel decoder device 371 to a line direction q side by side pixel circuit 377, provide selection signal XWi by word line WLi, provide retentive control signal XHi by holding signal line HLi, and provide led control signal XGCi by led control signal line GCLi.On the other hand, a column direction p side by side pixel circuit 377 is connected to column data conversion IC chip 35 by a data lines DLj (j is the integer that satisfies 1≤j≤n).

A pixel driving is connected to pixel decoder device 371 with whole pixel circuits contained in the IC chip 37 377 through common test signal line TSL.Under this constitutes, provide test signal TS to each pixel circuit 377 simultaneously by test signal line TSL from pixel decoder device 371.By this, whole pixel circuit 377 carries out operational testing simultaneously.

＜scanning the formation of IC chip 33 〉

Below, with reference to figure 5, the concrete formation of scanning with IC chip 33 is described.And, below, for convenience of explanation, will be designated as " pixel driving IC chipset " by side by side a plurality of (" n/q " is individual) pixel driving with the group that IC chip 37 constitutes at line direction.

As shown in Figure 5, in the present embodiment, per two (i.e. 2 row parts) pixel driving are provided with scanning IC chip 33 with the IC chipset.Each scans the operation of using IC chip 37 with two pixel driving of IC chip 33 controls with a plurality of (" 2n/q " the is individual) pixel driving under the IC chipset.And, below, for convenience of explanation, scanning is designated as " r (=m/2p) " with the number of IC chip 33.With scanning 2 pixel driving corresponding with IC chip 33 with the IC chipsets in, a part of pixel driving being designated as " first pixel driving IC chipset 370a " with the IC chipset when, another part pixel driving is designated as " second pixel driving IC chipset 370b " with the IC chipset.

Respectively scanning, is connected to this scanning and uses on the IC chip 37 with two pixel driving that IC chip 33 is distributed by getting involved contained scan control line group YLk on the wiring cambium layer 2 (k is the integer that satisfies 1≤k≤r) with IC chip 33.Each scan control line group YLk comprises first part (local) clock cable LCak, second part (local) clock cable LCbk and local reseting signal line LRS.More specifically, each scanning is connected to first pixel driving with on a plurality of pixel driving usefulness IC chips 37 under the IC chipset 370a with IC chip 33 by getting involved the first local clock cable LCak.Equally, each scanning is connected to second pixel driving with on a plurality of pixel driving usefulness IC chips 37 under the IC chipset 370b with IC chip 33 by getting involved the second local clock cable LCbk.2 adjacent scannings are with being electrically connected by contained wiring on the wiring cambium layer 2 between the IC chip 33.

Here, Fig. 6 is the sequential chart that expression relates to the signal waveform of each pixel circuit 377 scanning.Reset signal RSET shown in the figure, clock signal YSCL and chip select clock signal YECL to offer the signal of each scanning with IC chip 33 from control with IC chip 31.Reset signal RSET wherein is the signal that is used for the time length of regulation whole in order to scan " m * n " individual 10 required times of organic EL (being called " data write during " later on), rises to the H level its zero hour during each data writes.On the other hand, clock signal YSCL is the signal with the cycle that is equivalent to a horizontal scan period length.This horizontal scan period is equivalent to n time that pixel circuit 377 is selected simultaneously under the delegation.Chip selects clock signal YECL to be used for selecting in fact should carry out pixel driving is used IC chip 33 with the scanning of the control of IC chip 37 signal in a plurality of scannings with IC chip 33.Therefore, chip selects clock signal YECL only to be equivalent to scan " r " the inferior H of rising to level with the number of IC chip in during data write.

Each scanning is exported the first local clock signal SCKak and the second local clock signal SCKbk after selecting clock signal YECL to select with IC chip 33 by this chip successively.The first local clock signal SCKak and the second local clock signal SCKbk are used for every row to select the clock signal of each pixel driving with a plurality of pixel circuits 377 under the IC chipset.

More specifically, as shown in Figure 6, k scanning is at first exported first local clock signal SCKak with a plurality of pixel driving under the IC chipset 370a with IC chip 37 to first pixel driving with IC chip 33.This first local clock signal SCKak carries out the signal that level changes during being equivalent to " p " individual horizontal scan period and with the cycle identical with clock signal YSCL, " p " be first pixel driving with IC chipset 370a at the number of column direction pixel circuit 377 side by side.By chip select scanning that clock signal YECL selects with IC chip 33 when finishing based on the first local clock signal SCKak and to the selection of the capable pixel circuit 377 of p, to second pixel driving with a plurality of pixel driving under the IC chipset 370b with the IC chip 37 outputs second local clock signal SCKbk.This second local clock signal SCKbk carries out the signal that level changes during being equivalent to " p " individual horizontal scan period and with the cycle identical with clock signal YSCL, " p " be second pixel driving with IC chipset 370b at the number of column direction pixel circuit 377 side by side.The first local clock signal SCKak and the second local clock signal SCKbk transmit by the first local clock cable LCak and the second local clock cable LCbk respectively.

On the other hand, when finishing based on the second local clock signal SCKbk and to the selection of the capable pixel circuit 377 of p, as shown in Figure 6, next stage scanning is turned to the H level with the enable signal EOk that is exported on the IC chip 33 with IC chip 33 in each scanning.This enable signal EOk is used for and will scans the signal of using IC chip 33 with the information notice subordinate that 2 row pixel driving are selected to finish with the IC chipset of IC chip 33 gained according to scanning.(k+1) level scanning that has been provided H level enable signal EOk is exported the first local clock signal SCKak+1 and the second local clock signal SCKbk+1 with IC chip 33 according to program same as described above.

The formation of＜pixel circuit 377 〉

Below, with reference to figure 7, the electricity formation as the pixel circuit 377 of unit circuit is described.Fig. 7 expresses a pixel circuit 377 that is positioned at the capable j row of i.This formation is common formations for all pixel circuits 377.

Pixel circuit 377 is made of a plurality of MOS transistor and a capacitor C0.Particularly, pixel circuit 377 has: pair of switches transistor Q1a and Q1b; A pair of transistor Q2a and the Q2b of reading in; Capacitor C0; Distribution oxide-semiconductor control transistors Q3; Test transistor Q8a and Q8b; The 377a of analog memory portion.Wherein transistor Q1a, Q1b, Q2a, Q2b and Q3 are the p channel type MOS transistor, and transistor Q8a and Q8b are the n channel type MOS transistor.Transistor Q2b is the driving transistors that is used for providing constant current to organic EL 10.Transistor Q3 is the transistor that is used to control this constant current conduction and cut-off.

Transistor Q1a is connected to data line DLj and transistor Q1b, and its gate terminal is connected to word line WLi.Transistor Q1b is connected to an end and the transistor Q1a of capacitor C 0, and its gate terminal is connected to word line WLi.On the other hand, the other end of capacitor C 0 is connected to power lead L1.Applied supply voltage VDD on this power lead L1.

Transistor Q2a and Q2b constitute current mirror circuit.Particularly, each gate terminal of transistor Q2a and Q2b is connected to the end of capacitor C0.A transistor Q2a connects between transistor Q1a and the power lead L1.Therefore, when the selection signal XWi that is provided on word line WLi developed into the L level, transistor Q1a and Q1b became conducting state.Like this when transistor Q1b becomes conducting state, transistor Q2a is just as the function of gate terminal and the connected diode of drain terminal.Therefore, just flow through the path that is called power lead L1 → transistor Q2a → transistor Q1a → data line DLj according to the electric current of the data-signal Dj of data line DLj, the electric charge savings corresponding with the grid voltage of transistor Q2a is on capacitor C0.Another transistor Q2b is connected on the source terminal and power lead L1 of transistor Q3.Transistor Q2b and transistor Q2a constitute current mirror circuit, and the electric charge of putting aside on capacitor C0 promptly flows to transistor Q3 according to the electric current that the grid voltage of transistor Q2b produces.

The gate terminal of transistor Q3 is connected to led control signal line GCLi.The drain terminal of transistor Q3 is connected to organic EL 10 by contained wiring on the wiring cambium layer 2.Under this structure, transistor Q3 became conducting state when led control signal XGCi developed into the L level.At this moment, the drive current Iel according to transistor Q2b grid voltage offers organic EL 10 by transistor Q2b and Q3.By the supply of this drive current Iel, organic EL 10 is luminous.And, in the present embodiment, as transistor Q2a, though Q2b and Q3 adopt the p transistor npn npn,, these transistors also can become the n transistor npn npn suitably according to the annexation between organic EL 10 and the power lead L1.

On the other hand, the 377a of analog memory portion keeps stable circuit with the electric charge that capacitor C0 is put aside.Particularly, the 377a of analog memory portion has transistor Q4a, Q4b, Q5, Q6 and Q7.Wherein transistor Q4a and Q4b are the n channel type MOS transistor, and transistor Q5, Q6 and Q7 are the p channel type MOS transistor.Transistor Q4a and Q4b constitute current mirror circuit.Equally, transistor Q5 and Q6 constitute current mirror circuit.

Transistor Q5 is connected on power lead L1 and the transistor Q4a, and its gate terminal is connected to the end of capacitor C0.Transistor Q6 is connected on power lead L1 and the transistor Q4b, and its gate terminal is connected to transistor Q7.This transistor Q7 is connected to an end and the transistor Q6 of capacitor C0, and its gate terminal is connected to holding signal line HLi.Therefore, transistor Q7 becomes conducting state when holding signal Xhi becomes the L level.

On the other hand, transistor Q4a is connected on transistor Q5 and the ground wire, and its gate terminal is connected to transistor Q5.Transistor Q4b is connected on transistor Q6 and the ground wire, and its gate terminal is connected on the gate terminal of transistor Q5 and transistor Q4a.

Under this constituted, the 377a of analog memory portion was by following work.That is, when being put aside on capacitor C0, flow to transistor Q4a from transistor Q5 according to the electric current of transistor Q2b grid voltage according to the electric charge of data-signal.Here, because current mirror circuits doubly such as transistor Q4a and Q4b formations, the electric current that equates with streaming current on transistor Q4a is flow to transistor Q4b, and this electric current also flows to transistor Q6.Then, when the transistor Q7 in this state became conducting state, the grid voltage of transistor Q6 was fed back to capacitor C0 by transistor Q7.By this, capacitor C0 goes up the electric charge of savings and is kept stable.And, in other mode, can adopt Nonvolatile memory circuit to replace the analog memory 377a of portion.The 377a of analog memory portion is in order to open again rapidly in case the efficient circuit of the demonstration after extinguishing, and the demonstration after this extinguishes is in order to reduce power consumption and program warm start etc., but it in the present invention not necessarily.

Below, illustrate that pixel driving is with IC chip 37 contained pixel counter 374 and pixel decoder device 371.Pixel counter 374 shown in Figure 4 is to be used for pixel driving with IC chip 37 contained each row pixel circuit 377 as alternative and specific successively device.Local reset signal line LRS, the first local clock cable LCak or the second local clock cable LCbk have been connected on this pixel counter 374.

After the detailed description, " 1 " all is provided count value when the first local clock signal SCKak that is provided with IC chip 33 by scanning or the second local clock signal SCKbk rise to the H level at every turn for pixel counter 374.And " 0 " all is provided count value when the local reset signal RS that is provided with IC chip 33 by scanning rises to the H level pixel counter 374 at every turn.Therefore, in the count value of pixel counter 374 is during data write, in each horizontal scan period, increase " 1 ", can get access to the value of " p " from " 0 ".The count value of pixel counter 374 is output to pixel decoder device 371.

This pixel decoder device 371 is to be used for selecting successively the device of a pixel driving with contained each row pixel circuit 377 on the IC chip 37.This pixel decoder device 371 has connected the first local clock cable LCak or the second local clock cable LCbk.A plurality of (q) pixel circuit 377 under pixel decoder device 371 is selected in the corresponding row of count value with pixel counter 374 simultaneously.That is, pixel decoder device 371 is selected the level of signal XWi, retentive control signal XHi and led control signal XGCi by control as follows.

As shown in Figure 8, selecting signal XWi is the signal that becomes the L level in the horizontal scan period during data write.That is, select signal XWi when the first local clock signal SCKak or the second local clock signal SCKbk are i rising edge, to be turned into the L level in during data write, be turned into the H level when being (i+1) individual rising edge.Therefore, select signal XW1, XW2 ..., XWp and the first local clock signal LCak or the second local clock signal LCbk rising edge be turned to the L level synchronously successively.Retentive control signal XHi is turned to the L level selecting signal XWi just to be turned to the H level in moment through the stipulated time only after dropping to the L level after passing through the time that is equivalent to a horizontal scan period.And led control signal XGCi will select the signal of the level upset of signal XWi.Therefore, led control signal XGC1, XGC2 ..., XGCp and the first local clock signal LCak or the second local clock signal LCbk rising edge be turned to the H level synchronously successively.

On the other hand, as shown in Figure 7, the gate terminal of transistor Q8a and Q8b is connected to test signal line TSL.Wherein the drain terminal of transistor 8a is connected to the drain terminal of transistor Q3.In the pattern (test pattern) of test pixels circuit 377 work,, be turned into the H level by test signal TS and make transistor Q8a become conducting state according to forcing cut-off signals Doff to make transistor Q3 become cut-off state.By this, the anode layer of organic EL 10 is connected to ground wire through transistor Q8a.The drain terminal of transistor 8b is connected to data line DL.After test signal TS in the test pattern was turned into the H level, transistor Q8b became conducting state.By this, data line DL is connected to ground wire through transistor Q8b.At this moment, after transistor Qa1 and Qb1 became conducting state, the grid voltage of transistor Q2a was become earthing potential forcibly.In this test pattern,, leakage (1eak) electric current of pixel circuit 377 and the current potential retentivity of capacitor C0 etc. have been checked by the specified level of selecting signal XWi and data-signal Dj or holding signal XHi is set.In test pattern, the count value of pixel counter 374 is set to a plurality of numerical value bigger than " p ", and carries out the test to each assigned content of these numerical value.And, as transistor Q8a and Q8b, also can adopt the p channel transistor.

Below, the work of each pixel circuit 377 is described.Here, have a pixel circuit 377 that is positioned at the capable j row of i especially in mind its work is described, still, this work is work total in whole pixel circuit 377.

At first, the selection signal XWi that is provided from pixel decoder device 371 is when be turned to the L level zero hour of horizontal scan period, and all the transistor Q1a and the Q1b of pixel circuits 377 became conducting state under i was capable.Its result, the electric current corresponding with data-signal Dj flows through on transistor Q2a, and the electric charge savings corresponding with this electric current is on capacitor C0.On the other hand, when the zero hour of horizontal scan period, led control signal XGCi was turned to the H level, transistor Q3 became cut-off state.Therefore, in capacitor C0 charging, there is not streaming current on organic EL 10.After selection signal XWi was turned to the L level, in the moment through the stipulated time, retentive control signal XHi was turned to the H level, and transistor Q7 becomes cut-off state.

Then, when selecting signal XWi to be turned to the H level finish time of horizontal scan period, all the transistor Q1a and the Q1b of pixel circuit 377 became cut-off state under i was capable.On the other hand, when the finish time of horizontal scan period, led control signal XGCi was turned to the L level, the transistor Q3 of whole pixel circuits 377 became conducting state under i was capable.By this, supply with organic EL 10 via transistor Q2b and Q3 according to the drive current Ie1 of institute's sustaining voltage on the capacitor C0.Its result, organic EL 10 is luminous with the brightness corresponding with the size of drive current Ie1.

Beginning the only moment of delay stipulated time from horizontal scan period finish time, when retentive control signal XHi is turned to the L level, under i is capable all the transistor Q7 of pixel circuits 377 become conducting state.Therefore, the grid voltage of transistor Q2b is kept constant by the 377a of analog memory portion.

On the other hand, as above-mentioned, on pixel decoder device 371, be provided from the pressure cut-off signals Doff of control with IC chip 31.This pressure cut-off signals Doff is turned to after the H level, pixel decoder device 371 with whole led control signal XGC1, XGC1 ..., XGC1p is turned to the H level.By this, pixel driving becomes cut-off state with the transistor Q3 in all pixel circuits 377 in the IC chip 37.Therefore, whole organic EL 10 is according to forcing cut-off signals Doff to stop luminous.

The selection operation of＜pixel circuit 377 〉

Below, describe the selection operation of the pixel circuit of realizing according to structure shown in above 377 in detail.

At first, as shown in Figure 6, offering each reset signal RSET that scans with IC chip 33 from control with IC chip 31 becomes the H level in whole specified time limit.Each scanning with IC chip 33 with the rising edge of this reset signal RSET as origin or beginning, be set at the L level with offering the enable signal EOk of next stage scanning with IC chip 33.And each scanning is turned to H level with first pixel driving with the local reset signal RS that IC chipset 370a and second pixel driving are provided on IC chipset 370b in the whole stipulated time with IC chip 33.Its result, each pixel driving resets to count value " 0 " with contained pixel counter 374 in the IC chipset.

On the other hand, select the beginning of clock signal YECL during data write to be turned to the H level, selected first order scanning IC chip 33 by chip.The time clock of the first local clock signal SCKa1 is provided based on the clock signal YSCL that is provided with IC chip 31 by control with IC chip 33 in this scanning.This first local clock signal SCKa1 is provided for first pixel driving IC chipset 370a through the first local clock cable LCa1.

First pixel driving makes count value be increased to " 1 " from " 0 " as origin or beginning the rising edge of the beginning of clock in the first local clock signal LCa1 with the pixel counter 374 of pixel circuit 377 under among the IC chipset 370a.On the other hand, pixel decoder device 371 is used to flow through operation (being called " selection operation " later on) according to the electric current of data-signal Dj to the organic EL 10 corresponding with these pixel circuits 377 when having selected corresponding with this count value " 1 " the first row pixel circuit 377.

That is, pixel decoder device 371 is turned to the L level at the horizontal scanning period chien shih selection signal XW1 corresponding with this count value " 1 ".Its result, all the transistor Q1a and the Q2a of pixel circuit 377 become conducting state under first row.That is, the affiliated all pixel circuits 377 of first row have been selected.By this, be charged to capacitor C0 according to the electric charge of the electric current of data-signal Dj.In the time of just selecting delegation's pixel circuit 377, pixel decoder device 371 is set to the H level by led control signal XGC1 and makes transistor Q3 become cut-off state when being set to the H level by retentive control signal XH1 and making transistor become cut-off state.

On the other hand, select signal to be turned to after the L level through a horizontal scan period time, pixel decoder device 371 makes selects signal XW1 to be turned to the H level.By this, in whole pixel circuits 377, transistor Q1a and Q1b become cut-off state under first row.And pixel decoder device 371 makes retentive control signal XH1 be turned to the L level from the moment of selecting signal XW1 rising edge to begin to be postponed a little.Its result, the transistor Q7 of pixel circuit 377 becomes conducting state under first row.Pixel decoder device 371 makes led control signal XGC1 be turned to the L level with selecting signal XW1 rising edge synchronously.Its result, the transistor Q3 of pixel circuit 377 becomes conducting state under first row.

By aforesaid operations, under first row all in the pixel circuits 377, the electric current I e1 corresponding with capacitor C0 institute sustaining voltage flows at the source/drain interpolar of transistor Q2b.Therefore, organic EL 10 is luminous with the brightness corresponding with data-signal Dj (grade).

After the selection operation of the first row pixel circuit 377 that so is through with, pixel counter 374 makes count value be increased to " 2 " from " 1 ".Then, in second time horizontal scan period, first pixel driving is carried out selection operation same as described above with the second row pixel circuit 377 under the IC chipset 370a as object.After this, will until first pixel driving with IC chipset 370a under the capable pixel circuit 377 of p carry out same selection operation.That is, at every turn when the zero hour of each horizontal scan period, pixel counter 374 count value was only increased " 1 ", all to according to this count value and the pixel circuit 377 of specific row carries out selection operation.According to more generally statement, when the count value of pixel counter 374 is " k ", select first pixel driving with the capable pixel circuit 377 of k under the IC chipset 370a, and make the organic EL 10 corresponding with luminous with the corresponding brightness of data-signal Dj with these pixel circuits 377.

Then, after the selection operation of whole pixel circuits 377 that p is capable under relevant first pixel driving is used IC chipset 370a finished, the time clock of the second local clock signal SCKb1 was exported in first order scanning based on clock signal YSCL with IC chip 33.This second local clock signal SCKb1 is provided for second pixel driving IC chipset 370b through the second local clock cable LCb1.Then, each pixel driving is used in the IC chip 37 under second pixel driving is used IC chipset 370b, repetition and the above-mentioned relevant first pixel driving same selection operation of IC chipset 370a.That is, second pixel driving is all selected in each horizontal scan period with each row of pixel circuit 377 under the IC chipset 370b, and the organic EL 10 corresponding with these pixel circuits 377 is with luminous with the corresponding brightness of data-signal Dj.

On the other hand, after the selection operation of the capable pixel circuit 377 of p finished under relevant second pixel driving is used IC chipset 370b, first order scanning made second level scanning be turned to the H level with the enable signal EO1 that is provided on the IC chip 33 with IC chip 33.By this, to as object, carry out above-mentioned selection operation with IC chipset 370b (fourth line pixel driving with IC chip 37) successively with IC chipset 370a (the third line pixel driving with IC chip 37) and second pixel driving with corresponding first pixel driving of IC chip 33 with second level scanning.Same later on, select clock signal YECL and enable signal EO to select scanning with IC chip 33 by chip, and will scan with the first corresponding pixel driving of IC chip 33 with this selections and carry out same selection operation with IC chipset 370b successively as object with the IC chipset 370a and second pixel driving.According to more generally statement, selected k level scanning usefulness IC chip 33 by chip selection clock signal YECL and enable signal EOk-1 after, at first, the selection operation that first pixel driving is carried out successively with the capable pixel circuit 377 of p under the IC chipset 370a (the pixel driving IC chipset of (2k-1) row).After it finishes, to the selection operation that carries out successively with the capable pixel circuit 377 of the affiliated p of IC chipset 370b (the pixel driving IC chipset that (2k) is capable) with the second corresponding pixel driving of IC chip 33 with the scanning of k level.More than the corresponding image with the view data Xd that is provided by external device (ED) has been provided Cao Zuo result.

Use IC chip 33 and pixel driving with IC chip 37 according to the scanning of present embodiment, obtained following effect.

(1) be used for selecting successively the pixel counter 374 of each pixel circuit 377 and pixel decoder device 371 to be set at pixel driving IC chip 37, each pixel driving is connected to scanning IC chip 33 with IC chip 37 through scan control line group YLk.Therefore, that scan control line group YLk is set is dispensable to every row of each row pixel circuit 377.Its result compares with the prior art structure that every row to each row pixel circuit 377 is provided with sweep trace, and the radical of scan control line group YLk has tailed off, and scan control line group YLk has reduced in shared space.On the other hand, the radical of scan control line group YLk tails off, and just means by constituting identical space with prior art to form wide wiring.In this case, owing to reduced the impedance of wiring, even have under the situation of the big picture that is made of many pixels at for example electro-optical device D, also available good demonstration grade realizes the display device of high brightness.And, tailing off owing to be used for that driving IC chip is connected to pad (pad) number that scans with IC chip 33, pixel driving reduces with the size of IC chip 37.

(2) owing to carry out the test of each pixel circuit 377 by test signal TS, pixel driving can be done little with the pad (splicing ear) that organic EL 10 in the IC chip 37 is connected.That is, by when probe Mechanical Contact pixel driving is carried out the test of pixel circuit 377 with the pad of IC chip 37, be necessary with pixel driving with the pad of IC chip 37 contact with this probe make very big.In contrast, according to present embodiment, owing to the test pixels circuit 377 by the supply of test signal, pixel driving is dispensable with on 10 pads that should connect of organic EL it being contacted with probe in the IC chip 37.Therefore, compare with the needed size of contacting of probe, pixel driving can be very little with the pad of IC chip 37.By this, pixel driving is dwindled with the size of IC chip 37, and use the wiring number of IC chip 37 to reduce with IC chip 33 and each pixel driving, thereby realize more high resolving power owing to be used to connect scanning.

Fig. 5 example has represented that a scanning bears the structure of 2 row pixel driving with the control of IC chips 37 with IC chip 33, and still, the pixel driving that scanning is distributed with IC chip 33 is not limited to this with the number of IC chip 37.

＜column data conversion the formation of IC chip 〉

Below, the formation of each column data conversion with IC chip 35 is described.As shown in Figure 2, in the present embodiment, be provided with column data conversion IC chip 35 with IC chip 37 here by multiple row (hypothesis amounts to " s " row) pixel driving.Each column data conversion provides data-signal Dj with IC chip 37 contained pixel circuits 377 through data line DLj to these pixel driving with IC chip 35.

As shown in Figure 9, each column data conversion has the control circuit of enabling 351, first latch cicuit 353, second latch cicuit 354, D/A translation circuit 356 and reference current supply circuit 358 with IC chip 35.And, in Fig. 9, although only detailed icon the formation of first order column data conversion with IC chip 35, the later column data conversion in the second level also is identical formation with IC chip 35.

Each column data conversion is connected to control IC chip 31 with IC chip 35 through Data Control line LXD.This Data Control line LXD comprises enable signal line LXECL, viewdata signal line LXd, clock cable LXCL, reference current control line LBP and latch pulse signal line LLP.

Wherein enable signal line LXECL is used for providing the wiring that enable control signal XECL with the conversion of 31 pairs of first order column data of IC chip with the control circuit 351 that enables of IC chip 35 from control.Enable control circuit 351 and generate enable signal EN based on enabling control signal XECL.This enable signal EN represents to permit or disapprove the operation of first latch cicuit 353 and reference current supply circuit 358.Be output to input terminal with door 353a, 353b and 359 by enabling enable signal EN that control circuit 351 generates.

Each column data conversion is carried out cascade and is connected with the control circuit 351 that enables of IC chip 35 with 351 pairs of next stage column data of control circuit conversion that enables of IC chip 35.Under this constituted, the later column data conversion in the second level received respectively from the enable signal EN that enable control circuit 351 of prime column data conversion with IC chip 35 with the control circuit 351 that enables of IC chip 35, and based on this signal generation enable signal EN.

Connected on first latch cicuit 353 with the lead-out terminal of door 353a and with the lead-out terminal of door 353b.Wherein with on the input terminal of door 353a be transfused to from the view data Xd of control with IC chip 31 through viewdata signal line LXd.That is, and door 353a the logical and between enable signal EN and the view data Xd is outputed to first latch cicuit 353.In other words, just during enable signal EN is the H level, just pass through to be provided for first latch cicuit 353 with the view data Xd of IC chip 31 outputs from control with door 353a.On the other hand, with the input terminal of door 353b on be transfused to from the clock signal XCL of control through clock cable LXCL with IC chip 31.That is, and door 353b the logical and between enable signal EN and the clock signal XCL is outputed to first latch cicuit 353.In other words, just during enable signal EN is the H level, just pass through to be provided for first latch cicuit 353 with the clock signal XCL of IC chip 31 outputs from control with door 353b.Clock signal XCL is so-called point (dot) clock.Under above-mentioned formation, first latch cicuit 353 is preserved view data Xd synchronously and in proper order with clock signal XCL during enable signal EN is the H level.On the other hand, enable signal EN is turned to the L level in the moment that the view data Xd for " s " individual pixel circuit 377 is extracted first latch cicuit 353.Therefore, on first latch cicuit 353, just obtained view data Xd for " s " individual pixel circuit 377.

The lead-out terminal of first latch cicuit 353 is connected to the input terminal of second latch cicuit 354.On the other hand, the lead-out terminal of second latch cicuit 354 is connected to the input terminal of D/A translation circuit 356.On second latch cicuit 354, imported latch pulse signal LP from control with IC chip 31 through latch pulse signal line LLP.Latch pulse signal LP is the signal that is turned to the H level in the zero hour of horizontal scan period.The view data Xd of " s " individual pixel circuit 377 that second latch cicuit 354 keeps on first latch cicuit 353 at the rising edge of latch pulse signal LP is taken into simultaneously and the view data Xd that this is taken into is outputed to D/A translation circuit 356.Promptly carry out the serial conversion by first latch cicuit 353 and second latch cicuit 354.

D/A translation circuit 356 is as to the data-signal Dj of " s " data lines and the circuit of exporting with the electric current corresponding with 354 output image datas of second latch cicuit.That is, the view data Xd that D/A translation circuit 356 is exported second latch cicuit 354 is transformed into the data-signal Dj as simulating signal, and this data-signal Dj is outputed to data line DLj.D/A translation circuit 356 in the present embodiment is transformed into data-signal Dj based on the reference current Ir that reference current supply circuit 358 is provided with view data Xd.

As shown in Figure 9, on this reference current supply circuit 358, connected lead-out terminal with door 359.This with door 359 input terminal on, LBP has imported reference current write signal BP from control with IC chip 31 through the reference current control line.And the logical and between door 359 computing enable signal EN and the reference current write signal BP, and its result exported as control wave CP.In other words, only during enable signal EN was the H level, the reference current write signal BP process that control is exported with IC chip 31 just offered reference current supply circuit 358 as control wave CP with door 359.This reference current write signal BP is used to indicate the signal that reference current supply circuit 358 is generated reference current Ir.And, in the present embodiment, whether permit the generating run that is taken into operation and whether permits the reference current Ir that carries out according to reference current supply circuit 358 of the view data Xd that carries out according to first latch cicuit 353 by common enable signal EN control.But, also can adopt and control the structure of whether permitting these operations by other signal.

Figure 10 is the formation synoptic diagram of each column data conversion of expression with reference current supply circuit 358 in the IC chip 35.Although only show the first order and second level column data conversion contained reference current supply circuit 358 on the IC chip 35 among the figure, other column data conversion also is identical formation with the reference current supply circuit 358 of IC chip 35.After, the conversion of first order column data with contained reference current supply circuit 358 on the IC chip 35 only souvenir be " first order reference current supply circuit 358 ", on the later a plurality of column data conversion usefulness IC chips 35 in the second level contained reference current supply circuit 358 each all only souvenir be " the reference current supply circuit 358 that the second level is later ".

As shown in figure 10, each reference current supply circuit 358 has constant current source 3581, capacitor C1 and first～the 4th switchgear SW1～SW4.And each reference current supply circuit 358 has transistor T sw, T1, T2, T3, Tm.Transistor T sw wherein, T1, T2, Tm are respectively n channel-type FET (Field Effect Transistor: field effect transistor).On the other hand, transistor T 3 is p channel-type FET.

The formation of the reference current supply circuit 358 that the second level is later is identical with the formation of first order reference current supply circuit 358.But, in the second level later reference current supply circuit 358 and first order reference current supply circuit 358, the connection status difference of the 4th switchgear SW4.That is, in the first order reference current supply circuit 358, applied the power supply potential (VDD) of high-order side on the gate terminal of transistor T sw and the 4th switchgear SW4.Therefore, in the first order reference current supply circuit 358, transistor T sw becomes normally on, and on the other hand, the end of the drain terminal of transistor T m and the first switchgear SW1 often is connected through the 4th switchgear SW4.In contrast, in the later reference current supply circuit 358 in the second level, applied the power supply potential (earthing potential) of low level side on the gate terminal of transistor T sw and the 4th switchgear SW4.Therefore, in the later reference current supply circuit 358 in the second level, transistor T sw becomes normal cut-off state, and on the other hand, the end of the drain terminal of transistor T m and the first switchgear SW1 is often cut off.Therefore, in the later reference current supply circuit 358 in the second level, constant current source 3581, transistor T 1 and transistor T m be Attended Operation not.

Constant current source 3581 generates constant electric current I o, this steady current Io is offered the drain terminal of transistor T sw.The source terminal of this transistor T sw is connected to the drain terminal of transistor T 1.Transistor T 1 connects into diode, its source terminal ground connection.The gate terminal of transistor T 1 is connected to the gate terminal of transistor T m.Therefore, transistor T 1 and transistor T m constitute current mirror circuit.That is, flow to transistor T m with the steady current Io corresponding reference electric current I ref that on transistor T 1, flows.The source ground of transistor T m.

The drain terminal of transistor T m is connected to the end of the first switchgear SW1 through the 4th switchgear SW4.The other end of the first switchgear SW1 is connected on the drain terminal of the end of second switch device SW2 and transistor T 3.The other end of this second switch device SW2 is connected to the gate terminal of transistor T 3.The end of capacitor C1 is connected to the gate terminal of transistor T 3.The source terminal of the other end of capacitor C1 and transistor T 3 is connected to power lead.

On the other hand, the drain terminal of transistor T 3 is connected to the end of the 3rd switchgear SW3.The other end of the 3rd switchgear SW3 is connected to the drain terminal of transistor T 2.The source terminal ground connection of transistor T 2.

The first switchgear SW1 and second switch device SW2 according to control wave CP (CP1, CP2 ...) and be switched into any of on-state and off-state.More specifically, the first and second switchgear SW1, each of SW2 becomes on-state when control wave CP is the H level, and becomes off-state when control wave CP is the L level.

The 3rd switchgear SW3 according to control upset pulse signal CSW (CSW1, CSW2 ...) and be switched into any of on-state and off-state.This control upset pulse signal CSW is the signal that is delayed after the upset of the level of control wave CP.That is, to the gate circuit input control wave CP that is made of delay circuit 3586 and rejection gate 3585, its output signal is provided for the 3rd switchgear SW3 as control upset pulse signal CSW.More specifically, as shown in figure 11, control upset pulse signal CSW became the L level when control wave CP was the H level.At this moment, the 3rd switchgear SW3 becomes off-state.On the other hand, this control constantly of the delay a little after control wave CP is turned to L level upset pulse signal CSW becomes the H level.At this moment, the 3rd switchgear SW3 becomes on-state.

Under constituting shown in above, after enable signal EN and reference current write signal BP became the H level, control wave CP became the H level, the first and second switchgear SW1, and SW2 becomes on-state.At this moment, in first order reference current supply circuit 358, according to the electric current of sizing flows through transistor T m, the first and second switchgear SW1 by constant current source 3581 steady current that generates, SW2 puts aside on capacitor C1 corresponding to the electric charge of this electric current.On the other hand, because the 3rd switchgear SW3 becomes off-state, on transistor seconds T2, there is not electric current to flow through.

Then, after control wave CP is turned to the L level, the first and second switchgear SW1, SW2 becomes off-state, and the 3rd switchgear SW3 becomes on-state.Its result, the reference current Ir1 that the electric charge of putting aside on capacitor C1 is promptly corresponding with the grid voltage of transistor T 3 flows to transistor T 3.This reference current Ir1 is provided for transistor T 2.

On the other hand, the end of the first switchgear SW1 in the first order reference current supply circuit 358 is connected to the end of the 4th switchgear SW4 in the later whole reference current supply circuits 358 in the second level through reference current supply line Lr.Therefore, at the first and second switchgear SW1 of first order reference current supply circuit 358, SW2 becomes after the off-state, and whole reference current supply circuits 358 later to the second level are supplied with reference current Iref by reference current supply line Lr.Then, just put aside on the capacitor C1 of the later whole reference current supply circuits 358 in the second level with the corresponding electric charge of being supplied with by this reference current supply line Lr of reference current Iref.

Like this, in the present embodiment, be provided for the reference current supply circuit 358 of other column data conversion with IC chip 35 with the proportional reference current Iref of continuous current Io that is exported with the constant current source 3581 of IC chip 35 from a column data conversion.Therefore, the size of the reference current Ir that uses in IC chip 35 in whole column data conversion becomes equal.And, replace capacitor C1 shown in Figure 10, also can adopt other device with the function that keeps reference current Ir (for example for having the nonvolatile memory with the function of capacitor C1 equivalence).

Below, with reference to Figure 12 and Figure 13, the concrete formation of D/A translation circuit 356 is described.And although figure 12 illustrates the D/A translation circuit 356 of first order column data conversion with IC chip 35, other column data conversion also is same formation with the D/A translation circuit 356 of IC chip 35.

As shown in figure 12, each column data conversion has " s " individual D/A transformation component 356a of the radical that is equivalent to 35 distribute data lines of this column data conversion usefulness IC chip with the D/A translation circuit 356 of IC chip 35.Be provided for each of these " s " individual D/A transformation components 356a from the electric current I r1 of reference current supply circuit 358 output.Each D/A transformation component 356a receives the view data Xd corresponding with a pixel circuit 377 from second latch cicuit 354.Then, each D/A transformation component 356a is transformed into data-signal Dj based on electric current I r1 with this view data, and Dj outputs to data line XLj with the gained data-signal.And in the present embodiment, view data Xd is 6 bit data.

Figure 13 is the synoptic diagram that each D/A transformation component 356a of expression constitutes.As shown in FIG., D/A transformation component 356a has 6 transistor Tr c1～Trc6 and 6 transistor T s1～Ts6.

The gate terminal of transistor Tr c1～Trc6 is connected to the gate terminal of the transistor T 2 in the reference current supply circuit 358.Therefore, each of transistor Tr c1～Trc6 and transistor T 2 constitute current mirror circuit simultaneously.Constitute according to this, transistor Tr c1～Trc6 is as the function of exporting the constant current source of rated current value respectively.In the present embodiment, for the output current that makes transistor Tr c1～Trc6 than (Ia: Ib: Ic: Id: Ie: If) become 1: 2: 4: 8: 16: 32, the size of selected each transistor Tr c1～Trc6.

The drain terminal of transistor T s1～Ts6 is connected respectively to transistor Tr c1～Trc6.The source terminal of transistor T s1～Ts6 is connected on the data lines XLj.On the other hand, each position from the view data Xd of second switch circuit 354 output is provided for transistor T s1～Ts6 respectively.Particularly, the lowest order of view data Xd offers transistor T s1, and the most significant digit of view data Xd offers transistor T s6.Constitute according to this, any one of on-state or cut-off state is provided into according to each of the view data that provides from second latch cicuit 354 transistor T s1～Ts6.

Under above-mentioned formation, the electric current of exporting from transistor Tr c1～Trc6 is provided for the data line XLj that selects according to the state of transistor T s1～Ts6.Its result, the electric current corresponding with the content of view data Xd flows to data line XLj as data-signal Dj.As from the output current of above-mentioned each transistor Tr c1～Trc6 than what learn, the current value of data-signal Dj can adopt 64 kinds of values.Therefore, the brightness of organic EL 10 is controlled so as to 64 grades according to 6 bit image data Xd.

＜column data conversion the operation of IC chip 35 〉

Below, be described in detail in the supply operation of the data-signal Dj that carries out under the structure shown in above-mentioned.As above-mentioned, during writing, data select each pixel circuit 377 successively.Then, in order to carry out successively in a whole frame (vertical scanning period) with the scan-synchronized of pixel circuit 377 from the supply of column data conversion with the data-signal Dj of 35 pairs of each pixel circuits 377 of IC chip.In the present embodiment, as shown in figure 11, among during each data writes during on be the charging of carrying out capacitor C1 in each reference current supply circuit 358 during the part of each frame in (being called " during the setting " later on) successively.And, data-signal is offered pixel circuit 377 during beyond during in carry out the demonstration of image.That is, during setting and also carry out the demonstration of image in data any one during writing.

At first, during setting after the beginning, the reference current write signal BP that is provided with IC chip 35 in the conversion of first order column data and all be turned to the H level by the enable signal EN that enables control circuit 351 generations.Make by this after control wave CP1 develops into the H level, the first and second switchgear SW1 in the first order reference current supply circuit 358, SW2 becomes on-state.On the other hand, as shown in figure 11, along with the level upset of control wave CP1, control upset pulse signal CSW1 is turned to the L level.Therefore, the 3rd switchgear SW3 in the first order reference current supply circuit 358 becomes off-state.Its result, the electric charge corresponding with the constant current Io that supplies with from constant current source 3581 put aside on the capacitor C1 of first order reference current supply circuit 358.

Then, as shown in figure 11, control wave CP1 is turned to the L level.By this, the first and second switchgear SW1 in the first order reference current supply circuit 358, SW2 becomes off-state.At this moment, control upset pulse signal CSW1 is turned to the H level.Therefore, the 3rd switchgear in the first order reference current supply circuit 358 becomes on-state.Its result, the charging of the capacitor C1 in the first order reference current supply circuit 358 finishes.

Then, the reference current write signal BP that is provided with IC chip 35 in second level column data conversion and all be turned to the H level with the enable signal EN that control circuit 351 generates that enables of IC chip 35 by its column data conversion.Make by this after control wave CP2 is turned into the H level, the first and second switchgear SW1 in the second level reference current supply circuit 358, SW2 becomes on-state.At this moment, control upset pulse signal CSW2 is turned into the L level, and the 3rd switchgear in the second level reference current supply circuit 358 becomes off-state.Its result is provided for second level column data conversion IC chip 35 with the constant current Io corresponding reference electric current I ref in the IC chip 35 through reference current supply line Lr with the conversion of first order column data.Then, corresponding with this reference current Iref electric charge is charged on the capacitor C1 of second level column data conversion with IC chip 35.

Then, as shown in figure 11, control wave CP2 is turned to the L level, and control upset pulse signal CSW2 is turned to the H level.By this, the first and second switchgear SW1 in the second level reference current supply circuit 358, SW2 becomes off-state, and the 3rd switchgear SW3 becomes on-state.Its result, the charging of the capacitor C1 in the second level reference current supply circuit 358 finishes.

After this, also carry out same operation in other column data conversion in IC chip 35.Its result, and is put aside on the capacitor C1 of the later whole reference current supply circuits 358 in the second level by the first order reference current supply circuit 358 corresponding electric charges of reference current Iref that provide at the finish time during setting.That is, the reference current Iref that provided of first order reference current supply circuit 358 is sequentially copied to the capacitor C1 of each reference current supply circuit 358 by the time-division.Although the situation during example illustrates every frame setting once set in the present embodiment also can adopt the formation during a plurality of frame settings are once set.Perhaps, also can adopt the structure of giving the capacitor C1 charging of each reference current supply circuit 358 in (be equivalent to line sequential scanning return line during) during the gap of D/A translation circuit 356 outputting data signals Dj.That is, in multiframe, disperseed to be provided with during once setting and be fine, in an image duration, disperseed to be provided with and also be fine, still, during returning line, carried out the charging of capacitor C1 in wishing during setting.

On the other hand, during the data during then setting write in, with the scan-synchronized of each row pixel circuit 377, carry out the output of data-signal with IC chip 35 by the column data conversion.Promptly, each column data conversion with IC chip 35 in, will reference current Ir (Ir1, the Ir2 corresponding with the electric charge of reference current supply circuit 358 capacitor C1, ...) generate data-signal Dj as reference value, and offer the present selected pixel circuit 377 of this data-signal Dj.About the operation of the operation of scanning element circuit 377 and the pixel circuit 377 that is accompanied by is same as described above.

Column data conversion IC chip 35 according to present embodiment has obtained following effect.

(1) in the present embodiment, the later whole reference current supply circuits 358 in 358 pairs of second level of first order reference current supply circuit provide reference current Iref.Then, each reference current supply circuit 358 offers D/A translation circuit 356 with the reference current Ir corresponding with this reference current Iref.Constitute according to this, the size of reference current Ir becomes identical in the whole reference current supply circuit 358.Therefore, suppressed from the output error of each column data conversion with the data-signal Dj of IC chip output.Its result in display image, can prevent to take place the improper situation of nicking on the part on the border that is equivalent to column data conversion usefulness IC chip 35.

(2) in the present embodiment, the conversion of first order column data is identical structures with the later column data conversion in the IC chip 35 and the second level with IC chip 35.Therefore, when making electro-optical device D, there is no need to distinguish the first order column data conversion later column data conversion IC chip 35 of the IC chip 35 and the second level.Therefore, use IC chip 35 to export the structure of reference current Irefs with IC chip 35 to other column data conversion though adopt from the conversion of first order column data, compare with the electro-optical device of prior art, its manufacturing cost can not increase considerably.

And, as being arranged on pixel driving, D/A translation circuit 356 and reference current supply circuit 358 also be fine with the structure in the IC chip 37, also can obtain and above-mentioned same effect by this structure.

＜B: the stromatolithic structure of electro-optical device and manufacture method 〉

Below, the stromatolithic structure of electro-optical device D of the present invention and its manufacture method are described.Below, example shows 3 kinds of different electro-optical device D of manufacture method respectively, and each stromatolithic structure and manufacture method have been described.And, below, in pixel driving with IC chip 37, control with IC chip 31, scanning with IC chip 33 and column data conversion with each of IC chip 35 not especially under situation of difference, these all are " IC chip 30 " by the general name souvenir.

＜according to the stromatolithic structure of first manufacture method 〉

At first, with reference to Figure 14, the stromatolithic structure of the electro-optical device D that obtains according to first manufacture method is described.As shown in the figure, electronic unit layer 3 comprises basalis 301, metal level 302, IC chip 30 and packed layer 304.IC chip 30 shown in Figure 14 is pixel driving IC chips.

Basalis 301 is the layers that cover 6 one faces of whole support substrate, for example is made of insulativity materials such as monox, silicon nitride or oxidized silicon nitrides.This basalis 301 is to be used for preventing being sneaked into such as the electronic unit of pixel driving with IC chip 37 grades by the impurity of support substrate 6 strippings.

Metal level 302 is arranged on the layer above the basalis 301, is formed by the metal of for example copper (Cu) and golden (Au) etc.This metal level 302 comprises installation portion 302a and telltale mark 302b.Wherein installation portion 302a is the layer towards the light of IC chip 30 that also interdicts when being used for that support substrate 6 improved the connecting airtight property of IC chips 30 from support substrate 6 side incidents.Therefore, installation portion 302a is set to and the region overlapping that should dispose IC chip 30.By this installation portion 302a, prevented the faulty operation of the IC chip 30 that causes because of rayed.On the other hand, telltale mark 302b is the mark that is used for the relative position between IC chip 30 and the support substrate 6 is adjusted to desired locations.

IC chip 30 has a plurality of pad P as splicing ear.Each IC chip 30 is configured on the installation portion 302a towards the state with the opposite side of support substrate 6 pad P is formed face (being called " pad formation face " later on).Pad in this IC chip 30 forms the face of opposite side of face promptly according to being provided with metal level 30a at the face of support substrate 6 vis-a-vis on (being called " substrate face " later on) in the installation steps on the support substrate 6.

Figure 15 is the expression pixel driving forms face with the pad of IC chip 37 a planimetric map.As shown in the figure, pixel driving is divided into the first pad P1 and the second pad P2 that varies in size with a plurality of pad P set on the IC chip 37.Wherein the second pad P2 is the terminal that is used for pixel driving is connected to IC chip 37 other IC chip (control IC chip 31, scanning IC chip 33 and column data conversion IC chip 35) and power lead.Make each second pad P2 do very greatly because of probe Mechanical Contact when checking pixel driving with IC chip 37.Particularly, the flat shape of each second pad P2 is that the length of vertical and horizontal all is the rectangle of 70 μ m (micron)～100 μ m sizes.On the other hand, the first pad P1 is the terminal that is used for pixel driving is connected to IC chip 37 organic EL 10.Each first pad P1 is littler than the second pad P2.Particularly, the flat shape of each first pad is that the length of vertical and horizontal all is the rectangle of 10 μ m～30 μ m sizes.

According to above-mentioned, the pixel driving of present embodiment has 2 kinds of pad P that vary in size with IC chip 37.Therefore, by being to compare with the situation of the identical size of second pad with whole pad P, the area that the pad in each IC chip 30 can be formed face is done little.Especially, because an electro-optical device D is provided with a plurality of pixel driving IC chip 37, each pixel driving can help the minimizing of whole electro-optical device D size with the minimizing of the size of IC chip 37.In order to obtain this effect, wish the area of first pad is made 1/50～1/6 of second bonding pad area.And, control with IC chip 31, scan with IC chip 33 and column data conversion and be and the identical size of above-mentioned second pad with the pad of IC chip 35.But the pad of part or all of these IC chips also is fine as the size identical with above-mentioned first pad.

As shown in figure 14, packed layer 304 is layers that the zone between each IC chip 30 is provided with.That is, packed layer 304 section that is provided for filling up between the pad formation face of surface (more specifically being the surface of basalis 301) at support substrate 6 and IC chip 30 is poor.This packed layer 304 is formed by the material with high-cooling property.Particularly, packed layer 304 for example is made of copper (Cu), nickel (Ni) or tin metals such as (Sn).By this, improved the thermal uniformity of whole electro-optical device D, eliminated the improper situation that causes because of heat.

Then, wiring cambium layer 2 comprises first insulation course 41, first wiring layer 43, second insulation course 45, second wiring layer 47, anode layer 49, the 3rd insulation course 50, storage lattice cofferdam (bank) layer, conductive layer 54, restraining barrier 56 and cathode layer 58.Wherein first insulation course 41, second insulation course 45 and the 3rd insulation course 50 are made of material that for example comprises inorganic silicon or organic material with heat impedance more than 300 ℃.At least the first insulation course 41 is made of one or more materials of selecting among polyarylether resinoid (for example SiLK), aryl oxide resinoid, aromatic polymer, polyimide, fluoridize polyimide, fluororesin, benzocyclobutene, polyphenylene resinoid, polyparaphenylene resin in these insulation courses.On the other hand, second insulation course 45 and the 3rd insulation course 50 are by material or TEOS (tetraethyl the silicyl oxide)/O same with first insulation course 41 ₂Film or be called the SiO of glass spin coating (spin on glass) film (SOG) ₂Film constitutes.In optimal way, first insulation course 41 and second insulation course 45 are made of the insulating material of low conductivity.According to this, crosstalking between can suppressing to connect up.

First insulation course 41 is the layers that cover the whole support substrate 6 that is provided with IC chip 30 and packed layer 304.In this first insulation course 41, with the pad P lap of each IC chip 30 on be provided with contact hole (contact hole) 41a.Even the openings of sizes of each contact hole 41a is to depend on that the pad P that also makes each IC chip 30 under the situation that produces foozle (the sum of errors contact hole 41a of IC chip configuration position is provided with the error of position) exposes through contact hole 41a.As above-mentioned, first pad of IC chip 30 and varying in size of second pad.Therefore, the size of the opening of the contact hole 41a corresponding with first pad and with the varying in size of the opening of the corresponding contact hole 41a of second pad.Particularly, under the length of the vertical and horizontal of the first pad P1 all is situation about 16 μ m, wish that the length of the vertical and horizontal of contact hole 41a its opening corresponding with this pad P1 all is about 4 μ m.On the other hand, under the length of the vertical and horizontal of the second pad P2 all is situation about 80 μ m, wish that the length of the vertical and horizontal of contact hole 41a its opening corresponding with this pad P2 all is about 60 μ m.

First wiring layer 43 also is electrically connected to the pad P of each IC chip 30 on be arranged at first insulation course 41 through contact hole 41a.First wiring layer 43 is made of the metal that for example electric conductivity such as aluminium and aluminium-containing alloy is high.This first wiring layer 43 comprises anode wiring 43a and cathode power line 43b.Wherein anode wiring 43a is connected to anode layer 49.On the other hand, cathode power line 43b is connected on the cathode layer 58 of organic EL 10.First wiring layer 43 comprises and is used for data-signal Dj is offered the data line DL of pixel circuit 377 with IC chip 35 and is used for data controlling signal XD (with reference to figure 9) is offered with IC chip 31 from control the Data Control line LXD etc. of column data conversion usefulness IC chip 35 from the column data conversion.

Second insulation course 45 is set to cover the surface of first insulation course 41 that is provided with first wiring layer 43.In this second insulation course 45, with 43 1 overlapping parts of first wiring layer on be provided with contact hole 45a.On the other hand, second wiring layer 47 on be arranged at second insulation course 45 in, conduct by the contact hole 45a and first wiring layer 43.This second wiring layer 47 is made of the metal of the high conductivity identical with first wiring layer 43.Second wiring layer 47 of present embodiment is the rhythmo structure of the layer that is made of aluminium and the layer that is made of titanium (Ti).According to this structure,, can avoid owing to the oxide that uses as anode layer 49 makes the oxidized situation of aluminium lamination because aluminium lamination is covered by titanium layer.

This second wiring layer 47 comprises the scan control line group YL that uses IC chip 37 from scanning with IC chip 33 to pixel driving.And second wiring layer 47 comprises and is used for and will forces cut-off signals Doff to offer pixel driving with the wiring of IC chip 37 be used for various signals (reset signal RSET, clock signal YSCL and chip are selected clock signal YECL) are offered with IC chip 31 from control and scan the wiring of using IC chip 33 from control with IC chip 31.Connecting the column data conversion in second wiring layer 47 forms with vertical in form with being connected in the wiring of IC chip 37 and first wiring layer 43 to scan with the wiring with IC chip 37 of IC chip 33 and pixel driving with IC chip 35 and pixel driving.

Applying the power lead of power supply potential of high-order side and the appropriate combination of power lead by first wiring layer 43 and second wiring layer 47 that applies the power supply potential (earthing potential) of low level side forms.Here, Figure 16 is the planimetric map of expression electro-optical device D structure.The sectional view of seeing from the XIVA-XIVB line among the figure is equivalent to Figure 14.As shown in figure 16, the power lead L of first wiring layer 43 and second wiring layer, 47 formations is arranged in the gap of matrix form organic EL 10 side by side.Therefore, the flat shape of power lead L is cancellate.

Anode layer 49 is arranged on the surface of second wiring layer 47.This anode layer 49 comprises anode portion 49a and middle interconnecting piece 49b.Wherein anode portion 49a is formed in the layer under the aftermentioned EL layer 13.Therefore, anode portion 49a is set on the position corresponding with a plurality of organic EL 10 and is arranged into matrix shape.On the other hand, middle interconnecting piece 49b is the layer that is used to connect the anode layer 58 and first wiring layer 43.This middle interconnecting piece 49b is positioned on the gap of each organic EL 10.Particularly, as shown in figure 16, middle interconnecting piece 49b is arranged in the gap of 2 organic ELs 10 that vergence direction adjoins each other.Therefore, a plurality of middle interconnecting piece 49b become matrix shape side by side.But middle interconnecting piece 49b can be omitted suitably according to the used current value of the driving of organic EL 10.

Tin indium oxide) and the compound (In of indium oxide and zinc paste this anode layer 49 is for example by the compound of indium oxide and tin oxide (ITO: ₂O ₃-ZnO) or the big conductive material of gold (Au) and so on work function constitute.And because the light that sends from organic EL 10 is shone the opposite side of anode layer 49, anode layer 49 there is no need to have light transmission.

Then, the 3rd insulation course 50 is set to cover second insulation course 45 that is provided with second wiring layer 47 and anode layer 49.The 3rd insulation course 50 has pixel peristome 50a and negative electrode contact site 50b.Wherein pixel peristome 50a be in the anode layer 49 with anode portion 49a corresponding opening part.On the other hand, negative electrode contact site 50b be in the anode layer 49 with middle interconnecting piece 49b corresponding opening part.

Storage lattice cofferdam (bank) layer 52 is the layers that cover the surface of second insulation course 45 that has formed the anode layer 49 and second wiring layer 47.This storage lattice cofferdam layer 52 for example is made of the organic resin material of photosensitive polyimide, propylene, polyamide and so on.Storage lattice cofferdam layer 52 is the layers that are used to be spaced from each other between the organic EL 10 of adjacency.Therefore, storage lattice cofferdam layer 52 has corresponding with organic EL 10 and the pixel peristome 52a of opening.Storage lattice cofferdam layer 52 in the present embodiment has the negative electrode contact site 52b that is used for cathode layer 58 is conducting to second wiring layer 47.As shown in figure 16, this negative electrode contact site 52b is for and the part of opening corresponding with middle interconnecting piece 49b.

Conductive layer 54 be used for 47 1 ones of second wiring layers be connected with cathode layer 58 the layer.Particularly, conductive layer 54 arrives the surface of second wiring layer 47 from the surface of storage lattice cofferdam layer 52 by the negative electrode contact site 50b that gets involved negative electrode contact site 52b and the 3rd insulation course 50.These conductive layer 54 metals by high conductivity such as aluminium alloys form.Restraining barrier 56 is the layers that are used to prevent conductive layer 54 oxidations, and it is set to cover whole conductive layer 54.This restraining barrier 56 for example has the rhythmo structure of layer that is made of titanium and the layer that is made of gold.

Then, cathode layer 58 is arranged on the EL layer 13 lip-deep layer that constitute organic EL 10.This cathode layer 58 by getting involved restraining barrier 56 and conductive layer 54 with 47 conductings of second wiring layer.Cathode layer 58 has the character (transparency) that organic EL 10 issued lights are seen through.In optimal way, cathode layer 58 is formed by the low material of work function.Particularly, cathode layer 58 have first film that constitutes by lithium fluoride (LiF) and barium fluoride, the rhythmo structure of second film that constitutes by calcium (Ca), the tertiary membrane that constitutes by gold.Wherein the material of first film and second film wish metal under II family from the periodic table of elements or the III family and comprise the alloy of this metal or compound among select.On the other hand, tertiary membrane is the film that is used to reduce the impedance of first film and second film.As the material of this tertiary membrane, except that Au, also can adopt Pt, Ni or Pb.Tertiary membrane can be formed by the oxide that comprises In, Zn or Sn.

Organic EL layer 1 comprises EL layer 13 and sealant 15.Wherein EL layer 13 is made of known EL material.That is, EL layer 13 has the rhythmo structure that is made of by known technology hole injection layer, hole transmission layer, luminescent layer, electron transfer layer and electron injecting layer.This EL layer 13 is set to occupy between wiring cambium layer 2 contained anode layers 49 (anode portion 49a) and the cathode layer 58.Under this constitutes, after electric current flows through, from EL layer 13, send light between anode layer 49 and cathode layer 58 by the compound of hole and electronics.As the material of EL layer 13, also can use any of inorganic EL material and organic EL Material.And, to organic EL Material, low molecular material and macromolecular material are arranged.

Sealant 15 is the layers that are used for EL layer 13 and outside blocking.In order to make the light that is sent from EL layer 13 shine the outside, sealant 15 has light transmission.Sealing layer 15 has the structure of a plurality of flattening resin layers 151 and a plurality of restraining barriers 152 mutual laminations.Wherein flattening resin layer 151 is by forming propylene class and ethene row resin monomer or resin oligomer polymerization sclerosis.And restraining barrier 152 is by Al ₂O ₃And SiO ₂, (metal) oxide such as nitride film constitutes.The structure of pasting protective material above sealing layer 15 also is fine.Perhaps, pasting protective material replaces the structure of sealant 15 shown in Figure 14 also to be fine.As this protective material, for example can use tabular (perhaps film shape) the portion's material that constitutes by glass and rigid plastic etc. with light transmission.

＜the first manufacture method 〉

Below, the manufacture method of electro-optical device D shown in Figure 14 is described.

At first, as shown in figure 17, on a face of support substrate 6, form basalis 301.This basalis 301 is for example by according to the plasma CVD method and the cvd silicon oxide resin obtains.The thickness of this basalis 301 is 100nm (nanometer)～300nm.Then, formation metal level 302 on basalis 301.That is, at first,, form the metal film that constitutes by copper and gold etc. by sputter in order to cover whole basalis 301.Then, metal film is applied the pattern that uses photoetching technique and form (patterning) processing and etching (etching) processing.By this, as shown in figure 17, obtained to comprise the metal level 302 of installation portion 302a and telltale mark 302b.

Then, as shown in figure 18, each IC chip 30 (be here pixel driving with IC chip 37) is configured on the installation portion 302a with the form that pad formed the opposition side facing support substrate 6.It is that ± 5 μ m are with interior high precision nude film fitting machine that installation accuracy is used in the configuration of this IC chip 30.And, adjust relative position relation between each IC chip 30 and the support substrate 6 by observing telltale mark 302b.

On each IC chip 30, implement processing shown below in advance.That is, on the wafer (wafer) before cutting apart IC chip 30, be equivalent to stick boundary belt (tape) (not shown) on the face of its substrate face by cutting (dicing).This boundary belt is made of the material with UV cured property.Therefore, on the pad formation face of each IC chip 30 that installation portion 302a is disposed, stick boundary belt.On the other hand, in the wafer, on the face of the pad formation face that is equivalent to each IC chip 30, implement to grind.Grind by this, each IC chip 30 becomes the thickness that is suitable for forming wiring cambium layer 2.Particularly, the thickness of IC chip 30 is 100 μ m following (being more preferably 25 μ m～30 μ m).And, on being equivalent to the face that pad forms face, form metal level 30a after, cut crystal.And, in other form, replace metal level 30a, stick chips welding band (die bonding tape).

Then, as shown in figure 19,, form packed layer 304 in order to fill up the gap of each IC chip 30 of configuration on support substrate 6.This packed layer 304 obtains by the plating that IC chip 30 is used as mask.Packed layer 304 forms thinner than each IC chip 30.Particularly, packed layer 304 forms than IC chip 30 thin about 0.1 μ m～3 μ m.

After this, remove the boundary belt of on the substrate face of each IC chip 30, being pasted.Particularly, at first, with the substrate face of ultraviolet ray irradiation IC chip 30.By this, the bonding force of boundary belt is descended.Then, by removing boundary belt on the substrate face that organic solvent is coated in IC chip 30 fully.

Then, as shown in figure 20, form first insulation course 41 in order to cover the whole support substrate 6 that is provided with IC chip 30 and packed layer 304.That is, at first, by using TEOS/O ₂The plasma CVD method, form to cover the dielectric film of whole support substrate 6.The thickness of this dielectric film is the degree of 400nm～900nm.Because of forming under the not enough situation of wiring, make the dielectric film planarization in the flatness of the dielectric film that forms by this method by CMP (cmp) method.This dielectric film also can be by insulating material coating and fire formation.That is, with silanol (Si (OH) ₄) solution that is dissolved in alcohol is coated on the support substrate 6, obtains dielectric film by baking on 400 ℃ temperature.Through above-mentioned operation, each IC chip 30 is molded on the support substrate 6.

Then, as shown in figure 20, form contact hole 41a by removing part corresponding in this dielectric film with the pad of IC chip 30.These contact holes 41a forms processing by the pattern that uses photoetching technique and etch processes is unified to form.By above operation, obtained first dielectric film 41.And, making after the surface of pad P exposes by getting involved contact hole 41a, the oxide film that forms on this pad P surface is removed by contrary sputter.

Then, as shown in figure 21, formation first wiring layer 43 on first insulation course 41.That is, cover first insulation course 41 and form metal film.This metal film for example obtains by the sputtering sedimentation aluminium alloy.The thickness of metal film is the degree of 300nm～500nm.This metal film arrives IC chip 30 pad P surfaces through contact hole 41a.Then, implement to use the pattern of photoetching technique to form processing and etch processes to metal film.By this, as shown in figure 21, obtained to comprise first wiring layer 43 of anode wiring 43a and cathode power line 43b.First wiring layer 43 also can form by ink-jet (ink jet) technology.That is, the China ink that will comprise metal particle is ejected on the support substrate 6 from ink gun, should obtain first wiring layer 43 by China ink by the thermal treatment drying.

Then, as shown in figure 22, as the surface that first wiring layer 43 covers first insulation course 41 that is formed, form second insulation course 45.This second insulation course 45 is formed by the method identical with above-mentioned first insulation course 41.That is, at first, form dielectric film by plasma CVD method or sputtering method.The thickness of this dielectric film is the degree of 500nm～900nm.Under the not enough situation, make flattening surface owing to form anode in the flatness of this dielectric film by the CMP method.Then, in this dielectric film by with an equitant part of first wiring layer 43 on the unified contact hole 45a that forms obtain second insulation course 45.With anode wiring 43a and equitant part of cathode power line 43b on form this contact hole 45a.

Then, as shown in figure 23, the metal film 701 that becomes second wiring layer 47 is formed and covers whole second insulation course 45.This metal film 701 is by for example sputter and vacuum vapour deposition or above-mentioned ink ejecting method formation.Metal film 701 for example has first film that forms and second film that covers this first film on second insulation course 45.Wherein first film is formed the thickness of 300nm～500nm degree by for example aluminium alloy.On the other hand, second film is formed the thickness of 50nm～100nm degree by for example titanium.After this, as shown in Figure 2, form the anode material film 702 that covers metal film 701.This anode material film 702 is formed the thickness of 50nm to the 150nm degree by for example sputter.

Then, form and etching, selectively remove the part of anode material film 702 and metal film 701 by the pattern that uses photoetching technique.By this, as shown in figure 24, second wiring layer 47 and anode layer 49 have been obtained.Wherein anode layer 49 has to become and is positioned at the anode portion 49a under the EL layer 13 and becomes the middle interconnecting piece 49b that is positioned at organic EL 10 gaps.

After this, as shown in figure 25, form the 3rd insulation course 50.That is at first, be the thickness of 150nm～300nm degree, by plasma CVD method cvd silicon oxide resin.Then, in this silica resin film, obtain the 3rd insulation course 50 by selectively removing the zone suitable with negative electrode contact site 50b with pixel peristome 50a according to photoetching technique.When selecting to remove silica resin, also remove near the part being positioned at around the support substrate 6 in the silica resin.

Then, as shown in figure 26, become the resin molding 705 of storage lattice cofferdam layer 52.Particularly, by applying organic material such as photosensitive polyimide, propenyl, polyamide and obtaining resin molding 705 by heating this organic material that hardens.The thickness of this resin molding 705 is degree of 1.0 μ m～3.5 μ m.In order to interdict the light towards the IC chip that sends from EL layer 13, resin molding 705 is opaque in completion status.After this, apply the pattern that uses photomask at resin molding 705 and form processing and development treatment, and anticathode contact site 52b opening.Its result as shown in figure 26, exposes the middle interconnecting piece 49b of cathode layer 49.And, when forming negative electrode connecting portion 52b, also remove near the part being positioned at around the support substrate 6 in the resin molding 705.

Then, as shown in figure 27, by resin molding 705 is carried out the part that middle interconnecting piece 49b is removed in etching as mask.Its result, the restraining barrier (Ti layer) of exposing second wiring layer 47.After this, as shown in figure 28, form the metal film 707 that constitutes conductive layer 54.This metal film 707 obtains by metals such as sputtering sedimentation aluminium.The thickness of metal film 707 is the degree of 300nm～500nm.Then, as shown in figure 28, become the metal film 708 on restraining barrier 56.This metal film 708 is films as thin as a wafer of being made of titanium and is the rhythmo structure of the film of 5nm～15nm degree by the thickness that gold constitutes.This metal film 708 forms by for example sputter.Then, implement to use the pattern of photomask to form processing and etch processes to metal film 707 and metal film 708.By this, as shown in figure 29, obtain conductive layer 54 and restraining barrier 56.And after this operation, for the part outside the negative electrode contact site 52b in the overlay tree adipose membrane 705, the no reflection events layer that black is set also is fine.This no reflection events layer is the low layer of light reflectivity (being the high layer of absorptivity), for example by CrO ₃, MnO ₂, Mn ₂O ₃, NiO, Pr ₂O ₅Constitute Deng oxide and the resin material that comprises carbon particle.

Then, resin molding 705 is applied with exposure and the development of conductive layer 54 as mask.As a result, as shown in figure 30, above anode portion 49a, be provided with pixel section peristome 52a among the resin bed 705.Then, fix storage lattice cofferdam (bank) shape by baking of resin film 705.Obtain storing lattice cofferdam layer 52 by above operation.Then, storage lattice cofferdam layer 52 is applied tetrafluoromethane is introduced lyophobic group after as the Cement Composite Treated by Plasma of reacting gas on this surface.By this, the surface of storage lattice cofferdam layer 52 is rendered as lyophobicity.On the other hand, owing to do not introduce lyophobic group on the 3rd insulation course 50 and anode layer 49, the surface of these layers presents lyophily.

Below, as shown in figure 31, in the pixel peristome 52a of storage lattice cofferdam layer 52, form EL layer 13.Under the situation that EL layer 13 is formed by macromolecular material, at first, apply for example PEDO (polythiophene)/PSS or PAni (polyaniline) as hole injection layer.Then, for overlapping with this hole injection layer, coating will be dissolved in solution in the solvent such as luminescent materials such as polyparaphenylene-1,2-ethenylidene (polypara-phenylenevinylene:PPV) class, Polyvinyl carbazole (polyvinylcarbazole:PVK) class or poly-fluorenes (polyfiuorene) classes.As above-mentioned, the surface of the 3rd insulation course 50 and anode layer 49 presents lyophily, and on the other hand, the surface of storage lattice cofferdam layer 52 is rendered as lyophobicity.Therefore, the liquid of EL layer 13 is trapped in the pixel peristome 52a of storage lattice cofferdam layer 52 effectively.And, under the situation that EL layer 13 forms by macromolecular material, when it forms, can use ink-jet method and straightforward procedures such as printing, spin-coating method.On the other hand, under the situation that EL layer 13 forms by low molecular material, when it forms, can utilize the vapour deposition method of use shield mask (shadow mask) or transfer printing etc.To the pixel peristome 52a of each storage lattice cofferdam layer 52,, then can coloredly show if formed the EL layer 13 of any light that is used to send three primary colours.Perhaps, forming chromatic filter above the EL of the coloured light that turns white layer 13 also is fine.Certainly, also be fine as only sending monochromatic structure.

Below, shown in figure 32, form cathode layer 58 and cover whole storage lattice cofferdam layer 52 and EL layer 13.That is, the film formation device by multi-cavity chamber mode (cluster tool mode) carries out continuous evaporating-plating in a vacuum.As a result, formed cathode layer 58, it has by alkaline metal such as thin as a wafer BaF and LiF fluoridizes the rhythmo structure that the Au film of the Ca film of film, about 10nm～20nm and about 2nm～15nm constitutes.And the formation of this cathode layer 58 is to carry out after the organic material low by thermotolerance formed EL layer 13.Therefore, wish cathode layer 58 film forming in low temperature environment as far as possible.

After this, as shown in figure 14, form the sealant 15 that comprises planarization resin bed 151 and restraining barrier 152.Particularly, at first, the monomer or the oligomer of spray in a vacuum propylene base class and resin such as vinyl-based, anticathode layer 58 usefulness resin apply.Then, to this resin bed irradiation ultraviolet radiation.By obtaining above-mentioned smooth resin bed 151 behind this polymerization hard resin-layer.Then, on the surface of planarization resin bed 151, form Al by various one-tenth embrane methods ₂O ₃And SiO ₂The film of quasi-metal oxides, obtain restraining barrier 152.This film forming can be used vacuum vapour deposition and sputtering method, perhaps the various one-tenth embrane methods of ion plating and so on.In the present embodiment, this planarization resin bed 151 and restraining barrier 152 are gone through repeatedly and are formed.As a result, as shown in figure 14, a plurality of planarization resin beds 151 and a plurality of restraining barrier 152 mutual stacked sealants 15 have been obtained.After this, on surface, paste protective material as the restraining barrier 152 of the superiors.Make electro-optical device D by above-mentioned operation.

According to first manufacture method, can obtain following effect.

(1) owing to stack gradually and obtain electro-optical device D, the simplification of manufacturing process and the reduction of manufacturing cost have been realized by electronic unit layer 3, wiring cambium layer 2 and organic EL layer 1 being amounted to 3 layers.And, because each layer is stepped construction very close to each other, therefore can obtain the light electro-optical device of extremely thin (thickness 1mm (millimeter)).

(2) pixel driving that comprises the pixel circuit 377 that is used to drive organic EL 10 is arranged on electronic unit layer 3 with IC chip 37, and on the other hand, organic EL 10 is set in place on the organic EL layer 1 of electronic unit layer 3 top.Therefore, should dispose the position of organic EL 10 time, unnecessary consideration should be disposed the space of pixel circuit 377 selected.That is, be not subjected to the restriction that causes by pixel circuit 377, thereby can improve aperture opening ratio.

(3) owing to formed various wirings in unification on the wiring cambium layer 2 between electronic unit layer 3 and the organic EL layer 1, compare with the situation that on electronic unit layer 3 or organic EL layer 1, comprises these wirings, can improve the degree of freedom of layout (1ayout) design.

The contact hole 41a of (4) first insulation courses 41 forms by photoetching technique is unified, unified first wiring layer 43 that forms in order to fill up this contact hole 41a.Therefore, even the first pad P1 of IC chip 30 is microsizes of vertical 16 μ m * horizontal 16 μ m, each first pad P1 also can unify reliable the connection with first wiring layer 43.Even since the number of pad P how also to make with connect up between to be connected the needed time constant, sought the raising of production efficiency and the densification of wiring.

The stepped construction of＜the second manufacture method 〉

Below, with reference to Figure 33, the stepped construction of the electro-optical device D that obtains by second manufacture method is described.In each one, the part identical with the electro-optical device D of first manufacture method adopts and the common symbol of each of Figure 14 shown in the figure.It is as shown in figure 16 that the plane of electro-optical device D constitutes.Electro-optical device D shown in Figure 33 has the same structure with electro-optical device D shown in Figure 14 except the structure of electronic unit layer 3.

As shown in figure 33, the electronic unit layer 3 of this electro-optical device D comprises packed layer 305, light shield layer 306, basalis 307 and IC chip (being pixel driving IC chip 37 here).Wherein packed layer 305 is provided with on whole of support substrate 6 for the gap of filling up each IC chip 30.Packed layer 305 is formed by the material with high-cooling property.By this, improved the generation of the improper situation that the thermal uniformity and can suppressing of whole electro-optical device D causes because of heat.Packed layer 305 is formed by the material that thermal expansivity and IC chip 30 are similar to.Therefore, suppressed between packed layer 305 and the IC chip 30 generation of the thermal stress that the difference because of linear expansion coefficient causes.Particularly, packed layer 305 constitutes by the heat-resistant resin material of sneaking into silica filled thing (silica filler), low-melting glass, oxide or such as the metal of copper.

Light shield layer 306 is arranged on the top of packed layer 305 so that cover 6 whole of support substrates comprising the zone that has disposed IC chip 30.This light shield layer 306 is the light that is used to interdict from support substrate 6 incidents towards IC chip 30, for example is made of metals such as aluminium and copper.By this light shield layer 306, prevented the misoperation of the IC chip that the irradiation because of light causes.And, under the situation that packed layer 306 is made of the conductive material of light-proofness, can omit this light shield layer 306.

On the other hand, basalis 307 is arranged on the top of light shield layer 306 so that cover 6 whole of support substrates.This basalis 307 is the layers that are used to form the formation substrate of wiring cambium layer 2, for example is made of silica resin.By this basalis 307, slowed down the distortion of following packed layer 305 and the stress that produces.Each IC chip 30 with substrate face towards the form of support substrate 6 be configured in basalis 307 above.Prevented from IC chip 30 to be immersed impurity by basalis 307 from support substrate 6 or packed layer 305.Basalis 307 has also been born the task that will connect up cambium layer 2 contained wirings and light shield layer 306 carry out electrical isolation.

＜the second manufacture method 〉

Below, the manufacture method of electro-optical device D shown in Figure 33 is described.

At first, as shown in figure 34, on whole base plate 710, form photospallation layer 712.This substrate 710 is the plate-like portion materials with light transmission, for example is made of glass etc.On the other hand, photospallation layer 712 is by for example being obtained by the plasma CVD method deposition of amorphous silicon.

Then, as shown in figure 35, on the surface of this photospallation layer 712, form metal level 714.This metal level 714 is by for example being obtained by method deposition of aluminum such as sputters.After this, implement to use the pattern of photomask to form processing and etch processes to metal level 714.By this, be formed for adjusting the telltale mark of the position of each IC chip 30.

Then, as shown in figure 35, form resin molding 716 so that cover photospallation layer 712.This resin molding 716 is the layer that constitutes first insulation course 41 in the operation of back, is made of stable on heating organic material.Resin molding 716 forms by methods such as spin coating and coatings.In this stage, resin molding 716 is in half polymerization state, has cementability.The thickness of resin molding 716 is degree of 0.1 μ m～5 μ m.

Then, as shown in figure 36, each IC chip 30 of configuration on the assigned position of resin molding 716.At this moment, each IC chip 30 with pad is formed face towards the form of substrate 710 be configured in resin molding 716 above.Therefore, prevented the damage of pad P in subsequent handling.Adjust relative position relation between each IC chip 30 and the substrate 710 by the telltale mark of observing metal level 714.Having used installation accuracy in the configuration of this IC chip 30 is that ± 5 μ m are with interior high precision nude film fitting machine.After whole IC chips 30 is configured, baking of resin film 716 and make it complete polymerization.By this, improve the cementability between resin molding 716 and each the IC chip 30.

Then, as shown in figure 37, form basalis 307 has disposed IC chip 30 with covering whole base plate 710.This basalis 307 is for example by depositing SiO by the plasma CVD method ₂Obtain.The thickness of basalis 307 is degree of 100nm～500nm.Then, as shown in figure 37, form light shield layer 306 to cover whole basalis 307.Metal such as copper and aluminium obtains this light shield layer 306 by for example deposited by sputtering method.

And, as shown in figure 38, fill hard resin so that fill up the gap of each IC chip 30.This hard resin for example is the heat-resistant resin material and the low-melting glass of having sneaked into silica filled thing.Then, by getting involved this hard resin, on the substrate face of IC chip 30, paste support substrate 6.At this moment, IC chip 30 is used as the isolated body (spacer) that is used to adjust interval between support substrate 6 and the substrate 710.After this, obtain packed layer 305 by solidifying hard resin by heating.

Then, as shown in figure 38, shine from substrate 71 1 sides as the light R of the excimer laser (excimer laser) of ultraviolet light.Burst photospallation layer 712 by this.That is, photospallation layer 712 contained hydrogen are gasified, and this layer is gone up and produced the crack.Under this state, peel off substrate 710 through photospallation layer 712.Then, remove metal level 714 and photospallation layer 712 by etching solution.This etching solution has dissolved metal level 714 and photospallation layer 712, and on the other hand, it is again the liquid that resin molding 716 is not produced any influence.

After this, as shown in figure 39, support substrate 6 spun upside down so as the configuration plane that makes IC chip 30 towards the top.By this, form the electronic unit layer 3 of electro-optical device D shown in Figure 33.In the electronic unit layer 3 that obtains by this manufacture method, the surface that the pad of each IC chip 30 forms face and basalis 307 almost is positioned at identical face.After this, on resin molding 716, implement pattern formation processing and etch processes and obtain first insulation course 41.Later manufacturing process is with identical to first manufacture method shown in Figure 32 from Figure 20.

Obtain following effect according to second manufacture method.

(1) owing to the gap of filling up each IC chip 30 by packed layer 305, unnecessary for planarization packed layer 305 with the surperficial consistent of each IC chip 30.Therefore, realized the simplification of manufacturing process.And, compare with first manufacture method, because the unnecessary IC chip 30 that makes is thin, make the processing of each IC chip 30 become easy.Therefore, can be reduced in the possibility that produces bad IC chip 30 in the manufacturing process.

(2) owing under the state of substrate 710, forming basalis 307 and packed layer 305, so when these layers form, avoided the damage of pad P at pad P with each IC chip 30.Therefore, prevented bad electrical connection between each the IC chip 30 and first wiring layer 43.As a result, the characteristic of electro-optical device D is maintained at high level, and can improve yield rate.

(3), fix after there is no need to be close to each IC chip 30 on the substrate 710 because each IC chip 30 is fixing by basalis 307 and packed layer 305.That is owing to only each IC chip 30 easy configuration can be finished, cripetura the needed time of installation of each IC chip 30.

(4) because wiring cambium layer 2 is laminated on the electronic unit layer 3 of exposed pad P, for example the wiring of the pad P of IC chip 30 and wiring cambium layer 2 can be connected by unified by (photography) technology of taking a picture.Therefore, unnecessaryly be provided for connecting the pad P of each IC chip 30 and the projection (bump) of wiring etc.As a result, the simplification of manufacturing process and the shortening of manufacturing time have been realized.

(5) owing to constitute the layer that the resin molding 716 of first insulation course 41 is used as each IC chip 30 that is used for boning, compare with the method that insulation course 41 is provided with in addition tack coat, manufacturing process has simplified.But, also can adopt the method that first insulation course 41 is provided with in addition tack coat.That is, replace the resin molding 716 among Figure 35, can adopt the tack coat of each IC chip that is provided for boning and after substrate 710 is peeled off, remove the method for this tack coat.In this case, tack coat is removed the back and is formed first insulation course 41.

, high-order side and low level side power supply potential apply power lead can with the formation operation of first wiring layer 43 and second wiring layer 47 outside operation on form.For example, as shown below, in second manufacture method, before each IC chip 30 arrangement step, can carry out power lead and form operation.

At first, as shown in figure 36, before each IC chip 30 configuration, on resin molding 716, form power lead 309.In Figure 40, be shown in broken lines the profile of each the IC chip 30 that in the operation of back, on resin molding 716, disposes.Power lead 309 be formed in the zone that dispose outside each IC chip 30 zone with the nonoverlapping position of the telltale mark of metal level 714 on.

Particularly, at first, the conductive layer that is made of aluminium and copper and so on conductive material is formed on above the resin molding 716.This conductive layer forms by for example plated by electroless plating, sputter or ink-jet technology.Then, this conductive layer is implemented to obtain power lead 309 shown in Figure 40 after pattern forms processing and etch processes.After this, identical with operation shown in Figure 36 each IC chip 30 is configured in above the resin molding 716, then, forms light shield layer 306 and basalis 307 to cover power lead 309 and IC chip 30.Later operation is same as described above.And in other example, power lead 309 forms operation and can carry out after each IC chip 30 is configured in above the resin molding 716.And, in above-mentioned first manufacture method and the 3rd manufacture method shown below, also can form power lead 309 by same program.

Figure 41 is the rhythmo structure of expression by the electro-optical device D of this manufacture method acquisition.As shown in the figure, among this electro-optical device D, power lead 309 is between the basalis 307 and first insulation course 41.This power lead 309 is connected to first wiring layer 43 by get involved the contact hole 41a that is provided with on first insulation course 41.

The stepped construction of＜the three manufacture method 〉

Below, with reference to Figure 42, the stepped construction of the electro-optical device D that obtains according to the 3rd manufacture method is described.Shown in the figure in each one the part identical with the electro-optical device D of first manufacture method provided common symbol with each of Figure 14.It is by mode shown in Figure 16 that the plane of electro-optical device D constitutes.

As shown in figure 42, in the electro-optical device D that obtains by the 3rd manufacture method, on the pad P of IC chip 30, formed projection (bump) (projected electrode) 308.This projection 308 is made of for example indium (In) or gold metals such as (Au).Projection 308 is connected to projection 42.This projection 42 is connected to first wiring layer 43 by getting involved at the contact hole 41a of first insulation course, 41 upper sheds.Projection 42 and projection 308 are identical to be made of for example metal such as indium and gold.

＜the three manufacture method 〉

Below, the manufacture method of electro-optical device D shown in Figure 42 is described.

At first, as shown in figure 43, form insulation course 722 with 720 whole of covered substrates.This substrate 720 is the plate-like portion materials with light transmission, for example is made of glass etc.On the other hand, insulation course 722 is by for example depositing SiO by plasma CVD method ₂And obtain.And, under the not enough situation of the flatness of this insulation course 722, can carry out planarization by the CMP method.Then, as shown in figure 43, on whole of this insulation course 722, form photospallation layer 724.This photospallation layer 724 is by for example being obtained by plasma CVD method deposition of amorphous silicon.

Then, as shown in figure 44, on overall optical peel ply 724, form dielectric film 726.This dielectric film 726 is by depositing SiO by plasma CVD method ₂And obtain.Dielectric film 726 is the layers that constitute the 3rd insulation course 50 shown in Figure 42.After this, as shown in figure 44, the conducting film 728 that constitutes anode layer 49 is formed on above the dielectric film 726.This conducting film 728 is obtained by sputtering sedimentation by big conductive materials of work function such as for example ITO.And as shown in figure 44, the metal film 730 that constitutes second wiring layer 47 forms and covers conducting film 728.This metal film 730 obtains by the stacked layer that is made of aluminium etc. on the laminar surface that is made of titanium etc.For example sputtering method has been used in the formation of metal film 730.Then, as shown in figure 45, by on conducting film 728 and metal film 730, implementing to use the pattern formation processing and the etch processes of photomask to obtain the anode layer shown in Figure 42 49 and second wiring layer 47.

Below, as shown in figure 46, form second insulation course 45.This second insulation course 45 is by SiO ₂Be formed to cover after the anode layer 49 and second wiring layer 47 and form by the pattern of implementing to use photomask that processing and etch processes obtain Deng the insulation course that constitutes.Then, form first wiring layer 43 as shown in figure 47.This first wiring layer 43 is that pattern forms processing and etch processes obtains by the metal levels such as aluminium that formed by sputter are implemented.

After this, as shown in figure 48, form first insulation course 41.That is, at first, SiO ₂Be formed covering first wiring layer 43 Deng dielectric film.Then, part that should be relative with the pad P of IC chip 30 in this dielectric film is being removed back acquisition first insulation course 41 by pattern formation processing and etch processes.Then, as shown in figure 49, in first wiring layer 43, should form projection 42 on the part relative with the projection 308 of IC chip.This projection 42 is formed thickness from 0.5 μ m to 5 μ m by for example emission (lift-off) method.Projection 42 is made of metals such as indium and gold.Under the situation that projection 42 is formed by indium, its surface is covered by metals such as gold.By this, prevented the oxidation of projection 42.

On the other hand, on the pad P of each IC chip 30, form projection 308.This projection 308 is made of metals such as indium and gold.The thickness of projection 308 is degree of 2 μ m～10 μ m.After this, as shown in figure 50, each IC chip 30 with its projection 308 vis-a-vis the state of the projection 42 on first wiring layer 43 be configured on first insulation course 41.It is that ± 5 μ m are with interior high precision nude film fitting machine that installation accuracy has been used in the configuration of each IC chip.Then, transient heating projection 42 and projection 308.By this, that projection 42 and projection 308 is bonding.

Then, shown in Figure 51, the potting resin material is to fill up the gap of each IC chip 30.This resin material contains carbon particle and has light-proofness.After this, shown in Figure 51, on the substrate face of IC chip 30, paste support substrate.And, obtain packed layer 305 by 30 resin materials of being filled of sclerosis IC chip.

Then, shown in Figure 51, shine from substrate 720 1 sides as the light R of the excimer laser (excimer laser) of ultraviolet light.Burst photospallation layer 724 by this, shown in Figure 52, peel off substrate 720 through photospallation layer 724.Amorphous silicon residual on the dielectric film 726 removes by etch processes.

After this, on dielectric film 726, implement to use the pattern of photomask to form processing and etch processes, obtain the 3rd insulation course 50 as shown in figure 42.After this manufacturing process is with identical to first manufacture method shown in Figure 32 from Figure 26.

According to the 3rd manufacture method, obtain following effect.

If after electronic unit layer 3 and each wiring layer and the formation of each insulation course, form anode layer 49 according to above-mentioned first and second manufacture methods, then have the differential possibility that causes anode layer 49 surface flatnesses to reduce because of these layers.In contrast, according to the 3rd manufacture method, be formed on more earlier on the flat substrate 720 than other key element part owing to constitute the conducting film 728 of anode layer 49, the surface flatness of anode layer 49 is maintained at high level.By this, owing to guaranteed the homogeneity of organic EL 10 thickness, luminosity is uniform on whole display surface.And, except be used in the situation among the electro-optical device D at the IC chip 30 that comprises active component, the 3rd manufacture method also is equally applicable to be used in situation among the electro-optical device D by the active component that low temperature polycrystalline silicon (polysilicon) etc. forms.

＜C: electronic equipment 〉

Below, electronic equipment of the present invention is described.

＜personal computer 〉

Figure 53 is the formation oblique view of expression as the personal computer of electronic equipment one example of the present invention.As shown in FIG., personal computer 81 comprises main part 812 that keyboard 811 has been installed and the display part 814 that above-mentioned electro-optical device D has been installed.

During this constituted, the IC chip with the various functions that relate to the image demonstration was comprised on the electronic unit layer 3.As this IC chip, mobile motion picture expert group version) and the IC chip of MP3 data expanded functions such as (MPEG Audio Layer-3:MPEG audio layer-3) etc. for example, has the IC chip that display buffer memory and CPU have been installed or (the Motion Picture Experts Group: according to MPEG has been installed.And, be used as under the situation of touch-screen at the display surface of electro-optical device D, the IC chip that comprises the function relevant with its input can be included on the electronic unit layer 3.

＜e-book 〉

Figure 54 is the formation oblique view of expression as the e-book of electronic equipment one example of the present invention.As shown in FIG., e-book 83 has main part 830, first display part 831 and second display part 832.Wherein main part 830 comprises the keyboard of the operation of accepting the user.First display part 831 comprises above-mentioned electro-optical device D, promptly is used for the electro-optical device D of display image by the luminous of organic EL 10.On the other hand, second display part 832 comprises and is used for the electro-optical device D ' of display image by a plurality of pixels.But the pixel of second display part 832 self is non-luminous.Particularly, non-light emitting type displays such as electrophoretic display device (EPD), reflection type LCD (LCD), toner (toner) display, twisted board (twist board) display are used as the electro-optical device D ' of second display part 832.

First display part 831 is by getting involved the periphery that hinge is installed in main part 830.Therefore, first display part 831 can rotate as axle with the periphery of main part 830.On the other hand, by in first display part 831 with the opposite side periphery of main part 830 on insert hinge second display part 832 be installed.Therefore, second display part 832 can rotate as axle with the periphery of first display part 831.

Under this structure, luminous and show by first display part 831 by making organic EL 10.On the other hand, under situation about showing by second display part 832, the organic EL 10 of first display part 831 is almost luminous with identical brightness.Observe by the observer in the display surface reflection back of second display part 832 from the light that first display part 831 sends.That is, first display part 831 himself not only as the function of display device, and by second display part, 832 display images the time also as the function of lighting device (light (front light) before so-called).According to this structure,, also there is no need to be provided for separately guaranteeing the lighting device of its display brightness although second display part 832 is non-light emitting type displays.As a result, can allow the thickness of first display part 831 and second display part 832 be aggregated in below about 2mm, it has realized H.D e-book than thin and light of the books that use paper more.

And the present invention's electronic equipment applicatory is not limited to the equipment shown in Figure 53 and Figure 54.That is the applicable the present invention of various device who, other is had the function of display image such as pocket telephone, game machine, Electronic Paper, video camera, digital camera, automobile navigation apparatus, Car Stereo, driver behavior panel, printer, scanner, televisor, video machines, pager, electronic memo, counter, word processor etc.

＜D: variation 〉

More than shown in form illustration only, can increase various distortion to these forms.Variation is as described below.

(1) is configured in structure support substrate 6 on IC chip 35 and control with IC chip 31 with IC chip 33, column data conversion with IC chip 37, scanning although example illustrates pixel driving, also is fine with an one of IC chip 31 or the structure that all is configured on other substrate with IC chip 35 and control as scanning with IC chip 33, column data conversion.And, with scanning with IC chip 33, column data conversion with IC chip 35 with control with one one of IC chip 31 or all also be fine as the structure of an IC chip.

(2),, systematization and integrated device substrate and encapsulation (package) have been realized by the present invention being applicable to various electronic equipments as as shown in the personal computer of electronic equipment example.That is, in this device substrate, the electronic unit layer with various active components and passive element seals according to the wiring cambium layer with the wiring that is connected to each electronic unit splicing ear.As the example of the contained active component of electronic unit layer, have the various parts of IC chip (CMOS type and ambipolar), storer or compound semiconductor of being used to realize various functions and so on.On the other hand, as the example of the contained passive element of electronic unit layer, have the various chip parts of resistance, capacitor or inductance and so on.According to this device substrate, because various electronic units by systematization and integrated, have been sought miniaturization, lightweight and the high performance of electronic equipment.

(3) the present invention is also applicable to the electro-optical device beyond the device that uses EL element.That is, so long as possess the device that electro ultrafiltration is transformed into the electrooptic element of light action, then applicable the present invention.As this electro-optical device, have: the liquid crystal indicator that uses liquid crystal; Use comprises pigmented fluids and disperse the electrophoretic display apparatus of the microcapsules (micro capsule) of white particles in this liquid; The twisted board display of the twisted board that use applies respectively with different colours different each zone of polarity; Use the toner display of black toner; Use the field-emitter display of fluorescent powder; Use the light-emitting diode display of LED (light emitting diode); Use the plasma display panel (PDP) of high pressure gas bodies such as helium and neon etc.

Electro-optical device of the present invention is not limited to the device that is used for display image, and for example the present invention is also applicable to using organic EL, ELD or the image processing system of field emission element (FED) and light engine (engine) part of electro-photography apparatus.In this device, the light corresponding with view data is irradiated on the photoreceptor of photosensitive drums (drum) etc., and toner is adsorbed on the sub-image that forms thus.Then, this toner is transferred on the recording materials such as blank.Electro-optical device of the present invention also is mapped to device on the photoreceptor applicable to being used for the illumination corresponding with view data.That is, the electro-optical device under this situation comprises and is used for that light shone the light-emitting component (electrooptic element) of photoreceptor respectively and is used for driving circuit with each light-emitting component individual drive.In the preferred mode, adopt line (1ine) exposure structure of the various recording materials width that are suitable for A4 size and A3 size and so on.According to electro-optical device of the present invention, can realize slim printing equipment of high-performance and compounding machine.

The present invention is also applicable to the electro-optical device that uses CCD electrooptic elements such as (charge-coupled image sensors), and this CCD exports and corresponding electric current or the voltage of irradiation light quantity.This electro-optical device is used as the photosensor array device (camera head) in the digital camera for example.By the organic EL of CCD with the electro-optical device D that replaces above-mentioned embodiment is being set, the A/D transducer that also will be used for the simulating signal of CCD output is transformed into digital signal simultaneously is arranged to replace D/A translation circuit 356 to realize this photosensor array device.And, in other form, be combined into one as the electro-optical device of display device use and the electro-optical device that uses as photosensor array.According to this device,, can adjust the luminosity of display device automatically according to the surrounding brightness that detects by the photosensor array device.

The present invention is also applicable to comprising the device of electrooptic element with external component.That is, the present invention also is applicable to cell driving device, the unit circuit that it comprises on the diverse location planar (for example being configured to matrix form) a plurality of driven elements of configuration respectively and is used to drive each driven element.For example, replace the electrooptic element (for example CCD of above-mentioned photosensor array) of electro-optical device of the present invention, be used as driven element, then can realize being used to detecting the device of user's operation if will be used for the element of detected pressures and static.This cell driving device can be used in various electronic equipments as for example input media such as touch-screen and slight keyboard.

By above explanation,, suppressed in the unordered difference of circuit active component on characteristic that is used for driving driven elements such as electrooptic element according to the present invention.

Claims (18)

1, a kind of electro-optical device is characterized in that, has:

A plurality of electrooptic elements;

A plurality of element drives IC chip, it has a plurality of unit circuits that are used to drive electrooptic element respectively; And select the control circuit controlled, described selection is controlled at the unit circuit of selecting successively in these a plurality of unit circuits more than 1, allows selected unit circuit more than 1 be used to drive the action of electrooptic element simultaneously; With

Select circuit, it selects IC chip more than 1 in the IC chip successively in described a plurality of element drives, allows the control circuit of selected IC chip carry out described selection simultaneously and controls.

2, electro-optical device according to claim 1 is characterized in that,

Described each element drives has particular electrical circuit with the IC chip, its specific successively this element drives contained unit circuit more than 1 of IC chip;

Described control circuit will carry out described selection control as object by the specific unit circuit more than 1 of described particular electrical circuit.

3, electro-optical device according to claim 2 is characterized in that,

Described selection circuit outputs to selected element drives with on the IC chip with clock signal;

Described each element drives with specific successively synchronously this element drives of the described particular electrical circuit of IC chip and the clock signal that provides by described selection circuit with the contained unit circuit more than 1 of IC chip.

4, electro-optical device according to claim 1 is characterized in that,

Described constituent parts circuit has:

Holding circuit, it keeps and the drive current or the corresponding electric charge of driving voltage that are used to drive electrooptic element; With

Holding circuit, it keeps the electric charge that is kept by described holding circuit.

5, electro-optical device according to claim 1 is characterized in that,

Described control circuit will be used to check that the test signal of the action of described constituent parts circuit outputs to this constituent parts circuit.

6, a kind of driving circuit of electro-optical device, the circuit being used for driving the electro-optical device with a plurality of electrooptic elements is characterized in that,

Has the selection circuit, it is at a plurality of element drives IC chip with the control circuit that is used for driving a plurality of unit circuits of electrooptic element and selects to control, select the IC chip more than 1 successively, allow the control circuit of selected IC chip carry out described selection control simultaneously, described selection is controlled at the unit circuit of selecting successively in these a plurality of unit circuits more than 1, allows selected unit circuit more than 1 be used to drive the action of electrooptic element simultaneously.

7, a kind of cell driving device is characterized in that, has:

A plurality of driven elements;

A plurality of element drives IC chip, it has respectively: a plurality of unit circuits that are used to drive driven element; With the control circuit of selecting to control, described selection is controlled at the unit circuit of selecting successively in these a plurality of unit circuits more than 1, allows selected unit circuit more than 1 be used to drive the action of driven element simultaneously;

Select circuit, it selects IC chip more than 1 in the IC chip successively in described a plurality of element drives, allows the control circuit of selected IC chip carry out described selection simultaneously and controls.

8, a kind of electro-optical device has:

A plurality of electrooptic elements, it is driven by the drive current by the data-signal appointment respectively; With

A plurality of data supply circuits, its by one or more electrooptic element each and be provided with and comprise the first data supply circuit and the second data supply circuit, comprise the reference current supply circuit that generates reference current based on reference current respectively, export the data-signal output circuit of the current value corresponding based on the reference current that generates by described reference current supply circuit with described data-signal;

The described reference current that the described first data supply circuit will use for the reference current supply circuit generation reference current of this first data supply circuit outputs to the described second data supply circuit; On the other hand

The described reference current that the reference current supply circuit of the described second data supply circuit is supplied with based on the described first data supply circuit generates described reference current.

9, electro-optical device according to claim 8 is characterized in that,

The described reference current of described first data supply circuit output is with time division way each supply to a plurality of described second data supply circuits.

10, electro-optical device according to claim 9 is characterized in that,

The described reference current of described first data supply circuit output is supplied with to each second data supply circuit through electric current supplying wire, and this electric current supplying wire has for the common part of described a plurality of second data supply circuits.

11, electro-optical device according to claim 9 is characterized in that,

Each of described a plurality of data supply circuits has control circuit, is used to switch whether supply with described reference current to the reference current supply circuit of this data supply circuit.

12, electro-optical device according to claim 11 is characterized in that,

The enable signal that the control circuit of described each second data supply circuit is supplied with according to the control circuit of the past level data supply circuit, switch whether provide described reference current, simultaneously enable signal is outputed to the control circuit of back level data supply circuit described reference current supply circuit.

13, electro-optical device according to claim 8 is characterized in that,

Described each data supply circuit comprises the holding circuit that keeps described reference current;

The reference current supply circuit of described each data supply circuit generates reference current according to the reference current that described holding circuit kept.

14, electro-optical device according to claim 13 is characterized in that,

To the supply of the reference current of the reference current supply circuit of described each data supply circuit be beyond during the data-signal output circuit outputting data signals of this data supply circuit during in carry out.

15, electro-optical device according to claim 8 is characterized in that,

The formation of the described first data supply circuit is identical with the formation of the described second data supply circuit.

16, electro-optical device according to claim 8 is characterized in that,

Comprise element drives IC chip, it has a plurality of unit circuits that the drive current corresponding with described data-signal offered described electrooptic element;

The data-signal output circuit of described each data supply circuit outputs to the unit circuit of described element drives with the IC chip with the data-signal that generates.

17, a kind of cell driving device is characterized in that, has:

A plurality of driven elements, it is driven by the drive current by the data-signal appointment respectively; With

A plurality of data supply circuits, its by one or more driven element each and be provided with and comprise the first data supply circuit and the second data supply circuit, comprise the reference current supply circuit that generates reference current based on reference current respectively, export the data-signal output circuit of the current value corresponding based on the reference current that generates by described reference current supply circuit with described data-signal;

The described reference current that the described first data supply circuit will use for the reference current supply circuit generation reference current of this first data supply circuit outputs to the second data supply circuit beyond the described first data supply circuit; On the other hand

The reference current supply circuit of the described second data supply circuit generates described reference current according to the described reference current of being supplied with by the described first data supply circuit.

18, a kind of electronic equipment is characterized in that, comprises each described electro-optical device in claim 1～5 and the claim 8～16.

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