CN101009327B - Semiconductor part and its making method - Google Patents
Semiconductor part and its making method Download PDFInfo
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- CN101009327B CN101009327B CN200610001958A CN200610001958A CN101009327B CN 101009327 B CN101009327 B CN 101009327B CN 200610001958 A CN200610001958 A CN 200610001958A CN 200610001958 A CN200610001958 A CN 200610001958A CN 101009327 B CN101009327 B CN 101009327B
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Abstract
A semiconductor component comprises base, gate pile structure, adulteration area and high stress material layer. Thereinto the gate pile structure is at the base, and the gate pile structure at leastincludes dielectric layer which is piled sequentially and gate. The adulteration area is at side of the gate pile structure. The high stress material layer is configured to the adulteration area. Because the high stress material layer can increase the carrier mobility ratio of the adulteration area, so the running speed of the component can be quickened.
Description
Technical field
The invention relates to a kind of integrated circuit, and particularly relevant for a kind of semiconductor element and manufacture method thereof.
Background technology
In recent years, semi-conducting material has been widely used in the middle of the various electronics industries because of characteristics such as its special conductive capabilities.The application category of semi-conducting material is very extensive, and transistor, high voltage devices, logic element, memory component or the like all are contained in wherein such as.For instance, because having, the non-volatility memorizer in the memory component can repeatedly carry out the actions such as depositing in, read, erase of data, therefore and the advantage that the data that deposits in also can not disappear after outage has become extensively a kind of semiconductor element of employing of PC and electronic equipment institute.
In general, non-volatility memorizer, for example its manufacture method of silicon nitride ROM normally forms silicon oxide/silicon nitride/silicon oxide (oxide-nitride-oxide earlier in substrate, be called for short ONO) material layer, on this silicon oxide/silicon nitride/silicon oxide (ONO) material layer, form one deck doped polysilicon layer then.Follow this doped polysilicon layer of patterning and ONO material layer again, to form silicon oxide/silicon nitride/silicon oxide (ONO) stacked structure (stackedstructure) of grid (doped polysilicon layer) and grid below.At last in silicon oxide/silicon nitride/silicon oxide (ONO) stacked structure substrate on two sides, form doping region in embedding type (buried diffusion region) with ion implantation manufacture process, and doping region in embedding type promptly can be used as the usefulness of embedded type bit line (buried bit line).
Yet along with the integrated level of element constantly promotes, the size of memory component is also and then done littler and littler.Thus, the passage in the memory component (basal region that grid covered) length also can be reduced thereupon.So, utilize the formed embedded type bit line of ion implantation manufacture process, make admixture (dopant) diffusion wherein easily because of hot processing procedure, cause the reduction of the effective passage of element, and short-channel effect (short channel effect) takes place.
In addition, because the resistance of embedded type bit line (doped region) itself is very high, after the live width of embedded type bit line is dwindled, will cause its resistance rising ground more.The result that resistance improves causes memory in operation, and the electric current of bit line descends, and the running speed of not only slowing down memory also can cause problems such as power consumption increase.Especially when element after high integration development, the problems referred to above will be more serious.
Summary of the invention
In view of this, purpose of the present invention is to provide a kind of semiconductor element exactly, can improve the carrier transport factor of doped region, and then improves the running speed of element.
Another object of the present invention provides a kind of manufacture method of semiconductor element, can strengthen the carrier mobility of doped region, reduces the dopant concentration of the required implantation of doped region, avoids problems such as short-channel effect.
The present invention proposes a kind of semiconductor element, its at least by substrate, gate stack structure, doped region and heavily stressed material layer constituted.Wherein gate stack structure is positioned in the substrate, and gate stack structure comprises dielectric layer and the grid that is piled up in regular turn by substrate surface at least.Doped region is positioned at the gate stack structure side.Heavily stressed material layer only is disposed on the doped region, and cover gate stacked structure not.
According to the described semiconductor element of preferred embodiment of the present invention, the stress of above-mentioned heavily stressed material layer is higher than-7.28 * 10
7Dyne/square centimeter.
According to the described semiconductor element of preferred embodiment of the present invention, the stress of above-mentioned heavily stressed material layer is between 1.53 * 10
7Dyne/square centimeter is to 2.71 * 10
9Between dyne/square centimeter.
According to the described semiconductor element of preferred embodiment of the present invention, the material of above-mentioned heavily stressed material layer is made of nitrogen and silicon, and wherein the thickness of heavily stressed material layer is higher than half of this gate stack structure thickness.The material of heavily stressed material layer for example is the material that silicon nitride, silicon oxynitride or its combination are formed.
According to the described semiconductor element of preferred embodiment of the present invention, above-mentioned gate stack structure for example is to comprise dielectric layer, electric charge storage layer, electric charge barrier layer and the grid that is piled up in regular turn by substrate surface.Wherein the material of electric charge storage layer can be a silicon nitride.The material of dielectric layer and electric charge barrier layer can be a silica.In addition, doped region for example is the usefulness as embedded type bit line.
According to the described semiconductor element of preferred embodiment of the present invention, the material of above-mentioned grid for example is a doped polycrystalline silicon.In addition, in semiconductor element of the present invention, more one deck conductor layer can be set on grid.The material of conductor layer for example is a metal silicide.
The present invention proposes a kind of manufacture method of semiconductor element, and it is prior to forming gate stack structure in the substrate, and gate stack structure comprises dielectric layer and the grid that is piled up in regular turn by substrate surface at least.Afterwards, form doped region in the gate stack structure both sides, then, on doped region, form heavily stressed material layer, and the heavily stressed material layer on the grid is removed.
According to the manufacture method of the described semiconductor element of preferred embodiment of the present invention, the material of above-mentioned heavily stressed material layer is made of nitrogen and silicon, and it for example is the material that silicon nitride, silicon oxynitride or its combination are formed.The method that forms above-mentioned heavily stressed material layer for example is to carry out chemical vapor deposition process, and the ratio of adjusting nitrogenous gas and silicon-containing gas in the chemical vapor deposition process is to form it.
According to the manufacture method of the described semiconductor element of preferred embodiment of the present invention, above-mentioned gate stack structure for example is to comprise dielectric layer, electric charge storage layer, electric charge barrier layer and the grid that is piled up in regular turn by substrate surface at least.The material of electric charge storage layer for example is a silicon nitride.In addition, doped region for example is the usefulness as embedded type bit line.
Therefore the present invention can improve the carrier transport factor of doped region because of form the heavily stressed material layer of one deck on doped region, and then improves doped region resistance height, shortcoming that electric current is little.In addition, because the setting of heavily stressed material layer, can improve the carrier transport factor of doped region, therefore when forming doped region, can reduce the dopant concentration of implantation, the short-channel effect of avoiding dopant diffusion to cause more helps the integrated level of element.
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
Description of drawings
Fig. 1 is the section of structure that illustrates a kind of semiconductor element of one embodiment of the invention.
Fig. 2 A to Fig. 2 C is the manufacturing process profile that illustrates a kind of semiconductor element of one embodiment of the invention.
100: substrate 110: gate stack structure
121: dielectric layer 121a: dielectric materials layer
123: electric charge storage layer 123a: the charge storage material layer
125: electric charge barrier layer 125a: the electric charge barrier material layer
130: grid 130a: gate material layers
140: doped region 150: heavily stressed material layer
Embodiment
Seeing also Fig. 1 is a kind of semiconductor element that illustrates one embodiment of the invention.
As shown in Figure 1, the semiconductor element of the present invention's proposition is made of with heavily stressed material layer 150 substrate 100, gate stack structure 110, doped region 140.
Wherein, doped region 140 is the substrates 100 that are arranged in gate stack structure 110 sides.Admixture in the doped region 140 can be P type admixture or N type admixture, and it is looked closely the kenel of element and decides.
Heavily stressed material layer 150 is disposed in the substrate 100, and covers doped region 140.The thickness power of heavily stressed material layer is higher than half of gate stack structure thickness in this way.The material of heavily stressed material layer 150 is made of nitrogen and silicon, and it for example is the material that silicon nitride, silicon oxynitride, silica or its combination are formed.Wherein, if the material of heavily stressed material layer 150 is a silicon nitride, nitrogen silicon ratio is approximately more than or equal to 1.33.Because in silicon nitride, the ratio of nitrogen is higher, therefore can improves the stress of this heavily stressed material layer 150, and then strengthen the mobility of carrier in the doped region 140.The stress of heavily stressed material layer 150 for example is to be higher than-7.28 * 10
7Dyne/square centimeter is preferably between 1.53 * 10
7Dyne/square centimeter is to 2.71 * 10
9Between dyne/square centimeter.
In one embodiment, gate stack structure 110 is made of with grid 130 dielectric layer 121 that piles up in regular turn from substrate 100, electric charge storage layer 123, electric charge barrier layer 125.Wherein, dielectric layer 121 is the usefulness as a tunneling dielectric layer herein, and the material of dielectric layer 121 for example is a silica.The material of electric charge storage layer 123 can be silicon nitride, doped polycrystalline silicon, or other can store charge in material wherein, for example tantalum pentoxide, strontium titanates thing and hafnium oxide etc.The material of electric charge barrier layer 125 can be silica or other suitable materials.The material of grid 130 for example is a doped polycrystalline silicon.And, above-mentioned gate stack structure 110, the doped region 140 in the collocation in the substrate 100 has promptly constituted a memory component.In addition, doped region 140 can be used as the usefulness of embedded type bit line in memory component.What deserves to be mentioned is that heavily stressed material layer 150 is arranged on the embedded type bit line (doped region 140), then can increase the carrier transport factor of embedded type bit line, and then improve the service speed of memory component.
In addition, in one embodiment, one deck conductor layer (not illustrating) can be set more on the grid 130 of semiconductor element.The material of conductor layer (not illustrating) for example be metal silicide such as tungsten silicide, titanium silicide, cobalt silicide or nickle silicide one of them.Conductor layer the resistance that can reduce grid 130 is set, and then increase ducting capacity.
Above-mentioned semiconductor element because the heavily stressed material layer 150 of one deck is set, therefore can be strengthened the carrier mobility of doped region 140 on doped region 140.And for memory component, can also improve embedded type bit line (being doped region 140) resistance height, shortcoming that electric current is little.Can accelerate the running speed of element, reduce the consumption of electric energy simultaneously.
The manufacture method of above-mentioned semiconductor element below is described.Fig. 2 A to Fig. 2 C is the manufacturing process profile that illustrates above-mentioned semiconductor element.
At first, see also shown in Fig. 2 A, provide substrate 100. then, in substrate 100, form dielectric layer and grid at least. in one embodiment, can in substrate 100, form dielectric materials layer 121a in regular turn, charge storage material layer 123a, charge material layer 125a and gate material layers 130a, and formed semiconductor element after making it, usefulness as memory component. wherein, the material of dielectric materials layer 121a for example is a silica, its formation method for example is a thermal oxidation method. the material of charge storage material layer 123a for example is a silicon nitride, its formation method for example is a chemical vapour deposition technique. the material of electric charge barrier material layer 125a for example is a silica, its formation method for example is a chemical vapour deposition technique. certainly, dielectric materials layer 121a and electric charge barrier material layer 125a also can be other similar materials. the material of charge storage material layer 123a is not limited to silicon nitride, also can be that other can make Charge Storage in material wherein, doped polycrystalline silicon for example, tantalum pentoxide, strontium titanates thing or hafnium oxide etc. the material of gate material layers 130a for example is a doped polycrystalline silicon, its formation method for example is after utilizing chemical vapour deposition technique to form one deck undoped polycrystalline silicon, carry out the ion implantation step to form, can certainly adopt the mode of implanting admixture when participating in the cintest to form doped polycrystalline silicon with chemical vapour deposition technique.
Then, see also shown in Fig. 2 B, define gate stack structure 110.It for example is to go up prior to gate material layers 130a to form patterning photoresist layer (not illustrating), then be mask with the patterning photoresist layer, gate material layers 130a, electric charge barrier material layer 125a, charge storage material layer 123a and dielectric materials layer 121a are carried out anisotropic etching, with grid 130, electric charge barrier layer 125, the electric charge storage layer 123 and dielectric layer 121 that defines gate stack structure 110.Wherein dielectric layer 121 is as the usefulness of the tunneling dielectric layer of memory component.
In another embodiment, after the gate material layers 130a that forms Figure 1A, can also go up prior to gate material layers 130a and form one deck conductor material layer (not illustrating), form the lithographic process and the etch process of patterning photoresist layer or the like again.The material of above-mentioned conductor material layer for example is a metal silicide, and it is as tungsten silicide, titanium silicide, cobalt silicide or nickle silicide or the like.The formation method of conductor material layer for example is a chemical vapour deposition technique, or aims at the metal silicide processing procedure voluntarily.Thus, conductor layer the resistance that can reduce grid 130 is set, improve the ducting capacity of grid 130.
Afterwards, in gate stack structure 110 substrate on two sides 100, form doped region 140.The method that forms doped region 140 for example is to be mask with gate stack structure 110, carries out ion implantation manufacture process to form it, and its admixture of implanting can be P type admixture or N type admixture, and it is looked closely the kenel of element and decides.
Then, see also shown in Fig. 2 C, in substrate 100, form heavily stressed material layer 150, cover doped region 140.The material of heavily stressed material layer 150 is made of nitrogen and silicon, and it for example is the material that silicon nitride, silicon oxynitride, silica or its combination are formed.The method that forms heavily stressed material layer 150 for example is to carry out chemical vapor deposition process, to form the heavily stressed material layer of a whole layer, cover grid stacked structure 110 in substrate 100.Remove the heavily stressed material layer on gate stack structure 110 surfaces afterwards, to form it.Particularly, if the material of heavily stressed material layer 150 is a silicon nitride, more can be by the ratio of adjusting nitrogenous gas and silicon-containing gas in the chemical vapor deposition process, make the nitrogen silicon ratio of formed heavily stressed material layer 150 approximately more than or equal to 1.33.
In sum, the semiconductor element that the present invention proposes because of form the heavily stressed material layer of one deck on doped region, therefore can improve the carrier transport factor of doped region.And, for memory component, can also improve the little shortcoming of resistance height, electric current of embedded type bit line (being doped region).In addition, because the setting of this heavily stressed material layer, improved the carrier transport factor of doped region, therefore when forming doped region, just can reduce the dopant concentration of implantation process, the short-channel effect of avoiding dopant diffusion to cause more helps the integrated level of element.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; anyly have the knack of this skill person; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is when looking aforesaid being as the criterion that technical scheme defines of applying for a patent.
Claims (16)
1. semiconductor element is characterized in that it comprises:
One substrate;
One gate stack structure is positioned in this substrate, and this gate stack structure comprises a dielectric layer and a grid that is piled up in regular turn by this substrate surface at least;
One doped region is positioned at this gate stack structure side; And
One heavily stressed material layer only is configured on this doped region, and wherein the thickness of this heavily stressed material layer is higher than half of this gate stack structure thickness.
2. semiconductor element according to claim 1 is characterized in that the stress of wherein said heavily stressed material layer is higher than-7.28 * 10
7Dyne/square centimeter.
3. semiconductor element according to claim 2, the stress that it is characterized in that wherein said heavily stressed material layer is between 1.53 * 10
7Dyne/square centimeter is to 2.71 * 10
9Dyne/square centimeter.
4. semiconductor element according to claim 1, the material that it is characterized in that wherein said heavily stressed material layer is made of nitrogen and silicon.
5. semiconductor element according to claim 4 is characterized in that the material of wherein said heavily stressed material layer comprises the material that silicon nitride, silicon oxynitride or its combination are formed.
6. semiconductor element according to claim 1 is characterized in that wherein said gate stack structure comprises this dielectric layer, an electric charge storage layer, an electric charge barrier layer and this grid that is piled up in regular turn by this substrate surface.
7. semiconductor element according to claim 6 is characterized in that the material of wherein said electric charge storage layer comprises silicon nitride.
8. semiconductor element according to claim 6 is characterized in that the material of wherein said dielectric layer and this electric charge barrier layer comprises silica.
9. semiconductor element according to claim 6 is characterized in that wherein said doped region is an embedded type bit line.
10. the manufacture method of a semiconductor element is characterized in that it comprises:
Form a gate stack structure in a substrate, this gate stack structure comprises a dielectric layer and a grid that is piled up in regular turn by this substrate surface at least;
Form a doped region in these gate stack structure both sides; And
On this doped region, form a heavily stressed material layer, and the heavily stressed material layer on this gate stack structure is removed, make the thickness of this heavily stressed material layer be higher than half of this gate stack structure thickness.
11. the manufacture method of semiconductor element according to claim 10, the material that it is characterized in that wherein said heavily stressed material layer is made of nitrogen and silicon.
12. the manufacture method of semiconductor element according to claim 10 is characterized in that the material of wherein said heavily stressed material layer comprises the material that silicon nitride, silicon oxynitride or its combination are formed.
13. the manufacture method of semiconductor element according to claim 10, the method that it is characterized in that wherein forming this heavily stressed material layer comprises carries out a chemical vapor deposition process, and adjusts the ratio of nitrogenous gas and silicon-containing gas in this chemical vapor deposition process.
14. the manufacture method of semiconductor element according to claim 10 is characterized in that wherein said gate stack structure comprises this dielectric layer, an electric charge storage layer, an electric charge barrier layer and this grid that is piled up in regular turn by this substrate surface.
15. the manufacture method of semiconductor element according to claim 14 is characterized in that the material of wherein said electric charge storage layer comprises silicon nitride.
16. the manufacture method of semiconductor element according to claim 14 is characterized in that wherein said doped region is an embedded type bit line.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200610001958A CN101009327B (en) | 2006-01-23 | 2006-01-23 | Semiconductor part and its making method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200610001958A CN101009327B (en) | 2006-01-23 | 2006-01-23 | Semiconductor part and its making method |
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|---|---|
| CN101009327A CN101009327A (en) | 2007-08-01 |
| CN101009327B true CN101009327B (en) | 2010-05-12 |
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| CN200610001958A Expired - Fee Related CN101009327B (en) | 2006-01-23 | 2006-01-23 | Semiconductor part and its making method |
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| US8466508B2 (en) | 2007-10-03 | 2013-06-18 | Macronix International Co., Ltd. | Non-volatile memory structure including stress material between stacked patterns |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6309932B1 (en) * | 1999-01-14 | 2001-10-30 | Agere Systems Guardian Corp | Process for forming a plasma nitride film suitable for gate dielectric application in sub-0.25 μm technologies |
| CN1507032A (en) * | 2002-12-12 | 2004-06-23 | 国际商业机器公司 | Isolation structure for applying stress pattern |
| US20040191975A1 (en) * | 2003-03-31 | 2004-09-30 | Weber Cory E. | Nitrogen controlled growth of dislocation loop in stress enhanced transistor |
| US20050032321A1 (en) * | 2003-08-08 | 2005-02-10 | Chien-Chao Huang | Strained silicon MOS devices |
| US20050247986A1 (en) * | 2004-05-06 | 2005-11-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Offset spacer formation for strained channel CMOS transistor |
-
2006
- 2006-01-23 CN CN200610001958A patent/CN101009327B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6309932B1 (en) * | 1999-01-14 | 2001-10-30 | Agere Systems Guardian Corp | Process for forming a plasma nitride film suitable for gate dielectric application in sub-0.25 μm technologies |
| CN1507032A (en) * | 2002-12-12 | 2004-06-23 | 国际商业机器公司 | Isolation structure for applying stress pattern |
| US20040191975A1 (en) * | 2003-03-31 | 2004-09-30 | Weber Cory E. | Nitrogen controlled growth of dislocation loop in stress enhanced transistor |
| US20050032321A1 (en) * | 2003-08-08 | 2005-02-10 | Chien-Chao Huang | Strained silicon MOS devices |
| US20050247986A1 (en) * | 2004-05-06 | 2005-11-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Offset spacer formation for strained channel CMOS transistor |
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| CN101009327A (en) | 2007-08-01 |
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