CN101004525A - Liquid crystal display device of thin film transistor - Google Patents
Liquid crystal display device of thin film transistor Download PDFInfo
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- CN101004525A CN101004525A CN 200610169587 CN200610169587A CN101004525A CN 101004525 A CN101004525 A CN 101004525A CN 200610169587 CN200610169587 CN 200610169587 CN 200610169587 A CN200610169587 A CN 200610169587A CN 101004525 A CN101004525 A CN 101004525A
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Abstract
A liquid crystal display of film transistor type consists of color filtering baseplate, film transistor array baseplate being opposite-set to color filtering baseplate and liquid crystal layer being packaged between two said base plates. It is featured as forming said color filtering baseplate by a top surface plate, color film on said top surface plate, block matrix and cylindrical isolation pad; forming film transistor array base plate by bottom surface plate, a set of gate line and data line both being formed on said bottom surface plate.
Description
Technical field
The present invention relates to Thin Film Transistor-LCD (TFT LCD), relate in particular to a kind of Thin Film Transistor-LCD of improvement white Mura (the heterogeneity phenomenon that picture quality is white in color) phenomenon.
Background technology
In recent years, along with popularizing of digital to television, traditional CRT shows owing to its digitizing difficulty, and volume is big, weight is big, and shortcomings such as radiation are arranged, and the trend that is substituted by display technique of new generation occurred, representational new display technique has PDP, OLED, LCD etc.Wherein, LCD is in light weight owing to having, and volume is thin, and radiationless, power consumption is little, and the display resolution advantages of higher has begun a large amount of popularizing, begins to become main product.
But existing LCD (LCD) technology still has much room for improvement.For control enclosure thick, generally adopt spherical chock insulator matter (Ball Spacer) or cylindrical spacer (Post Spacer) to reach the thick purpose of control enclosure in the LCD technology, because having, cylindrical spacer can eliminate the light scattering that partition produces, can effectively improve advantages such as contrast, in nearest thin film transistor (TFT) (TFT) manufacturing process, adopt in a large number.But, because cylindrical spacer can produce slip when being under pressure, cause black matrix and TFT dislocation to produce light leak, on picture quality, show as white Mura phenomenon.
Fig. 1 a is depicted as dot structure synoptic diagram on the prior art array, and the sectional view that A-A ' locates among Fig. 1 a is shown in Fig. 1 b.This array structure comprises: dielectric substrate; Be formed on grid line 1, gate electrode 8 on the dielectric substrate; Be formed on the gate insulation layer 9 on the gate electrode 8; Be formed on the silicon island 10 on the gate insulation layer 9; Be formed on the top drain electrode 11 and the source electrode 12 of silicon island 10; Data line 13 is structure as a whole with the source electrode 12 of source-drain electrode; Be formed on passivation layer 14 on the source-drain electrode, and cover whole base plate; Form passivation layer via hole 5 on the passivation layer on the drain electrode 11; Pixel electrode 15 links to each other with drain electrode 11 by passivation layer via hole 5; Grid line protuberance 16 and pixel electrode 15 common formation memory capacitance.
The manufacture craft flow process that it is concrete, shown in Fig. 2 a, deposition grid metal level on glass substrate forms grid line 1 (comprising the grid protuberance), gate electrode 8 by common photoetching and etching technics earlier, and the surface chart that B-B ' locates among Fig. 2 a is shown in Fig. 2 b; Then, shown in Fig. 3 a, deposition gate insulation layer 9, semiconductor layer (active layer and ohmic contact layer) form active layer silicon island 10 by common photoetching and etching technics, and the sectional view that C-C ' locates among Fig. 3 a is shown in Fig. 3 b; Afterwards, shown in Fig. 4 a, sedimentary origin leaks metallic film, forms source electrode 12 and drain electrode 11 by common photoetching and etching, and the sectional view that D-D ' locates among Fig. 4 a is shown in Fig. 4 b; Subsequently, deposit passivation layer 14 shown in Fig. 5 a, and form passivation layer via hole 5 by common photoetching and etching, and the sectional view that E-E ' locates among Fig. 5 a is shown in Fig. 5 b; At last, the pixel deposition electrode film, and by photoetching formation pixel electrode 15, wherein pixel electrode 15 links to each other with drain electrode 11 by passivation layer via hole 5, promptly finishes the making of matrix structure, shown in Fig. 1 a, 1b.
Fig. 6 a is that column shaped spacer is formed on the sectional view that becomes in the technology on the grid line behind the box (Cell), after forming black matrix 17 and color film 18 on the colored filter substrate, position with the grid line correspondence below black matrix 17 forms cylindrical spacer 22, by finding out among the figure that cylindrical spacer 22 is supported on the insulation course of grid line top, thereby keep thick the stablizing of box, but when being under pressure, cylindrical spacer 22 can produce and slide, cause the black matrix 17 and the grid line of below to misplace, thereby the generation light leakage phenomena promptly produces white Mura; Fig. 6 b is that column shaped spacer is formed on the sectional view that becomes in the technology on the thin film transistor (TFT) behind the box (Cell), after forming black matrix 17 and color film 18 on the colored filter substrate, position with the TFT correspondence below black matrix 17 forms cylindrical spacer 22, by finding out among the figure that cylindrical spacer 22 is supported on the TFT top, thereby keep thick the stablizing of box, but when being under pressure, cylindrical spacer 22 can produce and slide, cause the black matrix 17 and the grid line of below to misplace, thereby the generation light leakage phenomena promptly produces white Mura.
Summary of the invention
The objective of the invention is defective at prior art, the scheme that a kind of thin-film transistor LCD array substrate pixel structure is provided and mates with the design of colored filter column shaped spacer, by this structure-improved and manufacture method thereof, can effectively improve white Mura phenomenon, can increase the technology degree of freedom, reduce defective workmanship, improve picture quality.
To achieve these goals, the invention provides a kind of Thin Film Transistor-LCD, comprise: a colored filter substrate and the thin-film transistor array base-plate that is oppositely arranged, liquid crystal layer is packaged between this colored filter substrate and this thin-film transistor array base-plate, wherein said colored filter substrate comprises a top panel, is formed on the color film on the top panel, black matrix and column shaped spacer; Wherein said thin-film transistor array base-plate comprises a lower panel, be formed on one group of grid line on the lower panel and data line, grid line and data line intersects definition one pixel region, and wherein said pixel region comprises a thin film transistor (TFT) and a pixel electrode; Wherein said thin film transistor (TFT) is arranged on the grid line; Described column shaped spacer comprises main chock insulator matter and secondary chock insulator matter, and main chock insulator matter and secondary chock insulator matter laid respectively at the both sides of described thin film transistor (TFT) after colored filter substrate and thin-film transistor array base-plate were oppositely arranged.
In the such scheme, the passivation layer of described main chock insulator matter top and grid line top contact, and the bottom surface at secondary chock insulator matter top is lower than the top, silicon island of thin film transistor (TFT) but does not contact passivation layer above the grid line.The main chock insulator matter of described thin film transistor (TFT) both sides and secondary chock insulator matter can be all near thin film transistor (TFT)s, and main chock insulator matter and secondary chock insulator matter are the 0-4 micron apart from the lateral distance of thin film transistor (TFT).The main chock insulator matter of described thin film transistor (TFT) one side can also adopt between grid line and data line overlapping position and thin film transistor (TFT) and be staggered, one of them main chock insulator matter is near grid line and data line overlapping place, the main chock insulator matter of adjacent with it another is near the thin film transistor (TFT) silicon island, and main chock insulator matter is the 0-4 micron apart from the distance of grid line and side, data line overlapping place, or main chock insulator matter is the 0-4 micron apart from the lateral distance of thin film transistor (TFT), secondary chock insulator matter apart from the lateral distance of thin film transistor (TFT) for being the 0-4 micron.The position of the corresponding main chock insulator matter strong point in described grid line top can also include a guide rail shape active layer, and the guide rail shape active layer is the silicon island part of thin film transistor (TFT).The bottom width 5-40 micron of described main chock insulator matter, top width 5-40 micron, laterally inclined angle is the 30-90 degree.The cross sectional shape of described main chock insulator matter is rectangle, circle, square or other polygons.The density range of described main chock insulator matter is 1/30-1/1.The bottom width of described secondary chock insulator matter is the 5-20 micron, and top width is the 5-20 micron, and laterally inclined angle is the 30-90 degree.The cross sectional shape of described secondary chock insulator matter is rectangle, circle, square or other polygons.The density range of described secondary chock insulator matter is 1/30-1/1.
The present invention can effectively improve white Mura phenomenon with respect to prior art, can increase the technology degree of freedom, reduce defective workmanship, improve picture quality, especially bad to equipment precision, when design proposal that too becomes more meticulous and process conditions do not match,, can realize good compensation not improving specification of equipment and increasing under the prerequisite of exposure technology exposure process.
The present invention is with respect to prior art, can adopt the big chock insulator matter of topside area, when topside area increases, the laterally inclined angle of chock insulator matter is big, iris action is more obvious, dislocation for vertical direction, can adopt the big topside area compensation of main chock insulator matter, when topside area reaches 20 microns, 10 microns technology remaining (margin) is respectively arranged, because actual contact area supports that just area is very little up and down, so can not influence deformation rate because of the main chock insulator matter that has adopted big topside area, can realize simultaneously the chock insulator matter density remaining of more widening, all can select in the scope of main chock insulator matter density range from 1/30 to 1/1 that reason is that main chock insulator matter topside area does not contact entirely with grid line, place a main chock insulator matter when each sub-pix and also can realize, so just strengthened the dirigibility of chock insulator matter design greatly.For the dislocation of horizontal direction, can reduce dislocation by the iris action of main chock insulator matter and thin film transistor (TFT), by the iris action of main chock insulator matter and grid line and data line overlapping part, add that the iris action on secondary chock insulator matter and TFT island compensates simultaneously.So not only can keep thick the stablizing of box, and when being subjected to the external force extruding, cylindrical spacer is equivalent to be stuck at left and right sides both direction, reduce and move, above-below direction is by the top area of main chock insulator matter, prevent that main chock insulator matter from dropping from grid line, thereby can effectively improve white Mura phenomenon, increased the technology degree of freedom, reduced defective workmanship, improved picture quality, in addition, because main chock insulator matter is on grid, rather than on thin film transistor (TFT), itself be exactly a low-energy state, so, improved the grade of product even if also helping the position after having taken place to misplace recovers rapidly.
Below in conjunction with the drawings and specific embodiments the present invention is further illustrated in more detail.
Description of drawings
Fig. 1 a is a dot structure synoptic diagram on the array base palte of prior art;
Fig. 1 b is the sectional view that A-A ' locates among Fig. 1 a;
Fig. 2 a is the floor map after prior art forms grid line and gate electrode;
Fig. 2 b is the sectional view that B-B ' locates among Fig. 2 a;
Fig. 3 a is the floor map after prior art forms the silicon island;
Fig. 3 b is the sectional view that C-C ' locates among Fig. 3 a;
Fig. 4 a is the floor map after prior art forms data line and source, drain electrode;
Fig. 4 b is the sectional view that D-D ' locates among Fig. 4 a;
Fig. 5 a is the floor map after prior art forms via hole;
Fig. 5 b is the sectional view that E-E ' locates among Fig. 5 a;
Fig. 6 a is that column shaped spacer is formed on the sectional view that becomes in the technology on the grid line behind the box (Cell);
Fig. 6 b is that column shaped spacer is formed on the sectional view that becomes in the technology on the thin film transistor (TFT) behind the box (Cell);
Fig. 7 is a dot structure synoptic diagram on the thin-film transistor array base-plate of the present invention;
Fig. 8 a is first implementation column colored filter substrate of the present invention and the thin-film transistor array base-plate skeleton view after to box;
Fig. 8 b is first implementation column colored filter substrate of the present invention and the thin-film transistor array base-plate sectional view after to box;
Fig. 9 a is the floor map after the present invention forms grid line and grid;
Fig. 9 b is the sectional view that F-F ' locates among Fig. 9 a;
Figure 10 a is the floor map after the present invention forms silicon island and active layer track;
Figure 10 b is the sectional view that G-G ' locates among Figure 10 a;
Figure 11 is the floor map after the present invention forms data line and source, drain electrode;
Figure 12 is the floor map after the present invention forms via hole;
Figure 13 is second embodiment of the invention colored filter substrate and the thin-film transistor array base-plate skeleton view after to box;
Figure 14 is third embodiment of the invention colored filter substrate and the thin-film transistor array base-plate skeleton view after to box.
Mark among the figure: 1, grid line; 2, active layer; 4, main chock insulator matter; 5, via hole; 6, secondary chock insulator matter; 7, pixel electrode layer; 8, gate electrode; 9, gate insulation layer; 10, silicon island; 11, drain electrode; 12, source electrode; 13, data line; 14, passivation layer; 15, pixel electrode; 16, grid line teat; 17, black matrix; 18, color film; 19, grid line and data line overlapping position; 20, thin film transistor (TFT); 21, active layer guide rail; 22, column shaped spacer.
Embodiment
Figure 7 shows that the dot structure synoptic diagram of the present invention's one specific embodiment thin-film transistor array base-plate.As shown in Figure 7, this array substrate pixel structure comprises: dielectric substrate; Be formed on grid line 1, gate electrode 8 on the dielectric substrate; Be formed on the gate insulation layer (not drawing among the figure) on the gate electrode 8; Be formed on the silicon island 10 of gate insulation layer, and the silicon island there is part to form the active layer track along grid line; Be formed on the drain electrode 11 and the source electrode 12 of 10 tops, silicon island; Data line 13 is structure as a whole with the source electrode 12 of source-drain electrode; Be formed on the passivation layer on the source-drain electrode, and cover whole base plate (not drawing among the figure); Form the passivation layer via hole 5 on the drain electrode 11; Pixel electrode 15 links to each other with drain electrode 11 by passivation layer via hole 5; Grid line protuberance 16 and pixel electrode 15 common formation memory capacitance.
Wherein, grid line 1 and gate electrode 8 can be the monofilm of AlNd, Al, Cu, Mo, MoW or Cr, also can adopt among AlNd, Al, the Cu one of or arbitrarily and one of Mo, MoW or Cr or any composite membrane of forming, as Mo/AlND/Mo, AlNd/Mo.Gate insulation layer or passivation layer can be one of the monofilm of SiNx, SiOx or SiOxNy or SiNx, SiOx, SiOxNy or any composite membrane of forming.Source electrode 12 and drain electrode 11 can be the monofilm of Mo, MoW or Cr, perhaps for one of Mo, MoW, Cr or form composite membrane arbitrarily.
Fig. 8 a and Fig. 8 b are present embodiment colored filter substrate and thin-film transistor array base-plate skeleton view and the sectional views after to box.Shown in Fig. 8 a and 8b, after forming black matrix 17 and color film 18 on the colored filter substrate, position corresponding with the thin film transistor (TFT) grid line below black matrix 17 forms cylindrical spacer 4, wherein column shaped spacer 4 is made of main chock insulator matter 4 and secondary chock insulator matter 6 two parts, and 4 one of main chock insulator matters are formed on the thin film transistor (TFT) close position, distance is the 0-4 micron, the main chock insulator matter 4 of adjacent with it another is formed near grid line and 19 positions, data line overlapping position, distance is the 0-4 micron, main chock insulator matter 4 is staggered structure setting on whole glass substrate, secondary chock insulator matter 6 is arranged on the opposite side of thin film transistor (TFT), and nearer apart from the thin film transistor (TFT) position, distance is the 0-4 micron.In addition, passivation layer on the active layer track of the top of main chock insulator matter 4 and array base palte grid line top contacts, the passivation layer that forms main chock insulator matter top and grid line top is with the supporting construction in the face of line, and active track layer by layer is the 0-5000 dust as the section difference of passivation layer on the part of thin film transistor (TFT) silicon island and the grid line, its width range is at the 0-20 micron, (these data pin are to the sub-pix of 80*240 micron at the 0-80 micron for length range, if the design size of sub-pix increases or dwindles, active layer rail layer size is done the equal proportion change).
And the top of secondary chock insulator matter 6 does not contact with array base palte, and the bottom surface, top of secondary chock insulator matter 6 is the state of suspending below the extreme higher position of thin film transistor (TFT).
Wherein, the shape of major and minor chock insulator matter can be for various, as rectangle, and circle, square or other polygons, what select in the present embodiment is rectangle; Main chock insulator matter bottom width is the 5-40 micron, and top width is the 5-40 micron, and laterally inclined angle is the 30-90 degree, and is good more near 90 degree effects more; Secondary chock insulator matter bottom width is the 5-20 micron, and top width is the 5-20 micron, and laterally inclined angle is the 30-90 degree, and is good more near 90 degree effects more; The density range of main chock insulator matter and secondary chock insulator matter is 1/30-1/1.
The present invention is owing to formed between insulation course above the grid line below the main chock insulator matter 4 and passivation layer and the corresponding active layer track in cylindrical spacer 4 tops, like this in molding process, cylindrical spacer 4 can be dropped on the grid line this low-energy state position on the passivation layer on the active layer track; The present invention adopts the big main chock insulator matter of topside area in addition, when topside area increases, the laterally inclined angle of main chock insulator matter is big, iris action is more obvious, dislocation for vertical direction, the topside area that main chock insulator matter is big can play compensating action, when topside area reaches 20 microns, 10 microns technology remaining is respectively arranged up and down, because actual contact area, support that just area is very little,, can effectively keep thick the stablizing of box like this so can not influence deformation rate because of the main chock insulator matter that has adopted big topside area.
When upper and lower base plate is subjected to external force and may causes colored filter substrate direction moves left with respect to thin-film transistor array base-plate, thin film transistor (TFT) has barrier effect to secondary chock insulator matter 6, and the 19 pairs of main chock insulator matters 4 near it in grid line and data line overlapping position have barrier effect simultaneously; When upper and lower base plate be subjected to external force may cause colored filter substrate with respect to thin-film transistor array base-plate when right moves, thin film transistor (TFT) has barrier effect to the main chock insulator matter 4 near it, like this when substrate is subjected to external force, cylindrical spacer is equivalent to be stuck at left and right sides both direction, reduces and moves.
Shown in Fig. 8 a to 12, the thin-film transistor array base-plate of LCD can be made by the following method in the foregoing description, below in detail this manufacture method will be described in detail, but should not be construed limitation of the present invention.
At first, shown in Fig. 9 a, adopting magnetically controlled sputter method deposition grid metallic film on the glass substrate or on other substrates, that the grid metallic film adopts is the Mo/AlND/Mo (400/4000/600 ) of three-decker, forms grid line 1 (comprising the grid protuberance), gate electrode by common photoetching and etching technics; The sectional view that F-F ' locates among Fig. 9 a is shown in Fig. 9 b.
Grid metallic film in this step can be the monofilm of AlNd, Al, Cu, Mo, MoW or Cr, also can adopt among AlNd, Al, the Cu one of or arbitrarily and one of Mo, MoW or Cr or any composite membrane of forming, as Mo/AlND/Mo, AlNd/Mo.
Then, deposition grid insulating film (the SiNx of 4000 , do not draw among the figure), semiconductive thin film (comprises active layer (amorphous silicon layers of 1800 ) and ohmic contact layer (N+ silicon layer 500 ), by common mask etching form silicon island 10 and with the active layer track 21 of the grid line top of silicon island one, the vertical view of finishing above-mentioned steps is shown in Figure 10 a, and the sectional view that G-G ' locates among Figure 10 a is shown in Figure 10 b.
Grid insulating film in this step can be one of the monofilm of SiNx, SiOx or SiOxNy or SiNx, SiOx, SiOxNy or any composite membrane of forming.
Then, as shown in figure 11, sedimentary origin leaks metallic film, and the source is leaked metal level and adopted Mo (2200 ), forms source electrode 12 and drain electrode 11 by common photoetching and etching;
The monofilm that metallic film can be Mo, MoW or Cr is leaked in this step source, perhaps for one of Mo, MoW, Cr or form composite membrane arbitrarily.
Subsequently, as shown in figure 12, deposition passivation protection film (2500 PVX) forms via hole 5 by passivation layer mask and passivation layer etching.
At last, pixel deposition electrode ITO layer forms pixel electrode 15 and makes pixel electrode 15 contact conducting with drain electrode 11 by via hole by pixel electrode mask and pixel electrode etching, as shown in Figure 7, finishes the making of thin-film transistor array base-plate.
Under the existing processes condition, finish the design of thin-film transistor array base-plate and colored filter substrate according to said process respectively, and be assembled into box, the relative position of chock insulator matter after the assembling and thin film transistor (TFT) silicon island as shown in Figure 1a.Main chock insulator matter takes alternating expression to arrange.Promptly adopt ZIGZAG to arrange.The main chock insulator matter of neighbor is respectively near grid line and data line overlapping position and thin film transistor (TFT) silicon island.The white MURA of product after the assembling improves significantly.
Under embodiment 1 described content and existing processes condition, finish the design of thin-film transistor array base-plate and colored filter substrate respectively, and be assembled into box.The difference that is embodied is the position of main chock insulator matter, and the column shaped spacer after the assembling and the relative position of thin film transistor (TFT) are as shown in figure 13.Main chock insulator matter does not take alternating expression to arrange.The main chock insulator matter of neighbor is all near the thin film transistor (TFT) side.The white MURA of product after the assembling improves significantly.
Embodiment 3
, under the existing processes condition, finish the design of thin-film transistor array base-plate and colored filter substrate respectively, and be assembled into box according to embodiment 1 described process.The difference that is embodied is the position of main chock insulator matter, and the relative position of chock insulator matter after the assembling and thin film transistor (TFT) side as shown in figure 14.Main chock insulator matter does not take alternating expression to arrange.The main chock insulator matter that faces pixel mutually is all near grid line and data line overlapping part position.The white MURA of product after the assembling improves significantly.
Said structure and manufacture method provide as specific embodiment for the present invention is directed to a specific pixel structure and manufacture method, it is by main chock insulator matter and secondary chock insulator matter are set on colored filter substrate, rely on array base palte upper film transistor or grid line and data line overlapping position barrier effect to the major-minor chock insulator matter, prevent that thin-film transistor array base-plate and colored filter substrate from producing dislocation when being subjected to external force, the master who provides in above-mentioned each implementation column, structure is set should be considered as restriction of secondary chock insulator matter, it can carry out various accommodations, be that spirit of the present invention is at exposure sources or to the cartridge device precision when bad, or the technology remaining is when not enough, increase the technology remaining of product, improve the error tolerance degree of product, thereby improve display quality, it may be used among various dot structures and the manufacture method thereof.
It should be noted that at last, above embodiment is only unrestricted in order to technical scheme of the present invention to be described, although the present invention is had been described in detail with reference to preferred embodiment, those of ordinary skill in the art should can use different materials and equipment to realize it as required, promptly can make amendment or be equal to replacement, and not break away from the spirit and scope of technical solution of the present invention technical scheme of the present invention.
Claims (13)
1, a kind of Thin Film Transistor-LCD, comprise: a colored filter substrate and the thin-film transistor array base-plate that is oppositely arranged, liquid crystal layer is packaged between this colored filter substrate and this thin-film transistor array base-plate, wherein said colored filter substrate comprises a top panel, is formed on the color film on the top panel, black matrix and column shaped spacer; Wherein said thin-film transistor array base-plate comprises a lower panel, be formed on one group of grid line on the lower panel and data line, grid line and data line intersects definition one pixel region, and wherein said pixel region comprises a thin film transistor (TFT) and a pixel electrode; It is characterized in that: described thin film transistor (TFT) is arranged on the grid line; Described column shaped spacer comprises main chock insulator matter and secondary chock insulator matter, and main chock insulator matter and secondary chock insulator matter laid respectively at the both sides of described thin film transistor (TFT) after colored filter substrate and thin-film transistor array base-plate were oppositely arranged.
2, Thin Film Transistor-LCD according to claim 1, it is characterized in that: the passivation layer of the top of described main chock insulator matter and grid line top contact, and the bottom surface, top of secondary chock insulator matter is lower than the top, silicon island of thin film transistor (TFT) but does not contact passivation layer above the grid line.
3, Thin Film Transistor-LCD according to claim 2 is characterized in that: the main chock insulator matter of described thin film transistor (TFT) both sides and secondary chock insulator matter are all near thin film transistor (TFT).
4, Thin Film Transistor-LCD according to claim 3 is characterized in that: described main chock insulator matter and secondary chock insulator matter are the 0-4 micron apart from the lateral distance of thin film transistor (TFT).
5, Thin Film Transistor-LCD according to claim 2, it is characterized in that: the main chock insulator matter of described thin film transistor (TFT) one side adopts between grid line and data line overlapping position and thin film transistor (TFT) and is staggered, one of them main chock insulator matter is near grid line and data line overlapping position, and the main chock insulator matter of adjacent with it another is near the silicon island of thin film transistor (TFT).
6, Thin Film Transistor-LCD according to claim 5, it is characterized in that: described main chock insulator matter is the 0-4 micron apart from the distance of grid line and side, data line overlapping position, or main chock insulator matter is the 0-4 micron apart from the lateral distance of thin film transistor (TFT), and described secondary chock insulator matter is the 0-4 micron apart from the lateral distance of thin film transistor (TFT).
7, according to the arbitrary described Thin Film Transistor-LCD of claim 1 to 6, it is characterized in that: the position of the corresponding main chock insulator matter strong point in described grid line top, a guide rail shape active layer is arranged, the guide rail shape active layer is the silicon island part of thin film transistor (TFT).
8, Thin Film Transistor-LCD according to claim 7 is characterized in that: described main chock insulator matter bottom width 5-40 micron, and top width 5-40 micron, laterally inclined angle is the 30-90 degree.
9, Thin Film Transistor-LCD according to claim 8 is characterized in that: the cross sectional shape of described main chock insulator matter is rectangle, circle, square or other polygons.
10, Thin Film Transistor-LCD according to claim 9 is characterized in that: the density range of described main chock insulator matter is 1/30-1/1.
11, Thin Film Transistor-LCD according to claim 7 is characterized in that: the bottom width of described secondary chock insulator matter is the 5-20 micron, and top width is the 5-20 micron, and laterally inclined angle is the 30-90 degree.
12, Thin Film Transistor-LCD according to claim 11 is characterized in that: the cross sectional shape of described secondary chock insulator matter is rectangle, circle, square or other polygons.
13, Thin Film Transistor-LCD according to claim 12 is characterized in that: the density range of described secondary chock insulator matter is 1/30-1/1.
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| CNB2006101695874A CN100432814C (en) | 2006-12-22 | 2006-12-22 | Liquid crystal display device of thin film transistor |
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