CN101002316A - 具有发射极多晶硅源/漏区的eeprom单元的制造 - Google Patents

具有发射极多晶硅源/漏区的eeprom单元的制造 Download PDF

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CN101002316A
CN101002316A CNA2005800274373A CN200580027437A CN101002316A CN 101002316 A CN101002316 A CN 101002316A CN A2005800274373 A CNA2005800274373 A CN A2005800274373A CN 200580027437 A CN200580027437 A CN 200580027437A CN 101002316 A CN101002316 A CN 101002316A
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M·I·昌德里
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Abstract

一种EEPROM存储单元利用发射极多晶硅膜(701)来制造浅源/漏区以增加阱(105、109、111)的击穿电压。将阱(105、109、111)制造成约100nm(0.1微米(μm))厚并具有约14伏或更高的击穿电压。双极工艺中阱的典型击穿电压约是10伏。由于获得了增加的击穿电压，EEPROM存储单元可连同双极器件一起在单个集成电路芯片上形成并在共用的半导体制造线上制造。

Description

具有发射极多晶硅源/漏区的EEPROM单元的制造
技术领域
这里所描述的发明一般涉及用于制造集成电路结构的工艺，尤其涉及电子存储器件以及制造工艺。
背景技术
半导体存储器件一般分为易失性存储器件和非易失性存储器件。易失性存储器件细分为动态随机存取存储器(DRAM)和静态随机存取存储器(SRAM)。非易失性存储器类型包括可擦除可编程只读存储器(EPROM)和电可擦除可编程只读存储器(EEPROM)。EEPROM越来越多地用于需要连续地更新或辅助存储器件的系统程序设计中。具体地，闪速EEPROM作为大容量存储器件是有利的，因为与常规的EEPROM相比其集成密度比较高。
能够将诸如EEPROM和其它存储器件之类的集成电路器件类型和诸如NPN晶体管之类的双极集成电路混合在单个集成电路芯片上时常是方便的。然而，由于BiCMOS技术中所使用的典型的阱的固有低击穿电压(约10伏)和EEPROM存储器件的高编程电压(约14伏)的要求，没有简单且经济的方式来将这两种器件类型集成到单个集成电路上。以前，在本领域中该问题可通过利用另外的掩模形成用于EEPROM的高电压阱来避免。
发明概述
本发明涉及利用发射极多晶硅膜来制造浅掺杂区的EEPROM存储单元，该浅掺杂区用作EEPROM的源/漏区以增加EEPROM阱的击穿电压。将源/漏区制造成深度约100nm(0.1微米(μm))并具有约14伏的击穿电压。常规的CMOS器件的低击穿电压部分地由于深源/漏区(例如，大于0.2μm)引起。由于本发明实现了增加的击穿电压，因此EEPROM存储单元可连同BiCOMS器件一起形成于单个集成电路芯片上并制造在用于双极和CMOS器件的阱中。
本发明是一种通过在最上面的表面上形成p-阱、掺杂第一源掺杂区和第一漏掺杂区、以及掺杂组合漏/源掺杂区来制造集成电路的方法。阱和掺杂区都被制造在半导体衬底的最上面的表面内。第一漏掺杂区和第一源掺杂区以及第一组合漏/源掺杂区都是轻掺杂的施主部位。还掺杂了一部分栅区，且该栅区具有比源掺杂区或漏掺杂区或组合漏/源掺杂区中的任一个都高的施主部位浓度。然后将多晶硅沉积在第一源掺杂区和第一漏掺杂区上以形成发射极多晶硅区。将该发射极多晶硅区制造成具有比源掺杂区或漏掺杂区或组合漏/源区中的任一个都高的施主浓度。至少一个NMOS晶体管由第一漏掺杂区和组合漏/源掺杂区来制造，且该NMOS晶体管被构造成用作存储单元中的选择晶体管。至少一个另外的NMOS晶体管由第一源掺杂区和组合漏/源掺杂区制造，同时该另外的NMOS晶体管被构造成用作存储单元中的存储晶体管。
本发明还是一种制造在单个集成电路芯片上的电子集成电路。该集成电路芯片包括被构造成控制存储晶体管的工作的第一CMOS晶体管、被构造成作为存储晶体管来工作并耦合到第一晶体管的第二CMOS晶体管、以及至少一个NPN晶体管。第二CMOS晶体管被构造成具有约14伏的编程电压。第一CMOS晶体管和第二CMOS晶体管被构造成作为EEPROM单元来工作。NPN晶体管被构造成具有大于或等于第二CMOS晶体管的编程电压(即，约14伏)的击穿电压。
附图简述
图1示出用于形成本发明的电子器件结构的掺杂区。
图2示出沉积在图1的掺杂区上的多晶硅膜。
图3示出由图2的沉积的多晶硅膜形成的存储晶体管栅多晶硅区和选择晶体管栅多晶硅区。
图4示出沉积在图3的蚀刻层上的氮化物薄膜层。
图5示出蚀刻的氮化物隔片和沉积在图4的蚀刻层上的另外的薄膜层。
图6示出在图5的薄膜叠层中打开的发射极窗口。
图7示出沉积到图6的发射极窗口中以及周围的区域上的发射极多晶硅膜。
图8示出在主要的处理步骤完成后EEPROM存储单元800的横截面。
图9示出添加到图8的EEPROM存储单元800的横截面的触点。
本发明的最佳实施方式
本发明的电子存储器件具有击穿电压相对较高(例如，约14伏或约12-15伏)的源/漏结。典型的BiCOMS工艺中的MOS器件的击穿电压仅是约10伏。较低的阱击穿电压归因于深源/漏掺杂区(例如，约200nm或更大(0.2μm))。利用本发明的发射极多晶硅膜来制造MOS器件的源/漏区得到浅结(即，小于0.1μm)以及所得的较高的击穿电压。因此，高击穿电压允许在集成的CMOS/双极(即，BiCOMS)线中制造本发明，从而允许COMS、双极器件(即，NPN晶体管)以及EEPROM形成于一个集成电路中。
参考图1-9，根据以下处理步骤描述了本发明的示例性实施例。图1包括用于形成诸如EEPROM单元和NPN晶体管之类的电子器件结构的注入的掺杂区的横截面100。图1还包括衬底101、注入的p阱103、轻掺杂存储晶体管源注入105、存储晶体管栅注入107、轻掺杂漏/源注入109以及轻掺杂选择晶体管漏注入111。所有的注入区都通过本领域的技术人员熟知的工艺来形成。或者，p阱103可以是p型掺杂的外延沉积层。
衬底101通常是硅晶片。在该实施例中，硅晶片包含p型掺杂物。或者，可将另一元素族IV半导体或化合物半导体(例如，族III-V或II-VI)选为衬底101。对于p型硅衬底101，形成p阱103的外延沉积层仍将含有p型掺杂物。存储晶体管源注入105和漏/源注入109用n型掺杂物注入，而存储晶体管栅注入107是掩埋n型(n+)。存储晶体管栅注入107用于形成耦合电容器的底板和用于上覆的隧道二级管窗口(TDW)的重掺杂区，以下将参考图2来详细讨论。
在一个具体的示例性实施例中，存储源注入105、存储栅注入107、漏/源注入109以及选择漏注入111都通过离子注入步骤和随后的驱入步骤(例如，快速热退火(RTA))来形成，以具有约100nm(0.1μm)的结深。
图2包括施加在图1的注入掺杂区100上的薄膜叠层的横截面。薄膜叠层包括栅氧化物层201、隧道二级管窗口(TDW)203以及多晶硅层205。栅氧化物层201或者是热生长的，或者通过化学汽相沉积(CVD)来沉积。在栅氧化物层201生长或沉积后，且在多晶硅层205沉积之前，在栅氧化物层201中形成开口以便在其中形成TDW 203。开口通过涂光刻胶层(未示出)、光刻曝光该光刻胶层、然后显影并蚀刻光刻胶层来形成，以形成用于TDW 203的蚀刻掩模。然后，TDW 203可通过诸如湿法蚀刻(例如，诸如包含在标准缓冲氧化物蚀刻等中的氢氟酸蚀刻或正磷酸)或干法蚀刻(例如，反应离子蚀刻(RIE))技术之类的各种蚀刻技术来蚀刻。进行短暂的热氧化步骤以再生长TDW 203的薄隧道氧化物。
在一个具体的示例性实施例中，栅氧化物层201是热生长的，且厚度是18nm-20nm(18-20)，TDW 203的氧化物的厚度是7nm(70)。
参考图3，图2的多晶硅层205通过曝光、显影和蚀刻上覆的光刻胶层(未示出)、并蚀刻多晶硅层205来图案化；该技术对于本领域的技术人员是公知的。在蚀刻后，多晶硅层205形成存储晶体管栅多晶硅区301和选择晶体管栅多晶硅区303。
将氮化物层401沉积在存储晶体管栅多晶硅区301和选择晶体管栅多晶硅区303上(图4)。使氮化物层401图案化并干法蚀刻氮化层401(例如，通过RIE)，从而形成围绕栅多晶硅区301、303的氮化物隔片501(图5)。取决于所选择的用于RIE工艺的蚀刻剂的选择性，可能有氮化物层401的少许过蚀刻以及进入到栅氧化物层201。如果该工艺考虑到了以上讨论的集成CMOS/双极技术，则氮化物隔片501的形成结束CMOS处理步骤。
图5构想了双极器件形成处理步骤的开始，并以CVD氧化物503和第二多晶硅层505的沉积开始。将覆盖CVD氧化物503和第二多晶硅层505的光刻胶(未示出)曝光、显影并蚀刻。蚀刻的光刻胶层用作用于蚀刻CVD氧化物503和第二多晶硅层505的蚀刻掩模，从而形成发射极窗口601(图6)。
参考图7，将发射极多晶硅膜701沉积到图6的发射极窗口(即，存储晶体管源注入105和选择晶体管漏注入111上)和周围的区域上。例如，用砷掺杂发射极多晶硅膜701(形成N+材料)，然后涂另外的光刻胶层(未示出)。对光刻胶和下面的发射极多晶硅膜701的光刻曝光、显影和蚀刻在其中形成用于存储和选择器件的源/漏接触区801(图8)。
参考图9，形成用于耦合到源/漏接触区的金属触点901。金属触点901通过本领域技术人员所熟知的工艺形成。该工艺简要地包括例如，在现存的结构(例如，如图8所示)上沉积CVD介电层、在介电层中图案化并蚀刻通孔(每一个源/漏接触区801上一个)、在通孔的内壁上沉积氮化钛(TiN)或钛(Ti)衬垫、在每一个加衬垫的通孔中沉积钨(W)或铜(Cu)塞。
本领域的技术人员已知的金属化步骤(未示出)在后面用于CMOS和双极器件的处理步骤中将提供实际的连接端子。图9中涉及的主要的处理步骤完成后，使用将本领域技术人员公知的技术来进行例如另外的金属化、电子测试和封装步骤，以完成半导体存储单元器件和一个或多个双极器件。发射极多晶硅沉积和图案化也用于制造双极器件的发射极。
虽然详细示出并描述了处理步骤和技术，但本领域技术人员将认识到，可采用仍包含在所附权利要求书的范围内的其它技术和方法。例如，经常有几种用于沉积薄膜层的技术(例如，化学汽相沉积、等离子体增强汽相沉积、外延、原子层沉积等。)。虽然并非所有的技术都适合于这里所述的所有薄膜类型，但本领域的技术人员将认识到可采用多种方法来沉积给定层和/或薄膜类型。此外，各种技术可用于掺杂半导体中的区域。虽然在示例性实施例中描述了注入，但本领域的技术人员认识到诸如扩散之类的其它掺杂工序可代替此处描述的注入工序或与之结合。此外，按照水平布置的CMOS和双极器件描述了总的布图。然而，本领域技术人员将认识到所公开的本发明同样容易地适用于垂直布置的器件的形成。因此，本发明的范围仅由所附权利要求书的范围限定。

Claims (15)

1.一种集成电路的制造方法，包括：
在半导体衬底的最上面的表面中形成p阱；
在所述半导体衬底的最上面的表面中掺杂第一源掺杂区和第一漏掺杂区，所述第一漏掺杂区和所述第一源掺杂区是轻掺杂施主部位；
在所述半导体衬底的最上面的表面中掺杂组合漏/源掺杂区，所述第一组合漏/源掺杂区是轻掺杂施主部位；
掺杂栅区，所述栅区具有比所述掺杂区或所述漏/源区中的任一个都高的施主部位浓度；
在所述第一源掺杂区和所述第一漏掺杂区上沉积多晶硅以形成发射极多晶硅区，所述发射极多晶硅区具有比所述掺杂区或所述漏/源区中的任一个都高的施主浓度；
由所述第一漏掺杂区和所述组合漏/源掺杂区制造NMOS晶体管，所述NOMS晶体管被构造成用作存储单元中的选择晶体管；
由所述第一源掺杂区和所述组合漏/源掺杂区制造NMOS晶体管，所述NMOS晶体管被构造成用作所述存储单元中的存储晶体管；以及
在所述集成电路中制造双极器件，所述双极器件具有足以承受所述存储单元的编程电压的击穿电压。
2.如权利要求1所述的集成电路制造方法，其特征在于，所述p阱是通过在所述半导体衬底的最上面的表面上沉积外延层来形成的，其中所述外延层被掺杂成具有比所述半导体衬底高的受主部位浓度。
3.如权利要求1所述的集成电路制造方法，其特征在于，所述p阱是通过掺杂至少一部分所述半导体衬底的最上面的表面来形成的，以便具有比所述半导体衬底高的受主部位浓度。
4.如权利要求1所述的集成电路制造方法，其特征在于，还包括由发射极多晶硅区形成用于至少一个NPN晶体管的集电极和发射极区。
5.如权利要求1所述的集成电路制造方法，其特征在于，还包括隧道二级管窗口，其中所述隧道二级管窗口位于所述掺杂的栅区附近，并且所述隧道二级管窗口中的氧化物的厚度约是7纳米。
6.如权利要求1所述的集成电路制造方法，其特征在于，所述第一源掺杂区、所述第一漏掺杂区、所述组合漏/源掺杂区以及所述栅区都被掺杂成约100nm深。
7.一种电子集成电路，包括：
单个集成电路芯片，所述集成电路芯片包括被构造成控制存储晶体管的工作的第一NMOS晶体管；
被构造成作为存储晶体管来工作并耦合到所述第一晶体管的第二NMOS晶体管，所述第二NMOS晶体管被构造成具有约12-15伏的编程电压，所述第一NMOS晶体管和所述第二NMOS晶体管被构造成作为EEPROM单元来工作；以及
至少一个双极器件，所述至少一个双极器件被构造成具有大于或等于所述第二NMOS晶体管的编程电压的击穿电压。
8.如权利要求7所述的电子集成电路，其特征在于，所述第一NMOS晶体管还包括第一漏掺杂区和组合漏/源掺杂区，其中所有的所述掺杂区都被掺杂成约100nm深。
9.如权利要求7所述的电子集成电路，其特征在于，所述第二NMOS晶体管还包括全部都被掺杂成约100nm深的组合漏/源掺杂区、栅区和源区。
10.如权利要求7所述的电子集成电路，其特征在于，所述第二NMOS晶体管还包括隧道二级管窗口。
11.如权利要求10所述的电子集成电路，其特征在于，所述隧道二级管窗口中的氧化物的厚度约是7nm。
12.一种集成电路的制造方法，包括：
在半导体衬底的最上面的表面中形成p阱，所述p阱是通过在所述半导体衬底的最上面的表面上沉积外延层来形成的，所述外延层被掺杂成具有比所述半导体衬底高的受主部位浓度；
在所述p阱中掺杂第一源掺杂区和第一漏掺杂区，所述第一漏掺杂区和第一源掺杂区是轻掺杂施主部位；
在所述p阱中掺杂组合漏/源掺杂区，所述第一组合漏/源掺杂区是轻掺杂施主部位；
掺杂栅区，所述栅区具有比所述掺杂区或所述漏/源区中的任一个都高的施主部位浓度；
在所述第一源掺杂区和所述第一漏掺杂区上沉积多晶硅以形成发射极多晶硅区，所述发射极多晶硅区具有比所述掺杂区或所述漏/源区中的任一个都高的施主浓度；
由所述第一漏掺杂区和所述组合漏/源掺杂区制造NMOS晶体管，所述NOMS晶体管被构造成用作存储单元中的选择晶体管；
由所述第一源掺杂区和所述组合漏/源掺杂区制造NMOS晶体管，所述NMOS晶体管被构造成用作所述存储单元中的存储晶体管；以及
由所述发射极多晶硅区形成用于至少一个NPN晶体管的发射极区。
13.如权利要求12所述的集成电路制造方法，其特征在于，所述第一源掺杂区、所述第一漏掺杂区、所述组合漏/源掺杂区以及所述栅区全部都被掺杂为约100nm深。
14.一种集成电路的制造方法，包括：
在半导体衬底的最上面的表面中形成p阱，所述p阱是通过掺杂所述半导体衬底的最上面的表面的至少一部分来形成的，以具有比所述半导体衬底高的受主部位浓度；
在所述半导体衬底的最上面的表面中掺杂第一源掺杂区和第一漏掺杂区，所述第一漏掺杂区和第一源掺杂区是轻掺杂施主部位；
在所述半导体衬底的最上面的表面中掺杂组合漏/源掺杂区，所述第一组合漏/源掺杂区是轻掺杂施主部位；
掺杂栅区，所述栅区具有比所述掺杂区或所述漏/源区中的任一个都高的施主部位浓度；
在所述第一源掺杂区和所述第一漏掺杂区上沉积多晶硅以形成发射极多晶硅区，所述发射极多晶硅区具有比所述掺杂区或所述漏/源区中的任一个都高的施主浓度；
由所述第一漏掺杂区和所述组合漏/源掺杂区制造NMOS晶体管，所述NOMS晶体管被构造成用作存储单元中的选择晶体管；
由所述第一源掺杂区和所述组合漏/源掺杂区制造NMOS晶体管，所述NMOS晶体管被构造成用作所述存储单元中的存储晶体管；以及
由所述发射极多晶硅区形成用于至少一个NPN晶体管的发射极区。
15.如权利要求14所述的集成电路制造方法，其特征在于，所述第一源掺杂区、所述第一漏掺杂区、所述组合漏/源掺杂区以及所述栅区全部都被形成为约100nm深。
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