CN1005797B - 双端自适应折叠位线布线 - Google Patents
双端自适应折叠位线布线 Download PDFInfo
- Publication number
- CN1005797B CN1005797B CN85107658.0A CN85107658A CN1005797B CN 1005797 B CN1005797 B CN 1005797B CN 85107658 A CN85107658 A CN 85107658A CN 1005797 B CN1005797 B CN 1005797B
- Authority
- CN
- China
- Prior art keywords
- sense amplifier
- bit line
- coupled
- bit lines
- bit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/18—Bit line organisation; Bit line lay-out
Landscapes
- Dram (AREA)
- Static Random-Access Memory (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US66685184A | 1984-10-31 | 1984-10-31 | |
| US666,851 | 1984-10-31 | ||
| US/666851 | 1984-10-31 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN85107658A CN85107658A (zh) | 1986-08-20 |
| CN1005797B true CN1005797B (zh) | 1989-11-15 |
Family
ID=24675755
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN85107658.0A Expired CN1005797B (zh) | 1984-10-31 | 1985-10-14 | 双端自适应折叠位线布线 |
Country Status (3)
| Country | Link |
|---|---|
| EP (1) | EP0180054A3 (enExample) |
| JP (1) | JPS61110400A (enExample) |
| CN (1) | CN1005797B (enExample) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61217994A (ja) * | 1985-03-25 | 1986-09-27 | Nippon Telegr & Teleph Corp <Ntt> | 半導体記憶装置 |
| JPS63161596A (ja) * | 1986-12-25 | 1988-07-05 | Nec Corp | 半導体記憶装置 |
| US4807195A (en) * | 1987-05-18 | 1989-02-21 | International Business Machines Corporation | Apparatus and method for providing a dual sense amplifier with divided bit line isolation |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51147931A (en) * | 1975-06-14 | 1976-12-18 | Fujitsu Ltd | Semiconductor memory circuit |
| DE3101802A1 (de) * | 1981-01-21 | 1982-08-19 | Siemens AG, 1000 Berlin und 8000 München | Monolithisch integrierter halbleiterspeicher |
| JPS57198592A (en) * | 1981-05-29 | 1982-12-06 | Hitachi Ltd | Semiconductor memory device |
| JPS5873095A (ja) * | 1981-10-23 | 1983-05-02 | Toshiba Corp | ダイナミツク型メモリ装置 |
-
1985
- 1985-10-03 EP EP85112541A patent/EP0180054A3/en not_active Withdrawn
- 1985-10-14 CN CN85107658.0A patent/CN1005797B/zh not_active Expired
- 1985-10-30 JP JP60243819A patent/JPS61110400A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| CN85107658A (zh) | 1986-08-20 |
| JPS61110400A (ja) | 1986-05-28 |
| EP0180054A3 (en) | 1988-05-11 |
| JPH0422315B2 (enExample) | 1992-04-16 |
| EP0180054A2 (en) | 1986-05-07 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C13 | Decision | ||
| GR02 | Examined patent application | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CX01 | Expiry of patent term |