CN100576495C - The manufacture method of interconnection structure - Google Patents
The manufacture method of interconnection structure Download PDFInfo
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- CN100576495C CN100576495C CN200610030075A CN200610030075A CN100576495C CN 100576495 C CN100576495 C CN 100576495C CN 200610030075 A CN200610030075 A CN 200610030075A CN 200610030075 A CN200610030075 A CN 200610030075A CN 100576495 C CN100576495 C CN 100576495C
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Abstract
A kind of manufacture method of interconnection structure comprises: the semiconductor-based end with device layer is provided; The cover layer of deposition middle dielectric layer and in-situ deposition and described middle dielectric layer same material in described substrate; In described middle dielectric layer, form opening.The inventive method has been simplified technological process, and wafer needn't take out from reaction chamber, has improved utilization rate of equipment and installations and productivity ratio.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of manufacture method of interconnection structure.
Background technology
When semiconductor technology strided forward to little live width technology node, the interconnection technique of its back segment was also from aluminum metal interconnection development copper interconnection technology, to solve the problem of the needed little interconnection resistance capacitance delays of little live width interconnection technique.Because copper has characteristics such as easy diffusion, difficult etching, traditional aluminum interconnecting manufacturing process also is not suitable for being used for the manufactured copper interconnection line, industry is introduced mosaic technology (Dual Damascene), promptly earlier form middle dielectric layer on the substrate of device and etch groove and through hole having, cement copper enters in the good figure of etching then, and uses flattening method and remove unnecessary copper.It is general in the existing copper interconnection mosaic technology that (Black diamond BD) waits advanced low-k materials as the dielectric layer material with fluorine silex glass, black diamond.Number of patent application is that 200410090926.0 Chinese patent discloses the manufacture method of a kind of black diamond as the metal interconnect structure of middle dielectric layer.Fig. 1～Fig. 3 is the generalized section of its disclosed manufacture method.
As shown in Figure 1, semiconductor substrate 100 at first is provided, in described substrate 100, be formed with a conductor layer 105, described conductor layer 105 materials can be copper or aluminium, deposition one etching stop layer 110 in described substrate then, described etching stopping layer material 110 can be a kind of in carborundum, the silicon nitride.Then, utilize plasma enhanced chemical vapor deposition (PECVD) method on described etching stop layer 110, to deposit the silicon dioxide layer 120 of a doping carbon as intermetallic dielectric layer.
As shown in Figure 2, after finishing the deposition of silicon dioxide layer 120 of doping carbon, described substrate 100 is moved to next process cavity form a cover layer 130 on the silicon dioxide layer 120 of described doping carbon, the thickness of described cover layer 130 is between 300～800 dusts, and its material is carborundum or silicon nitride.
As shown in Figure 3, form opening 140 on the silicon dioxide layer 120 of described doping carbon, described opening 140 comprises groove and connecting hole, fills metal material and promptly form interconnection structure in described groove.
In the above-mentioned open metal interconnect structure manufacture method, intermetallic dielectric layer 120 and cover layer 130 are finished in two step process, promptly behind the silicon dioxide layer 120 that forms doping carbon, substrate 100 need be moved in next process cavity, sedimentary cover 130 again, the processing step complexity, and the increase volume wafer handling number of times and time, reduced productivity ratio.
Summary of the invention
Therefore, the object of the present invention is to provide a kind of manufacture method of interconnection structure, existing middle dielectric layer and cover layer needs two step process are finished to solve, the processing step complicated problems.
For achieving the above object, the manufacture method of a kind of interconnection structure provided by the invention comprises:
The one semiconductor-based end with device layer, be provided;
The cover layer of deposition middle dielectric layer and in-situ deposition and described middle dielectric layer same material in described substrate;
In described middle dielectric layer, form opening.
Described intermediate medium layer material can be advanced low-k materials such as black diamond, fluorine silex glass.
The reaction material of described deposition middle dielectric layer comprises a kind of among OMCTS, the TMCTS.
The assist gas of described deposition middle dielectric layer comprises a kind of or its combination in helium, the oxygen.
The method of described deposition middle dielectric layer is chemical vapour deposition (CVD).
The flow of described OMCTS is 2600～2800mgm.
The flow of described helium is 800～1000sccm, and oxygen flow is 0～300sccm.
The reactive material of described sedimentary cover comprises a kind of among OMCTS, the TMCTS.
The assist gas of described sedimentary cover comprises a kind of or its combination in helium, the oxygen.
The flow of described OMCTS is 600～800mgm.
The flow of described helium is 850～1150sccm, and oxygen flow is 600～800sccm.
The chamber pressure of described sedimentary cover is 3～6torr.
The chamber temp of described sedimentary cover is 300～400 ℃.
Compared with prior art, the present invention has the following advantages: when forming middle dielectric layer and cover layer middle dielectric layer and tectal depositing operation be incorporated in the same processing chamber among the present invention and finish successively, simplified technological process, wafer needn't take out from reaction chamber, reduced the wafer handling number of times, thereby the minimizing wafer is subjected to contamination of heavy and has saved the turnaround time, has improved utilization rate of equipment and installations and productivity ratio.
Description of drawings
Fig. 1～Fig. 3 is existing interconnection structure manufacture method generalized section;
Fig. 4 is the flow chart according to the manufacture method of the embodiment of the invention;
Fig. 5～Figure 10 is the generalized section according to the manufacture method of the embodiment of the invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
The intermediate medium layer material of selecting for use in the copper enchasing technology is generally advanced low-k materials; this class material is because its hardness and density are less; be easy to remove the photoresist step at plasma; sustain damage in the cmp step; deposit intensity and density than the big cover layer of intermediate medium layer material as protective layer; can reduce the possibility that middle dielectric layer is subjected to extraneous damage; general covering layer material adopts silica; silicon nitride; the material of high rigidity such as carborundum and dielectric constant; thereby this cover layer can not do very thick, in order to avoid influence the dielectric constant of middle dielectric layer.Among the present invention, with middle dielectric layer and tectal formation process integration in a step process, wafer need not to take out in the slave unit process cavity after promptly finishing the deposition middle dielectric layer, but directly in same process cavity, on middle dielectric layer, continue deposition and the formation cover layer, the cover layer and the middle dielectric layer that form are made up of identical materials, but the hardness of rete and density are inequality.
Fig. 4 is the flow chart according to the inventive method embodiment.
As shown in Figure 4, at first, provide the semiconductor-based end (S200) with device layer.Described device layer can be a metal oxide semiconductor transistor.Described metal oxide semiconductor transistor can be electrically connected by the metal interconnecting wires on the device layer.
The cover layer (S210) of deposition middle dielectric layer and in-situ deposition and described middle dielectric layer same material on the described semiconductor-based end.During deposition, at first wafer is sent into processing chamber, in process cavity, feed for example for example oxygen, helium of TMCTS, OMCTS and assist gas of reactive material, the flow of described OMCTS is 2600～2800mgm, the flow of described helium is 800～1000sccm, and oxygen flow is 0～300sccm.Reaction chamber temperature can be 300～400 ℃, is 350 ℃ in the present embodiment; Pressure is 5torr.Reaction time is about 17～24S.After finishing the deposition middle dielectric layer, unlike the prior art be, the present invention need not to take out wafer, but continues to feed reacting gas in reative cell and assist gas generates cover layer in a reaction chamber, promptly original position (in sito) forms cover layer.This moment, the flow of described OMCTS was 600～800mgm, the flow of helium is 850～1150sccm, oxygen flow is 600～800sccm, the power of radio frequency source is 400～600W, chamber pressure is 3～6torr, and chamber temp is 300～400 ℃, and temperature is 350 ℃ in the present embodiment, reaction time is 3～6S, and the reaction time is 5S in the present embodiment.Generate the cover layer that thickness is about 200～600 dusts after reaction is finished on middle dielectric layer, this tectal density and thickness are all big than middle dielectric layer.
To finish deposition middle dielectric layer and lithographic equipment is sent at the tectal semiconductor-based end and etching apparatus forms opening on described middle dielectric layer, for example groove and connecting hole (S220).Form connecting hole after the method that forms can be gone ahead of the rest into groove, form groove after also can forming connecting hole earlier.In described groove and connecting hole, fill metal material and promptly form interconnection line.
Below in conjunction with embodiment the inventive method is described in detail.
Fig. 5～Figure 10 is the generalized section according to the manufacture method of the embodiment of the invention.
As shown in Figure 5, be formed with source electrode 202 and drain electrode 204 in the Semiconductor substrate 200, be formed with grid 206 on described Semiconductor substrate 200, described grid material can be polysilicon or metal silicide, isolates by grid oxygen 201 between described grid 206 and the substrate 200.Be formed with insulating barrier 210 on described grid and substrate 200, described insulating barrier 210 materials can be dielectric materials such as silica, silicon nitride, carborundum.In described insulating barrier 210, be formed with connecting hole 208, be filled with conductive materials in the described connecting hole 208, for example tungsten, aluminium or copper.Conductive materials bottom in the described connecting hole 208 is connected with drain electrode 204 with described source electrode 202.Be formed with dielectric layer 215 above described insulating barrier 210, described dielectric layer 215 materials can be advanced low-k materials such as fluorine silex glass, boron-phosphorosilicate glass, form interconnection layer 211 in described dielectric layer 215, and described interconnection layer material can be aluminium or copper.
As shown in Figure 6, on described dielectric layer 215, pass through method accumulation one dielectric layer 220 of physical vapour deposition (PVD) or chemical vapour deposition (CVD), described dielectric layer 220 materials can be a kind of or its combinations in silica, carborundum (SiC), silicon nitride (SiN), carbon silicon oxide compound (SiOC), the nitrogen-doped silicon carbide, and its thickness is 300～800 dusts.This dielectric layer 220 is the etching terminal detection layers that forms connecting hole in the subsequent technique, i.e. etching stop layer (Etch stop layer).
Depositing device is sent at the semiconductor-based end that will be formed with dielectric layer 220, thereon deposition middle dielectric layer 230 and cover layer as shown in Figure 8 240 as shown in Figure 7.Middle dielectric layer 230 and cover layer 240 form in a processing chamber among the present invention, and promptly original position forms cover layer.Described intermediate medium layer material can be advanced low-k materials such as black diamond, fluorine silex glass, and the mode of deposition is chemical vapour deposition (CVD).Forming the black diamond rete with deposition is example, during deposition, wafer is sent into processing chamber, in process cavity, feed for example for example oxygen, helium of TMCTS, OMCTS and assist gas of reactive material, the flow of described OMCTS is 2600～2800mgm, the flow of described helium is 800～1000sccm, oxygen flow is 0～300sccm, reaction chamber temperature can be 300～400 ℃, in the present embodiment be 350 ℃, pressure is 5torr, and radio frequency source power is 450～550W, and the reaction time is about 17～24S.After finishing the deposition middle dielectric layer, unlike the prior art be, the present invention need not to take out wafer, but continues to feed reacting gas and assist gas and generate cover layer in reative cell in same reaction chamber, promptly original position (in sito) forms cover layer.This moment, the flow of described OMCTS was 600～800mgm, the flow of helium is 850～1150sccm, oxygen flow is 600～800sccm, the power of radio frequency source is 400～600W, chamber pressure is 3～6torr, and chamber temp is 300～400 ℃, is 350 ℃ in the present embodiment, reaction time is 3～6S, and the reaction time is 5S in the present embodiment.Generate the cover layer 240 that thickness is about 200～600 dusts after reaction is finished on middle dielectric layer 230, the density of this cover layer 240 and thickness are all big than middle dielectric layer 230.The present invention forms middle dielectric layer 230 and original position, and to form the detailed step of cover layer 240 as follows: the first step is the chamber opening air valve at first, feeds helium (flow 1000sccm) and oxygen (flow 700sccm), and chamber temp is 350 ℃, and the time is about 10s; Second step fed reacting gas OMCTS, and its flow is 700mgm, and continued to feed helium and oxygen with the flow of the first step, and keeping the reaction chamber temperature is 350 ℃; The 3rd step continue to feed OMCTS, oxygen, helium, opened radio frequency source this moment, its power be 500W+/-50W, reacting gas is produced film precursor and some accessory substances under action of plasma; The 4th step, the flow that increases OMCTS to 2700+/-25mgm, and the power of keeping radio frequency source is to produce the film precursor endlessly, move and attached to dielectric layer 220 surfaces on dielectric layer 220 surfaces of film precursor on basad under the drive of plasma, the film precursor is in dielectric layer 220 diffusion into the surfaces simultaneously, surface reaction taking place and generate continuous film, generates some accessory substances simultaneously; The flow of the helium that feeds in this step is 900sccm, the flow of oxygen is 160sccm, help the uniformity of the intermediate medium rete 230 that forms as the oxygen of assist gas and helium and keep the low-k character of film, deposition forms 230 times of middle dielectric layer and is about 18～24s; The 5th step, continue deposition and form cover layer 240, radio frequency source power is constant, the flow that reduces the flow of OMCTS and increase helium is to 1000sccm, the flow of oxygen is 700sccm, this deposition process is approximately 5s, and cover layer 240 films of formation have than the big character of the big density of middle dielectric layer 230 hardness, can be as the protective layer of middle dielectric layer 240; Six, seven steps, finish the deposition of middle dielectric layer 230 and cover layer 240 after, stop to process cavity supply OMCTS, and continue to feed helium and oxygen, in the 8th step, the accessory substance of reaction is taken away simultaneously by pump arrangement.As seen among the present invention the depositing operation of middle dielectric layer 230 and cover layer 240 is incorporated in the same processing chamber and finishes successively, simplified technological process, wafer needn't take out from reaction chamber, reduced the wafer handling number of times, thereby the minimizing wafer is subjected to contamination of heavy and has saved the turnaround time, has improved utilization rate of equipment and installations and productivity ratio.
Need to prove that it is not unique forming middle dielectric layer and tectal parameter setting among the present invention, can be according to revising the cover layer that technological parameter obtains the middle dielectric layer of differing dielectric constant and different hardness and density, thickness; Middle dielectric layer also can be other advanced low-k materials among the present invention, and the raw material material that forms middle dielectric layer also need not be confined to OMCTS, for example also can be TMCTS, and its technological parameter can be set according to different situations, enumerates no longer one by one.
As shown in Figure 9, form opening 250 in described middle dielectric layer 230, described opening comprises groove and connecting hole, for the ground floor interconnection structure, also can be groove.The cover layer of this moment can be used as the damage that the protective layer protection middle dielectric layer 230 that forms when removing photoresist behind the opening is not subjected to the oxygen gas plasma podzolic process.The interconnection line 211 of the end point detection layer protection lower floor when etching stop layer 220 forms opening as etching is injury-free.
As shown in figure 10, in described opening 250, fill metal for example aluminium or copper formation interconnection line.
When forming middle dielectric layer and cover layer, the depositing operation of middle dielectric layer 230 and cover layer 240 is incorporated in the same processing chamber among the present invention and finishes successively, simplified technological process, wafer needn't take out from reaction chamber, reduced the wafer handling number of times, thereby the minimizing wafer is subjected to contamination of heavy and has saved the turnaround time, has improved utilization rate of equipment and installations and productivity ratio.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (4)
1, a kind of manufacture method of interconnection structure comprises:
The one semiconductor-based end with device layer, be provided;
Deposit middle dielectric layer in described substrate, wherein, the flow of OMCTS is 2600～2800mgm, and the flow of helium is 800～1000sccm, and oxygen flow is 0～300sccm, and reaction chamber temperature is 300～400 ℃, and radio frequency source power is 450～550W;
In-situ deposition and described middle dielectric layer same material but hardness and density are greater than the cover layer of described middle dielectric layer, wherein the flow of OMCTS is 600～800mgm, the flow of helium is 850～1150sccm, oxygen flow is 600～800sccm, reaction chamber temperature is 300～400 ℃, and the power of radio frequency source is and the identical power of deposition middle dielectric layer;
In described middle dielectric layer, form opening.
2, the manufacture method of interconnection structure as claimed in claim 1 is characterized in that: described intermediate medium layer material is black diamond or fluorine silex glass.
3, the manufacture method of interconnection structure as claimed in claim 1 is characterized in that: the method for described deposition middle dielectric layer is chemical vapour deposition (CVD).
4, the manufacture method of interconnection structure as claimed in claim 1 is characterized in that: the chamber pressure of described sedimentary cover is 3～6torr.
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| CN101996878B (en) * | 2009-08-11 | 2012-09-26 | 中芯国际集成电路制造(上海)有限公司 | Method for depositing low-dielectric constant insulating material layer |
| CN102053169B (en) * | 2009-11-10 | 2014-02-05 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing failure analysis sample in interconnection structure |
| CN102446725A (en) * | 2010-10-14 | 2012-05-09 | 中芯国际集成电路制造(上海)有限公司 | Cascaded grid production method |
| CN112271254B (en) * | 2020-10-27 | 2021-12-28 | 长江先进存储产业创新中心有限责任公司 | Phase change memory and manufacturing method thereof |
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Effective date of registration: 20111115 Address after: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Co-patentee after: Semiconductor Manufacturing International (Beijing) Corporation Patentee after: Semiconductor Manufacturing International (Shanghai) Corporation Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Patentee before: Semiconductor Manufacturing International (Shanghai) Corporation |
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