CN100570849C - Shallow groove isolated forming process - Google Patents
Shallow groove isolated forming process Download PDFInfo
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- CN100570849C CN100570849C CNB200610147949XA CN200610147949A CN100570849C CN 100570849 C CN100570849 C CN 100570849C CN B200610147949X A CNB200610147949X A CN B200610147949XA CN 200610147949 A CN200610147949 A CN 200610147949A CN 100570849 C CN100570849 C CN 100570849C
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Abstract
The present invention has disclosed a kind of shallow groove isolated forming process, comprising: active area liner oxidation and silicon nitride deposition; Dielectric reflection film deposition; Active area cushion oxide layer, dielectric reflection film and active area etching are wherein for the soft etching of being etched to of active area, to form the gradient at active area; Clearance wall oxidation, deposition and etching; The shallow trench etching; Shallow trench inwall oxide isolation layer and high-density plasma oxide deposition.Adopt technical scheme of the present invention, soft etching by active area forms the gradient, make and when carrying out the shallow trench etching forming, can easily obtain uniform circular drift angle, shallow trench etching step complicated in the prior art and Liner Oxidation step have repeatedly been avoided, reduce cost, improved production efficiency.
Description
Technical field
The present invention relates to semiconductor fabrication process, more particularly, relate to a kind of shallow groove isolated forming process.
Background technology
Along with constantly dwindling of feature sizes of semiconductor devices, the area of isolation between the device also will dwindle thereupon accordingly.Most widely used isolation technology is LOCOS (Local oxide isolate) technology in the integrated circuit fabrication process more than 0.35 micron at present.Though this technology developing history is longer, also comparative maturity of technology, but owing to adopted oxidation technology, so the degree of depth of oxide-film and because the beak effect that produces on the active region of oxidation and area edge on the scene has all limited the further application of this technology.Shallow trench isolation from (STI:shallowtrench isolate) technology then be for corresponding below 0.35 micron deep submicron process and a kind of isolation technology of developing.Though the shallow trench isolation technology is widely used in batch process, the pattern that how to improve shallow trench is to obtain desirable leakage current characteristic, and good narrow-channel effect still has many work to do.
By facts have proved, the drift angle shape of shallow trench has very big influence for the overall performance of device.Such as the double-hump effect of metal-oxide-semiconductor, anti-narrow channel effect etc.
In the shallow groove isolated forming process that uses at present, in order to obtain good shallow trench shape, need carry out particular processing, use special shallow trench inwall oxide isolation layer (LinerOxidation) or 2 times Liner Oxidation to obtain desirable shallow trench shape such as needs.Such as, in the process of Liner Oxidation, should be noted that the consistency of the radius that keeps shallow trench drift angle fillet and the radius of other regional drift angle fillet, with the performance of assurance device.
The shallow trench Liner Oxidation of relative complex or 2 times Liner Oxidation have increased the overall complexity of shallow groove isolated forming process, make cost improve, and therefore the efficient of production also reduce.So, just need a kind of effectively shallow groove isolated forming process, can obtain good shallow trench shape by simple relatively mode.
Summary of the invention
Purpose of the present invention aims to provide a kind of new shallow groove isolated forming process, can obtain good shallow trench shape by simple relatively mode.
According to of the present invention, a kind of shallow groove isolated forming process is provided, comprising: active area liner oxidation and silicon nitride deposition; Dielectric reflection film deposition; Active area cushion oxide layer, dielectric reflection film and active area etching are wherein for the soft etching of being etched to of active area, to form the gradient at active area; Clearance wall oxidation, deposition and etching; The shallow trench etching; Shallow trench inwall oxide isolation layer and high-density plasma oxide deposition.
According to an embodiment, this technology also comprises: also comprise the step that forms protective layer after dielectric reflection film deposition, this protective layer defines when the active area etching needs etched zone; And before clearance wall oxidation, deposition and etching, also comprise the step of eliminating protective layer,
Wherein, the active area that is etched in of described active area forms the shape that caves inward, and center to edge forms the gradient.The LPVCD oxidation technology is adopted in the clearance wall oxidation, by different LPVCD oxide thickness, obtains different clearance wall width.
This shallow groove isolated forming process can obtain to have the shallow trench of even round drift angle.
Adopt technical scheme of the present invention, soft etching by active area forms the gradient, make and when carrying out the shallow trench etching forming, can easily obtain uniform circular drift angle, shallow trench etching step complicated in the prior art and Liner Oxidation step have repeatedly been avoided, reduce cost, improved production efficiency.
Description of drawings
The above and other features of the present invention, character and advantage will become more obvious by the description below in conjunction with drawings and Examples, in the accompanying drawings, identical Reference numeral is represented identical feature all the time, wherein,
Fig. 1-Fig. 5 shows according to the technological process from manufacturing process of the shallow trench isolation of one embodiment of the invention;
Fig. 6 is according to the shallow trench isolation of one embodiment of the invention flow chart from manufacturing process.
Embodiment
With reference to figure 1-Fig. 6, wherein Fig. 1-Fig. 5 shows according to the technological process from manufacturing process of the shallow trench isolation of one embodiment of the invention; Fig. 6 is according to the shallow trench isolation of one embodiment of the invention flow chart from manufacturing process.The invention provides a kind of shallow groove isolated forming process 100, comprising:
102. active area liner oxidation and silicon nitride deposition.With reference to shown in Figure 1, on active area (ActiveArea), carry out liner oxidation, form pad oxide PAD, afterwards deposited silicon nitride SiN on this pad oxide PAD.
104. dielectric reflection film deposition.With reference to structure shown in Figure 2, after deposited silicon nitride SiN, continue deposit dielectric anti-reflective film on SiN (Dielectric AntiReflectingCoating, DARC).
106. active area cushion oxide layer, dielectric reflection film and active area etching are wherein for the soft etching of being etched to of active area, to form the gradient at active area.Continue with reference to shown in Figure 2; define by protective layer (for example photoresistance) PR and need carry out etched zone; carry out active area cushion oxide layer, dielectric reflection film and active area etching afterwards, wherein for the soft etching that is etched to of active area substrate S ubstrate, to form the gradient.With reference to shown in Figure 2, this active area forms the shape that caves inward, and center to edge forms the gradient.This gradient will help can easily obtain uniform circular drift angle when carrying out the shallow trench etching forming.
108. clearance wall oxidation, deposition and etching.With reference to figure 3, carry out oxidation, deposition and the etching of clearance wall Spacer.Before carrying out this step, also need to eliminate protective layer PR.The LPVCD oxidation technology is adopted in clearance wall Spacer oxidation, by different LPVCD oxide thickness, obtains different clearance wall width.
110. shallow trench etching.With reference to figure 4, carry out shallow trench etching forming step.
112. shallow trench inwall oxide isolation layer (Liner Oxidation) and high-density plasma oxide deposition (HDP deposition).With reference to shown in Figure 5,, therefore can easily obtain uniform circular drift angle in step 110 and 112 because the soft etching by active area has formed the gradient in step 106.
Adopt technical scheme of the present invention, soft etching by active area forms the gradient, make and when carrying out the shallow trench etching forming, can easily obtain uniform circular drift angle, shallow trench etching step complicated in the prior art and Liner Oxidation step have repeatedly been avoided, reduce cost, improved production efficiency.
Though technical scheme of the present invention is illustrated in conjunction with preferred embodiment; but it should be appreciated by those skilled in the art; various modifications or change for the above embodiments are predictable; this should not be regarded as having exceeded protection scope of the present invention; therefore; protection scope of the present invention is not limited to above-mentioned specifically described embodiment, and should be the most wide in range scope that meets the inventive features that discloses in this place.
Claims (5)
1. shallow groove isolated forming process comprises:
Active area liner oxidation and silicon nitride deposition;
Dielectric reflection film deposition;
Active area cushion oxide layer, dielectric reflection film and active area etching are wherein for the soft etching of being etched to of active area, to form the gradient at active area;
Clearance wall carries out oxidation, deposition and etching, to form clearance wall on the sidewall of cushion oxide layer, silicon nitride layer and dielectric reflection film;
The shallow trench etching;
Shallow trench inwall oxide isolation layer and high-density plasma oxide deposition.
2. shallow groove isolated forming process as claimed in claim 1 is characterized in that,
Also comprise the step that forms protective layer after dielectric reflection film deposition, this protective layer defines when the active area etching needs etched zone; And
Carrying out oxidation, deposition and etching, before forming clearance wall on the sidewall of cushion oxide layer, silicon nitride layer and dielectric reflection film, also to comprise the step of eliminating protective layer.
3. shallow groove isolated forming process as claimed in claim 2 is characterized in that,
The active area that is etched in of described active area forms the shape that caves inward, and center to edge forms the gradient.
4. shallow groove isolated forming process as claimed in claim 3 is characterized in that,
The LPVCD oxidation technology is adopted in the clearance wall oxidation, by different LPVCD oxide thickness, obtains different clearance wall width.
5. shallow groove isolated forming process as claimed in claim 4 is characterized in that,
The shallow trench isolation that described shallow groove isolated forming process obtains to have even round drift angle from.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB200610147949XA CN100570849C (en) | 2006-12-25 | 2006-12-25 | Shallow groove isolated forming process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB200610147949XA CN100570849C (en) | 2006-12-25 | 2006-12-25 | Shallow groove isolated forming process |
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| CN101211816A CN101211816A (en) | 2008-07-02 |
| CN100570849C true CN100570849C (en) | 2009-12-16 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB200610147949XA Expired - Fee Related CN100570849C (en) | 2006-12-25 | 2006-12-25 | Shallow groove isolated forming process |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104022066B (en) * | 2014-04-22 | 2017-01-04 | 上海华力微电子有限公司 | A kind of method forming shallow trench isolation |
| CN104658902B (en) * | 2015-01-28 | 2018-05-08 | 株洲南车时代电气股份有限公司 | Trench gate engraving method |
| CN112880554B (en) * | 2021-01-18 | 2022-01-11 | 长江存储科技有限责任公司 | Preparation method of standard plate of infrared interferometer, standard plate and global calibration method |
| CN113782484A (en) * | 2021-11-11 | 2021-12-10 | 广州粤芯半导体技术有限公司 | Method for manufacturing semiconductor device |
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Effective date of registration: 20111121 Address after: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Co-patentee after: Semiconductor Manufacturing International (Beijing) Corporation Patentee after: Semiconductor Manufacturing International (Shanghai) Corporation Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Patentee before: Semiconductor Manufacturing International (Shanghai) Corporation |
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