CN1260803C

CN1260803C - Forming process of shallow channel

Info

Publication number: CN1260803C
Application number: CN 01132667
Authority: CN
Inventors: 赖二琨; 陈昕辉; 黄宇萍
Original assignee: Macronix International Co Ltd
Current assignee: Macronix International Co Ltd
Priority date: 2001-09-06
Filing date: 2001-09-06
Publication date: 2006-06-21
Anticipated expiration: 2021-09-06
Also published as: CN1404128A

Abstract

The present invention provides a forming process of a trench structure, which at least comprises the following steps: a pad oxide layer is formed on a substrate; a first polysilicon layer is formed on the pad oxide layer; an oxide layer is formed on the first polysilicon layer; a second polysilicon layer is formed on the oxide layer; part of the second polysilicon layer, the oxide layer, the first polysilicon layer and the pad oxide layer are removed to expose part of the substrate; the second polysilicon layer and part of the substrate are etched to form a trench structure in the substrate and expose the oxide layer. The etched depth of the trench structure is well controlled via the etched thickness of the second polysilicon layer.

Description

A kind of formation method of shallow trench

Technical field

The present invention relates to a kind of method that forms shallow trench, relate in particular to a kind of little year (micro-loading) and the shallow ridges groove forming method that reduces corner depression (corner recess) can reduce shallow trench and form the time.

Background technology

The shortcoming of traditional area oxidation isolated component is between the heat of oxidation on the scene, and it is heavily stressed and cause defective to form that it is easy to be subjected under nitration case, narrow and small active region produces; Secondly, also be easy to produce defective because of the Kooi effect.When physical dimension is dwindled gradually, when beak is invaded (bird ' s beak encroachment) and taken an oxygen surface area most of, cause the formation of defective more easily.Thereby when isolating the semiconductor element below 0.35 micron, the shortcoming that overcomes conventional method is very important to form the good isolation zone.

Using shallow trench isolation to come isolated component from (shallow-trench isolation) technology in integrated circuit fabrication process is a kind of way.Generally speaking, on the semiconductor ground, use silicon nitride, use anisotropic etching manufacturing process to form precipitous groove as shade.Then, fill up groove forming the shallow trench isolated component with oxide, its surface is that the surface with ground has same level height.

Unfortunately, for high integrated circuit, when the etching shallow slot structure, the situation that has little year produces; So (time-mode) etching of temporal mode causes being difficult to control the degree of depth of shallow ditch groove structure.At shallow trench isolation after forming, the problem of corner depression also can cause shallow trench isolation from deterioration.

In any case, when forming the shallow trench isolated component, how to improve its characteristic, and reduce semiconductor element reliability deterioration, be very important problem.

Summary of the invention

In above-mentioned background of invention, the invention provides a kind of method that forms the shallow trench isolated component; The degree of depth of groove is controlled by the thickness of polysilicon, and non-traditional temporal mode (time-mode) is controlled

Another object of the present invention is to provide a kind of form the trench isolations element method.Little year phenomenon when utilizing polysilicon layer can avoid the trench isolations element to form and Kooi effect.

A further object of the present invention is to provide the method that forms the trench isolations element; When forming the backing layer (liner layer) of groove, the oxidation of polysilicon layer can avoid the corner depression situation of groove to produce.

According to above-described purpose, disclosed a kind of formation method of groove structure, comprise at least: form pad oxide on ground; Form first polysilicon layer on pad oxide; Form oxide layer on first polysilicon layer; Form second polysilicon layer on oxide layer; Remove part second polysilicon layer, oxide layer, first polysilicon layer and pad oxide to expose the part ground; And etching second polysilicon layer and part ground with the formation groove structure in ground, and expose oxide layer.The etch depth of groove structure has good control by the etched thickness of second polysilicon layer.

Description of drawings

The present invention cooperates following figure that more deep understanding can be arranged:

Figure 1A to Fig. 1 F is a succession of generalized section that forms the shallow trench isolated component with the inventive method.

Embodiment

Semiconductor design of the present invention can be widely applied in many semiconductor design, and can utilize many different semi-conducting material manufacturings, when the present invention illustrates the inventive method with a preferred embodiment, being familiar with the due cognition of person of this field is that many steps can change, material and impurity are also replaceable, and these general replacements also do not break away from spirit of the present invention and category far and away.

Secondly, the present invention is described in detail as follows with schematic diagram, and when the detailed description embodiment of the invention, the profile of expression semiconductor structure can be disobeyed general ratio and be done local the amplification in order to explanation in the semiconductor fabrication process, so should be with this as the cognition that qualification is arranged.In addition, in the making of reality, should comprise the three dimensions size of length, width and the degree of depth.

In this embodiment, disclose a kind of formation method of groove structure, comprise at least: form a pad oxide on ground; Form first polysilicon layer on pad oxide; Form oxide layer on first polysilicon layer; Form second polysilicon layer on oxide layer; Remove part second polysilicon layer, oxide layer, first polysilicon layer and pad oxide to expose the part ground; And etching second polysilicon layer and part ground with the formation groove structure in ground, and expose oxide layer.The etch depth of groove structure has good control by the etched thickness of second polysilicon layer.Then, when the sidewall of groove structure forms backing layer, on the sidewall of first polysilicon layer, form sidewall oxide, can protect groove structure, to avoid the corner depression.

With reference to Figure 1A, on silicon base material 10, form pad oxide 20, polysilicon layer 30, oxide layer 40 form in regular turn thereon with another polysilicon layer 50.On polysilicon layer 50, form photoresist layer 60 through pattern transfer, definition trench isolations.

Etching polysilicon layer 50, oxide layer 40, polysilicon layer 30 and pad oxide 20 are to expose the part surface of silicon base material 10; Remove photoresist layer 60 then, shown in Figure 1B.

One of committed step of the present invention, the surface of the silicon base material 10 of etch exposed is to form groove in silicon base material 10; The etching of silicon base material 10 is controlled by etched polysilicon layer 50 of while, and etching stops at oxide layer 40.Moreover, little year (micro-loading) situation when etching can avoid groove to form in the time of polysilicon layer 50 and silicon base material 10.So, the degree of depth of groove is controlled by the thickness of polysilicon layer 50, shown in Fig. 1 C.

Then, form backing layer 70 by the sidewall oxidation of groove; When backing layer 70 formed, the sidewall oxide 90 of polysilicon layer 30 (side-wall oxide layer) also can form, shown in Fig. 1 D; Because of no thin layer of sin, so in the high-temperature oxidation process of sidewall oxide 90, do not have the situation of Kooieffect.

Then with the silica of high density plasma CVD, the cmp mode after following forms groove structure 80.Afterwards, remove oxide layer 40 and polysilicon layer 30 with suitable method, shown in Fig. 1 E.

Afterwards, remove pad oxide 20; One of committed step of the present invention, when removing pad oxide 20, sidewall oxide 90 can be protected groove structure 80, to avoid the corner depression, shown in Fig. 1 F.

The above is preferred embodiment of the present invention only, is not in order to limit claim of the present invention; All other do not break away from the equivalence of being finished under the disclosed spirit and changes or modification, all should be included in the following claim scope.

Claims

1. the formation method of a groove structure, this method comprises at least:

Form pad oxide on ground;

Form first polysilicon layer on this pad oxide;

Form oxide layer on this first polysilicon layer;

Form second polysilicon layer on this oxide layer;

Remove this second polysilicon layer of part, this oxide layer, this first polysilicon layer and this pad oxide to expose this ground of part; And

This second polysilicon layer of etching and this ground of part to be forming this groove structure in this ground, and expose this oxide layer.

2. method as claimed in claim 1 is characterized in that, also comprises forming backing layer on the first side wall of this groove structure.

3. method as claimed in claim 2 is characterized in that, also comprises forming sidewall oxide on second sidewall of this first polysilicon layer.

4. method as claimed in claim 1 also comprises:

Dielectric layer and is inserted in this groove structure on this oxide layer;

This dielectric layer of planarization and this oxide layer; And

Remove this first polysilicon layer and this pad oxide.

5. method as claimed in claim 4 is characterized in that, above-mentioned deposition step forms with the high density plasma CVD method.

6. the formation method of a groove structure, this method comprises at least:

Form pad oxide on ground;

Form first polysilicon layer on this pad oxide;

Form oxide layer on this first polysilicon layer;

Form second polysilicon layer on this oxide layer;

Remove this second polysilicon layer of part, this oxide layer, this first polysilicon layer and this pad oxide to expose this ground of part;

This second polysilicon layer of etching and this ground of part to be forming groove structure in this ground, and expose this oxide layer; And

Form simultaneously backing layer on the sidewall of this groove structure with sidewall oxide on the sidewall of this first polysilicon, this sidewall oxide is in order to protecting this groove structure, to avoid the corner depression.

7. method as claimed in claim 6 is characterized in that, also comprises:

Insert dielectric layer in this groove structure with this oxide layer on; And

This dielectric layer of planarization and this oxide layer.

8. method as claimed in claim 7 is characterized in that above-mentioned dielectric layer comprises silicon oxide layer at least.

9. method as claimed in claim 7 is characterized in that above-mentioned dielectric layer comprises polysilicon layer at least.