CN100561349C - Prevent the bit line method for making of the COB-DRAM of bit line collapse - Google Patents
Prevent the bit line method for making of the COB-DRAM of bit line collapse Download PDFInfo
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- CN100561349C CN100561349C CNB2006100265883A CN200610026588A CN100561349C CN 100561349 C CN100561349 C CN 100561349C CN B2006100265883 A CNB2006100265883 A CN B2006100265883A CN 200610026588 A CN200610026588 A CN 200610026588A CN 100561349 C CN100561349 C CN 100561349C
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- bit line
- coating
- metal
- oxide skin
- deposit
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Abstract
The present invention relates to prevent the bit line method for making of the COB-DRAM of bit line collapse.This method adopts " opposite-bit line " (Reverse-Bitline) method for making.Promptly after forming bit line plug metal and deposit first oxide skin(coating), carry out the bit line etching groove, after forming the bit line spacer layer then, fill barrier layer and bit line metal between bit line metal and the oxide skin(coating), and it is carried out planarization and eat-back, form bit line, form hard mask and deposit second oxide skin(coating) again and make.The advantage of this method is no matter whether the detection critical size of bit line is too little, can not produce the problem of bit line collapse.
Description
Technical field
The present invention relates to (the CapacitorOver Bit Line-Dynamic Random Memory of capacitor type dynamic RAM on the manufacture of semiconductor neutrality line, the method for making of bit line COB-DRAM) particularly relates to the bit line method for making of the COB-DRAM of problems such as can solving bit line collapse, destruction.
Background technology
For the consideration of cost and high travelling speed, it is more and more littler that size of devices becomes.Therefore the manufacture craft to integrated circuit has proposed more challenges.
In the manufacturing process of present COB-DRAM device, bit line manufacturing process usually goes wrong, as the collapse of the bit line after the bit line etching, destruction etc.Along with device size is more and more littler, this problem will be more and more serious.
As the bit line method for making of prior art shown in Figure 1A～1C.At first with reference to Figure 1A, (1) deposit on prefilter layer 101 be used to form the contact of second polysilicon (Poly Two Contact, high-density plasma P2C) (High Density Plasma, HDP) oxide skin(coating) 102; (2) form the second polysilicon contact hole 103 (that is, and Poly Two Contact 1, P2C1 and Poly Two Contact2, P2C2); (3) be deposited on barrier layer (Barrier) Titanium/titanium nitride layer 104 between bit line metal and contacting metal and the oxide skin(coating); (4) contacting metal tungsten, 105 deposits of bit line tungsten metal; (5) hard mask silicon nitride 106 deposits of bit line; (6) form bit line photoresist pattern 107; (7) then with reference to Figure 1B, carry out bit line metal hard mask silicon nitride etch, form silicon nitride mask 1061; (8) etching bit line tungsten and barrier layer metal form bit line 1051; (9) shown in Fig. 1 C, deposit wall silicon nitride goes forward side by side in the ranks that interlayer eat-backs, and forms bit line spacer layer 108; (10) deposit is used to form the contact of the 3rd polysilicon (Poly Three Contact, high-density plasma monox (HDP-SiO P3C)
2) layer 109, and carrying out planarization with cmp (CMP), the deposit plasma strengthens oxide skin(coating) (Plasma Enhanced Oxide, PEOX) 110 again.
In the step in above-mentioned manufacturing process (8), after finishing the bit line etching, because it is too little to detect critical size after the etching, in the removal photoresist and wet-cleaned process after the bit line etching, cause the collapse (shown in Fig. 2 A) of bit line, and pollute other bit lines, (shown in Fig. 3 A, 3B).
Along with device size is more and more littler, this problem will be more and more serious, therefore need new solution.
Summary of the invention
In order to solve the bit line crash issue that occurs in the above-mentioned too little bit line critical size bit line manufacturing process, the present invention has been proposed.
The object of the invention is to provide a kind of bit line method for making that overcomes the bit line crash issue that has.
The present invention's employing " opposite-bit line " (Reverse-Bitline) method has realized above-mentioned purpose." opposite-bit line " (Reverse-Bitline) method is meant on the contrary with the method that at first forms bit line tungsten of prior art, at first forms the bit line groove of oxide skin(coating), forms processes such as wall, barrier layer, bit line tungsten then successively.
The bit line method for making that prevents the COB-DRAM of bit line collapse of the present invention comprises the steps:
A) deposit is used to form the second polysilicon contact hole (Poly Two Contact, oxide skin(coating) P2C);
B) etching form the second polysilicon contact hole (that is, and Poly Two Contact 1, P2C1 and Poly Two Contact 2, P2C2);
C) carry out the contacting metal deposit of contacting metal and the barrier layer between the oxide skin(coating) (Barrier) the metal deposit and the metal plug of metal plug;
D) carry out the planarization (CMP) of the contacting metal of described barrier layer and metal plug, end at the described oxide skin(coating) that forms the second polysilicon contact hole;
E) deposit one first oxide skin(coating), and form bit line trench lithography glue pattern;
F) bit line etching groove;
G) bit line spacer layer deposit, and eat-back (Etching Back);
H) barrier layer (Barrier) the metal deposit between bit line metal and described first oxide skin(coating);
I) bit line metal deposit, and planarization ends at first oxide skin(coating) that forms the bit line groove;
J) the bit line metal eat-backs (Etching Back);
K) bit line hard mask layer deposition of materials, and eat-back, stop at described first oxide skin(coating) that forms the bit line groove;
L) deposit second oxide skin(coating).
The method according to this invention, (Poly TwoContact, oxide skin(coating) P2C) are high-density plasma (High Density Plasma, HDP) oxides to the second polysilicon contact hole that is used to form of deposit.
The method according to this invention, the contacting metal of the metal plug that forms in the second polysilicon contact hole and the barrier layer between the oxide skin(coating) (Barrier) they are titanium/titanium nitrides, the contacting metal of metal plug is a tungsten.
The method according to this invention, cmp (CMP) is adopted in the contacting metal tungsten planarization of metal plug.
The method according to this invention, first and second oxide skin(coating)s are plasma-reinforced chemical vapor deposition method (Plasma Enhanced Oxide, PEOX) silicon oxide layers of deposit.
Barrier layer (Barrier) between bit line metal of the present invention and the oxide skin(coating) is titanium/titanium nitride, the bit line metal is a tungsten, and the planarization of bit line metal adopt cmp, bit line metal to eat-back to adopt reactive ion etching (Reactive Ion Etch, RIE).
The method according to this invention, the hard mask of bit line adopts silicon nitride.
According to bit line method for making of the present invention, at first the deposit first oxide plasma strengthens oxide (PEOX) layer, resist coating layer then, and photoetching, developing defines this bit line position.Then the etching plasma strengthens oxide skin(coating) and forms a groove, and barrier layer (Barrier) titanium/titanium nitride and the tungsten between deposit wall, bit line metal and the oxide skin(coating) forms bit line therein.
Because the first oxide skin(coating) etching produces the groove that is used to fill as the tungsten metal of bit line, so the formation of bit line is to be made in the mode of deposition tungsten metal in groove, whether therefore too little no matter actual bit line detects critical size, bit line all will can not produce the problem of collapse.Adopt " opposite-bit line " (Reverse-Bitline) method to make the back of developing detect critical size opposite with detection critical size after the development that the bit line method for making of prior art obtains.
Description of drawings
Figure 1A is the bit line method for making according to prior art, after the completion bit line photolithographic pattern development and etching before the vertical cross-section synoptic diagram.
Figure 1B is the bit line method for making according to prior art, the vertical cross-section synoptic diagram before the laggard interlayer in the ranks of bit line tungsten etching silicon nitride deposition.
Fig. 1 C is the bit line method for making according to prior art, the vertical cross-section synoptic diagram after finishing bit line making and deposit first and second oxide skin(coating)s.
Fig. 2 A is the bit line method for making according to prior art, after the bit line etching, photoresist is removed and wet-cleaned after, detect critical size after the etching of bit line and hour produce the scanning electron micrograph synoptic diagram of actual bit line collapse.
Fig. 3 A, 3B are the bit line method for makings according to prior art, in the removal photoresist and wet-cleaned process after the bit line etching, because of detecting the scanning electron micrograph synoptic diagram that critical size hour produces actual bit line collapse and pollutes other bit lines after the etching of bit line.
Fig. 4 A is according to bit line method for making of the present invention, after the completion bit line trenches photoresist pattern development and etching before the vertical cross-section synoptic diagram.
Fig. 4 B is according to bit line method for making of the present invention, the vertical cross-section synoptic diagram after line trenches etching on the throne and removal photoresist and the cleaning.
Fig. 4 C is according to bit line method for making of the present invention, in the line trenches on the throne deposit bit line spacer layer and eat-back (Etching Back) after, the vertical cross-section synoptic diagram that deposit titanium/titanium nitride and deposition tungsten are later.
Fig. 4 D is according to bit line method for making of the present invention, the tungsten planarization, eat-backs the vertical cross-section synoptic diagram that forms behind the bit line.
Fig. 4 E is according to bit line method for making of the present invention, deposit silicon nitride, eat-backs the vertical cross-section synoptic diagram behind the silicon nitride.
Fig. 4 F is according to bit line method for making of the present invention, the vertical cross-section synoptic diagram of deposit second oxide skin(coating).
Description of reference numerals
101 prefilter layers
102 are used to form the second polysilicon contact hole (Poly Two Contact, oxidation P2C)
Thing layer HDP
103 second polysilicon contact holes (that is, Poly Two Contact 1, P2C1 and Poly Two
Contact 2, and P2C2), and deposit barrier layer (Barrier) titanium/titanium nitride, metal have been inserted
The contacting metal tungsten of plug
The contacting metal of 104 bit line metals, metal plug and the barrier layer between the oxide skin(coating)
(Barrier) titanium/titanium nitride
The bit line tungsten of 105 deposits
1051 bit lines
106 hard mask layers
1061 hard masks
107 photoresist patterns
108 walls
109 first oxide skin(coating)s
110 second oxide skin(coating)s
401 prefilter layers
402 are used to form the second polysilicon contact hole (Poly Two Contact, oxidation P2C)
Thing layer HDP
Barrier layer between 403 contacting metals and the oxide skin(coating) (Barrier) titanium/titanium nitride
404 second polysilicon contact holes (that is, Poly Two Contact 1, P2C1 and Poly Two
Contact 2, P2C2), and deposit barrier layer (Barrier) titanium/titanium nitride, metal
The contacting metal tungsten of connector
405 first oxide skin(coating)s
4051 etchings form first oxide skin(coating) of bit line groove structure
4052 grooves
406 opposite bit line (Reverse-Bitline) photoresist patterns
407 walls
Barrier layer (Barrier) titanium/titanium nitride between 408 bit line metal levels and the oxide skin(coating)
4081 barrier layers (Barrier) titanium/titanium nitride
409 bit line tungsten illuviums
4091 bit line tungsten
410 hard masks
411 second oxide skin(coating)s
Embodiment
Describe the present invention in detail below in conjunction with the drawings and specific embodiments.
The bit line of the COB-DRAM that prevents bit line collapse of the present invention by the following stated " opposite-bit line) process makes.
An at first preferred silicon substrate forms polysilicon gate, forms source and drain areas and protective seam thereof, is called prefilter layer 401 here.Because the making step of prefilter layer is known technology, be not described in detail at this.
On prefilter layer 401, carry out following steps successively:
A) with routine techniques, as chemical gas-phase deposition method deposit high-density plasma (HighDensity Plasma, HDP) silicon oxide layer 402, be used to form the second polysilicon contact hole (Poly TwoContact, P2C), shown in Fig. 4 A;
B) with routine techniques, as reactive ion etching (Reactive Ion Etch, RIE) this high-density plasma of etching (High Density Plasma, HDP) silicon oxide layer 402, form the second polysilicon contact hole (that is, Poly Two Contact 1, P2C1 and Poly Two Contact 2, P2C2), shown in Fig. 4 A;
C) in the above-mentioned second polysilicon contact hole, adopt routine techniques, carry out the deposit of the contacting metal and the barrier layer between the oxide skin(coating) (Barrier) titanium/titanium nitride 403 of tungsten plug as low-pressure chemical vapor phase deposition method (LPCVD), shown in Fig. 4 A;
D) with routine techniques, carry out the deposit of the contacting metal 404 of tungsten plug as low-pressure chemical vapor phase deposition method (LPCVD), and cmp carries out planarization, and ends at high-density plasma (HDP) silicon oxide layer 402 that forms the second polysilicon contact hole, shown in Fig. 4 A;
E),, and form bit line trench lithography glue pattern 406 as plasma-reinforced chemical vapor deposition method deposit one first silicon oxide layer (PEOX) 405 with routine techniques; What form in this is not bit line photoresist pattern in step, but the bit line groove is a bit line photoresist pattern at interval, shown in Fig. 4 A.
F) carry out the bit line etching groove with routine techniques, the plasma that forms the bit line groove structure strengthens monox 4051 and groove 4052, shown in Fig. 4 B.
G), carry out the deposit of bit line spacer layer silicon nitride as chemical gas-phase deposition method, and eat-back formation wall 407, shown in Fig. 4 C with routine techniques;
H), carry out the deposit of barrier layer (Barrier) titanium/titanium nitride layer 408 between bit line metal and the oxide skin(coating) as low-pressure chemical vapor phase deposition method (LPCVD), shown in Fig. 4 C with routine techniques;
I) with routine techniques, carry out 409 deposits of bit line tungsten metal, shown in Fig. 4 C, and carry out the cmp planarization, stop at first oxide skin(coating) that forms the bit line groove;
J) with routine techniques, as reactive ion etching (Reactive Ion Etch, RIE) carry out eat-backing of bit line tungsten illuvium 409 and barrier layer (Barrier) titanium/titanium nitride layer 408, form titanium/titanium nitride barrier layer (Barrier) 4081 and tungsten metal bit line 4091, shown in Fig. 4 D;
Owing to is to be filled in the groove by above process bit line metal, therefore no matter after its etching critical size whether too little, can not produce bit line metal collapse phenomenon.
K) with routine techniques, (LPCVD) carries out the deposit of bit line hard mask layer 410 as the low-pressure chemical vapor phase deposition method, eat-backs then, and stops at first silicon oxide layer 405, shown in Fig. 4 E;
L) with routine techniques, deposit forms second silicon oxide layer 411 as the plasma-reinforced chemical vapor deposition method, shown in Fig. 4 F.
In sum, " opposite-bit line " of the present invention be the bit line method for making comparison of method and prior art (Reverse-Bitline), can avoid occurring the problem that bit line collapses after the bit line etching and after removing photoresist and wet-cleaned easily in the art methods, thereby improve the permission of bit line processing procedure and the qualification rate of COB-DRAM.
More than be to be elaborated, but other and further embodiment of the present invention can design not deviating under the basic design scope of the present invention, so protection scope of the present invention is by the scope decision of claims at one embodiment of the invention.
Claims (10)
1. prevent the bit line method for making of the COB-DRAM of bit line collapse, comprise the steps:
A) deposit is used to form the oxide skin(coating) of the second polysilicon contact hole;
B) etching forms the second polysilicon contact hole;
C) carry out the contacting metal deposit of the contacting metal of metal plug and barrier layer metal deposit between the oxide skin(coating) and metal plug;
D) carry out the planarization of the contacting metal of its barrier layer and metal plug, end at the oxide skin(coating) that forms the second polysilicon contact hole;
E) deposit one first oxide skin(coating), and form bit line trench lithography glue pattern;
F) bit line etching groove;
G) bit line spacer layer deposit, and eat-back;
H) the barrier layer metal deposit between bit line metal and the oxide skin(coating);
I) bit line metal deposit, and planarization ends at first oxide skin(coating) that forms the bit line groove;
J) the bit line metal eat-backs;
K) bit line hard mask material deposit, and eat-back, stop at first oxide skin(coating) that forms the bit line groove;
L) deposit second oxide skin(coating).
2. method according to claim 1 is characterized in that, described contacting metal is a tungsten, and the barrier layer between contacting metal and the oxide skin(coating) is titanium/titanium nitride.
3. method according to claim 1 is characterized in that, described bit line metal is a tungsten, and the barrier layer between bit line metal and the oxide skin(coating) is titanium/titanium nitride.
4. according to claim 1 or 3 described methods, it is characterized in that described bit line metal illuvium adopts cmp to carry out planarization.
5. method according to claim 1 is characterized in that, the used oxide of described a) step is the high-density plasma oxide.
6. method according to claim 1 is characterized in that, described material spacer layer is a silicon nitride.
7. method according to claim 1 is characterized in that, described hard mask is a silicon nitride.
8. method according to claim 1 is characterized in that, described first oxide skin(coating) is that plasma strengthens oxide.
9. method according to claim 1 is characterized in that, described second oxide skin(coating) is that plasma strengthens oxide.
10. method according to claim 1 is characterized in that, described etching groove adopts reactive ion etching.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100265883A CN100561349C (en) | 2006-05-16 | 2006-05-16 | Prevent the bit line method for making of the COB-DRAM of bit line collapse |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100265883A CN100561349C (en) | 2006-05-16 | 2006-05-16 | Prevent the bit line method for making of the COB-DRAM of bit line collapse |
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| CN101075093A CN101075093A (en) | 2007-11-21 |
| CN100561349C true CN100561349C (en) | 2009-11-18 |
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| CN114121812A (en) * | 2020-08-28 | 2022-03-01 | 长鑫存储技术有限公司 | Memory manufacturing method and memory |
| US11856758B2 (en) | 2020-09-24 | 2023-12-26 | Changxin Memory Technologies, Inc. | Method for manufacturing memory and same |
| CN115116962A (en) * | 2021-03-22 | 2022-09-27 | 长鑫存储技术有限公司 | Preparation method of semiconductor structure and semiconductor structure |
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Effective date of registration: 20111201 Address after: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Co-patentee after: Semiconductor Manufacturing International (Beijing) Corporation Patentee after: Semiconductor Manufacturing International (Shanghai) Corporation Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Patentee before: Semiconductor Manufacturing International (Shanghai) Corporation |
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