JP2010080625A - Method of forming mask pattern, and method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of forming a mask pattern that discriminates the formation history of patterns of workpiece materials formed, and to provide a method of manufacturing a semiconductor device. <P>SOLUTION: A sidewall pattern is formed on a long sidewall of a line part of a first line-and-space pattern on a foundation region; a protective pattern that covers and protects part of the line part of the first line-and-space pattern is formed on the first line-and-space pattern; and the protective pattern is used as a mask to wet-etch the line part of the first line-and-space pattern and remove it, thus forming a second line-and-space pattern constructed by a residual pattern portion that leaves behind the line part of the first line-and-space pattern, a first space that is a region from which the line part of the first line-and-space pattern is removed, and a second space that is a region between sidewall patterns adjoining via the space of the first line-and-space pattern. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a mask pattern forming method and a semiconductor device manufacturing method.

  The miniaturization of a semiconductor device greatly depends on lithography technology. For this reason, it is generally difficult to form a device pattern having a width less than the resolution limit of lithography. To solve this problem, there is a double patterning technique as a method for forming a dense device pattern that exceeds the resolution of lithography. For example, a sidewall pattern is formed on the sidewall of a dummy pattern, and etching is performed using this sidewall pattern as a mask. A method of performing this has been proposed (see, for example, Patent Document 1). According to this method, it is possible to form a line and space pattern with a half pitch of the dummy pattern.

  Hereinafter, a double patterning method using sidewall processing as a typical double patterning technique will be described. In the double patterning method, a line-and-space resist pattern having a desired double pitch is first formed in lithography. Then, using the resist pattern as a mask, the lower side wall core material film is etched, and the resist pattern is transferred to the side wall core material film to form a core material pattern.

  Next, the core material pattern is thinned to a desired dimension by performing a slimming process on the core material pattern. Next, a deposited film having a desired thickness is deposited on the side wall portion of the core material pattern, and the core material is removed, thereby forming a line-and-space side wall deposited film pattern having a half pitch of the resolution pattern of lithography. Finally, a desired film pattern to be processed can be formed by etching the film to be processed under the side wall deposited film pattern as a mask.

  The film pattern thus formed has a space formed by removing the core material pattern (hereinafter referred to as “Pair portion”) and a space when the original resist pattern is formed (hereinafter referred to as “Adjacent portion”). ) And two types of space portions having different histories exist alternately.

  In the semiconductor manufacturing process, dimensional management and feedback to each process are required to improve yield and quality. In a process in which a pattern exposed by conventional lithography is transferred as it is to a dry etching base, feedback can be applied to the control from the dimension after lithography with respect to the exposure amount.

  However, in the pattern formed by the double patterning method (side wall process) by the side wall processing as described above, there are two types of space portions having different histories, a Pair portion and an Adjacent portion, and the discrimination between them is as follows. It was difficult. For this reason, in the pattern formed by the double patterning method, when a defect occurs, it is difficult to determine whether the defect has occurred in the Pair portion or the Adjacent portion. And there was a problem that countermeasures were difficult.

  In addition, since the process that should be fed back to the control is different between the Pair part and the Adjacent part, it is necessary to manage the dimensions separately. For this reason, for the construction of a mass production system using a side wall process, it is indispensable to distinguish between a pair part and an adjacent part. However, only by looking at the formed pattern, there is a problem that it is difficult to discriminate between the pair part and the adjacent part, and it is difficult to control by feedback.

JP 2006-303022 A

  The present invention has been made in view of the above, and an object of the present invention is to provide a mask pattern forming method and a semiconductor device manufacturing method capable of determining the pattern formation history of the formed workpiece. And

  According to one aspect of the present invention, a step of forming a first line and space pattern on a base region, a step of forming a side wall pattern on a long side wall of a line portion of the first line and space pattern, Forming a protective pattern on the first line and space pattern to cover and protect a part of the line portion of the first line and space pattern; and using the protective pattern as a mask, the first line By removing the line portion of the and space pattern by wet etching, the remaining pattern portion in which the line portion of the first line and space pattern covered with the protective pattern remains, and the first line and space pattern A first space portion from which the line portion has been removed, and the first line and space. Forming a second line-and-space pattern composed of a second space portion that is a region between the side wall patterns adjacent to each other via a space portion of a pattern. A method of forming a pattern is provided.

  Moreover, according to one aspect of the present invention, the step of forming the first line and space pattern formed intermittently by having the plurality of cut portions in the longitudinal direction on the base region, Forming a side wall pattern on a long side wall of the line portion of one line and space pattern and the cut portion, and covering and protecting the line portion of the first line and space pattern whose outer peripheral portion is covered by the side wall pattern Forming a protective pattern on the first line and space pattern, and removing the line portion of the first line and space pattern by wet etching using the protective pattern as a mask. A remaining pattern in which the line portion of the first line and space pattern covered is left. Between the sidewall portion adjacent to the first space portion through the space portion of the first line and space pattern, and the first space portion that is the region from which the line portion of the first line and space pattern has been removed. And a step of forming a second line-and-space pattern constituted by a second space portion which is a region. A method for forming a mask pattern is provided.

  According to another aspect of the present invention, there is provided a semiconductor device manufacturing method for forming a line and space pattern as a monitor pattern for monitoring dimensions in a semiconductor device, wherein the first line and space pattern is formed on a base region. Forming a side wall pattern on the long side wall of the line portion of the first line and space pattern, and protecting to cover a part of the line portion of the first line and space pattern A step of forming a pattern on the first line and space pattern, and wet etching removal of the line portion of the first line and space pattern using the protective pattern as a mask, thereby covering the pattern with the protective pattern. In addition, the line portion of the first line and space pattern remains. The remaining pattern portion, the first space portion that is the region from which the line portion of the first line and space pattern is removed, and the sidewall pattern that is adjacent via the space portion of the first line and space pattern A step of forming a second line and space pattern constituted by a second space portion, which is a region between, and etching of the base region using the second line and space pattern as a mask Forming a third line and space pattern in which the second line and space pattern is transferred to the base region as the monitor pattern, thereby providing a method of manufacturing a semiconductor device The

  According to another aspect of the present invention, there is provided a semiconductor device manufacturing method for forming a line and space pattern as an actual device pattern in a semiconductor device, the step of forming a first line and space pattern on a base region; Forming a side wall pattern on the long side wall of the line portion of the first line and space pattern, and a protection pattern for covering and protecting a part of the line portion of the first line and space pattern. Forming on the line and space pattern, and removing the line portion of the first line and space pattern by wet etching using the protective pattern as a mask, thereby A remaining pattern portion that leaves the line portion of the line and space pattern; and A first space portion that is a region from which a line portion of the first line and space pattern is removed and a first space portion that is an area between the side wall patterns that are adjacent to each other through the space portion of the first line and space pattern. A step of forming a second line and space pattern composed of two space portions, and etching the underlying region using the second line and space pattern as a mask. And a step of forming a third line and space pattern in which the second line and space pattern is transferred to the base region.

  According to the present invention, there is an effect that it is possible to provide a mask pattern forming method capable of discriminating a pattern forming history of a formed workpiece.

  According to the present invention, there is an effect that it is possible to provide a method for manufacturing a semiconductor device capable of determining a pattern formation history of a formed workpiece.

  A mask pattern forming method and a semiconductor device manufacturing method according to the present invention will be described below with reference to the accompanying drawings. In addition, this invention is not limited to the following description, In the range which does not deviate from the summary of this invention, it can change suitably. In the drawings shown below, the scale of each member may be different from the actual scale for easy understanding. The same applies between the drawings.

(First embodiment)
In the first embodiment, a method for forming a mask pattern and a method for manufacturing a semiconductor device will be described with reference to FIGS. 1 to 7, taking as an example the formation of an element isolation region having an STI (Shallow Trench Isolation) structure in a semiconductor manufacturing process. To do. 1 to 4 are cross-sectional views for explaining a mask pattern forming method and a semiconductor device manufacturing method according to the present embodiment. 5 to 7 are plan views for explaining a mask pattern forming method and a semiconductor device manufacturing method according to the present embodiment.

  First, a semiconductor substrate (for example, a silicon substrate) 10 is prepared, and a sidewall core film 11 is deposited on one surface of the semiconductor substrate 10 as shown in FIG. 1A, and further on the sidewall core film 11. A photoresist film 12 is formed. Then, by using normal photolithography, a first photoresist pattern 12a having a desired double pitch line-and-space is formed on the sidewall core material film 11 as shown in FIGS. 1B and 5A. To do.

  Next, as shown in FIGS. 1C and 5B, using the first photoresist pattern 12a as a mask, the underlying sidewall core film 11 is etched by, for example, RIE (reactive ion etching). The first photoresist pattern 12a is transferred to the sidewall core material film 11 to form the sidewall core material pattern 11a. Further, the first photoresist pattern 12a is removed.

  Next, as shown in FIGS. 1D and 5C, the sidewall core pattern 11a is thinned to a desired dimension by performing a slimming process on the sidewall core pattern 11a. Next, as shown in FIGS. 2A and 6A, a sidewall pattern 13 is formed by depositing a SiN film having a desired thickness on the sidewall portion of the sidewall core material pattern 11a by, for example, CVD.

  Next, the process of removing the side wall core material pattern 11a is entered. In order to leave a part of the side wall core material pattern 11a, a protective pattern that covers and protects at least a part of the side wall core material pattern 11a as a protection region is lithography. Form with. That is, as shown in FIGS. 2B and 6B, the second photoresist pattern 14 is formed by lithography on a desired region where the sidewall core material pattern 11a is desired to remain. FIG. 2B is a cross-sectional view taken along line AA in FIG.

  Then, by removing the sidewall core material pattern 11a by wet etching in the state where the second photoresist pattern 14 is formed, as shown in FIGS. 2C, 2D, and 6C, A line-and-space side wall mask pattern 13a having a half pitch of the resolution pattern of the lithography is formed. FIG.2 (c) is sectional drawing in line segment AA of FIG.6 (c). FIG. 2D is a cross-sectional view taken along line BB in FIG.

  In the line and space of the sidewall mask pattern 13a, the space portion (Pair portion) 13SP of the sidewall mask pattern 13a, which is the region from which the sidewall core material pattern 11a has been removed, and the space portion from the formation of the first photoresist pattern. There are alternately two types of space portions having different formation histories from the space portion (Adjacent portion) 13SA of the space portion (Pair portion) 13SP, which is a region between adjacent sidewall mask patterns 13a.

  In the region where the second photoresist pattern 14 is not formed, the sidewall core material pattern 11a is removed as shown in FIGS. 2 (d) and 6 (c), and the Pair portion 13SP is formed. On the other hand, in the region where the second photoresist pattern 14 is formed, as shown in FIGS. 2C and 6C, the sidewall core material pattern 11a remains in a part of the line-and-space Pair 13SP. A discrimination pattern portion 11b which is a remaining pattern is formed.

  Thereby, in the space part of the line and space of the side wall core material pattern 11a, by confirming the presence or absence of the discrimination pattern part 11b in the space part, the space part is the Pair part 13SP or the Adjacent part 13SA. Can be easily determined. That is, in the line-and-space space portion of the sidewall mask pattern 13a, the space portion where the discrimination pattern portion 11b exists is the Pair portion 13SP, and the space portion where the discrimination pattern portion 11b does not exist is the Adjacent portion 13SA.

  Next, using the sidewall mask pattern 13a and the discrimination pattern portion 11b as a mask, the underlying semiconductor substrate 10 is etched by RIE, for example, as shown in FIGS. 3 (a) and 3 (b). A line-and-space workpiece pattern to which the mask pattern 13a and the pattern of the discrimination pattern portion 11b are transferred is formed. FIG. 3A is a cross-sectional view corresponding to the position of the line segment AA in FIG. FIG. 3B is a cross-sectional view corresponding to the position of the line segment BB in FIG.

  That is, a line portion 10 </ b> L is formed on the surface of the semiconductor substrate 10 as a line-and-space line portion of the workpiece pattern. Further, as the line and space portion of the workpiece pattern, the space portion 10SP corresponding to the line and space pair portion 13SP of the sidewall mask pattern 13a and the line and space adjustment portion 13SA of the sidewall mask pattern 13a are supported. The space portion 10SA is formed. The space portion 10SP and the space portion 10SA serve as an STI element isolation trench. In addition, a discrimination pattern portion 10C that connects adjacent line portions 10L is formed in a part of the space portion 10SP.

  Thereby, in the space part of the line and space formed in the semiconductor substrate 10, by confirming the presence or absence of the discrimination pattern part 10C in the space part, the space part is a space part formed by the Pair part 13SP. It is possible to easily determine whether the portion is the portion 10SP or the space portion 10SA that is the space portion formed by the Adjacent portion 13SA. That is, in the line-and-space space portion, the space portion where the discrimination pattern portion 10C exists is the space portion 10SP, and the space portion where the discrimination pattern portion 10C does not exist is the space portion 10SA.

  Thereafter, as shown in FIGS. 3C, 3D, and 7A, the sidewall mask pattern 13a and the discrimination pattern portion 11b are removed. FIG. 3C is a cross-sectional view corresponding to the position of the line segment AA in FIG. FIG. 3D is a cross-sectional view corresponding to the position of the line segment BB in FIG. Then, a silicon oxide film, for example, is formed as an insulator in the space portion 10SP and the space portion 10SA by a CVD (Chemical Vapor Deposition) method, so that FIG. 4 (a), FIG. As shown in FIG. 4, an element isolation region 15 is formed, and a region surrounded by the element isolation region 15 is an active area AA. FIG. 4A is a cross-sectional view taken along line AA in FIG. FIG. 4B is a cross-sectional view taken along line BB in FIG.

  In the above description, the discrimination pattern portion 11b is left at a plurality of locations. However, since the Pair portion 13SP and the Adjacent portion 13SA exist alternately, if the discrimination pattern portion 11b can discriminate only at one location, other space portions are present. It is possible to determine whether it is the Pair unit 13SP or the Adjacent unit 13SA.

  In the above description, the formation of the element isolation region 15 on the substrate in the semiconductor manufacturing process has been described as an example. However, the present invention is not limited to this. For example, a device pattern such as a gate electrode or a dimension in a semiconductor device is monitored. Therefore, it can be widely applied to a monitor pattern (TEG: Test Element Group).

  As described above, according to the mask pattern forming method according to the embodiment, the discrimination pattern portion 11b for discriminating between the Pair portion 13SP and the Adjacent portion 13SP is one of the line-and-space Pair portions 13SP in the mask pattern. A mask pattern formed on the part is formed.

  Then, by etching the semiconductor substrate 10 using this mask pattern, the discrimination pattern portion 10C is formed in the space portion 10SP formed by the pair portion 13SP among the processed patterns formed on the semiconductor substrate 10. . As a result, when a defect occurs in the pattern formed on the semiconductor substrate 10, it is possible to easily determine whether the defect generation region is the pair portion 13SP or the adjustment portion 13SP, and a pattern defect has occurred. It becomes possible to easily know the formation history of the region. Therefore, according to the mask pattern forming method according to the embodiment, it is possible to form a pattern capable of easily discriminating the pattern defect generation process.

  In addition, according to the method for manufacturing a semiconductor device according to the embodiment, the semiconductor substrate 10 is formed on the semiconductor substrate 10 by etching using the mask pattern manufactured by using the mask pattern forming method described above. Among the processed patterns, the discrimination pattern portion 10C is formed in the space portion 10SP formed by the pair portion 13SP. As a result, when a defect occurs in the pattern formed on the semiconductor substrate 10, it is possible to easily determine whether the defect generation region is the pair portion 13SP or the adjustment portion 13SP, and a pattern defect has occurred. It becomes possible to easily know the formation history of the region. Therefore, according to the method of manufacturing a semiconductor device according to the embodiment, it is possible to easily determine the pattern defect generation process, and to investigate the cause of the defect and take a countermeasure smoothly. A pattern that can be easily improved can be formed.

  Furthermore, in the work pattern formed as described above, it can be determined whether the formation history corresponds to the pair part 13SP or the adjacent part 13SP, so that the space part 10SP and the space part 10SA of the work material pattern Depending on the dimensions, the process to be fed back can be individually controlled by the space part 10SP and the space part 10SA, and dimensional management can be realized for yield and quality improvement.

(Second Embodiment)
In the first embodiment, in the step of removing the sidewall core material pattern 11a by wet etching (FIG. 2 (c), FIG. 2 (d), FIG. 6 (c)), the etching chemical is a space portion (Pair portion). By entering 13SP, as shown in FIG. 8, the side wall core material pattern 11a may recede from the region where the second photoresist pattern 14 is formed, and the discrimination pattern portion 11b may be formed smaller than the desired size. There is. In FIG. 8, when the etching chemical enters the space portion (pair portion) 13SP, the side wall core material pattern 11a covered with the second photoresist pattern 14 recedes by the receding region 11c, and the discrimination pattern portion. 11b is formed. FIG. 8 is a cross-sectional view showing a state in which the side wall core material pattern 11a is retracted from the region where the second photoresist pattern 14 is formed.

  Therefore, in the second embodiment, a mask pattern forming method and a semiconductor device manufacturing method for preventing the sidewall core material pattern 11a from retreating will be described with reference to FIGS. 9 to 11 are plan views for explaining a mask pattern forming method and a semiconductor device manufacturing method according to the present embodiment. The second embodiment is different from the first embodiment in that a plurality of cuts (cut portions) are formed in the first photoresist pattern 12a in the longitudinal direction. That is, the first photoresist pattern 12a is intermittently formed in the longitudinal direction.

  In the mask pattern forming method according to the second embodiment, first, a semiconductor substrate (for example, a silicon substrate) 10 is prepared as in the first embodiment, and a sidewall core is formed on one surface of the semiconductor substrate 10. A material film 11 is deposited, and a photoresist film 12 is formed on the sidewall core material film 11 (see FIG. 1A).

  Then, as shown in FIG. 9A, first photoresist patterns 12b and 12c having a desired double pitch line-and-space are formed on the sidewall core material film 11 using ordinary photolithography. Here, like the first photoresist pattern 12a of the first embodiment, the first photoresist pattern 12b is a continuous pattern that is continuous in the longitudinal direction. The first photoresist pattern 12c is an intermittently formed pattern having a cut in the longitudinal direction.

  Next, as shown in FIG. 9B, using the first photoresist patterns 12b and 12c as a mask, the lower sidewall core material film 11 is etched by, for example, RIE (reactive ion etching). One photoresist pattern 12b, 12c is transferred to the sidewall core material film 11 to form sidewall core material patterns 11d, 11e. Here, the side wall core material pattern 11d is a continuous pattern without a break in the longitudinal direction, similarly to the side wall core material pattern 11a of the first embodiment. The side wall core material pattern 11e is an intermittently formed pattern having cuts (cut portions) in the longitudinal direction. Further, the first photoresist patterns 12b and 12c are removed.

  Next, as shown in FIG. 9C, the side wall core material patterns 11d and 11e are thinned to a desired dimension by performing a slimming process on the side wall core material patterns 11d and 11e. Next, as shown in FIG. 10A, a sidewall pattern 13 is formed by depositing a SiN film having a desired thickness on the sidewall portions and cuts (cut portions) of the sidewall core material patterns 11d and 11e by, for example, CVD. To do. Here, since the side wall core material pattern 11e is an intermittently formed pattern having a cut in the longitudinal direction, the side wall pattern 13 is also formed in the cut portion of the side wall core material pattern 11e. That is, the sidewall pattern 13 is also formed in the region to be the Pair portion 13SP, and the sidewall core material pattern 11e is entirely covered with the sidewall pattern 13 in the in-plane direction of the semiconductor substrate 10.

  Next, the process of removing the side wall core material patterns 11d and 11e is started. In order to leave a part of the side wall core material pattern 11e, a removal cover region that covers and protects the side wall core material patterns 11d and 11e is obtained by lithography. Form. That is, as shown in FIG. 10B, the second photoresist pattern 14 is formed by lithography on a desired region where the side wall core material pattern 11e is left.

  Then, by removing the sidewall core material patterns 11d and 11e by wet etching in the state where the second photoresist pattern 14 is formed, as shown in FIG. 10C, the pitch of the half of the resolution pattern of the lithography is obtained. A line and space sidewall mask pattern 13a is formed. Here, since the side wall core material pattern 11e is entirely covered with the side wall pattern 13 in the in-plane direction of the semiconductor substrate 10, the side wall core material pattern 11e is entirely covered with the second photoresist pattern 14. Is a remnant pattern in which the side wall core material pattern 11e remains in the same size, preventing retreat due to the etching chemical solution entering from the region (space portion (pair portion) 13SP) from which the side wall core material pattern 11e has been removed. A certain discrimination pattern portion 11b is used.

  In the line and space of the sidewall mask pattern 13a, a space portion (Pair portion) 13SP formed by removing the sidewall core material patterns 11d and 11e and a space portion that has been a space portion since the first photoresist pattern was formed. Two types of space portions having different formation histories are alternately present with the portion (Adjacent portion) 13SA.

  In the region where the second photoresist pattern 14 is not formed, the sidewall core material patterns 11d and 11e are removed as shown in FIG. 10C, and the Pair portion 13SP is formed. On the other hand, in the region where the second photoresist pattern 14 is formed, as shown in FIG. 10C, the sidewall core material pattern 11e remains in a part of the line-and-space Pair 13SP, and the discrimination pattern portion 11b It is formed.

  Thereby, in the space part of the line and space of the side wall mask pattern 13a, whether the space part is the Pair part 13SP or the Adjacent part 13SA is confirmed by checking the presence or absence of the discrimination pattern part 11b in the space part. Can be easily discriminated. That is, in the line-and-space space portion of the sidewall mask pattern 13a, the space portion where the discrimination pattern portion 11b exists is the Pair portion 13SP, and the space portion where the discrimination pattern portion 11b does not exist is the Adjacent portion 13SA.

  Next, using the sidewall mask pattern 13a and the discrimination pattern portion 11b as a mask, the semiconductor substrate 10 in the lower layer is etched by, for example, RIE, and the sidewall mask pattern 13a and the discrimination pattern portion 11b are removed. As a result, as shown in FIG. 11A, a line-and-space work material pattern to which the patterns of the sidewall mask pattern 13a and the discrimination pattern portion 11b are transferred is formed.

  On the surface of the semiconductor substrate 10, a line portion 10L is formed as a line-and-space line portion. Further, as the space portion of the line and space, a space portion 10SP corresponding to the line portion and space pair portion 13SP of the sidewall mask pattern 13a, and a space portion 10SA corresponding to the line and space adjustment portion 13SA of the sidewall mask pattern 13a, and Is formed. The space portion 10SP and the space portion 10SA serve as an STI element isolation trench. In addition, a discrimination pattern portion 10C that connects adjacent line portions 10L is formed in a part of the space portion 10SP.

  Thereby, in the space part of the line and space formed in the semiconductor substrate 10, by confirming the presence or absence of the discrimination pattern part 10C in the space part, the space part is a space part formed by the Pair part 13SP. It is possible to easily determine whether the portion is the portion 10SP or the space portion 10SA that is the space portion formed by the Adjacent portion 13SA. That is, in the line-and-space space portion, the space portion where the discrimination pattern portion 10C exists is the space portion 10SP, and the space portion where the discrimination pattern portion 10C does not exist is the space portion 10SA.

  Then, by forming, for example, a silicon oxide film as an insulator in the space portion 10SP and the space portion 10SA by a CVD (Chemical Vapor Deposition) method, an element isolation region 15 is formed as shown in FIG. A region surrounded by the element isolation region 15 is defined as an active area AA.

  As described above, according to the mask pattern forming method according to the embodiment, the discrimination pattern portion 11b for discriminating between the Pair portion 13SP and the Adjacent portion 13SP is one of the line-and-space Pair portions 13SP in the mask pattern. A mask pattern formed on the part is formed.

  In addition, according to the mask pattern forming method according to this embodiment, the sidewall core material pattern 11e is formed as an intermittently formed pattern having a cut in the longitudinal direction. Then, the side wall core material pattern 11e is covered with the side wall pattern 13 and the second photoresist pattern 14 is formed on the outer periphery of the semiconductor substrate 10 in the in-plane direction, and the side wall core material patterns 11d and 11e are formed. Is removed by wet etching. Thereby, when the side wall core material patterns 11d and 11e are removed, the side wall core material pattern 11e to be left is etched back by the etching chemical solution, that is, the discrimination pattern portion 11b is formed smaller than a desired size. This can be prevented, and the desired discrimination pattern portion 11b can be formed more reliably.

  Then, by etching the semiconductor substrate 10 using this mask pattern, the discrimination pattern portion 10C is formed in the space portion 10SP formed by the pair portion 13SP among the processed patterns formed on the semiconductor substrate 10. . As a result, when a defect occurs in the pattern formed on the semiconductor substrate 10, it is possible to easily determine whether the defect generation region is the pair portion 13SP or the adjustment portion 13SP, and a pattern defect has occurred. It becomes possible to easily know the formation history of the region. Therefore, according to the mask pattern forming method according to the embodiment, it is possible to form a pattern capable of easily discriminating the pattern defect generation process.

  Furthermore, in the pattern to be processed formed as described above, it can be determined whether the formation history corresponds to the pair part 13SP or the adjacent part 13SP, and therefore the dimensions of the space part 10SP and the space part 10SA of the pattern to be processed. Accordingly, the process to be fed back can be individually controlled by the space part 10SP and the space part 10SA, and dimensional management can be realized for yield and quality improvement.

(Third embodiment)
In the third embodiment, the pattern dimension determining step is performed according to the dimensions of the space portion 10SP and the space portion 10SA of the pattern to be processed produced by the method described in the first embodiment and the second embodiment. The feedback method is explained. FIG. 12 is a flowchart for explaining a dimension data feedback method to main processes for determining a pattern dimension during pattern formation.

  A first photoresist pattern 12a is formed by lithography (step S100), and the dimensions of the first photoresist pattern 12a are measured (step S110). The dimension of the first photoresist pattern 12a is fed back to the exposure amount as needed (step S180).

  Next, the side wall core material pattern 11a is formed (step S120), and a slimming process is performed on the side wall core material pattern 11a (step S130). Next, a sidewall deposition film is formed on the sidewall of the sidewall core material pattern 11a (step S140), the sidewall core material pattern 11a is removed, and the sidewall mask pattern 13a and the discrimination pattern portion 11b are formed (step S150).

  Next, using the sidewall mask pattern 13a and the discrimination pattern portion 11b as a mask, the underlying semiconductor substrate 10 is etched by, for example, RIE to form a line-and-space workpiece pattern (step S160). Are measured (step S170). That is, it is determined whether each space portion of the workpiece pattern is a space portion 10SP that is a space portion formed by the Pair portion 13SP or a space portion 10SA that is a space portion formed by the Adjacent portion 13SA. In addition, the dimensions are measured, and the dimension of the line portion 10L is measured.

  And each dimension of the measured workpiece pattern is fed back to the corresponding process. That is, the dimension of the space portion 10SP is fed back to the slimming dimension at any time (step S190). The dimension of the line portion 10L is fed back to the film thickness dimension of the sidewall deposition film as needed (step S200). The dimension of the space portion 10SA is fed back to the RIE condition as needed (step S210).

As described above, in the method described in the first embodiment and the second embodiment,
By applying feedback using each dimension of the measured workpiece pattern, detailed dimension management for quality improvement is possible, and high yield can be realized.

It is sectional drawing for demonstrating the formation method of the mask pattern according to one Embodiment of this invention, and the manufacturing method of a semiconductor device. It is sectional drawing for demonstrating the formation method of the mask pattern according to one Embodiment of this invention, and the manufacturing method of a semiconductor device. It is sectional drawing for demonstrating the formation method of the mask pattern according to one Embodiment of this invention, and the manufacturing method of a semiconductor device. It is sectional drawing for demonstrating the formation method of the mask pattern according to one Embodiment of this invention, and the manufacturing method of a semiconductor device. It is a top view for demonstrating the formation method of the mask pattern according to one Embodiment of this invention, and the manufacturing method of a semiconductor device. It is a top view for demonstrating the formation method of the mask pattern according to one Embodiment of this invention, and the manufacturing method of a semiconductor device. It is a top view for demonstrating the formation method of the mask pattern according to one Embodiment of this invention, and the manufacturing method of a semiconductor device. In the mask pattern formation method and semiconductor device manufacturing method according to one embodiment of the present invention, it is a cross-sectional view showing a state in which the sidewall core material pattern recedes from the region where the second photoresist pattern is formed. It is a top view for demonstrating the formation method of the mask pattern according to one Embodiment of this invention, and the manufacturing method of a semiconductor device. It is a top view for demonstrating the formation method of the mask pattern according to one Embodiment of this invention, and the manufacturing method of a semiconductor device. It is a top view for demonstrating the formation method of the mask pattern according to one Embodiment of this invention, and the manufacturing method of a semiconductor device. It is a flowchart for demonstrating the feedback method of the dimension data to the main process which determines the dimension of a pattern at the time of the pattern formation by the formation method of the mask pattern according to one Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Semiconductor substrate, 10C Discriminating pattern part, 10L line part, 10SA Space part of workpiece pattern, 10SP Space part of workpiece pattern, 11 Side wall core material film,
11a Side wall core material pattern, 11b Discrimination pattern portion, 11c Retraction region, 12 Photoresist film, 12a First photoresist pattern, 12b First photoresist pattern, 12c First photoresist pattern, 13 Sidewall pattern, 13a Sidewall Mask pattern, 13SP Side wall mask pattern space part (Pair part), 13SA Side wall mask pattern space part (Adjacent part), 14 Second photoresist pattern, 15 Element isolation region.

Claims (5)

Forming a first line and space pattern on the underlying region;
Forming a side wall pattern on the long side wall of the line portion of the first line and space pattern;
Forming a protective pattern on the first line and space pattern to cover and protect a part of the line portion of the first line and space pattern;
The residual line portion of the first line and space pattern covered with the protective pattern is left by wet etching and removing the line portion of the first line and space pattern using the protective pattern as a mask. Between the pattern part, the first space part which is the region from which the line part of the first line and space pattern is removed, and the side wall pattern adjacent to each other through the space part of the first line and space pattern Forming a second line and space pattern constituted by a second space portion that is a region; and
A method of forming a mask pattern, comprising: Forming a first line and space pattern formed intermittently by having a plurality of cut portions in the longitudinal direction on the underlying region;
Forming a side wall pattern on a long side wall of the line portion of the first line and space pattern and the cut portion; and
Forming a protective pattern on the first line and space pattern to cover and protect the line portion of the first line and space pattern whose outer peripheral portion is covered with the sidewall pattern;
The residual line portion of the first line and space pattern covered with the protective pattern is left by wet etching and removing the line portion of the first line and space pattern using the protective pattern as a mask. Between the pattern part, the first space part which is the region from which the line part of the first line and space pattern is removed, and the side wall pattern adjacent to each other through the space part of the first line and space pattern Forming a second line and space pattern constituted by a second space portion that is a region; and
A method of forming a mask pattern, comprising: A manufacturing method of a semiconductor device for forming a line and space pattern as a monitor pattern for monitoring dimensions in a semiconductor device,
Forming a first line and space pattern on the underlying region;
Forming a side wall pattern on the long side wall of the line portion of the first line and space pattern;
Forming a protective pattern on the first line and space pattern to cover and protect a part of the line portion of the first line and space pattern;
The residual line portion of the first line and space pattern covered with the protective pattern is left by wet etching and removing the line portion of the first line and space pattern using the protective pattern as a mask. Between the pattern part, the first space part which is the region from which the line part of the first line and space pattern is removed, and the side wall pattern adjacent to each other through the space part of the first line and space pattern Forming a second line and space pattern constituted by a second space portion that is a region; and
A third line and space pattern in which the second line and space pattern is transferred to the base region as the monitor pattern by etching the base region using the second line and space pattern as a mask. Forming a step;
A method for manufacturing a semiconductor device, comprising: A method of manufacturing a semiconductor device for forming a line and space pattern as an actual device pattern in a semiconductor device,
Forming a first line and space pattern on the underlying region;
Forming a side wall pattern on the long side wall of the line portion of the first line and space pattern;
Forming a protective pattern on the first line and space pattern to cover and protect a part of the line portion of the first line and space pattern;
The residual line portion of the first line and space pattern covered with the protective pattern is left by wet etching and removing the line portion of the first line and space pattern using the protective pattern as a mask. Between the pattern part, the first space part which is the region from which the line part of the first line and space pattern is removed, and the side wall pattern adjacent to each other through the space part of the first line and space pattern Forming a second line and space pattern constituted by a second space portion that is a region; and
A third line and space in which the second line and space pattern is transferred to the underlying region as the actual device pattern by etching the underlying region using the second line and space pattern as a mask. Forming a pattern;
A method for manufacturing a semiconductor device, comprising: Measuring the dimension of the space portion of the third line and space pattern to obtain dimension data;
Depending on the presence or absence of a pattern corresponding to the remaining pattern portion, each of the space portions in the third line and space pattern is either a space portion corresponding to the first space portion or a space portion corresponding to the second space portion. A step of determining whether or not
When the space portion in the third line and space pattern is a space portion corresponding to the first space portion, the dimension data of the space portion is fed back to the step of forming the first line and space pattern. And a process of
When the space portion in the third line and space pattern is a space portion corresponding to the second space portion, the dimension data of the space portion is fed back to the step of forming the third line and space pattern. And a process of
The method for manufacturing a semiconductor device according to claim 3, wherein:

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