CN100552752C

CN100552752C - Display device and driving method thereof

Info

Publication number: CN100552752C
Application number: CN 200480019500
Authority: CN
Inventors: 庄司秀彦; 大平一雄; 谷口启成
Original assignee: Matsushita Electric Industrial Co Ltd
Current assignee: Panasonic Holdings Corp
Priority date: 2003-07-11
Filing date: 2004-06-23
Publication date: 2009-10-21
Anticipated expiration: 2024-06-23
Also published as: CN1820292A

Abstract

The 1st data driver group is connected to sub-field processor, the 1st Power Recovery circuit and PDP.The 2nd data driver group is connected to sub-field processor, the 2nd Power Recovery circuit and PDP.The 1st applies mutually different data pulse of phase place with the 2nd data driver group to PDP.The the 1st and the 2nd Power Recovery circuit utilizes LC resonance to produce the voltage that is used for producing in the 1st and the 2nd data driver group data pulse, carries out PDP is discharged electric charge and reclaims electric charge from PDP.The recovery current potential of the recovery capacitor of the 1st and the 2nd Power Recovery circuit changes with the discharge and the absence of discharge switching times of PDP discharge cell.

Description

Display device and driving method thereof

Technical field

The present invention relates to make selectively the display device and the driving method thereof of a plurality of discharge cell discharges and display image.

Background technology

In the field of the display device of display image, use plasma display panel (hereinafter referred is PDP) but plasma display system have the advantage of slimming and giant-screenization.Luminous when utilize constituting the discharge cell discharge of pixel of this plasma display system shows image.

Plasma display system is divided into AC type and DC type substantially according to drive form.

Figure 29 is the block diagram that the basic composition of existing AC type plasma display system is shown.

The plasma display system 900 of Figure 29 has analog-to-digital converter (analogue-digital converter hereinafter referred to as) 910, vision signal-son corresponder 920, sub-field processor 930, data driver 940, scanner driver 950, keeps driver 960 and PDP970.

Analogue-digital converter 910 is supplied with analog video signal VD.After analogue-digital converter 910 is transformed into Digital Image Data with vision signal VD, supplying video signal-son corresponder 920.A vision signal-son corresponder 920 is from 1 view data, produces view data SP of each son and supplies with sub-field processor 930, shows so that be divided into a plurality of sons with 1.

Sub-field processor 930 is from the view data SP of each son field, produce data driver drive control signal DS, scanner driver drive control signal CS and keep driver drives control signal US, and supply with data driver 940, scanner driver 950 respectively and keep driver 960.

PDP970 comprises a plurality of address electrodes (data electrode) 911, a plurality of scan electrode 912 and a plurality of maintenance electrode 913.A plurality of address electrodes 911 are arranged in the vertical direction of screen, and a plurality of scan electrodes 912 and a plurality of maintenance electrode 913 are arranged in the horizontal direction of screen.And, a plurality of maintenance electrodes 913 are linked together jointly.

Each intersection point at address electrode 911, scan electrode 912 and maintenance electrode 913 forms generator unit 914, the pixel that each generator unit 914 constitutes on screens.

Data driver 940 connects a plurality of address electrodes 911 of PDP970.The inside of scanner driver 950 has the driving circuit that is arranged on each scan electrode 912, and each driving circuit connects the respective scan electrode 912 of PDP970.Keep driver 960 to connect a plurality of maintenance electrodes 913 of PDP970.

Data driver 940 is applied to data pulse according to view data SP the suitable address electrode 911 of PDP970 according to data driver control signal DS during writing.Scanner driver 950 is according to scanner driver control signal CS, and one side makes shift pulse toward the vertical scanning direction displacement during writing, and one side will write a plurality of scan electrodes 912 that pulse is applied to PDP70 successively.Thus, in suitable discharge cell 914, carry out the address discharge.

Scanner driver 950 will periodically keep pulse to be applied to a plurality of scan electrodes 912 of PDP970 during keeping according to scanner driver control signal CS.On the other hand, keep driver 960, during keeping, will be offset the maintenance pulse of 180 degree, be applied to a plurality of maintenance electrodes 913 of PDP70 simultaneously the maintenance pulse of scan electrode 912 according to keeping driver drives control signal US.Thus, in suitable discharge cell 914, keep discharge.

Figure 30 illustrates address electrode, scan electrode among the PDP7 of an illustration 29 and the sequential chart that keeps the driving voltage of electrode.

During initialization, simultaneously a plurality of scan electrodes 912 are applied initial setting pulse Pset.Then, during writing, each address electrode 911 is applied the data pulse Pda that carries out conducting or disconnection according to vision signal, and synchronously a plurality of scan electrodes 912 are applied with this data pulse Pda and to write pulse Pw.Thus, in the selected discharge cell 914 of PDP970, the address discharge takes place successively.

Then, during keeping, a plurality of scan electrodes 912 are periodically applied maintenance pulse Psc, a plurality of maintenance electrodes are periodically applied maintenance pulse Psu.Make the phase place that keeps pulse Psu to keeping pulse Psc skew 180 degree.Thus, follow-up in the address discharge, discharge takes place to keep.

In this plasma display system, the quantity of discharge cell 14 is along with giant-screenization and high-definition significantly increase (pixel increases) in recent years.Because the quantity of discharge cell 14 increases, the peak point current increase of the address discharge current of circulation on 1 scan electrode 912 when discharge in the address sometimes.The peak point current of address discharge current increases, and then makes the pulse Pw that writes that is added in scan electrode 912 produce big voltage drop.As a result, address discharge instability.Therefore, the voltage SH2 that writes pulse Pw that must should be added in scan electrode 912 sets highly, so that carry out stable address discharge.

Be directed to this,, propose the driving method for plasma display apparatus of Figure 29 as the method for the peak point current that reduces the address discharge current.That is, data driver 940 is divided into a plurality of, between a plurality of data drivers, provides phase differential (for example with reference to the flat 8-305319 communique of Japan's patent disclosure) the data pulse Pda that is added in address electrode.

This driving method for plasma display apparatus is described.

Figure 31 illustrates the mode chart of an example by the PDP970 show state that is divided into the plasma display system that a plurality of data drivers constitutes.Figure 32 is the figure that explanation address discharge current is used the dependence of data pulse phase difference.Set forth the data pulse phase differential below.

Among Figure 31, the 1st and the

2nd data driver

940a, 940b are connected to the sub-field processor 930 of Figure 29.PDP970 has the composition identical with the PDP970 of Figure 29 except that comprising a plurality of

address electrode

911a, 911b.

With reference to Figure 32, illustrate that the 1st data driver 940a applies the skew TR between the timing of the timing of data pulse Pda of Figure 30 and the 2nd data driver 940b applies Figure 30 to address electrode 911b data pulse Pda to address electrode 911a.

Below explanation in, the timing with the 1st and the

2nd data driver

940a and 940b apply data pulse Pda separately to address

electrode

911a, 911b is called data pulse and applies regularly.To apply the skew TR that regularly applies timing to the data pulse of address electrode 911a, be called data pulse phase differential TR with data pulse to address electrode 911b.

Among Figure 31, the discharge cell 914 that begins on the 1st scan electrode 912f that goes from the top in the discharge cell 914 on the PDP970 is all luminous.

Imagination makes the luminous situation of discharge cell 914 that begins from the top on the scan electrode 912f of the 1st row.Shown in Figure 32 (a), when not having data pulse phase differential TR, the discharge cell 914 on the discharge cell 914 on the address electrode 911a and the address electrode 911b produces the address discharge in identical timing t 1.Thus, scan electrode 912f produces the discharge current DA2 with 1 peak.

At this moment, the discharge cell 914 on the address electrode 911a that circulates simultaneously among the scan electrode 912f and the discharge current of the discharge cell 914 on the address electrode 911b, thereby the amplitude A M2 of discharge current DA2 becomes big.Thus, make the pulse Pw that writes that is added in scan electrode 912f produce big voltage drop E2.As a result, as mentioned above, the address discharge instability.

Otherwise shown in Figure 32 (b), when having the data pulse phase differential, the address discharge takes place in timing t 1 in the discharge cell 914 on the address electrode 911a, and the discharge cell 914 on the address electrode 911b in timing t 2 the address discharge takes place.Thus, scan electrode 912f produces the discharge current DA1 with 2 peaks.

At this moment, discharge current among the scan electrode 912f on different timing t 1, t2 circulation address electrode 911a and the discharge current on the address electrode 911b, thereby along with data pulse phase differential TR becomes big, the amplitude A M1 of discharge current DA1 diminishes.Thus, the voltage drop E1 that pulse Pw produces of writing that is added in scan electrode 912f also strengthens along with data pulse phase differential TR and diminishes.Therefore, even should be added in the voltage that writes pulse Pw of scan electrode 912f and set lowly the time, also can guarantee stable discharging.In other words,, discharge cell 914 stable dischargings can be guaranteed again, the voltage (driving voltage) of pulse Pw can be reduced to write again by setting data pulse phase differential TR greatly.

, in the plasma display system 900 of Figure 29, a plurality of discharge cells 914 of PDP970 have the function of capacitor.Hereinafter the electric capacity with a plurality of discharge cells 914 of PDP970 is called plate electric capacity.

During above-mentioned writing, the circuit loss (power attenuation) of the data driver 940 when each address electrode 911 is applied data pulse Pda is directly proportional with square the amassing of plate electric capacity and the driving voltage that is added in address electrode 911.It is as follows to be formulated this relation.

P?∝Cp×Vp ²……(1)

In the top formula (1), P is a circuit loss, and Cp is a plate electric capacity, and Vp is a driving voltage.At this moment, driving voltage Vp is the voltage of data pulse Pda.

Therefore, the overall power consumption of the plasma display system 900 in during writing is along with the maximization (increase of plate electric capacity) of PDP970 and driving voltage raise and increase.So,, developed the Power Recovery circuit for the power consumption (reducing circuit loss) that reduces plasma display system 900.

Figure 33 is the circuit diagram that a routine existing Power Recovery circuit is shown.Among Figure 33, in being connected to, Power Recovery circuit 980 is loaded on the data driver integrated circuit of the data driver 940 of Figure 29.The data driver integrated circuit is connected to a plurality of address electrodes 911 of PDP970 again.

Among Figure 33, the capacitance meter of a plurality of discharge cells 914 that will be formed by each address electrode 911 is shown address electrode capacitor C p1～Cpn, and the summation of these electric capacity is expressed as plate capacitor C p.

Power Recovery circuit 980 comprises recovery capacitor C1, reclaims inductance L, N slot field-effect transistor (hereinafter referred is a transistor) Q1～Q4 and diode D1, D2.

To reclaim capacitor C1 is connected between node N3 and the ground terminal.Transistor Q4 and diode D2 are connected between node N3 and the node N2, go back series diode D1 and transistor Q3 between node N2 and the node N3.

To reclaim inductance L is connected between node N2 and the node N1.Between node N1 and power supply terminal V1, be connected transistor Q1, between node N1 and ground terminal, be connected transistor Q2.

To power supply terminal V1 supply line voltage Vda.Grid to transistor Q1～Q4 is supplied with control signal S1～S4 respectively.Transistor Q1～Q4 carries out break-make according to control signal S1～S4 and switches running.

Figure 34 is the sequential chart that the running of Power Recovery circuit 980 during writing of Figure 33 is shown.The voltage NV1 of the node N1 of Figure 33 shown in Figure 34 and be added in the waveform of control signal S1～S4 of each transistor Q1～Q4 respectively.When control signal S1～S4 was high level (H), when Q1～Q4 conducting, control signal S1～S4 were low level (L), Q1～Q4 disconnected.

During TA, control signal S3 is a high level, and control signal S1, S2, S4 are low level.Thus, make transistor Q3 conducting, transistor Q1, Q2, Q4 disconnect.In the case, reclaim capacitor C1 and be connected the recovery inductance L with diode D1, utilize the LC resonance that reclaims inductance L and plate capacitor C p, the voltage NV1 of node N1 is slowly raise by transistor Q3.At this moment, the electric charge of recovery capacitor C1 is discharged into plate capacitor C p by transistor Q3, diode D1 and recovery inductance L.

During TB, control signal S1 is a high level, and control signal S2～S4 is a low level.Thus, make transistor Q1 conducting, transistor Q2～Q4 disconnects.At this moment, the voltage NV1 of node N1 is fixed on supply voltage Vda after sharply raising.

During TC, control signal S4 is a high level, and control signal S1～S3 is a low level.Thus, make transistor Q4 conducting, transistor Q1～Q3 disconnects.In the case, reclaim capacitor C1 and be connected to the recovery inductance L, utilize the LC resonance that reclaims inductance L and plate capacitor C p, the voltage NV1 of node N1 is slowly reduced by diode D2 and transistor Q4.At this moment, the Charge Storage that plate capacitor C p is stored by recovery inductance L, diode D2 and transistor Q4 arrives and reclaims capacitor C 1.Thus, with Power Recovery.

During TD, control signal S2 is a high level, and control signal S1, S3, S4 are low level.Thus, make transistor Q2 conducting, transistor Q1, Q3, Q4 disconnect.At this moment, N1 is connected to ground terminal with node, the voltage NV1 of node N1 is sharply reduced after, be fixed on earthing potential.

Like this, utilize Power Recovery circuit 980, the electric charge that then will be stored in plate capacitor C p is recovered to and reclaims capacitor C 1, again the electric charge that reclaims is supplied with plate capacitor C p simultaneously.Hereinafter will be called regenerative power based on the power that slave plate capacitor C p is recovered to the electric charge that reclaims capacitor C 1.

Thus, can reduce the foregoing circuit loss.The overall power consumption of plasma display system 900 is reduced.Among Figure 34, the change in voltage shown in the No.1 RQ of arrow is equivalent to regenerative power, and the change in voltage shown in the No.1 LQ of arrow is equivalent to circuit loss.

Yet,, must not necessarily carry out sufficient Power Recovery if according to above-mentioned Power Recovery circuit 980.According to Figure 35 and Figure 36 its reason is described.

Figure 35 is the mode chart that the show state of a routine PDP7 is shown, and Figure 36 is the oscillogram that is added in the data pulse on the address electrode for the show state of obtaining Figure 35.Figure 35 only illustrates the part of the PDP970 of Figure 29.

Figure 35 (a) illustrates 4 pixels (discharge cell) that an example is arranged on each address electrode 911 and shows " ?", " in vain ", " ?", " ?" from top to bottom successively.That is, this example is carried out the address discharge for the pixel (discharge cell) that the top of PDP970 only begins the 2nd row.

During without the Power Recovery circuit 980 of Figure 33,, produce data pulse Pda by power supply from power supply.Figure 36 (a) illustrates the waveform of example data pulse Pda at this moment.Among Figure 36 (a), the change in voltage shown in the No.1 LQ of arrow is equivalent to circuit loss.

During with power recovery circuit 980, produce data pulse Pda by power supply power supply with from the Power Recovery of above-mentioned plate capacitor C p.Figure 36 (b) illustrates the waveform of example data pulse Pda at this moment.Among Figure 36 (b), the change in voltage shown in the No.1 RQ of arrow is equivalent to regenerative power.

According to Figure 36 (a) and Figure 36 (b),, be used to regenerative power, the circuit loss of data driver 940 in the time of reducing to produce data pulse Pda from plate capacitor C p by using Power Recovery circuit 980.

On the other hand, Figure 35 (b) illustrates 4 pixels that an example is arranged on each address electrode 911 and shows " in vain ", " in vain ", " in vain ", " in vain " from top to bottom successively.That is, this example is carried out the address discharge for whole pixels of PDP970.At this moment, each address electrode 911 is applied a plurality of data pulse Pda continuously.

Here, imagine following situation:, be added to each address electrode 911 and a data pulse SPda who puts together is used as in continuous data pulse without power recovery circuit 980.

Figure 36 (c) illustrates the waveform of a routine data pulse Pda, SPda.Among Figure 36 (c), the No.1 LQ of arrow is equivalent to circuit loss.In the case, data pulse SPda produces the circuit loss of data driver 940 when rising, and does not produce the circuit loss of data driver 940 between each data pulse Pda.

Then, imagine following situation: use Power Recovery circuit 980, and apply continuous data pulse Pda at each address electrode 911.Figure 36 (d) illustrates the waveform of the continuous in the case data pulse Pda of an example.Among Figure 36 (d), the change in voltage shown in the No.1 LQ of arrow is equivalent to circuit loss, and the change in voltage shown in the No.1 RQ of arrow is equivalent to regenerative power.When using Power Recovery circuit 980, by Power Recovery and each continuous data pulse Pda of power supply power supply generation of plate capacitor C p.Thus, each rising edge of each data pulse Pda produces the circuit loss of data driver 940.

The waveform that compares the data pulse Pda shown in Figure 36 (c) and Figure 36 (d).Figure 36 (c) produces once big circuit loss when data pulse SPda rises.Then each produces once little circuit loss to Figure 36 (d) at each data pulse Pda.In view of the above, when the quantity of the data pulse Pda that produces further increases continuously,, also can not get circuit loss and fully reduce even carry out the Power Recovery of Power Recovery circuit 980.Like this, existing Power Recovery circuit 980 can not make circuit loss fully reduce sometimes.

The driving method that discloses for the patent disclosure 2002-156941 of Japan number is when all pixels are done the address discharge in PDP970 shown in Figure 35 (b), promptly when each address electrode 911 being applied continuously a plurality of data pulse Pda, reduce the amplitude of data pulse Pda, thereby reduce circuit loss.Yet, require further the address discharge stability and reduce power consumption.

Summary of the invention

The object of the present invention is to provide and a kind ofly can fully reduce power consumption, can carry out the display device and the driving method thereof of stable discharging again.

Display device according to one aspect of the present invention, have to comprise and be categorized into a plurality of groups the 1st electrode, be arranged to and the 2nd electrode of the 1st electrode crossing and the display board of a plurality of capacitive light emitting elements of the cross part that is arranged on the 1st electrode and the 2nd electrode, and driving circuit, this driving circuit applies the data pulse of the capacitive light emitting elements illuminating that makes selection respectively to a plurality of groups the 1st electrode, make and produce phase differential mutually among the described a plurality of group, driving circuit comprises to reclaim uses capacitive element, by from reclaiming with capacitive element to the 1st electrode discharge, or will be recovered to the recovery capacitive element from the electric charge of the 1st electrode, make and to apply the circuit that applies that driving pulse that data pulse uses is applied to the 1st electrode, and current potential restricting circuits, this current potential restricting circuits is recovered to the quantity of electric charge that reclaims with capacitive element by restriction and limits, and makes the current potential that reclaims with capacitive element be no more than setting.

In this display device, the 1st electrode of display board is categorized into a plurality of groups.In making display board, during the address of selected capacitive light emitting elements illuminating, will make the data pulse of the capacitive light emitting elements illuminating of selection be applied to a plurality of groups the 1st electrode by driving circuit.

Apply in the circuit, during the address, make electric charge use capacitive element from reclaiming to be discharged into the 1st electrode or electric charge is recovered to reclaim from the 1st electrode with capacitive element, thus the power consumption when reducing to produce driving pulse.

Apply circuit and operate, make that reclaiming the voltage that produces with capacitive element changes with the luminous and non-luminous switching times of a plurality of capacitive light emitting elements in the display board in the stipulated time.At this moment, limit, make the current potential that reclaims with capacitive element be no more than the setting that is lower than the 1st supply voltage, thereby the waveform of continuous driving pulse is separated by the current potential restricting circuits.

Thus, can to a plurality of groups the 1st electrode data pulse be applied to respectively from driving circuit and produce phase differential a plurality of groups mutually.At this moment, it is all different in each group of a plurality of crowds to be arranged on a plurality of groups the luminous timing of capacitive light emitting elements of the 1st electrode.Utilize this point, the glow current of the 2nd electrode flow is divided into a plurality of peaks, peak value is reduced.As a result, reduce to be added in the voltage drop that glow current causes in the driving voltage between the 1st electrode and the 2nd electrode.Therefore, capacitive light emitting elements can be stably luminous with low driving voltage.

Comprehensive The above results can reduce power consumption, and the display board driving margin is not impaired.

Here, driving margin is meant the scope that obtains the driving voltage that the capacitive light emitting elements stabilized illumination allowed that reaches.

Display device according to another aspect of the present invention, have to comprise and be categorized into a plurality of groups the 1st electrode, be arranged to and the 2nd electrode of the 1st electrode crossing and the display board of a plurality of capacitive light emitting elements of the cross part that is arranged on the 1st electrode and described the 2nd electrode, and driving circuit, this driving circuit applies the data pulse of the capacitive light emitting elements illuminating that makes selection respectively to the 1st described a plurality of groups electrode, make and produce phase differential mutually among the described a plurality of group, driving circuit comprises inductive element, reclaim and use capacitive element, electric capacity by utilizing display board and the running of the resonance of inductive element, from reclaiming with capacitive element to the 1st electrode discharge, or will be recovered to the recovery capacitive element by described inductive element from the electric charge of the 1st electrode, make the 1st described a plurality of groups electrode is applied the circuit that applies that driving pulse that data pulse uses is applied to described the 1st node, and current potential restricting circuits, this current potential restricting circuits is recovered to the quantity of electric charge that reclaims with capacitive element by restriction and limits, and makes the current potential that reclaims with capacitive element be no more than setting.

Apply circuit and operate, recovery is changed with the luminous and non-luminous switching times of a plurality of capacitive light emitting elements in the display board in the stipulated time with the voltage that capacitive element produces.At this moment, limit, make the current potential that reclaims with capacitive element be no more than the setting that is lower than the 1st supply voltage, thereby the waveform of continuous driving pulse is separated by the current potential restricting circuits.

Display device according to another aspect of the present invention, have to comprise and be categorized into a plurality of groups the 1st electrode, be arranged to and the 2nd electrode of the 1st electrode crossing and the display board of a plurality of capacitive light emitting elements of the cross part that is arranged on the 1st electrode and the 2nd electrode, and driving circuit, this driving circuit applies the data pulse of the capacitive light emitting elements illuminating that makes selection respectively to a plurality of groups the 1st electrode, make and produce phase differential mutually among the described a plurality of group, driving circuit comprises the 1st power supply terminal of accepting the 1st supply voltage, inductive element, reclaim and use capacitive element, utilize the resonance running of the electric capacity and the inductive element of display board, discharge electric charge from reclaiming with capacitive element, the current potential of the 1st node is risen, after connecting the 1st node and the 1st power supply terminal, cut off being connected of the 1st node and the 1st power supply terminal, and utilize the resonance running by inductive element electric charge to be recovered to reclaim and use capacitive element from the 1st node, the current potential of the 1st node is descended, thereby will apply the circuit that applies that driving pulse that data pulse uses is applied to described the 1st node to a plurality of groups the 1st electrode, and current potential restricting circuits, this current potential restricting circuits is recovered to the quantity of electric charge that reclaims with capacity cell by restriction and limits, and makes the current potential that reclaims with capacitive element be no more than the setting that is lower than described the 1st supply voltage.

Apply in the circuit, during the address, utilize the electric capacity of display board and the resonance of inductive element, discharge electric charge with capacitive element, the current potential of the 1st node is risen from reclaiming.And, by connecting the 1st node and the 1st power supply terminal, the current potential of the 1st node is elevated to the 1st supply voltage.Then, cut off being connected of the 1st node and the 1st power supply terminal, utilize the resonance running, by inductive element electric charge is recovered to reclaim from the 1st node and use capacitive element, and make the current potential decline of the 1st node.Thus, the 1st node is applied data pulse is added in the driving pulse that a plurality of groups the 1st electrode is used.

Like this, utilize the resonance running of the electric capacity and the inductive element of display board, make electric charge be discharged into the 1st node with capacitive element, utilize the resonance running of the electric capacity and the inductive element of display board again from reclaiming.Electric charge is recovered to reclaim from the 1st node uses capacitive element, thereby the power consumption when reducing to produce driving pulse.

Inductive element can be arranged between the 1st node and the 2nd node, will reclaim with capacitive element and be connected to the 3rd node, the current potential restricting circuits limits by the current potential that limits the 3rd node, makes the current potential of capacitive element be no more than setting; Apply circuit comprise the 1st on-off element that is arranged between the 1st power supply terminal and the 1st node, be arranged on ground terminal and the 2nd on-off element between the 1st node of accepting earthing potential, be arranged on the 3rd on-off element between the 2nd node and the 3rd node and be arranged on the 2nd node and the 3rd node between the 4th on-off element; During the address of the selected capacitive light emitting elements illuminating that makes display board, the 3rd on-off element conducting, thereby capacitive element discharges electric charge by inductive element to the 1st node, after making the current potential rising of described the 1st node, the 3rd on-off element disconnects, the 1st on-off element conducting, thereby after the current potential of the 1st node rises to the 1st supply voltage, the 1st on-off element disconnects, the 4th on-off element conducting, make electric charge be recovered to reclaim by inductive element and use capacity cell from the 1st node, and the decline of the current potential of the 1st node, thereby described driving pulse produced.

At this moment, apply in the circuit, during the address,, carry out the resonance running of the electric capacity and the inductive element of display board, by inductive element electric charge is discharged into the 1st node with capacitive element from reclaiming by the 3rd on-off element conducting.Again, disconnect by the 3rd on-off element, the 1st on-off element conducting makes the current potential of the 1st node rise to the 1st supply voltage.Then, disconnect by the 1st on-off element, the resonance running of the electric capacity and the inductive element of display board is carried out in the 4th on-off element conducting, electric charge is recovered to reclaim by inductive element from the 1st node uses capacitive element.As a result, produce driving pulse.

Like this, in applying circuit, utilize and switch the 1st on-off element, the 3rd on-off element and the 4th on-off element break-make separately, carry out the resonance running of the electric capacity and the inductive element of display board, thereby can utilize the generation of controlling and driving pulse easily of each switch of switching.

Again, utilize the current potential restricting circuits to limit, make the connection recovery be no more than the setting that is lower than the 1st supply voltage with the current potential of the 3rd node of capacitive element.Thus, separately with continuous drive pulse waveform.

Can make driving circuit also comprise the 1st on-off circuit that should be provided with the 1st electrode pair, and operate,, between the 1st node and the 1st electrode, carry out the recovery and the release of electric charge by the 1st on-off circuit conducting, disconnect by the 1st on-off circuit, set the 1st electrode of correspondence for earthing potential.

Thus, can be by switching the break-make of the 1st on-off element respectively, a plurality of capacitive light emitting elements is luminous and non-luminous in the control display board.

The 1st on-off circuit switching total degree of break-make separately is few more, and it is high more to reclaim the voltage that produces with capacity cell, also utilizes the current potential restricting circuits to limit simultaneously, makes recovery be no more than setting with the voltage that capacitive element produces.

The current potential restricting circuits is comprised by dividing the voltage between the 1st supply voltage and the earthing potential, generation is substantially equal to the division circuit and the 2nd on-off circuit of the current potential of setting, the 2nd on-off circuit is connected between the 3rd node and the earthing potential, the current potential that receives the generation of division circuit simultaneously is as control signal, and conducting when the current potential of the 3rd node surpasses setting.

At this moment, divide voltage between the 1st supply voltage and the earthing potential, be substantially equal to the current potential of setting with generation by dividing circuit.And the current potential that is connected the 2nd on-off circuit reception division circuit generation between the 3rd node and the ground terminal is as control signal, and conducting when the current potential of the 3rd node surpasses setting makes electric current flow to ground terminal from the 3rd node.Thus, the current potential of the 3rd node is no more than setting, also is no more than setting at the current potential that reclaims with the end generation of capacitive element.

Can make the current potential restricting circuits comprise the 2nd power supply terminal and the 2nd on-off circuit that acceptance is substantially equal to the 2nd supply voltage of setting, the 2nd on-off circuit is connected between the 3rd node and the earthing potential, the 2nd supply voltage that receives the acceptance of the 2nd power supply terminal simultaneously is as control signal, and conducting when the current potential of the 3rd node surpasses setting.

At this moment, the 2nd power supply terminal is supplied with the 2nd supply voltage that is substantially equal to setting.And the 2nd on-off circuit that is connected between the 3rd node and the ground terminal receives the 2nd supply voltage as control signal, and conducting when the current potential of the 3rd node surpasses setting makes electric current flow to ground terminal from the 3rd node.Thus, the current potential of the 3rd node is no more than setting, also is no more than setting at the voltage that reclaims with the end generation of capacitive element.

The 2nd on-off circuit is comprised be arranged between described the 3rd node and the 4th node, and make electric current from the 3rd node flow to the unidirectional breakover element of the 4th node and be arranged on the 4th node and institute ground terminal between, and have the 5th on-off element of the control terminal that receives control signal.

At this moment, when the current potential of the 3rd node surpasses setting, the 5th switch conduction, electric current flows to ground terminal from the 3rd node by unidirectional breakover element and the 5th on-off element.Thus, the current potential of the 3rd node is no more than setting, also is no more than setting at the voltage that reclaims with the end generation of capacitive element.

The current potential restricting circuits is comprised be arranged between the 3rd node and the ground terminal, and when the current potential of the 3rd node surpasses setting, make electric current flow to the unidirectional breakover element of ground terminal from the 3rd node.

At this moment, utilize the unidirectional breakover element that is arranged between the 3rd node and the ground terminal, when the current potential of the 3rd node surpasses setting, make electric current flow to ground terminal from the 3rd node.Thus, the current potential of the 3rd node is no more than setting, also is no more than setting at the voltage that reclaims with the end generation of capacitive element.And, be convenient to form.

Unidirectional breakover element can be a Zener diode.Thus, be convenient to form.

Also can have generation than the high current potential of the current potential of described the 1st node so that make the charge pump circuit of the 1st on-off element conducting.At this moment, produce the current potential of the current potential be higher than the 1st node, make the 1st on-off element conducting by the charge pump circuit.

The charge pump circuit is comprised be arranged on charging between the 1st node and the 5th node with capacity cell, be arranged between the 3rd power supply terminal and the 5th node of accepting the 3rd supply voltage, make electric current flow to the unidirectional breakover element of the 5th node and the current potential of the 5th node is added on the 1st node potential, and gained current potential after the addition is outputed to the control signal output circuit of the 1st on-off element as control signal from the 2nd power supply terminal.

At this moment, make electric current flow to the 5th node, be added on the current potential of the 1st node by the current potential of control signal output circuit, and gained current potential after the addition is outputed to the 1st on-off element as control signal the 5th node from the 2nd power supply terminal by unidirectional breakover element.

Can make setting greater than 1/2nd of the 1st supply voltage, and smaller or equal to 4/5ths of the 1st supply voltage.Thus, can guarantee the capacitive light emitting elements stabilized illumination.And, can obtain sufficient driving margin.

Can make phase differential more than or equal to 200ns.Thus, can guarantee the capacitive light emitting elements stabilized illumination.And, can obtain sufficient driving margin.

Can have a plurality of driving circuits, and a plurality of driving circuits are arranged to correspond respectively to a plurality of group, a plurality of driving circuits apply the data pulse that makes selected capacitive light emitting elements illuminating to a plurality of groups the 1st electrode respectively, make described a plurality of faciation produce phase differential mutually.

At this moment, by the requirement that produces phase differential mutually at a plurality of faciations, the data pulse that makes selected capacitive light emitting elements illuminating is applied to a plurality of groups the 1st electrode by a plurality of driving circuits of corresponding setting with a plurality of groups respectively respectively.Thus, the luminous timing that is arranged on the capacitive light emitting elements on a plurality of groups the 1st electrode is all different in each group of a plurality of crowds, thereby the glow current that circulates in the 2nd electrode is divided into a plurality of peaks, and peak value is reduced.As a result, the voltage drop that glow current causes in the driving voltage that is added between the 1st electrode and the 2nd electrode is reduced.Therefore, light-emitting component can be stably luminous with low driving voltage.

Also can have the rising number of times that detects the data pulse be applied to the 1st electrode or the number of times testing circuit of decline number of times, driving circuit yet can comprise the detected number of times of calculation times test section, and can the rise ratio of number of times or I decline number of times and running that control applies circuit makes its control part with the 1st node ground connection after ratio is reduced to the assigned voltage value with the current potential of the 1st node during greater than the requirement ratio value to data pulse maximum.

At this moment, detect the rising number of times or the decline number of times of the data pulse that is applied to the 1st electrode that is categorized into a plurality of groups by the number of times test section.Then, by the detected number of times of control part calculation times test section to can the rise ratio of number of times or I decline number of times of data pulse maximum, the comparison of ratio of calculating and requirement ratio value.

And control applies the running of circuit, when making the ratio of calculating greater than the requirement ratio value, after the current potential of the 1st node is reduced to the assigned voltage value, with the 1st node ground connection.

Here, apply power consumption in the circuit with the detected number of times of number of times test section to can the rise rate of change of number of times or I rising number of times of data pulse maximum.That is, the ratio of calculating is during greater than the requirement ratio value, and by with the 1st node ground connection, the luminance that can be regardless of a plurality of capacitive light emitting elements in the display board always reduces power consumption in the best condition.

Also can have the transformation component that 1 view data is transformed into the view data of each son, so that be divided into a plurality of sons with 1, and every make selected capacitive light emitting elements discharge, shows thereby carry out gray scale; The view data that the number of times test section is supplied with according to transformation component detects the number of times of each son field; The detected number of times of control part calculation times test section is to can the rise ratio of number of times or I decline number of times of data pulse maximum of each son, and control applies the running of circuit, make it at ratio during greater than the requirement ratio value, after the current potential of the 1st node is reduced to the assigned voltage value, with the 1st node ground connection.

At this moment, by transformation component 1 view data is transformed into the view data of each son field.Thus, can be divided into a plurality of son with 1, and every make selected capacitive light emitting elements discharge, show thereby carry out gray scale.

In each son field of a plurality of sons field, detect the rising number of times or the decline number of times of the data pulse that is applied to the 1st electrode that is categorized into a plurality of groups respectively by the number of times test section.Then, by the detected number of times of control part calculation times test section to can the rise ratio of number of times or I decline number of times of data pulse maximum, the comparison of ratio of calculating and requirement ratio value.

And control applies the running of circuit, when making the ratio of calculating greater than the requirement ratio value, after the current potential of the 1st node is reduced to the assigned voltage value, with the 1st node ground connection.Therefore, can be regardless of the luminance of a plurality of capacitive light emitting elements in the display board, always reduce power consumption in the best condition.

The rate value that can make regulation is more than or equal to 95%.Thus, can be regardless of the luminance of a plurality of capacitive light emitting elements in the display board, always reduce power consumption in the best condition.

Display-apparatus driving method according to another aspect of the present invention, this display device comprises to have and is categorized into a plurality of groups the 1st electrode, be arranged to the 2nd electrode of the 1st electrode crossing and be arranged on the 1st electrode and the display board of a plurality of capacitive light emitting elements of the cross part of the 2nd electrode, this method applies the data pulse of the capacitive light emitting elements illuminating that makes selection respectively to a plurality of groups the 1st electrode, make the step that produces phase differential among the described a plurality of group mutually, the step that applies data pulse comprises: utilize the resonance running of the electric capacity and the inductive element of display board, discharge electric charge from reclaiming with capacitive element, the current potential of the 1st node is risen, and after connecting the 1st node and the 1st power supply terminal, cut off being connected of the 1st node and the 1st power supply terminal, and utilize the resonance running by inductive element electric charge to be recovered to reclaim and use capacitive element from the 1st node, the current potential of the 1st node is descended, thereby will apply the step that driving pulse that data pulse uses is applied to the 1st node to a plurality of groups the 1st electrode, and be recovered to the quantity of electric charge that reclaims with capacity cell by restriction and limit, make recovery be no more than the step of the setting that is lower than the 1st supply voltage with the current potential of capacitive element.

In this display-apparatus driving method, in making display board during the address of selected capacitive light emitting elements illuminating, be applied to a plurality of groups the 1st electrode by the data pulse of the capacitive light emitting elements illuminating that will make selection.

When so a plurality of groups the 1st electrode being applied data pulse, during the address, utilize the electric capacity of display board and the resonance of inductive element, discharge electric charge with capacitive element, the current potential of the 1st node is risen from reclaiming.And, by connecting the 1st node and the 1st power supply terminal, the current potential of the 1st node is elevated to the 1st supply voltage.Then, cut off being connected of the 1st node and the 1st power supply terminal, utilize the resonance running, by inductive element electric charge is recovered to reclaim from the 1st node and use capacitive element, and make the current potential decline of the 1st node.Thus, the 1st node is applied data pulse is added in the driving pulse that a plurality of groups the 1st electrode is used.

Operate again, recovery is changed with the luminous and non-luminous switching times of a plurality of capacitive light emitting elements in the display board in the stipulated time with the voltage that capacitive element produces, and limit, make the current potential that reclaims with capacitive element be no more than the setting that is lower than the 1st supply voltage, thereby the waveform of continuous driving pulse is separated.

Produce phase differential among a plurality of groups mutually by respectively a plurality of groups the 1st electrode being applied to data pulse, make the luminous timing of capacitive light emitting elements of the 1st electrode that is arranged on a plurality of groups all different in each group of a plurality of crowds.Utilize this point, the glow current of the 2nd electrode flow is divided into a plurality of peaks, peak value is reduced.As a result, reduce to be added in the voltage drop that glow current causes in the driving voltage between the 1st electrode and the 2nd electrode.Therefore, capacitive light emitting elements can be stably luminous with low driving voltage.

Also can have the step of the rising number of times that detects the data pulse be applied to the 1st electrode or decline number of times and calculate detected number of times to data pulse maximum can rise the ratio of number of times or I decline number of times and running that control applies circuit, make its step after ratio is reduced to the assigned voltage value with the current potential of the 1st node during greater than the requirement ratio value with described the 1st node ground connection.

At this moment, detect the rising number of times or the decline number of times of the data pulse that is applied to the 1st electrode that is categorized into a plurality of groups.Then, the detected number of times of calculation times test section is to can the rise ratio of number of times or I decline number of times of data pulse maximum, the comparison of ratio of calculating and requirement ratio value.

Here, in this display device power consumption with the detected number of times of number of times test section to can the rise rate of change of number of times or I rising number of times of data pulse maximum.That is, the ratio of calculating is during greater than the requirement ratio value, and by with the 1st node ground connection, the luminance that can be regardless of a plurality of capacitive light emitting elements in the display board always reduces power consumption in the best condition.

Can make the requirement ratio value more than or equal to 95%.Thus, can be regardless of the luminance of a plurality of capacitive light emitting elements in the display board, always reduce power consumption in the best condition.

Description of drawings

Fig. 1 is the block diagram of basic composition that the plasma display system of embodiment 1 is shown.

Fig. 2 illustrates the sequential chart of driving voltage that an example is supplied with address electrode, scan electrode and the maintenance electrode of Fig. 1.

Fig. 3 is that explanation is used for the key diagram that the ADS mode of plasma display system of Fig. 1 is used.

Fig. 4 is the mode chart that the PDP show state of an illustration 1 is shown.

Fig. 5 is the figure that explanation address discharge current is used the dependence of data pulse phase difference.

Fig. 6 is the circuit diagram of the 1st data driver group, the 1st Power Recovery circuit and the PDP of Fig. 1.

Fig. 7 is the sequential chart that the 1st and the 2nd running of Power Recovery circuit during writing of Fig. 1 is shown.

Fig. 8 is the mode chart that a routine PDP show state is shown.

Fig. 9 be the node N1 of Fig. 6 when the show state of obtaining Fig. 8 is shown voltage, be added in the data pulse on the address electrode and supply with the sequential chart of the gating pulse of the 1st data driver group.

Figure 10 be the node N1 of Fig. 6 when the show state of obtaining Fig. 8 is shown voltage, be added in the data pulse on the address electrode and supply with the sequential chart of the gating pulse of the 1st data driver group.

Figure 11 be the node N1 of Fig. 6 when the show state of obtaining Fig. 8 is shown voltage, be added in the data pulse on the address electrode and supply with the sequential chart of the gating pulse of the 1st data driver group.

Figure 12 is the figure of running usefulness of the recovery current potential clamp circuit of key diagram 6.

Figure 13 is the figure of running usefulness of the recovery current potential clamp circuit of key diagram 6.

Figure 14 be illustrate write during in the oscillogram of recovery potential change of node N3 of Fig. 6.

Figure 15 is that recovery current potential and each gating pulse of sub that Figure 14 is shown are accumulated the curve map of the relation of rising number.

Figure 16 illustrates the circuit diagram that is arranged on the charge pump circuit of the 1st Power Recovery circuit in the illustration 6.

Figure 17 is the driving margin of plasma display system of key diagram 1 and the curve map that concerns usefulness of data pulse phase differential.

Figure 18 is the curve map of the relation that writes voltage and phase differential when demonstration " complete white " image is shown.

Figure 19 is the curve map of the relation that writes voltage and limiting voltage when demonstration " complete white " image is shown.

Figure 20 is the curve map of power consumption of power consumption and the plasma display system with another structure that is used for the plasma display system of comparison embodiment 1.

Figure 21 is the circuit diagram of the 1st data driver group, the 1st Power Recovery circuit and the PDP of embodiment 2.

Figure 22 is the circuit diagram of the 1st data driver group, the 1st Power Recovery circuit and the PDP of embodiment 3.

Figure 23 is the block diagram of basic composition that the plasma display system of embodiment 4 is shown.

Figure 24 is the block diagram of composition of the sub-field processor of explanation embodiment 4.

The sequential chart of the 1st and the 2nd running of Power Recovery circuit during writing among Figure 23 when Figure 25 illustrates by control signal power switched way of recycling.

Figure 26 is that recovery current potential and each gating pulse of sub that the plasma display system of embodiment 4 is shown are accumulated the curve map of the relation of rising number.

Figure 27 is the curve map of power consumption of power consumption and the plasma display system with another structure that is used for the plasma display system of comparison embodiment 4.

Figure 28 be rising ratio of being used for each son of comparison be 100% o'clock (San Chong ?when white) the figure of power consumption of plasma display system of no reclaiming type plasma display system, existing reclaiming type plasma display system and embodiment 1.

Figure 30 is the sequential chart of the driving voltage of address electrode, scan electrode and maintenance electrode that the PDP of an illustration 29 is shown.

Figure 31 illustrates the mode chart of an example by the PDP show state that is divided into the plasma display system that a plurality of data drivers constitutes.

Figure 32 is the figure that explanation address discharge current is used the dependence of data pulse phase difference.

As 33 are circuit diagrams that the existing Power Recovery circuit of an example is shown.

Figure 34 is the sequential chart that the running of Power Recovery circuit during writing of Figure 33 is shown.

Figure 35 is the mode chart that the show state of a routine PDP is shown.

Figure 36 is the oscillogram that is added on the address electrode with the data pulse of the show state that obtains Figure 35.

Embodiment

Below, an example as display device of the present invention and driving method thereof illustrates plasma display system and driving method thereof according to Fig. 1～Figure 28.

Embodiment 1

Fig. 1 is the block diagram of basic combination that the plasma display system of embodiment 1 is shown.

The plasma display system 100 of Fig. 1 has analog-to-digital converter (analogue-digital converter hereinafter referred to as) 1, vision signal-son corresponder 2, sub-field processor the 3, the 1st data driver group 4a, the 2nd data driver group 4b, scanner driver 5, keeps driver 6, plasma display panel (hereinafter referred is PDP) the 7, the 1st Power Recovery circuit 8a and the 2nd Power Recovery circuit 8b.

Analogue-digital converter 1 is supplied with analog video signal VD.After analogue-digital converter 1 is transformed into Digital Image Data with vision signal VD, supplying video signal-son corresponder 2.

Vision signal-son corresponder 2 produces the view data SP of each son field from 1 view data, supplies with sub-field processor 3, shows to be divided into a plurality of sons field with 1.In the plasma display system 100 of present embodiment,, adopt the address and show phase separate mode (phase place abbreviates the ADS mode as) as gray scale display driver mode.The detailed content of ADS mode is set forth in the back.

Sub-field processor 3 produces data driver control signal DSa and DSb, Power Recovery circuit control signal Ha and Hb, scanner driver control signal CS and keeps driver control signal US from the view data SP of described son field.

Data driver control signal DSa, DSb are supplied with the 1st data driver group 4a and the 2nd data driver group 4b respectively.Power Recovery circuit control signal Ha, Hb are supplied with the 1st Power Recovery circuit 8a and the 2nd Power Recovery circuit 8b respectively.Scanner driver control signal CS is supplied with scanner driver 5, keep driver control signal US then to supply with and keep driver 6.

Form each the 1st data driver group 4a and the 2nd data driver group 4b by unshowned a plurality of data driver integrated circuit and a plurality of module.The 1st data driver group 4a connexon field processor the 3, the 1st Power Recovery circuit 8a and PDP7, the 2nd data driver group 4b connexon field processor the 3, the 2nd Power Recovery circuit 8b and PDP7.And, on PDP7, connect scanner driver 5 respectively and keep driver 6.

PDP7 comprises a plurality of address electrodes (data electrode) 41 ₁～41 _nWith 42 ₁～42 _n, a plurality of scan electrodes 12 ₁～12 _mAnd a plurality of maintenance electrodes 13 ₁～13 _mM and n are respectively arbitrary integers.Vertical direction toward screen is arranged a plurality of address electrodes 41 ₁～41 _nWith 42 ₁～42 _n, arrange a plurality of scan electrodes 12 toward the horizontal direction of screen ₁～12 _mAnd a plurality of maintenance electrodes 13 ₁～13 _mMake a plurality of maintenance electrodes 13 ₁～13 _mLink together jointly.Among Fig. 1, with address electrode 41 ₁～41 _nCome the left side of screen, address electrode 42 ₁～42 _nCome the right side of screen.

At address electrode 41 ₁～41 _nWith 42 ₁～42 _n, scan electrode 12 ₁～12 _mAnd maintenance electrode 13 ₁～13 _mEach intersection point form discharge cell 14.The pixel that each discharge cell 14 constitutes on the screen.Among Fig. 1, the discharge cell on the screen 14 is arranged in " the capable 2n row of m ".

With a plurality of address electrodes 41 ₁～41 _nConnect the 1st data driver group 4a, a plurality of address electrodes 42 ₁～42 _nConnect the 2nd data driver group 4b.With a plurality of scan electrodes 12 ₁～12 _m Connect scanner driver 5, a plurality of maintenance electrodes 13 ₁～13 _mConnect and keep driver 6.

Here, scanner driver 5 has each scan electrode 12 in inside ₁～12 _mThe driving circuit that is provided with, each driving circuit connects the respective scan electrode 12 of PDP7 ₁～12 _m

The 1st data driver group 4a is applied to address electrode suitable among the PDP7 41 according to view data SP with data pulse according to data driver control signal DSa during writing ₁～41 _nThe power supply terminal of a plurality of data driver integrated circuit of the 1st data driver group 4a is supplied with in the output of the 1st Power Recovery circuit 8a, to produce described data pulse.The 1st Power Recovery circuit 8a operates according to Power Recovery circuit control signal H a.The 1st data driver group 4a during the back elaboration writes and the detailed operation of the 1st Power Recovery circuit 8a.

The 2nd data driver group 4b is applied to address electrode suitable among the PDP7 42 according to view data SP with data pulse according to data driver control signal DS b during writing ₁～42 _nIn some.The power supply terminal of a plurality of data driver integrated circuit of the 2nd data driver group 4b is supplied with in the output of the 2nd Power Recovery circuit 8b, to produce described data pulse.The 2nd Power Recovery circuit 8b operates according to Power Recovery circuit control signal H b.The 2nd data driver group 4b during writing is identical with the detailed operation of the 1st data driver group 4a that sets forth later and the 1st Power Recovery circuit 8a with the detailed operation of the 2nd Power Recovery circuit 8b.

Scanner driver 5 is according to scanner driver control signal CS, during initialization to whole scan electrodes 12 among the PDP7 ₁～12 _mApply the initial setting pulse simultaneously.Then, during writing in, toward vertical scanning direction displacement, one side will write pulse and be applied to a plurality of scan electrodes 12 successively one side with shift pulse ₁～12 _mThus, in selected discharge cell 14, carry out the address discharge.

Scanner driver 5 will periodically keep pulse to be applied to a plurality of scan electrodes 12 of PDP7 during keeping according to scanner driver control signal CS ₁～12 _mOn the other hand, keep driver 6 according to keeping driver control signal US, during keeping to the maintenance electrode 13 of PDP7 ₁～13 _mApply simultaneously scan electrode 12 ₁～12 _mThe maintenance pulses of maintenance impulse phase skew 180 degree.Thus, in the discharge cell 14 that carries out the address discharge, keep discharge.

Among Fig. 2, during initialization simultaneously to a plurality of scan electrodes 12 ₁～12 _mApply initial setting pulse Pset.Then, during writing to each address electrode 41 ₁～41 _n42 ₁～42 _nApply the data pulse Pda that carries out conducting or disconnection according to vision signal, and with this data pulse Pda synchronously successively to a plurality of scan electrodes 12 ₁～12 _mApply and write pulse Pw.Thus, the address discharge takes place in the selected discharge cell 14 of PDP1 successively.

In the present embodiment, as shown in Figure 2, produce the 1st data driver group 4a at address electrode 41 ₁～41 _nThe timing that applies data pulse Pda and the 2nd data driver group 4b are at address electrode 42 ₁～42 _nApply the skew TR between the timing of data pulse Pda.The detailed content of skew TR is set forth in the back.

Then, in keeping period P 3, periodically to a plurality of scan electrodes 12 ₁～12 _mApply maintenance pulse Psc, and periodically to a plurality of maintenance electrodes 13 ₁～13 _mApply and keep pulse Psu.Phase deviation 180 degree of phase place that keep pulse Psu to keeping pulse Psc.Thus, follow-up in the address discharge, discharge takes place to keep.

As mentioned above, in the plasma display system 100 of present embodiment, the ADS mode is used as gray scale display driver mode.Here, the ADS mode is described.Fig. 3 is that explanation is used for the key diagram that the ADS mode of plasma display system 100 of Fig. 1 is used.

In the ADS mode, with 1 (1/60 second=16.67ms) be divided into a plurality of son in time.For example, when carrying out 256 gray level display, be divided into 8 son SF1～SF8 with 1 with 8.Again height field SF1～SF8 is separated into initialization period P 1, writes period P 2 and keeps period P 3.Among each son SF1～SF8, identical with the example of Fig. 2, also carry out setting of each son in initialization period P 1, select the address of discharge cell 14 usefulness lighted to discharge writing period P 2, keeping period P 3 to show the maintenance discharge of usefulness.

In the maintenance period P 3 of son SF1～SF8, (brightness) is weighted to briliancy respectively.During the maintenance of each son SF1～SF8 to scan electrode 12 ₁～12 _mWith maintenance electrode 13 ₁～13 _mApply quantity and satisfy the maintenance pulse of the brightness of weighting.For example, among the son SF1, to keeping electrode 13 ₁～13 _m Apply 1 time and keep pulse, to scan electrode 12 ₁～1 ₂M applies 1 time and keeps pulse, and carries out 2 times and keep discharge writing period P 2 selected discharge cells 14.Among the son SF2, to keeping electrode 13 ₁～13 _m Apply 2 times and keep pulse, to scan electrode 12 ₁～12 _m Apply 2 times and keep pulse, and selected discharge cell 14 carries out keeping for 4 times discharging in writing period P 2.

Like this, son SF1～SF8 finish respectively 1,2,4,8,16,32,64 and 128 luminance weighted, and make up this a little SF1～SF8, thus can be with 256 grades of sizes of adjusting brightness of 0 to 255.The number of partitions of son field and weighted value etc. are not specifically limited to above-mentioned example, can do various changes, for example in order to take in sail the image simulation profile, a son SF8 can be divided into 2, and 2 sub weighted value is set at 64.

Then, in the key diagram 2 to address electrode 41 ₁～41 _nApply the timing of data pulse Pda with to address electrode 42 ₁～42 _nApply the skew TR of the timing of data pulse Pda.

In the following explanation, will be to address electrode 41 ₁～41 _n, 42 ₁～42 _nThe timing that applies data pulse Pda is called data pulse and applies regularly, to address electrode 41 ₁～41 _nApply the timing of data pulse Pda with to address electrode 42 ₁～42 _nThe skew TR that applies the timing of data pulse Pda is called data pulse phase differential TR.

Fig. 4 is the mode chart of show state that the PDP7 of an illustration 1 is shown, and Fig. 5 is the figure that explanation address discharge current is used the dependence of data pulse phase difference.

Among Fig. 4, in the discharge cell 14 on the PDP7 at scan electrode 12 ₁On discharge cell 14 all luminous.

The situation that does not have the data pulse phase differential when the show state of realizing Fig. 4 being described here.Shown in Fig. 5 (a), when not having the data pulse phase differential, discharge cell 14 on address electrode 411～41n and address electrode 42 ₁～42 _nOn discharge cell 14 the address discharge takes place in identical timing t 1.Thus, scan electrode 12 ₁Generation has the discharge current DA2 at a peak.

At this moment, scan electrode 12 ₁In, because address electrode 41 ₁～41 _nOn discharge cell 14 and address electrode 42 ₁～42 _nOn discharge cell 14 discharge current that circulates simultaneously, it is big that the amplitude A M2 of discharge current DA2 becomes.Thus, be added in scan electrode 12 ₁The pulse Pw that writes go up to produce big voltage drop amount E2.As a result, address discharge instability.Therefore, scan electrode 12 must should be added in ₁The voltage SH2 that writes pulse Pw set highly, to carry out the discharge of stable address.

The situation that has data pulse phase differential TR when then, the show state of the PDP7 that realizes Fig. 4 being described.Shown in Fig. 5 (b), when having data pulse phase differential TR, address electrode 41 ₁～41 _nOn discharge cell 14 address discharge, address electrode 42 take place in timing t 1 ₁～42 _nOn discharge cell 14 the addresses discharge takes place in timing t 2.Thus, scan electrode 12 ₁The middle discharge current DA1 that produces with 2 peaks.

At this moment, scan electrode 12 ₁In, because address electrode 41 ₁～41 _nOn discharge cell 14 and address electrode 42 ₁～42 _nOn discharge cell 14 at different timing circulation discharge current, the amplitude A M1 of discharge current DA1 strengthens along with data pulse phase differential TR and diminishes.Thus, be added in scan electrode 12 ₁The voltage drop amount E1 that pulse Pw go up to produce of writing also strengthen and diminish along with data pulse phase differential TR.Therefore, even should be added in scan electrode 12 ₁The voltage SH1 that writes pulse Pw set lowly, also whole stable discharging.In other words,, can guarantee discharge cell 14 stable dischargings again, can reduce the voltage (driving voltage) that writes pulse Pw again, and enlarge the driving margin of setting forth later by setting data pulse phase differential TR greatly.

Like this, in the plasma display system 100 of present embodiment, by the 1st data driver group 4a and the 2nd data driver group 4b to address electrode 41 ₁～41 _n, 42 ₁～42 _nWhen applying data pulse Pda, produce data pulse phase differential TR.Thus, can guarantee discharge cell 14 stable dischargings again, can reduce the voltage (driving voltage) that writes pulse Pw again, and enlarge the driving margin of setting forth later.

According to data driver group 4a, the 1st Power Recovery circuit 8a of middle Fig. 1 during Fig. 6～Figure 16 explanation writes and detailed composition and the running of PDP7.

Fig. 6 be the 1st data driver group 4a among Fig. 1, the 1st Power Recovery circuit 8a and PDP7 circuit diagram.As indicated above, the 1st Power Recovery circuit 8a connects a plurality of address electrodes 41 of PDP7 by the 1st data driver group 4a ₁～41 _nAmong Fig. 6, each address electrode 41 will be arranged among the PDP7 ₁～41 _nThe capacitance meter of a plurality of discharge cells 14 be shown Cp ₁～Cp _n, the summation of these electric capacity is expressed as plate capacitor C p.

According to Fig. 6, the 1st Power Recovery circuit 8a comprises recovery capacitor C1, reclaims inductance L, N slot field-effect transistor (hereinafter referred is a transistor) Q1～Q4, diode D1 and D2 and reclaims current potential clamp circuit 80.Reclaim current potential clamp circuit 80 and comprise resistance R 1, R2 and R3, diode D3 and D4 and bipolar transistor (hereinafter referred is a transistor) Q5.

To reclaim capacitor C1 is connected between node N3 and the ground terminal.Serial transistor Q3 and diode D1 between node N3 and node N2, then series diode D2 and transistor Q4 between node N2 and the node N3.

To reclaim inductance L is connected between node N2 and the node N1.Between node N1 and power supply terminal V1, be connected transistor Q1, then be connected transistor Q2 between node N1 and the ground terminal.

Reclaim in the current potential clamp circuit 80, be connected diode D3 between node N3 and node N4, node N4 also connects the emitter of transistor Q5, and the collector of transistor Q5 then is connected to ground terminal by resistance R 3.Between power supply terminal V1 and node N5, be connected resistance R 1, then be connected resistance R 2 between node N5 and the ground terminal.Node N5 connects the base stage of transistor Q5.Between node N5 and node N4, be connected diode D4.

The 1st data driver group 4a comprises a plurality of P-channel field-effect transistor (PEFT) transistors (hereinafter referred is a transistor) Q1 ₁～Q1 _n, a plurality of N slot field-effect transistors (hereinafter referred is a transistor) Q2 ₁～Q2 _nNode N1 and node ND at the 1st Power Recovery circuit 8a ₁～ND _nBetween connect transistor Q1 respectively ₁～Q1 _nAt node ND ₁～ND _nBe connected transistor Q2 between the ground terminal respectively ₁～Q2 _nTo a plurality of transistor Q1 ₁～Q1 _n, Q2 ₁～Q2 _nGrid supply with the gating pulse Sa that the data driver control signal DSa according to the sub-field processor 3 of Fig. 1 produces ₁～Sa _n

Node ND1～NDn of the 1st data driver group 4a connects the address electrode 41 of PDP7 respectively ₁～41 _nAt address electrode 41 ₁～41 _nAnd difference calculated address electrode capacitance Cp between the ground terminal ₁～Cp _nThere is stray capacitance Cf between the node N1 of the 1st Power Recovery circuit 8a and the ground terminal.

The composition of the 2nd data driver group 4b and the 2nd Power Recovery circuit 8b is identical with the composition of above-mentioned the 1st data driver group 4a and the 1st Power Recovery circuit 8a.A plurality of transistor Q1 to the 2nd data driver group 4b ₁～Q1 _n, Q2 ₁～Q2 _nGrid supply with the gating pulse Sa that the data driver control signal DSb according to Fig. 1 neutron field processor 3 produces ₁～Sa _n

With supply voltage Vda supply power terminal V1.Respectively the grid of transistor Q1～Q4 is supplied with control signal S1～S4.Transistor Q1～Q4 carries out the break-make blocked operation according to control signal S1～S4.The Power Recovery circuit control signal Ha that supplies with according to the sub-field processor 3 of Fig. 1 produces control signal S1～S4.Transistor Q1～Q4 to the 2nd Power Recovery circuit 8b of Fig. 1 supplies with the control signal S1～S4 that produces according to Power Recovery circuit control signal Hb.

Fig. 7 is the 1st and the 2nd Power Recovery circuit 8a that Fig. 1 is shown, the sequential chart of the running of 8b during writing.Among Fig. 7, illustrate by solid line Fig. 6 node N1 voltage NV1 and supply with the waveform of control signal S1～S4 of transistor Q1～Q4 respectively.The voltage NV1 of the node N1 of the 2nd data driver group 4b shown by dashed lines and supply with the signal waveform of control signal S1～S4 of transistor Q1～Q4 respectively.

Among Fig. 7, behind the voltage NV1 of the 1st Power Recovery circuit 8a and control signal S1～S4 with picture bracket label symbol 8a, behind the voltage NV1 of the 2nd Power Recovery circuit 8b and control signal S1～S4 with picture bracket label symbol 8b.

When control signal S1～S4 is high level, transistor Q1～Q4 conducting, when control signal S1～S4 was low level, transistor Q1～Q4 disconnected.

During TA, control signal S3 is a high level, and control signal S1, S2, S4 are low level.Thus, transistor Q3 conducting, transistor Q1, Q2, Q4 disconnect.At this moment, reclaim capacitor C1 and be connected the recovery inductance L with diode D1, utilize the LC resonance that reclaims inductance L, stray capacitance Cf and plate capacitor C p, the voltage NV1 of node N1 is slowly risen by transistor Q3.

At this moment, by transistor Q3, diode D1 with after reclaiming electric charge that inductance L will reclaim capacitor C1 and being discharged into stray capacitance Cf, and then be discharged into the plate capacitor C p of PDP7 by the 1st data driver group 4a.

During TB, control signal S1 is a high level, and control signal S2～S4 is a low level.Thus, transistor Q1 conducting, transistor Q2～Q4 disconnects.At this moment, by transistor Q1 node N1 is connected to power supply terminal V1.Thus, the voltage NV1 of node N1 is sharply risen, and be fixed on the supply voltage Vda of supply power terminal V1 thereupon.

During TC, control signal S4 is a high level, and control signal S1～S3 is a low level.Thus, transistor Q4 conducting, transistor Q1～Q3 disconnects.At this moment, will reclaim capacitor C1 by transistor Q4 and diode D2 and be connected to the recovery inductance L, utilize the LC resonance that reclaims inductance L and power transformation device Cp, the voltage NV1 of node N1 is slowly descended.At this moment, the electric charge of stray capacitance Cf and plate capacitor C p is recovered to reclaims capacitor C1 by reclaiming inductance L, diode D2 and transistor Q4.

The 1st Power Recovery circuit 8a repeats the running during TA～TC, thereby the electric charge of plate capacitor C p and stray capacitance Cf storage is recovered to recovery capacitor C1, again the electric charge that reclaims is supplied with plate capacitor C p and stray capacitance Cf simultaneously.Hereinafter will be called regenerative power based on the power that slave plate capacitor C p and stray capacitance Cf are recovered to the recovery electric charge that reclaims capacitor C1.

Identical based on the voltage that is recovered to the electric charge that reclaims capacitor C1 with the voltage of the node N3 of Fig. 6.Hereinafter the voltage with node N3 is called recovery current potential Vm.The recovery capacitor C1 of Fig. 6 and recovery inductance L are carried out based on the LC resonance that reclaims current potential Vm.Thus, as shown in Figure 7, the voltage NV1 of the node N1 of Fig. 6 produces variation AC.The variation AC of voltage NV1 changes with reclaiming current potential Vm.

In the above-mentioned explanation, during TA～TC in, control signal S2 is a low level always, and transistor Q2 is always disconnected.Yet control signal S2 becomes high level along with the end that writes period P 2 (Fig. 2), and writes period P 2 along with starting once more, becomes low level.Thus, transistor Q2 is writing beyond the period P 2, and conducting always makes node N1 be connected to ground terminal.Carry out this running, with the Charge Storage of ormal weight to the charge pump circuit of setting forth later.

During TA～TC, the recovery current potential clamp circuit 80 of the Power Recovery circuit 8a of Fig. 6 carries out following running.

Reclaim in the current potential clamp circuit 80, resistance R 1, R2 are connected between power supply terminal V1 and the ground terminal.Thus, the node N5 between resistance R 1, R2 produces the voltage NV5 of regulation.On the other hand, node N4 is supplied with the recovery current potential Vm of node N3.Here, in order to make illustrative ease, ignore the voltage drop (for example 0.7V) of diode D3.Recovery current potential Vm changes according to the running of the 1st data driver group 4a that sets forth later.

Transistor Q5 disconnects during more than or equal to the voltage of node N4 at the voltage NV5 of node N5, in the voltage NV5 of node N5 conducting during smaller or equal to the voltage of node N4.That is, transistor Q5 is lower than at the recovery current potential Vm of node N3 and disconnects when equaling voltage NV5, is higher than conducting when equaling voltage NV5 at the recovery current potential Vm of node N3.

Thus, reclaim current potential Vm and be lower than when equaling voltage NV5, transistor Q5 disconnects, thereby preserves and reclaim the electric charge that capacitor C1 stores, and it is not discharged into ground terminal.

Reclaim current potential Vm and be higher than when equaling voltage NV5, transistor Q5 conducting, thereby the electric charge that recovery capacitor C1 stores is discharged into ground terminal by node N3, diode D3, node N4, transistor Q5 and resistance R 3.As a result, the recovery current potential Vm of node N3 is no more than voltage NV5.

Below will according to by resistance R 1, the R2 of Fig. 6 and the higher limit that is added in the recovery current potential Vm that voltage NV5 that the supply voltage Vda on the power supply terminal V1 sets limited be called limiting voltage Vr.

In the above-mentioned explanation, when considering the voltage drop of diode D3, set the voltage NV5 of node N5 for share than the voltage drop of the low diode D3 of limiting voltage Vr.

Like this, make recovery current potential clamp circuit 80 when the recovery current potential Vm of node N3 oversteps the extreme limit voltage Vr, carry out the clamp running.Therefore, reclaim current potential Vm and be no more than limiting voltage Vr.The plasma display system 100 that present embodiment is set forth in the back is provided with the reason that reclaims current potential clamp circuit 80.

Among Fig. 7, the voltage NV1 of the voltage NV1 of the node N1 of the 2nd Power Recovery circuit 8b and the waveform of control signal S1～S4 and the node N1 of the 1st Power Recovery circuit 8a is identical with the waveform of control signal S1～S4, but produces phase deviation TR.This timing slip TR is equivalent to the data pulse phase differential TR of Fig. 5.

Then, according to the running of the 1st Power Recovery circuit 8a and the 1st data driver group 4a, the each recovery current potential Vm that rises and change of the voltage NV1 of key diagram 7.

Fig. 8 illustrates the mode chart that the show state of a routine PDP7 changes, Fig. 9～Figure 11 be the node N1 of Fig. 6 when the show state of obtaining Fig. 8 is shown voltage NV1, be added in address electrode 41 ₁On data pulse Pda and supply with the gating pulse Sa of the 1st data driver group 4a ₁～Sa ₄The figure of timing.Fig. 8 only illustrates the PDP7 of partial graph 1.

Among Fig. 8 (a), the example that whole pixels show " in vain " is shown among the PDP7 of Fig. 1.Hereinafter whole pixels among such PDP7 are shown that the show state of " in vain " is called " complete white ".At this moment, the whole discharge cells 14 that constitute the pixel of PDP7 all discharge.

Among Fig. 8 (b), illustrate among the PDP7 of Fig. 1 whole pixels show “ ?" an example.Hereinafter with among such PDP7 all pixels show “ ?" show state be called “ Quan ?".At this moment, the whole discharge cells 14 that constitute the pixel of PDP7 do not discharge.

Among Fig. 8 (c), be illustrated in the direction up and down of the PDP7 of Fig. 1, pixel Alternation Display " in vain " He “ ?" an example.Among Fig. 8 (c), by address electrode 41 ₁On the pixel that forms of discharge cell 14 show from top to bottom " in vain ", “ ?", " in vain " He “ ?", by address electrode 41 ₂On the pixel that forms of discharge cell 14 show from top to bottom “ ?", " in vain ", “ ?" and " in vain ".Hereinafter with the pixel of PDP7 like this in direction Alternation Display " in vain " up and down He “ ?" state be called San Chong ?white.At this moment, in the direction up and down of PDP7, separate a discharge cell 14 that constitutes pixel and discharge, the discharge cell 14 between these two unit does not discharge.

Under the show state of the PDP7 of Fig. 8 (a), the voltage NV1 of the node N1 of Fig. 6, be added in address electrode 41 ₁On data pulse Pda and supply with the gating pulse Sa of the 1st data driver group 4a ₁～Sa ₄By changing as shown in Figure 9.

As shown in Figure 9, when at PDP7 being " complete white ", the recovery current potential Vm of the node N3 of the variation AC response diagram 6 of the voltage NV1 of the node N1 of Fig. 6 changes.The voltage NV1 of Fig. 7 rises each time, reclaims current potential Vm and changes.

According to Fig. 9, voltage NV1 rises at every turn, and the variation AC of voltage NV1 diminishes successively.At this moment, gating pulse Sa ₁～Sa ₄Total in writing period P 2 is low level.Thus, when PDP7 is " complete white ", transistor Q1 ₁～Q1 ₄Total conducting, transistor Q2 ₁～Q2 ₄The total disconnection.As a result, address electrode 41 ₁On apply voltage NV1 as data pulse Pda, thereby address electrode 41 ₁Voltage and voltage NV1 similarly change.

During the PC of Fig. 9, as indicated above, the LC resonance of the recovery inductance L of Fig. 6 and stray capacitance Cf and plate capacitor C p raises the voltage NV1 of node N1, and after making it fixing by the voltage Vda that is added in power supply terminal V1, the LC resonance that reclaims inductance L and stray capacitance Cf and plate capacitor C p makes its reduction.

Because transistor Q1 ₁～Q1 ₄Total conducting, transistor Q2 ₁～Q2 ₄The total disconnection when voltage NV1 raises, is discharged into stray capacitance Cf and plate capacitor C p with the electric charge that reclaims capacitor C1 storage.Otherwise when voltage NV1 reduced, the electric charge that stray capacitance Cf and plate capacitor C p are stored was recovered to and reclaims capacitor C1.

When PDP7 is " complete white ",, the electric charge that reclaims capacitor C1 storage is increased gradually by repeating the above-mentioned PC phase.Therefore, the recovery current potential Vm of the node N3 of Fig. 6 is along with to address electrode 41 ₁～41 ₄Apply data pulse Pda, raise successively.Thus, reduce the circuit loss (the No.1 LQ of the arrow of Fig. 9) of the 1st data driver group 4a.Among the 2nd data driver group 4b, reduce circuit loss too.

But, reclaim current potential Vm and do not rise to such an extent that be higher than the limiting voltage Vr of Fig. 7 because of the recovery current potential clamp circuit 80 of Fig. 6.As a result, be fixed on limiting voltage Vr owing to reclaim current potential Vm, the variation AC of above-mentioned voltage NV1 is constant.The detailed variation of reclaiming current potential Vm is set forth in the back.

As shown in figure 10, PDP7 be “ Quan ?" time, the recovery current potential Vm of node N3 in the variation AC response diagram 6 of the voltage NV1 of node N1 changes among Fig. 6.The voltage NV1 of Fig. 7 rises each time, reclaims current potential Vm and changes.

According to Figure 10, voltage NV1 rises at every turn, and the variation AC of voltage NV1 diminishes successively.At this moment, gating pulse Sa ₁～Sa ₄Total in writing period P 2 is high level.Thus, PDP7 be “ Quan ?" time, transistor Q1 ₁～Q1 ₄Total disconnection, transistor Q2 ₁～Q2 ₄Total conducting.As a result, address electrode 41 ₁On apply voltage NV1 as data pulse Pda, thereby address electrode 41 ₁Voltage always be earthing potential Vg.

During the PC of Figure 10, as indicated above, the LC resonance of the recovery inductance L of Fig. 6 and stray capacitance Cf and plate capacitor C p raises the voltage NV1 of node N1, and after making it fixing by the voltage Vda that is added in power supply terminal V1, the LC resonance that reclaims inductance L and stray capacitance Cf and plate capacitor C p makes its reduction.

Because transistor Q1 ₁～Q1 ₄Total disconnection, transistor Q2 ₁～Q2 ₄Total conducting when voltage NV1 raises, is discharged into stray capacitance Cf and plate capacitor C p with the electric charge that reclaims capacitor C1 storage.Otherwise when voltage NV1 reduced, the electric charge that stray capacitance Cf is stored was recovered to recovery capacitor C1.

PDP7 be “ Quan ?" time, by repeating the above-mentioned PC phase, make and reclaim the electric charge that capacitor C1 stores and increase gradually.Therefore, voltage NV1 rises at every turn, and the recovery current potential Vm of the node N3 of Fig. 6 raises successively.Thus, reduce the circuit loss (the No.1 LQ of the arrow of Figure 10) of the 1st data driver group 4a.Among the 2nd data driver group 4b, reduce circuit loss too.

But, reclaim current potential Vm and do not rise to such an extent that be higher than the limiting voltage Vr of Fig. 7 because of the recovery current potential clamp circuit 80 of Fig. 6.As a result, be fixed on limiting voltage Vr owing to reclaim current potential Vm, the variation AC of above-mentioned voltage NV1 is constant.

As shown in figure 11, when PDP7 is " San Chong ?white ", when rising first except that voltage NV1, the variation AC of the voltage NV1 of node N1 is constant among Fig. 6.This is that the recovery current potential Vm of the node N3 of Fig. 6 is constant because except that voltage NV1 rises first.

At this moment, in writing period P 2, gating pulse Sa ₁, Sa ₃To voltage NV1 rise repetition low level and high level at every turn.Gating pulse Sa ₂, Sa ₄NV1 rises at every turn to voltage, with gating pulse Sa ₁, Sa ₃On the contrary, repeat high gentle low level.Thus, each PC phase is switched each transistor Q1 ₁～Q1 ₄Break-make and transistor Q2 ₁～Q2 ₄Break-make.As a result, address electrode 41 ₁Voltage at gating pulse Sa ₁, Sa ₃Rise to the voltage Vda of Fig. 7 during for low level, and at gating pulse Sa ₂, Sa ₄Become earthing potential Vg during for low level.

During the PC of Figure 11, as indicated above, the LC resonance of the recovery inductance L of Fig. 6 and stray capacitance Cf and plate capacitor C p raises the voltage NV1 of node N1, and after making it fixing by the voltage Vda that is added in power supply terminal V1, the LC resonance that reclaims inductance L and stray capacitance Cf and plate capacitor C p makes its reduction.

Interim at first PC phase to the 2PC, recovery current potential Vm does not reclaim current potential Vs from minimum and changes after being varied to the minimum recovery current potential Vs that sets forth later.

First PC is interim, when voltage NV1 rises, and transistor Q1 ₁Conducting, transistor Q2 ₁Disconnect, thereby the electric charge that will reclaim capacitor C1 storage is discharged into stray capacitance Cf and address electrode capacitor C p ₁Here, with address electrode capacitor C p ₁With the transistor Q1 that is in conducting state ₁Connect.And, by making transistor Q1 ₂Disconnect transistor Q2 ₂Conducting is recovered to stray capacitance Cf with the electric charge that reclaims capacitor C1 storage.

Then, when voltage NV1 descends, with stray capacitance Cf and address electrode capacitor C p ₁The electric charge that stores is recovered to and reclaims capacitor C1.Here, voltage NV1 is because of stray capacitance Cf and address electrode capacitor C p ₁The electric charge that stores and be reduced to regulation current potential Vgx is not reduced to earthing potential Vg.At this moment, the recovery current potential Vm of node N3 is that the minimum of setting forth later reclaims current potential Vs.

Interim at this first PC, as shown in figure 11, to address electrode 41 ₁Apply data pulse Pda.And, to address electrode 41 ₂Do not apply data pulse Pda.

Interim at the 2nd PC, when voltage NV1 rises, transistor Q1 ₁Disconnect transistor Q2 ₁Conducting, thus the electric charge that will reclaim capacitor C1 storage is discharged into stray capacitance Cf.Again, by making transistor Q1 ₂Conducting, transistor Q2 ₂Disconnect, the electric charge that reclaims capacitor C1 storage is discharged into stray capacitance Cf and address electrode capacitor C p ₂Here, with address electrode capacitor C p ₁With the transistor Q1 that is in conducting state ₁Connect.

Then, when voltage NV1 descends, with stray capacitance Cf and address electrode capacitor C p ₁The electric charge that stores is recovered to and reclaims capacitor C1.Here, voltage NV1 is because of stray capacitance Cf and address electrode capacitor C p ₁The electric charge that stores and be reduced to regulation current potential Vgx is not reduced to earthing potential Vg.With mentioned above identical, the recovery current potential Vm of node N3 is that the minimum of setting forth later reclaims current potential Vs.With the interim address electrode capacitor C p that is stored in of first PC ₂Electric charge by address electrode 41 ₁With transistor Q1 ₁Be discharged into ground terminal.

This PC2 is interim, as shown in figure 11, and to address electrode 41 ₂Apply data pulse Pda.And, address electrode 41 ₂On do not apply data pulse Pda.

Above according to 2

address electrodes

41 ₁, 41 ₂Change in voltage the variation of the voltage NV1 of Fig. 7 has been described, but to other address electrode 41 ₃～41 _nAlso produce and address

electrode

41 ₁, 41 ₂Identical change in voltage, thereby voltage NV1 is according to stray capacitance Cf and address electrode capacitor C p ₁～Cp _nThe electric charge that stores changes.

Like this, when PDP7 is " San Chong ?white ", each address electrode 41 ₁～41 _nAlternately repeat the running of above-mentioned PC phase, thereby whole address electrode 41 ₁～41 _nThe address electrode capacitor C p of last connection ₁～Cp _nIn the electric charge of stored number maximum not.As a result, reclaiming current potential Vm is the minimum current potential Vs that reclaims, and does not raise.The No.1 LQ of the arrow of Figure 11 illustrates the circuit loss of the 1st data driver group 4a at this moment.Consume this circuit loss too among the 2nd data driver group 4b.

Then, the plasma display system 100 of setting forth present embodiment according to Figure 12 and Figure 13 is provided with the reason that reclaims current potential clamp circuit 80.

Figure 12 and Figure 13 are the figure of running usefulness of the recovery current potential clamp circuit 80 of key diagram 6.As indicated above, the plasma display system 100 of present embodiment utilizes the 1st Power Recovery circuit 8a of Fig. 6 and the 2nd Power Recovery circuit 8b to reduce circuit loss.

For example, as indicated above when PDP7 is " complete white ", each address electrode 41 of Fig. 1 ₁～41 _n, 42 ₁～42 _nVoltage when applying data pulse Pda, raise successively (Figure 12 (a) and Figure 13 (a)).As a result, the regenerative power (the No.1 RQ of arrow) that is recovered to the electric charge that reclaims capacitor C1 based on the plate capacitor C p from Fig. 6 is along with to each address electrode 41 ₁～4 _1n, 42 ₁～42 _nApply data pulse Pda and reduce down successively.

Here, the 1st Power Recovery circuit 8a of key diagram 6 and the 2nd Power Recovery circuit 8b do not establish the situation that reclaims current potential clamp circuit 80, to make comparisons.In the case, continuously to address electrode 41 ₁～41 _n, 42 ₁～42 _nWhen applying data pulse Pda, shown in Figure 12 (b), (c), with address electrode 41 ₁～41 _n, 42 ₁～42 _nVoltage be fixed on the voltage Vda that applies on the power supply terminal V1 of Fig. 6.

The plasma display system 100 of present embodiment is to address electrode 41 ₁～41 _n, 42 ₁～42 _nWhen applying data pulse Pda, produce data pulse phase differential TR, thereby will be to address electrode 41 ₁～41 _nApply the timing t 1 of data pulse Pda with to address electrode 42 ₁～42 _nThe timing t 2 that applies data pulse Pda stagger (Figure 12 (b), (c)).

Yet, because with address electrode 41 ₁～41 _n, 42 ₁～42 _nVoltage be fixed on voltage Vda, the rising part of specified data pulse Pda can not obtain data pulse phase differential TR reliably.That is, address electrode 41 ₁～41 _n, 42 ₁～42 _nVoltage always surpass the required magnitude of voltage of address discharge with the difference that is added in the voltage that writes pulse Pw among Fig. 2 of scan electrode 121～12m.

Therefore, shown in Figure 12 (b), (c), and at 1 pair of address electrode 41 of timing t ₁～41 _nThe data pulse Pda that applies supplies with the scan electrode 12 that writes pulse Pw accordingly _kIn (k is the arbitrary integer among 1～m), address electrode 41 simultaneously circulates ₁～41 _nOn discharge cell 14 and address electrode 42 ₁～42 _nOn the discharge current of discharge cell 14.

That is to say, because specified address electrode 41 not ₁～41 _n, 42 ₁～42 _nThe rising edge of data pulse Pda, address electrode 41 ₁～41 _nOn discharge cell 14 and address electrode 42 ₁～42 _nOn discharge cell 14 identical timing with to scan electrode 12 _kApply the timing t 3 that writes pulse Pw and produce the address discharge accordingly.Thus, scan electrode 12 _kGeneration has the discharge current DA3 at 1 peak.

At this moment, scan electrode 12 _kIn the address electrode 41 that circulates simultaneously ₁～41 _nOn discharge cell 14 and address electrode 42 ₁～42 _nOn the discharge current of discharge cell 14, thereby the amplitude A M3 of discharge current DA3 becomes big (Figure 12 (e)).Thus, make the pulse Pw that writes that is added in scan electrode 12k produce big voltage drop E3 (Figure 12 (d)).As a result, as indicated above, the address discharge instability.

Like this, the 1st Power Recovery circuit 8a of Fig. 6 and the 2nd Power Recovery circuit 8b do not establish when reclaiming current potential clamp circuit 80, can not obtain data pulse phase differential TR, can not guarantee the address discharge stability.

In contrast, in the plasma display system 100 of present embodiment, recovery current potential clamp circuit 80 is set at the 1st Power Recovery circuit 8a and the 2nd Power Recovery circuit 8b of Fig. 6.

Reclaim current potential clamp circuit 80 regenerative power (the No.1 RQ of arrow) reduced to be limited to setting.Therefore, even continuously to address electrode 41 ₁～41 _n, 42 ₁～42 _nApply under the situation of data pulse Pda address electrode 41 ₁～41 _n, 42 ₁～42 _nVoltage also each data pulse Pda have rising part St, shown in Figure 13 (b), (c).

With mentioned above identical, in the plasma display system 100 of present embodiment, will be to address electrode 41 ₁～41 _nApply the timing t 1 of data pulse Pda with to address electrode 42 ₁～42 _nThe timing t 2 that applies data pulse Pda stagger (Figure 13 (b), (c)).

Because address electrode 41 ₁～41 _n, 42 ₁～42 _nVoltage each data pulse Pda is had rising part St, can obtain data pulse phase differential TR.That is, address electrode 41 ₁～41 _n, 42 ₁～42 _nVoltage be added in scan electrode 12 ₁～12 _mOn the difference of the voltage that writes pulse Pw of Fig. 2 surpass discharge required magnitude of voltage in address among each rising part St.

Therefore, shown in Figure 13 (b), (c), supply with the scan electrode 12 that writes pulse Pw _kIn (k is the arbitrary integer among 1～m), address electrode 41 ₁～41 _nOn discharge cell 14 and address electrode 42 ₁～42 _nOn the discharge current of discharge cell 14 in the timing of staggering data pulse phase differential TR, and at 1 pair of address electrode 41 of timing t ₁～41 _nThe data pulse Pda that applies circulates accordingly.

Thus, address electrode 41 ₁～41 _nOn discharge cell 14 produce address discharge, address electrode 42 in timing t 1 ₁～42 _nOn discharge cell 14 produce the addresses discharge in timing t 2.Therefore, scan electrode 12 _kGeneration has the discharge current DA4 at 2 peaks.

At this moment, scan electrode 12 _kIn, at the timing circulation address electrode 41 of the data pulse phase differential TR that staggers ₁～41 _nOn discharge cell 14 and address electrode 42 ₁～42 _nOn the discharge current of discharge cell 14, thereby the amplitude A M4 of discharge current DA4 diminish (Figure 13 (e)).Thus, make and be added in scan electrode 12 _kThe voltage drop E4 that pulse Pw produces that writes reduce (Figure 13 (d)).As a result, address discharge stability.

Like this, in the plasma display system 100 of present embodiment, recovery current potential clamp circuit 80 is set by the 1st Power Recovery circuit 8a and the 2nd Power Recovery circuit 8b at Fig. 6, can be to each address electrode 41 ₁～41 _n, 42 ₁～42 _nApply data pulse Pda with rising part St.As a result, data pulse phase differential TR can be obtained, the address discharge stability can be guaranteed.

Then, the variation of the recovery current potential Vm of the node N3 of key diagram 6.Figure 14 be illustrate write during in the oscillogram of variation of recovery current potential Vm of node N3 of Fig. 6.

Among Figure 14, the variation together with the voltage NV1 of the node N1 of Fig. 6 illustrates the variation of reclaiming current potential Vm together.In the following explanation, each pulse period Pa1, Pa2, Pa3 shown in the No.1 Pa1 of arrow, Pa2, the Pa3 comprise TA phase, TB phase, TC phase respectively in the figure.

The TA of pulse period Pa1 is interim, reclaim current potential Vm because of electric charge from reclaiming capacitor C1 and be discharged into stray capacitance Cf and plate capacitor C p reducing.Then, interim at TB, reclaim current potential Vm and keep steady state value.Then, interim at TC, the electric charge that stray capacitance Cf and plate capacitor C p are stored is recovered to and reclaims capacitor C1, thereby the value that reclaims current potential Vm raises.

This rising of reclaiming current potential Vm changes according to the quantity of electric charge from stray capacitance Cf and plate capacitor C p recovery.

The TA of pulse period Pa2 is interim, reclaim current potential Vm because of electric charge from reclaiming capacitor C1 and be discharged into stray capacitance Cf and plate capacitor C p reducing once more.Then, interim at TB, reclaim current potential Vm and keep steady state value.Then, interim at TC, the electric charge that stray capacitance Cf and plate capacitor C p are stored is recovered to once more and reclaims capacitor C1, thereby the value that reclaims current potential Vm raises.

Here, when the rising of reclaiming current potential Vm oversteps the extreme limit voltage Vr, utilize the effect of the recovery current potential clamp circuit 80 of Fig. 6, recovery current potential Vm is fixed on the limiting voltage Vr.Carry out the variation of the recovery current potential Vm among this pulse period Pa2 too at pulse period Pa3.

In each pulse period, be recovered to the electric charge that reclaims capacitor C1 in the TC phase and be less than the state consecutive hours of TA phase, reclaim current potential Vm and reduce successively in each pulse period from the electric charge of recovery capacitor C1 release.At this moment the minimum value of recovery current potential Vm is taken as the minimum current potential Vs that reclaims.The minimum value that reclaims current potential Vs is greater than 1/2nd of the supply voltage Vda of the power supply terminal V1 that is added in Fig. 6.

Figure 15 illustrates the recovery current potential Vm of Figure 14 and the gating pulse Sa of each son field ₁～Sa _nThe curve map of relation of accumulation rising number.Among Figure 15, the longitudinal axis is represented the recovery current potential Vm of each son field, and transverse axis is represented gating pulse Sa of each son field ₁～Sa _nAccumulation rising number.

Here, accumulation rising number is meant gating pulse Sa ₁～Sa _nThe rising cumulative frequency.In other words, accumulate the discharge of a plurality of discharge cells 14 among the PDP7 that the rising number is Fig. 1 and the switching times of absence of discharge.Reclaim current potential Vm with gating pulse Sa ₁～Sa _nAccumulation rising number change.

For example, PDP7 show " complete white " or “ Quan ?" time because the discharge or the absence of discharge of discharge cell 14 are continuous, do not have and switch, so gating pulse Sa ₁～Sa _nAccumulation rising number minimum.Like this, gating pulse Sa ₁～Sa _nThe few situation of accumulation rising number under, reclaim current potential Vm and converge to supply voltage Vda.Thus, make and reclaim current potential Vm rising, thereby the circuit loss of the 1st and the 2nd

data driver group

4a, 4b reduces with accumulation rising number.

In the present embodiment, utilize the effect of the recovery current potential clamp circuit 80 of Fig. 6, make recovery current potential Vm be no more than limiting voltage Vr.When recovery current potential Vm became limiting voltage Vr, as indicated above, it was the variation AC at center that voltage NV1 produces with limiting voltage Vr.

Recovery current potential clamp circuit 80 will reclaim current potential and be restricted to limiting voltage Vr, thereby can obtain the data pulse phase differential TR of Figure 12 and Figure 13 explanation.Utilize the effect of this data pulse phase differential, the peak of the discharge current of circulation in the scan electrode 12 is reduced, thereby stably carry out address electrode 41 ₁～41 _nThe discharge of each discharge cell 14 when applying data pulse Pda continuously.

When PDP7 shows " San Chong ?white ", all producing the switching of discharge between the discharge cells 14 with absence of discharge, thereby gating pulse Sa ₁～Sa _nAccumulation rising number maximum.Like this, under the accumulation rising number situation how, reclaim current potential Vm and converge to minimum recovery current potential Vs with setting.As shown in figure 15, the minimum current potential Vs that reclaims presents 1/2nd high value less than supply voltage Vda.

During the writing period P 2 and finish of each son of Fig. 3, the power non-restoring that the 1st Power Recovery circuit 8a and the 2nd Power Recovery circuit 8b reclaim is used it for during the writing of next son field.Therefore, except that writing period P 2, the recovery current potential Vm that reclaims capacitor C1 is slowly discharged.

Be loaded on the charge pump circuit of the 1st Power Recovery circuit 8a of Fig. 6 in the explanation.As indicated above, dress charge pump circuit in the 1st Power Recovery circuit 8a of Fig. 6.

Figure 16 illustrates the circuit diagram that an example is arranged on the charge pump circuit of the 1st Power Recovery circuit 8a.Among Figure 16, the charge pump circuit CG1 in the scope of the dotted line NF that is arranged on Fig. 6, the detailed composition of CG2 are shown.The control signal S1, the S3 that this charge pump circuit CG1, CG2 are used to control the grid that is added in transistor Q1, Q3.

Among Figure 16, charge pump circuit CG1 comprises diode Dp1, capacitor CCp1 and field effect transistor (hereinafter referred is FET) driver FD1.Charge pump circuit CG2 comprises diode Dp2, capacitor CCp2 and fet driver FD2.

Among Figure 16, the sub-field processor 3 of fet driver FD1 connection layout 1, power supply terminal Vp1, ground terminal, node N1 and Na and transistor Q1.Be connected diode Dp1 between power supply terminal Vp2 and the node Na, be connected capacitor CCp1 between node N1 and the node Na.

The sub-field processor 3 of fet driver FD2 connection layout 1, power supply terminal Vp3, ground terminal, node Nb and Nc and transistor Q3.Be connected diode Dp2 between power supply terminal Vp4 and the node Nc, be connected capacitor CCp2 between node Nb and the node Nc.

The running of charge pump circuit CG1 then, is described.Below explanation in, establish the grid of transistor Q1 supplied with when exceeding the voltage of about 15V than source electrode, this transistor turns.And on power supply terminal Vp1, apply the voltage of 5V, on power supply terminal Vp2, apply the voltage of 15V.

On fet driver FD1, the voltage that applies power supply terminal Vp1 is as power source voltage Vcc, and the voltage that applies node N1 is as reference voltage V Z, and the voltage that applies node Na is as voltage bias VB.And, from 3 couples of fet driver FD1 of sub-field processor supply power recovery circuit control signal Ha of Fig. 1.

Illustrate charge pump circuit CG1 Fig. 2 write beyond the period P 2 during running.At this moment, the transistor Q2 conducting of Fig. 6.Thus, N1 is connected to ground terminal with node, thereby the voltage NV1 of node N1 becomes earthing potential.Thus, the voltage of node Na is higher than the voltage NV1 of node N1, so utilize the supply voltage that is added in the 15V on the power supply terminal Vp2 that Charge Storage is arrived capacitor CCp1.As a result, node Na goes up the voltage bias VB that produces about 15V.

The running of the charge pump circuit CG1 that writes period P 2 is described.In writing period P 2, the voltage NV1 of node N1 changes as shown in Figure 7.

At this moment, to fet driver FD1 from node N1 service voltage NV1 as reference voltage V Z, also supply with simultaneously based on write beyond the period P 2 during in be stored in the voltage bias VB of about 15V of the electric charge of capacitor CCp1.

Fet driver FD1 according to Power Recovery circuit control signal Ha, rises to control signal S1 the level (high level) that exceeds voltage bias VB than reference voltage V Z during the TB of Fig. 7.As a result, the grid voltage of transistor Q1 exceeds about 15V than source voltage, makes transistor Q1 conducting.

The running of charge pump circuit CG2 then, is described.Below explanation in, establish the grid of transistor Q3 supplied with when exceeding the voltage of about 15V than source electrode, this transistor turns.And on power supply terminal Vp3, apply the voltage of 5V, on power supply terminal Vp4, apply the voltage of 15V.

On fet driver FD2, the voltage that applies power supply terminal Vp3 is as power source voltage Vcc, and the voltage that applies node Nb is as reference voltage V Z, and the voltage that applies node Nc is as voltage bias VB.And, from 3 couples of fet driver FD2 of sub-field processor supply power recovery circuit control signal Ha of Fig. 1.

Illustrate charge pump circuit CG2 Fig. 2 write beyond the period P 2 during running.At this moment, the transistor Q2 conducting of Fig. 6.Thus, N1 is connected to ground terminal with node, thereby the voltage NV1 of node N1 becomes earthing potential.Thus, the voltage of node N2 becomes earthing potential, and the current potential NVb of node Nb becomes earthing potential.The voltage of node Nc is higher than the voltage NVb of node Nb, so utilize the supply voltage that is added in the 15V on the power supply terminal Vp4 that Charge Storage is arrived capacitor CCp2.As a result, node Nc goes up the voltage bias VB that produces about 15V.

The running of the charge pump circuit CG2 that writes period P 2 is described.In writing period P 2, the voltage NVb of node Nb changes.

At this moment, to fet driver FD2 from node Nb service voltage NVb as reference voltage V Z, also supply with simultaneously based on write beyond the period P 2 during in be stored in the voltage bias VB of about 15V of the electric charge of capacitor CCp2.

Fet driver FD2 according to Power Recovery circuit control signal Ha, rises to control signal S3 the level (high level) that exceeds voltage bias VB than reference voltage V Z during the TA of Fig. 7.As a result, the grid voltage of transistor Q3 exceeds about 15V than source voltage, makes transistor Q3 conducting.

Like this, by using charge pump circuit CG1, CG2, even the change in voltage of node N1, N2 also can make transistor Q1, Q3 conducting reliably.

Determine the condition that discharge cell 14 stable dischargings of Fig. 1 are used according to the relation that writes voltage and sustaining voltage.Writing voltage and be meant voltage between the scan electrode that is added in the address electrode selected into address discharge and selection, is writing of Fig. 2 is added in Fig. 1 in the period P 2 address electrode 41 ₁～41 _n, 42 ₁～42 _nOn voltage and the scan electrode 12 of data pulse Pda of Fig. 2 ₁～12 _mOn the voltage that writes pulse Pw poor of Fig. 2.

Sustaining voltage is meant to keeping discharge to be added in voltage between each scan electrode and each maintenance electrode, is to be added in scan electrode 12 in the maintenance period P 3 of Fig. 2 ₁～12 _mOn Fig. 2 maintenance pulse Psc voltage with keep electrode 13 ₁～13 _mOn voltage difference and be added in and keep electrode 13 ₁～13 _mOn voltage and the scan electrode 12 of maintenance pulse Psu of Fig. 2 ₁～12 _mOn voltage poor.

Below the discharge cell on the PDP7 of Fig. 1 14 is reached the scope that writes voltage and sustaining voltage that discharge stability allows and be called driving margin.Illustrated as Fig. 5, when utilizing data pulse phase differential TR to reduce to write the voltage drop amount E2 of pulse Pw, the time driving margin enlarge.Illustrate that driving margin enlarges and the relation of the size of data pulse phase differential TR.

Figure 17 is the driving margin of plasma display system of key diagram 1 and the curve map that concerns usefulness of data pulse phase differential.In the curve map of Figure 17, transverse axis represents to write voltage, and the longitudinal axis is represented sustaining voltage.Driving margin shown in Figure 17 is the tolerance limit of the limiting voltage Vr with Figure 15 when setting 0.8 times of supply voltage Vda for.

Among Figure 17, to the PDP7 of Fig. 1 apply above curve L1 write voltage and sustaining voltage the time, the discharge cell selected sometimes 14 is made erroneous discharge with sustaining voltage.The scope that writes voltage and sustaining voltage that surpasses curve L1 is the scope shown in the No.1 MO1 of arrow.For example, with surpass curve L1 write voltage and sustaining voltage show “ Quan ?" during image, erroneous discharge is made in partial discharge unit 14, makes the picture quality variation.

Among Figure 17, when the PDP7 of Fig. 1 was applied the sustaining voltage that is lower than curve L2, selected sometimes discharge cell 14 discharges were insufficient.The scope that writes voltage and sustaining voltage that is lower than curve L2 is the scope shown in the No.1 MO2 of arrow.For example, when showing " complete white " image with the sustaining voltage that is lower than curve L2, the partial discharge unit does not discharge, and image produces flicker.

Determine the driving margin of the plasma display system 100 of Fig. 1 by the data pulse phase differential TR of these curves L1, L2 and Fig. 5.

Here, by curve L3 data pulse phase differential TR is shown reached each regulation sustaining voltage measurement to make the required minimum result who writes voltage of discharge cell 14 discharge stabilities in 0 o'clock.

When data pulse phase differential TR being shown being 150ns each regulation sustaining voltage measurement reached and make the required minimum result who writes voltage of discharge cell 14 discharge stabilities by curve L4.

When data pulse phase differential TR being shown being 200ns each regulation sustaining voltage measurement reached and make the required minimum result who writes voltage of discharge cell 14 discharge stabilities by curve L5.

As shown in figure 17, along with data pulse phase differential TR strengthens, reach the required minimum voltage that writes of discharge cell 14 discharge stabilities is reduced.That is,, the peak of the discharge current that circulates in the scan electrode can be reduced, thereby the required lower limit that writes voltage of discharge can be reduced by strengthening data pulse phase differential TR.Thus, make and allow that the voltage range that writes that discharge cell 14 reaches discharge stability enlarges.

According to the result of Figure 17, TR is set at 0 o'clock with the data pulse phase differential, and driving margin is the scope that curve L1, L2, L3 surround.When data pulse phase differential TR was set at 150ns, driving margin was the scope that curve L1, L2, L4 surround.When data pulse phase differential TR was set at 200ns, driving margin was the scope that curve L1, L2, L5 surround.In view of the above, distinguish that data pulse phase differential TR is big more, driving margin enlarges more.In the present embodiment, data pulse phase differential TR preferably is taken as more than or equal to about 200ns, and this point is set forth in the back.

Among Figure 17, in the scope shown in the No.1 MO3 of arrow, can not get voltage that sustaining voltage is enough write sometimes, discharge cell 14 discharges are insufficient.For example, when being lower than the writing voltage and show " complete white " image of curve L5, partial discharge unit 14 does not discharge, and image produces flicker.

In the present embodiment, the data pulse phase differential TR that preferably sets Fig. 5 is as follows.

Figure 18 is the curve map of the relation that writes voltage and phase differential when demonstration " complete white " image is shown.The longitudinal axis represents to write voltage, and transverse axis is represented data pulse phase differential TR.

Among Figure 18, solid line J1 illustrate with sustaining voltage be taken as assigned voltage value Ve (with reference to Figure 17), can obtain when limiting voltage Vr is taken as 0.8Vda (Vda is identical with the supply voltage Vda of Fig. 6) Fig. 1 discharge cell 14 discharge stabilities write the lower voltage limit value.Therefore, in the scope that adds hachure of Figure 18, can obtain discharge cell 14 discharge stabilities.

When paying close attention to the data pulse phase differential TR of transverse axis, under the situation with the phase differential that surpasses about 200ns, compare with the magnitude of voltage Vj (dotted line of Figure 18) of general use always, it is very low to write the lower voltage limit value.Therefore, in the plasma display system 100 of present embodiment, preferably data pulse phase differential TR is taken as more than or equal to about 200ns.

Figure 19 is the curve map that writes the relation of voltage and limiting voltage Vr when demonstration " complete white " image is shown.The longitudinal axis represents to write voltage, and transverse axis is represented limiting voltage Vr.

Among Figure 19, solid line J1 illustrate with sustaining voltage be taken as assigned voltage value Ve (with reference to Figure 17), can obtain when the data pulse phase differential TR of Fig. 5 is taken as 200ns Fig. 1 discharge cell 14 discharge stabilities write the lower voltage limit value.Therefore, in the scope that adds hachure of Figure 19, can obtain discharge cell 14 discharge stabilities.

When paying close attention to the limiting voltage Vr of transverse axis, limiting voltage Vr is being set under the situation that is lower than about 0.8Vda, comparing with the magnitude of voltage Vj (dotted line of Figure 18) of general use always, it is very low to write the lower voltage limit value.

Therefore, in the plasma display system 100 of present embodiment, it is good that limiting voltage Vr is taken as less than about 0.8Vda.Limiting voltage Vr setting is preferable into about 0.5Vda to 0.8Vda, and it is better that limiting voltage Vr is set at about 0.8Vda.

Like this, by setting data pulse phase difference TR and limiting voltage Vr, enlarge to obtain discharge cell 14 discharge stabilities required write the lower voltage limit value, thereby can guarantee again can reduce to write voltage again by discharge cell 14 discharge stabilities.

The power consumption of plasma display system 100 during the address of present embodiment is described.Here, the power consumption in this example is meant because of to address electrode 41 ₁～41 _n, 42 ₁～42 _nThe power that applies data pulse Pda and consume.This power consumption is equivalent to the circuit loss shown in the No.1 LQ of arrow of Fig. 9～Figure 11.

Figure 20 is the curve map of power consumption of power consumption and the plasma display system with another structure that is used for the plasma display system 100 of comparison embodiment 1.

In this example, as the comparison other of the plasma display system 100 of present embodiment, adopt the plasma display system (be called and have the reclaiming type plasma display system) that does not carry out the existing plasma display system (being called no reclaiming type plasma display system) of Power Recovery and have the Power Recovery circuit 980 of the Figure 33 that illustrates in the background technology.In the following explanation, establish except that a part, the plasma display system 100 of embodiment 1, no reclaiming type plasma display system and existing reclaiming type plasma display system have roughly the same composition.

Among Figure 20, the longitudinal axis represent the plasma display system 100 of embodiment 1, no reclaiming type plasma display system and existing reclaiming type plasma display system separately data driver group 4 and the data circuit loss of Power Recovery circuit 8 compare.It is " complete white " of data circuit loss maximum that will existing reclaiming type plasma display system is taken as the data circuit loss of plasma display system 100, no reclaiming type plasma display system and the existing reclaiming type plasma display system of embodiment 1 under 100% the situation when showing ratio that this data circuit loss compares.Transverse axis is represented the gating pulse Sa of each son field ₁～Sa _nThe rising ratio.This rising ratio is represented the gating pulse Sa of each son field ₁～Sa _nAccumulation several ratios that rise to each son maximum number of times that can rise, accumulation rising number is maximum when showing " San Chong ?white ", thereby the ratio of accumulation rising number is 100%.

According to Figure 20, if with dashed lines L2 represents that the data circuit loss of the existing reclaiming type plasma display system that the data circuit loss compares compares and be 100% (the rising ratio is 0%: " complete white " shows), then the maximal value that compares of the data circuit loss of the no reclaiming type plasma display system of representing with dot-and-dash line L1 is 200% (the rising ratio is 100%: " San Chong ?white " demonstration).On the other hand, the maximal value that the data circuit loss of the plasma display system 100 of the present embodiment of representing with thick line compares compares 2/3rds (the rising ratio is 100%: " San Chong ?white " shows) of 100% smaller or equal to the data circuit loss of existing reclaiming type plasma display system, and maximum data circuit loss is reduced significantly.

Even show etc. that in " complete white " as the problem of the data circuit loss of existing reclaiming type plasma display system when continuously address electrode being applied data pulse Pda, the plasma display system 100 of present embodiment also can reduce the data circuit loss significantly.

In the plasma display system 100 of present embodiment, produce data pulse phase differential TR by the 1st and the 2nd

data driver group

4a, 4b and the 1st and the 2nd Power Recovery circuit 8a, 8b.Thus, can guarantee discharge cell 14 discharge stabilities again, can reduce to write the voltage (driving voltage) of pulse Pw again, and enlarge driving margin.

In the present embodiment, by using 2 data driver group and 2 Power Recovery circuit, produce data pulse phase differential TR, but be not limited thereto, as long as can produce a plurality of data pulse phase differential TR, also a plurality of data driver group and Power Recovery circuit can be set further.

As indicated above, the recovery current potential Vm of the node N3 of Fig. 6 goes up the discharge of discharge cell 14 with the rising edge (data pulse rising edge) of the voltage NV1 of each node N1 or the switching times (the accumulation rising number of Figure 15) of absence of discharge changes.Particularly, accumulation rising number reclaims current potential Vm and raises after a little while.Thus, reduce circuit loss, thereby the power consumption of plasma display system 100 is fully reduced.

The plasma display system 100 of present embodiment is provided with the recovery current potential clamp circuit 80 of Fig. 6.Thus, though the rising edge (data pulse rising edge) of the voltage NV1 of each node N1 of recovery current potential Vm of the node N3 of Fig. 6 changes, be recovered current potential clamp circuit 80 and be controlled to and be not higher than limiting voltage Vr.Thus, reclaim the supply voltage Vda that current potential Vm does not rise to Fig. 6, thereby can be to address electrode 41 ₁～41 _nApply Fig. 2 data pulse Pda timing with to address electrode 42 ₁～42 _nApply and produce data pulse phase differential TR between the timing of data pulse Pda.

Its result reduces the power consumption of plasma display system 100 by the 1st and the 2nd

Power Recovery circuit

8a, 8b, can guarantee discharge cell 14 discharge stabilities of Fig. 1 simultaneously again, can reduce to write the voltage (driving voltage) of pulse Pw again, and enlarges driving margin.

In sum, in the present embodiment, the 1st and the 2nd

data driver group

4a, 4b are respectively by staggering to address electrode 41 ₁～41 _nWith address electrode 42 ₁～42 _nApply the output timing of data pulse Pda, produce data pulse phase differential TR.

Yet, as long as can obtain described data pulse phase differential TR, also can be for example by sub-field processor 3 stagger the data driver control signal DSa that supplies with the 1st data driver group 4a timing and supply with the 1st Power Recovery circuit 8a Power Recovery circuit control signal Ha timing and supply with the 2nd data driver group 4b data driver control signal DSb timing and supply with the timing of the Power Recovery circuit control signal Hb of the 1st Power Recovery circuit 8b, produce data pulse phase differential TR.

In addition,, also can delay circuit be set respectively, make address electrode 41 at the 1st and the 2nd

data driver group

4a, 4b in order to obtain data pulse phase differential TR ₁～41 _nWith address electrode 42 ₁～42 _nThe output that applies data pulse Pda is regularly different.

In order to obtain data pulse phase differential TR, also can delay circuit be set respectively at the 1st and the 2nd

Power Recovery circuit

8a, 8b, make the power-delay of supplying with the 1st and the 2nd

data driver group

4a, 4b.

The address electrode 41 that the 1st data driver group 4a connects ₁～41 _nMay not be a plurality of, also can be 1.Address electrode 42 to the 2nd data driver group 4b connection ₁～42 _nThe address electrode 42 also identical, that the 2nd data driver group 4b connects ₁～42 _nAlso may not be a plurality of, can be 1.

In the present embodiment, the address electrode 41 that the 1st data driver group 4a connects ₁～41 _nThe address electrode 42 that is connected with the 2nd data driver group 4b of number ₁～42 _nNumber identical, but be not limited thereto, be arranged on the 1st with the number of each address electrode of the 2nd

data driver group

4a, 4b can be different.

Embodiment 2

Except that following aspect, the plasma display system 100 of embodiment 2 has composition and the running identical with the plasma display system 100 of embodiment 1.

In the plasma display system 100 of embodiment 2, the recovery current potential clamp circuit 81 that is arranged on the 1st Power Recovery circuit 8a and the 2nd Power Recovery circuit 8b is different with the composition of the recovery current potential clamp circuit 80 of Fig. 6.

Figure 21 is the 1st data driver group 4a, the 1st Power Recovery circuit 8a of embodiment 2 and the circuit diagram of PDP7.Among Figure 21, reclaim current potential clamp circuit 81 and comprise resistance R 3, diode D3 and D4 and bipolar transistor (hereinafter referred is a transistor) Q5.

Reclaim in the current potential clamp circuit 81, between node N3 and node N4, be connected diode D3, the emitter of node N4 connection transistor Q5, and the collector of transistor Q5 is connected to ground terminal by resistance R 3.Power supply terminal V2 is connected to the base stage of transistor Q5.Between power supply terminal V2 and node N4, be connected diode D4.

Interim at the TA of Fig. 7 phase～TC, the recovery current potential clamp circuit 81 of the 1st Power Recovery circuit 8a carry out below shown in running.

Reclaim in the current potential clamp circuit 81, in advance power supply terminal V2 is applied the limiting voltage Vr of embodiment 1.On the other hand, node N4 is supplied with the recovery current potential Vm of node N3.Recovery current potential Vm changes according to the running of the 1st data driver group 4a that sets forth later.Here, for illustrative ease, ignore the voltage drop of diode D3.

Transistor Q5 disconnects conducting when the limiting voltage Vr of power supply terminal V2 is lower than the voltage of node N4 at the limiting voltage Vr of power supply terminal V2 during more than or equal to the voltage of node N4.That is, transistor Q5 disconnects conducting when the recovery current potential Vm of node N3 is higher than limiting voltage Vr at the recovery current potential Vm of node N3 during smaller or equal to limiting voltage Vr.

Thus, reclaim current potential Vm less than or when being lower than limiting voltage Vr transistor Q5 disconnect, preserve and reclaim the electric charge that capacitor C1 stores, it is not discharged into ground terminal.

When the recovery current potential Vm of node N3 is higher than limiting voltage Vr, transistor Q5 conducting, thereby the electric charge that recovery capacitor C1 stores is discharged into ground terminal by node N3, diode D3, node N4, transistor Q5 and resistance R 3.As a result, the recovery current potential Vm of node N3 is no more than limiting voltage Vr.

When considering the voltage drop of diode D3 in the above-mentioned explanation, the voltage that is applied to power supply terminal V2 is set for the share of hanging down the voltage drop of diode D3 than limiting voltage Vr.The voltage of diode D3 is reduced to for example 0.7V.

Like this, reclaim current potential clamp circuit 81 and when the recovery current potential Vm of node N3 oversteps the extreme limit voltage Vr, carry out the clamp running.Therefore, reclaim current potential Vm and be no more than limiting voltage Vr.

Like this, in the recovery current potential clamp circuit 81 of the 1st and the 2nd Power Recovery circuit 8a, the 8b of the plasma display system 100 of embodiment 2, power supply terminal V2 is directly applied limiting voltage Vr, thereby adjust easily the voltage that the grid to transistor Q5 applies.

Embodiment 3

Except that following aspect, the plasma display system 100 of embodiment 3 has composition and the running identical with the plasma display system 100 of embodiment 1.

In the plasma display system 100 of embodiment 3, the recovery current potential clamp circuit 82 that is arranged on the 1st Power Recovery circuit 8a and the 2nd Power Recovery circuit 8b is different with the composition of the recovery current potential clamp circuit 80 of Fig. 6.

Figure 22 is the 1st data driver group 4a, the 1st Power Recovery circuit 8a of embodiment 3 and the circuit diagram of PDP7.Among Figure 22, reclaim current potential clamp circuit 82 and comprise Zener diode D5.

Reclaim in the current potential clamp circuit 82, between node N3 and ground terminal, be connected Zener diode D5.Node N3 connects the negative electrode of Zener diode D5.On the Zener diode D5, by its negative electrode being applied voltage, the circulation inverse current above the limiting voltage Vr of embodiment 1.

Interim at the TA of Fig. 7 phase～TC, the recovery current potential clamp circuit 82 of the 1st Power Recovery circuit 8a carry out below shown in running.

Reclaim in the current potential clamp circuit 82, the negative electrode of zener diode D5 is supplied with the recovery current potential Vm of node N3.Recovery current potential Vm changes according to the running of the 1st data driver group 4a that sets forth later.As indicated above, Zener diode D5 is by applying the voltage of the voltage Vr that oversteps the extreme limit, the circulation inverse current at negative electrode.Thus, Zener diode D5 is at the recovery current potential Vm of node N3 circulating current not during smaller or equal to limiting voltage Vr, when the recovery current potential Vm of node N3 is higher than limiting voltage Vr, and the circulation inverse current.

Thus, reclaim current potential Vm less than or when being lower than limiting voltage Vr, preserve and reclaim the electric charge that capacitor C1 stores, it is not discharged into ground terminal.

When the recovery current potential Vm of node N3 is higher than limiting voltage Vr, the electric charge that reclaims capacitor C1 storage is discharged into ground terminal by Zener diode D5.As a result, the recovery current potential Vm of node N3 is no more than limiting voltage Vr.

Like this, reclaim current potential clamp circuit 82 and when the recovery current potential Vm of node N3 oversteps the extreme limit voltage Vr, carry out the clamp running.Therefore, reclaim current potential Vm and be no more than limiting voltage Vr.

In the recovery current potential clamp circuit 82 of the 1st and the 2nd Power Recovery circuit 8a, the 8b of the plasma display system 100 of embodiment 3, only utilize Zener diode D5 to carry out the control of the recovery current potential Vm of node N3.Therefore, form easily.

Embodiment 4

Except that following aspect, the plasma display system 100 of embodiment 4 has composition and the running identical with the plasma display system 100 of embodiment 1.

Figure 23 is the block diagram of basic composition that the plasma display system 100 of embodiment 4 is shown.

The plasma display system 100 of embodiment 4 also has accumulation rising number of times detecting device 20 except that the composition of the plasma display system 100 of embodiment 1.

To accumulate rising number of times detecting device 20 and connect vision signal-son corresponder 2, also connect sub-field processor 3 simultaneously.The view data SP that accumulation rising number of times detecting device 20 is supplied with according to vision signal-son corresponder 2 calculates a plurality of address electrodes 41 ₁～41 _n, 42 ₁～42 _nThe rising number of times of the data pulse Pda that applies, i.e. calculation control pulse Sa ₁～Sa _nThe rising number of times, and will represent that the count signal SL of this number of times supplies with sub-field processor 3.

Figure 24 is the block diagram of composition of the sub-field processor 3 of explanation embodiment 4.

As shown in figure 24, the sub-field processor 3 of embodiment 4 comprises rising number of times comparer 31, reclaims and switch determination section 32 and control-signals generator 33.

In the sub-field processor 3, will supply with rising number of times comparer 31 from the count signal SL of accumulation rising number of times detecting device 20.

Store gating pulse Sa in advance at sub-field processor 31 ₁～Sa _nThe maximum times that can rise in each son field.Rising number of times comparer 31 is calculated the rising ratio according to count signal SL.

And then rising number of times comparator circuit 31 is differentiated the rising ratio of calculating and whether is switched ratio β % more than or equal to power consumption, and will represent that this differentiation result's judgment signal UC supplies with recovery switching determination section 32.In the rising number of times comparer 31, also store power consumption in advance and switch ratio β %.The setting that ratio β % is switched in power consumption is set forth in the back.

Reclaim and switch the judgment signal UC that determination section 32 is supplied with according to rising number of times comparator circuit 31, produce the switching signal CT that switch-over control signal S2 uses.

Switching signal CT becomes high level when the rising ratio of for example calculating switches ratio β % more than or equal to power consumption, become low level when the rising ratio of calculating switches ratio β % less than power consumption.The switching signal CT that produces is supplied with control-signals generator 33.

Sub the view data SP that control-signals generator 33 is supplied with according to vision signal-son corresponder 2, produce data driver control signal DSa and DSb, Power Recovery circuit control signal Ha and Hb, scanner driver control signal CS and keep driver control signal US, also produce control signal S1～S4 simultaneously according to view data SP and switching signal CT.

Switch the switching signal CT generation control signal S2 that determination section 32 is supplied with according to reclaiming, and it is supplied with the transistor Q2 (Fig. 6) of the 1st and the 2nd Power Recovery circuit 8a, 8b.Whether the rising ratio that control signal S2 calculates according to rising number of times comparer 31 switches the break-make of ratio β % switching transistor Q2 more than or equal to power consumption.Thus, switch the Power Recovery mode of the plasma display system 100 of embodiment 4.Its detailed condition is set forth in the back.

In the present embodiment, also can use accumulation decline number of times detecting device, to replace the accumulation rising number of times detecting device 20 that rises.At this moment, accumulation decline number of times detecting device calculation control pulse Sa ₁～Sa _nThe decline number of times, with the expression this number of times count signal SL supply with sub-field processor 3.Then, in sub-field processor 3, carry out and identical processing mentioned above according to the received signal SL that supplies with.

Figure 25 is the sequential chart of the running during the writing of the 1st and the 2nd

Power Recovery circuit

8a, 8b of rising ratio that calculating is shown Figure 23 when switching under the situation of ratio β % according to switching signal CT power switched way of recycling more than or equal to power consumption.Among Figure 25, by the voltage NV1 of the node N1 of solid line presentation graphs 6 with supply with the waveform of control signal S1～S4 of transistor Q1～Q4 respectively.And, be illustrated by the broken lines the 2nd data driver group 4b node N1 voltage NV1 and supply with the signal waveform of control signal S1～S4 of transistor Q1～Q4 respectively.

Among Figure 25, the voltage NV1 of the 1st Power Recovery circuit 8a and the back of control signal S1～S4 picture bracket label symbol 8a, the voltage NV1 of the 2nd Power Recovery circuit 8b and the back of control signal S1～S4 picture bracket label symbol 8b.

Transistor Q1～Q4 conducting when control signal S1～S4 is high level, transistor Q1 when control signal S1～S4 is low level～Q4 disconnects.

The variation of control signal S1～S4 that the TA phase is interim with TB and the voltage NV1 of node N1 is identical with Fig. 7's of embodiment 1.

Interim at TC, control signal S4 is a high level, and control signal S 1～S3 is a low level.Thus, transistor Q4 conducting, transistor Q1～Q3 disconnects.At this moment, reclaim capacitor C1 and be connected the recovery inductance L with diode D2, utilize the LC resonance that reclaims inductance L and stray capacitance Cf and plate capacitor C p that the voltage NV1 of node N1 is slowly descended by transistor Q4.At this moment, the electric charge of stray capacitance Cf and plate capacitor C p is recovered to reclaims capacitor C1 by reclaiming inductance L, diode D2 and transistor Q4.

As indicated above, in the present embodiment,, produce the switching of Power Recovery mode by in the TD phase control signal S2 being changed according to switching signal CT.

At this moment, interim at TD, control signal S1, S3, S4 are low level, and control signal S2 is a high level.Thus, transistor Q1, Q3, Q4 disconnect, transistor Q2 conducting, thereby with node N1 ground connection.

Its result sharply reduces the interim voltage NV1 that drops to the node N1 of assigned voltage value of TC, and is fixed on earthing potential Vg.

The 1st Power Recovery circuit 8a repeats the running of TA～TD phase, thereby the electric charge of plate capacitor C p and stray capacitance C f storage is recovered to recovery capacitor C1, again the electric charge that reclaims is supplied with plate capacitor C p and stray capacitance Cf simultaneously.

At this moment, the voltage NV1 of node N1 is fixed on supply voltage Vda, in the TD phase voltage NV1 of node N1 is fixed on ground voltage Vg, thereby the value of the recovery current potential Vm of node N3 is 1/2nd (the variation AC of Figure 25) of supply voltage Vda in the TB phase.

Like this, in the plasma display system 100 of present embodiment, according to rising ratio and decreasing ratio power switched way of recycling.Carry out this and switch, with the power consumption during the address of seeking further to reduce plasma display system 100.The power consumption that back elaboration power switched way of recycling is brought reduces.

Figure 26 is recovery current potential Vm and each sub the gating pulse Sa that the plasma display system 100 of embodiment 4 is shown ₁～Sa _nThe curve map of relation of accumulation rising number.Among Figure 26, the longitudinal axis is represented the recovery current potential Vm of each son field, and transverse axis is represented gating pulse Sa of each son field ₁～Sa _nAccumulation rising number.

Among Figure 26, except that aspect described below, reclaim the gating pulse Sa of current potential Vm and each son field ₁～Sa _nRelation and the embodiment 1 of accumulation rising number in Figure 15 identical of explanation.

As mentioned above, in the plasma display system 11 of present embodiment, when the rising ratio switched ratio β % more than or equal to power consumption, the TD phase control signal S2 of Figure 25 was a high level.That is power switched way of recycling.

Gating pulse Sa of each son when here, rising ratio or decreasing ratio being become power consumption and switch ratio β % ₁～Sa _nAccumulation rising number or accumulation decline number be called way of recycling and switch number R y.

In the present embodiment, by the gating pulse Sa of each son field ₁～Sa _nAccumulation rising number or accumulation decline number form become way of recycling to switch number Ry, power switched way of recycling.As a result, as Figure 25 and shown in Figure 26, when accumulation rising number or accumulation decline number switched number Ry more than or equal to way of recycling, the value that reclaims current potential Vm was 1/2nd of supply voltage Vda.

The data circuit loss of plasma display system 100 during the address of present embodiment is described.

Figure 27 is the curve map of discharge of power consumption and the plasma display system with another structure that is used for the plasma display system 100 of comparison embodiment 4.

In this example,, adopt the plasma display system and the existing reclaiming type plasma display system of embodiment 1 as the comparison other of the plasma display system 100 of present embodiment.

Among Figure 27, identical with Figure 20, the longitudinal axis represents that the plasma display system 100 of embodiment 4, the plasma display system and the data circuit loss separately of existing reclaiming type plasma display system of embodiment 1 compare.Transverse axis is represented the gating pulse Sa of each son field ₁～Sa _nThe rising ratio.

Among Figure 27, the variation that the data circuit loss of the device that rising ratio and the decreasing ratio of the gating pulse Sa1～San of each son brought, the plasma display system of embodiment 1 and existing reclaiming type plasma display system compares is identical with Figure 20's of embodiment 1.With dashed lines L2 represents that the data circuit loss of existing reclaiming type plasma display system compares, and represents that with dot-and-dash line L3 the data circuit loss of the plasma display system of embodiment 1 compares.

The data circuit loss of representing the plasma display system 100 of present embodiment with thick line L4 compares.

Here, in the scope of the No.1 Bb of arrow of Figure 27, the data circuit loss of the plasma display system of embodiment 1 compares (dot-and-dash line L3) greater than the data circuit loss of existing reclaiming type plasma display system compare (dotted line L2).The rising ratio that the data circuit loss of switching this dot-and-dash line L3 and dotted line L2 is compared is defined as power consumption switching ratio β %.In described rising number of times comparer 31, store this power consumption in advance and switch ratio β %.

As shown in figure 27, except that the scope of the No.1 Bb of arrow, compare identical with the plasma display system of embodiment 1 of the data circuit loss of plasma display system 100.

In the scope of the No.1 Bb of arrow of Figure 27, dotted line L2 and thick line L4 are overlapping.Promptly, the decreasing ratio of switching the scope of ratio β % or each son at rising ratio of each son more than or equal to power consumption is switched the scope of ratio β % more than or equal to power consumption, and the plasma display system 100 of present embodiment is switched to the Power Recovery mode identical with existing reclaiming type plasma display system.

Its result, in the scope of the No.1 Bb of arrow, the data circuit loss that the data circuit loss that can prevent plasma display system 100 compares greater than existing reclaiming type plasma display system compares.And the plasma display system 100 of present embodiment is compared with the plasma display system of embodiment 1, and maximum data circuit loss is reduced.

Like this, the rising ratio of the plasma display system 100 of embodiment 4 in each son field switches the scope of ratio β % (accumulation rising number switches number Ry more than or equal to way of recycling) more than or equal to power consumption or the decreasing ratio of each son field is switched more than or equal to power consumption in the scope of ratio β % (accumulation decline number switches number Ry more than or equal to way of recycling), is switched the Power Recovery mode identical with existing reclaiming type plasma display system.Therefore, utilize the best power way of recycling, power consumption is fully reduced in the scope of whole rising ratio and decreasing ratio.

Here, to switch ratio β % be for example 95% for described power consumption.In the case, the plasma display system 100 of embodiment 4 rising ratio of each son more than or equal to the decreasing ratio of 95% scope or each son more than or equal to 95% scope in, be switched the Power Recovery mode identical with existing reclaiming type plasma display system.

The variation of power consumption magnitude relationship of the plasma display system 100 of no reclaiming type plasma display system, existing reclaiming type plasma display system and embodiment 1 is described according to Figure 28.

Figure 28 be rising ratio of being used for each son of comparison be 100% o'clock (San Chong ?when white) no reclaiming type plasma display system, have the figure of power consumption of the plasma display system 100 of reclaiming type plasma display system and embodiment 1.

Figure 28 (a) illustrates the address electrode 41 to no reclaiming type plasma display system ₁～41 _n, 42 ₁～42 _nThe data pulse Pda that applies, Figure 28 (b) illustrate the address electrode 41 to existing reclaiming type plasma display system ₁～41 _n, 42 ₁～42 _nThe data pulse Pda that applies, Figure 28 (c) illustrates the address electrode 41 to the plasma display system of embodiment 1 ₁～41 _n, 42 ₁～42 _nThe data pulse Pda that applies.

Shown in Figure 28 (a), the rising ratio be 100% o'clock (San Chong ?when white) to the address electrode 41 of no reclaiming type plasma display system ₁～41 _n, 42 ₁～42 _nThe data pulse Pda that applies and each pixel of PDP7 repeat to rise and descend accordingly.In the case, the power consumption of the no reclaiming type plasma display system linear voltage that is equivalent to the dotted line scope of arrow shown in No.1 changes.

Shown in Figure 28 (b), the rising ratio be 100% o'clock (San Chong ?when white) to the address electrode 41 of existing reclaiming type plasma display system ₁～41 _n, 42 ₁～42 _nThe data pulse Pda that applies is identical with no reclaiming type plasma display system, and also each pixel with PDP7 repeats to rise and descend accordingly.In the case, the power consumption of the existing reclaiming type plasma display system linear voltage that is equivalent to the dotted line scope of arrow shown in No.1 changes.

Shown in Figure 28 (c), the rising ratio be 100% o'clock (San Chong ?when white) to the address electrode 41 of the plasma display system 100 of embodiment 1 ₁～41 _n, 42 ₁～42 _nThe data pulse Pda that applies and each pixel of PDP7 repeat to rise and descend accordingly.In the case, the power consumption of the plasma display system 100 of embodiment 1 linear voltage that is equivalent to the dotted line scope of arrow shown in No.1 changes.

Above-mentioned Figure 28 (a) and (b), (c) are compared.Compare with the linear voltage intensity of variation of Figure 28 (b), (c), the linear voltage intensity of variation of Figure 28 (a) is very big.Therefore, the rising ratio be 100% o'clock (San Chong ?when white) the power consumption maximum of no reclaiming type plasma display system.

Shown in Figure 28 (c), in the plasma display system 100 of embodiment 1, the voltage of each data pulse Pda is made linear change with rising respectively when finishing when rising beginning.Therefore, when the rising of each data pulse Pda, produce power consumption when finishing with rising.

On the other hand, shown in Figure 28 (b), in the existing reclaiming type plasma display system, the voltage of each data pulse Pda is made linear change when rising end.Thus, when finishing, the rising of each data pulse Pda produces power consumption.

Therefore, the rising ratio is 100% o'clock (when three heavy ?are white), and the power consumption that produces in the plasma display system 100 of embodiment 1 is greater than the power consumption (scope of the No.1 Bb of arrow of Figure 20) that produces in the existing reclaiming type plasma display system.

In contrast, the plasma display system 100 of embodiment 4 the rising ratio be 100% o'clock (San Chong ?when white), with existing reclaiming type plasma display system power switched way of recycling in the same manner.Therefore, though the rising ratio be 100% o'clock (San Chong ?when white), compare with the power consumption of plasma display system with another structure, can prevent that also the power consumption of the plasma display system 100 of embodiment 4 from becoming big (Figure 27).

Like this, in the plasma display system 100 of embodiment 4, when rising ratio or decreasing ratio surpassed power consumption and switch ratio β %, the Power Recovery mode switched to the Power Recovery mode of existing reclaiming type plasma display system.As a result, according to the plasma display system 100 of embodiment 4, when rising ratio or decreasing ratio surpass power consumption and switch ratio β %, also can fully reduce power consumption.

That is, the plasma display system 100 of embodiment 4 is regardless of luminance, can fully reduce power consumption.

Power Recovery circuit 8a that the plasma display system 100 of embodiment 4 has and the 2nd Power Recovery circuit 8b are not limited to the structure of Fig. 6, also can have the structure of Figure 21 or Figure 22.

The rising number of times comparer 31 of Figure 24 that the plasma display system 100 of embodiment 4 has calculates the rising ratio according to the count signal SL from accumulation rising number of times detecting device 20, and whether the rising ratio that differentiation is calculated switches ratio β % more than or equal to power consumption, determination section 32 is switched in the recovery that its signal UC that differentiates the result supplies with Figure 24 with expression, but also can store way of recycling in advance and switch number Ry, and differentiate from the count signal SL that accumulates rising number of times detecting device 20 whether switch number Ry more than or equal to way of recycling, will represent that its signal UC that differentiates the result supplies with recovery and switches determination section 32.

In the above embodiment 1～4, plasma display system 100 is equivalent to display device, a plurality of address electrodes 41 ₁～41 _n, 42 ₁～42 _nBe equivalent to the 1st electrode, a plurality of scan electrodes 12 ₁～12 _mBe equivalent to the 2nd electrode, discharge cell 14 is equivalent to capacitive light emitting elements, PDP7 is equivalent to display board, and the circuit that circuit that sub-field processor the 3, the 1st data driver group 4a and the 1st Power Recovery circuit 8a constitute and the 2nd data driver group 4b and the 2nd Power Recovery circuit 8b constitute is equivalent to driving circuit.

The voltage NV1 of the node N1 of Fig. 6 is equivalent to driving pulse, and the period P 2 that writes of Fig. 2 and Fig. 3 is equivalent to during the address, and data pulse phase differential TR is equivalent to phase differential, and data pulse Pda is equivalent to data pulse.

Supply voltage Vda is equivalent to the 1st supply voltage, and power supply terminal V1 is equivalent to the 1st power supply terminal, and the node N1 of Fig. 6 is equivalent to the 1st node, and N slot field-effect transistor Q1 is equivalent to the 1st on-off element, and N slot field-effect transistor Q2 is equivalent to the 2nd on-off element.

Node N2 is equivalent to the 2nd node, reclaim inductance L and be equivalent to inductive element, node N3 is equivalent to the 3rd node, and N slot field-effect transistor Q3 is equivalent to the 3rd on-off element, N slot field-effect transistor Q4 is equivalent to the 4th on-off element, reclaims capacitor C1 and is equivalent to the recovery capacitive element.

Limiting voltage Vr is equivalent to setting, reclaims current

potential clamp circuit

80,81 and is equivalent to the current potential restricting circuits, P-channel field-effect transistor (PEFT) transistor Q1 ₁～Q1 _nBe equivalent to the 1st on-off circuit, P-channel field-effect transistor (PEFT) transistor Q2 ₁～Q2 _nBe equivalent to the 2nd on-off circuit, the voltage that applies on the voltage NV5 of the node N5 of Fig. 6 and the power supply terminal V2 of Figure 21 is equivalent to control signal, and the voltage that applies on the power supply terminal V2 is equivalent to the 2nd supply voltage, and power supply terminal V2 is equivalent to the 2nd power supply terminal.

Diode D3 and D4, bipolar transistor Q5 and resistance R 3 are equivalent to the 2nd on-off circuit, node N4 is equivalent to the 4th node, bipolar transistor Q5 is equivalent to the 5th on-off element, and diode D3 and Zener diode D5 are equivalent to unidirectional breakover element, and charge pump circuit CG1, CG2 are equivalent to the charge pump circuit.

Node Na, Nc are equivalent to the 5th node, capacitor CCp1, CCp2 are equivalent to the charging capacity cell, power supply terminal Vp2, Vp4 are equivalent to the 3rd power supply terminal, the voltage (15V) that is added in power supply terminal Vp2, Vp4 is equivalent to the 3rd supply voltage, diode Dp1, Dp2 are equivalent to unidirectional breakover element, and fet driver FD1, FD2 are equivalent to the control signal output circuit.

The 1st Power Recovery circuit 8a and the 2nd Power Recovery circuit 8b are equivalent to apply circuit, resistance R 1, R2 and node N5 are equivalent to divide circuit, accumulation rising number of times detecting device 20 is equivalent to the number of times test section, and determination section 32 is switched in sub-field processor 3, rising number of times comparer 31, recovery and control-signals generator 33 is equivalent to control part.Rising ratio and decreasing ratio are equivalent to number of times that the number of times test section calculates to can the rise ratio of number of times or the maximum number of times that can descend of data pulse maximum.View data SP is equivalent to view data, and vision signal-son corresponder 2 is equivalent to transformation component.

Claims

1, a kind of display device is characterized in that, has

Comprise the 1st electrode that is categorized into a plurality of groups,

Be arranged to the 2nd electrode of described the 1st electrode crossing,

Possess the cross part that is arranged on described the 1st electrode and described the 2nd electrode a plurality of capacitive light emitting elements display board and

Driving circuit, this driving circuit apply the data pulse of the capacitive light emitting elements illuminating that makes selection respectively to the 1st described a plurality of groups electrode, make to produce phase differential mutually among the described a plurality of group,

Described driving circuit comprises

The recovery capacitive element,

By from described recovery with capacitive element to described the 1st electrode discharge or will be recovered to described recovery capacitive element from the electric charge of described the 1st electrode, make apply driving pulse that data pulse uses be applied to described the 1st electrode apply circuit and

The current potential restricting circuits, this current potential restricting circuits is recovered to described recovery by restriction and limits with the quantity of electric charge of capacitive element, makes described recovery be no more than setting with the current potential of capacitive element.

2, a kind of display device is characterized in that, has

Comprise the 1st electrode that is categorized into a plurality of groups,

Be arranged to the 2nd electrode of described the 1st electrode crossing,

Described driving circuit comprises

Inductive element,

The recovery capacitive element,

Electric capacity by utilizing described display board and the running of the resonance of described inductive element, from described recovery with capacitive element to described the 1st electrode discharge, or will be recovered to described recovery capacitive element by described inductive element from the electric charge of described the 1st electrode, make to the 1st described a plurality of groups electrode apply driving pulse that data pulse uses be applied to described the 1st node apply circuit and

3, a kind of display device is characterized in that, has

Comprise the 1st electrode that is categorized into a plurality of groups,

Be arranged to the 2nd electrode of described the 1st electrode crossing,

Described driving circuit comprises

Accept the 1st supply voltage the 1st power supply terminal,

Inductive element,

The recovery capacitive element,

Utilize the resonance running of the electric capacity and the described inductive element of described display board, discharge electric charge from described recovery with capacitive element, the current potential of the 1st node is risen, after connecting described the 1st node and described the 1st power supply terminal, cut off being connected of described the 1st node and described the 1st power supply terminal, and utilize described resonance running by described inductive element electric charge to be recovered to described recovery capacitive element from described the 1st node, the current potential of described the 1st node is descended, thereby will apply the circuit that applies that driving pulse that data pulse uses is applied to described the 1st node the 1st described a plurality of groups electrode, and

The current potential restricting circuits, this current potential restricting circuits is recovered to described recovery by restriction and limits with the quantity of electric charge of capacity cell, makes described recovery be no more than setting with the current potential of capacitive element, and described setting is lower than described the 1st supply voltage.

4, the display device described in claim 3 is characterized in that,

Described inductive element is arranged between described the 1st node and the 2nd node, described recovery is connected to the 3rd node with capacitive element,

Described current potential restricting circuits limits by the current potential that limits described the 3rd node, makes the current potential of described capacitive element be no more than setting;

The described circuit that applies comprises

Be arranged on the 1st on-off element between described the 1st power supply terminal and described the 1st node,

Be arranged on the ground terminal of accepting earthing potential and the 2nd on-off element between described the 1st node,

Be arranged between described the 2nd node and described the 3rd node the 3rd on-off element and

Be arranged on the 4th on-off element between described the 2nd node and described the 3rd node;

During the address of the selected described capacitive light emitting elements illuminating that makes described display board, described the 3rd on-off element conducting, thereby described capacitive element discharges electric charge by described inductive element to described the 1st node, after making the current potential rising of described the 1st node, described the 3rd on-off element disconnects, described the 1st on-off element conducting, after thereby the current potential of described the 1st node rises to described the 1st supply voltage, described the 1st on-off element disconnects, described the 4th on-off element conducting, make electric charge be recovered to reclaim by described inductive element and use capacity cell from described the 1st node, and the decline of the current potential of described the 1st node, thereby described driving pulse produced.

5, the display device described in claim 3 is characterized in that,

Described driving circuit also comprises the 1st on-off circuit that should be provided with described the 1st electrode pair, and

Operate, make, between described the 1st node and described the 1st electrode, carry out the recovery and the release of electric charge, disconnect, set described the 1st electrode of correspondence for earthing potential by described the 1st on-off circuit by described the 1st on-off circuit conducting.

6, the display device described in claim 4 is characterized in that,

Described current potential restricting circuits comprises

By dividing the voltage between described the 1st supply voltage and the earthing potential, produce the current potential that is substantially equal to described setting the division circuit and

The 2nd on-off circuit, the 2nd on-off circuit are connected between described the 3rd node and the described ground terminal, and the current potential that receives described division circuit generation simultaneously is as control signal, and conducting when the current potential of described the 3rd node surpasses described setting.

7, the display device described in claim 4 is characterized in that,

Described current potential restricting circuits comprises

Acceptance be substantially equal to described setting the 2nd supply voltage the 2nd power supply terminal and

The 2nd on-off circuit, the 2nd on-off circuit are connected between described the 3rd node and the described ground terminal, and the 2nd supply voltage that receives described the 2nd power supply terminal acceptance simultaneously is as control signal, and conducting when the current potential of described the 3rd node surpasses described setting.

8, the display device described in claim 6 is characterized in that,

Described the 2nd on-off circuit comprises

Be arranged between described the 3rd node and the 4th node, and make electric current from described the 3rd node flow to described the 4th node unidirectional breakover element and

Be arranged between described the 4th node and the described ground terminal, and have the 5th on-off element of the control terminal that receives described control signal.

9, the display device described in claim 4 is characterized in that,

Described current potential restricting circuits comprises

Be arranged between described the 3rd node and the described ground terminal, and when the current potential of described the 3rd node surpasses setting, make electric current flow to the unidirectional breakover element of described ground terminal from described the 3rd node.

10, the display device described in claim 9 is characterized in that,

Described unidirectional breakover element is a Zener diode.

11, the display device described in claim 4 is characterized in that,

Also have generation than the high current potential of the current potential of described the 1st node so that make the charge pump circuit of described the 1st on-off element conducting.

12, the display device described in claim 11 is characterized in that,

Described charge pump circuit comprises

Be arranged between described the 1st node and described the 5th node charging with capacity cell,

Be arranged between the 3rd power supply terminal and described the 5th node of accepting the 3rd supply voltage, make electric current from described the 2nd power supply terminal flow to described the 5th node unidirectional breakover element and

The current potential of described the 5th node is added on described the 1st node potential, and gained current potential after the addition is outputed to the control signal output circuit of described the 1st on-off element as control signal.

13, the display device described in claim 3 is characterized in that,

Described setting is greater than 1/2nd of described the 1st supply voltage, and smaller or equal to 4/5ths of described the 1st supply voltage.

14, the display device described in claim 3 is characterized in that,

Described phase differential is more than or equal to 200ns.

15, the display device described in claim 3 is characterized in that,

Have a plurality of described driving circuits,

Described a plurality of driving circuits are arranged to correspond respectively to described a plurality of group,

A plurality of described driving circuits apply the data pulse that makes selected capacitive light emitting elements illuminating to described a plurality of groups described the 1st electrode respectively, make to produce phase differential mutually among the described a plurality of group.

16, the display device described in claim 3 is characterized in that,

Also have the rising number of times that detects the data pulse be applied to described the 1st electrode or the number of times test section of decline number of times,

Described driving circuit also comprises control part, this control part calculates the detected described number of times of described number of times test section to can the rise ratio of number of times or the maximum number of times that can descend of data pulse maximum, and control the described running that applies circuit, make at described ratio during greater than the requirement ratio value, after the current potential of described the 1st node is reduced to the assigned voltage value, with described the 1st node ground connection.

17, the display device described in claim 16 is characterized in that,

Also have the transformation component that 1 view data is transformed into the view data of each son, so that be divided into a plurality of sons with 1, and each son field makes selected described capacitive light emitting elements discharge, shows thereby carry out gray scale;

The view data that described number of times test section is supplied with according to described transformation component detects each described number of times of sub;

Described control part calculates the detected described number of times of described number of times test section to can the rise ratio of number of times or the maximum number of times that can descend of data pulse maximum of each son, and control the described running that applies circuit, make at described ratio during greater than the requirement ratio value, after the current potential of described the 1st node is reduced to the assigned voltage value, with described the 1st node ground connection.

18, the display device described in claim 16 is characterized in that,

The rate value of described regulation is more than or equal to 95%.

19, a kind of display-apparatus driving method, this display device comprises and has the 1st electrode that is categorized into a plurality of groups, is arranged to and the 2nd electrode of described the 1st electrode crossing and the display board that possesses a plurality of capacitive light emitting elements of the cross part that is arranged on described the 1st electrode and described the 2nd electrode, it is characterized in that

Comprise the data pulse that respectively the 1st described a plurality of groups electrode is applied the capacitive light emitting elements illuminating that makes selection, make the step that produces phase differential among the described a plurality of group mutually,

The described step that applies data pulse comprises

Utilize the resonance running of the electric capacity and the inductive element of described display board, discharge electric charge from reclaiming with capacitive element, the current potential of the 1st node is risen, after connecting described the 1st node and the 1st power supply terminal, cut off being connected of described the 1st node and described the 1st power supply terminal, and utilize described resonance running by described inductive element electric charge to be recovered to described recovery capacitive element from described the 1st node, the current potential of described the 1st node is descended, thereby will apply the step that driving pulse that data pulse uses is applied to described the 1st node the 1st described a plurality of groups electrode, and

Be recovered to described recovery by restriction and limit, make described recovery be no more than the step of setting with the current potential of capacitive element with the quantity of electric charge of capacity cell,

Described setting is lower than the 1st supply voltage that is applied to described the 1st power supply terminal.

20, the display-apparatus driving method described in claim 19 is characterized in that, also has

Detection be applied to the rising number of times of data pulse of described the 1st electrode or decline number of times step and

Calculate detected described number of times to can the rise ratio of number of times or the maximum number of times that can descend of data pulse maximum, and control the described running that applies circuit, make at described ratio during greater than the requirement ratio value, after the current potential of described the 1st node is reduced to the assigned voltage value, with the step of described the 1st node ground connection.

21, the display-apparatus driving method described in claim 20 is characterized in that,

Described requirement ratio value is more than or equal to 95%.

22, the display-apparatus driving method described in claim 19 is characterized in that,