CN1820292A - Display device and drive method thereof - Google Patents

Abstract

The first data driver group is connected to the subfield processor, the first power recovery circuit and the PDP. The second data driver group is connected to the subfield processor, the second power recovery circuit, and the PDP. The first and second data driver groups apply data pulses with mutually different phases to the PDP. The first and second power recovery circuits use LC resonance to generate voltages for generating data pulses in the first and second data driver groups, and perform charge discharge to and recovery from the PDP. The recovery potentials of the recovery capacitors of the first and second power recovery circuits vary with the number of switching times between discharge and non-discharge of the PDP discharge unit.

Description

Display device and driving method thereof

technical field

The present invention relates to a display device that selectively discharges a plurality of discharge cells to display images and a driving method thereof.

Background technique

In the field of display devices for displaying images, a plasma display device using a plasma display panel (hereinafter abbreviated as PDP) has the advantage of being thinner and larger. Such a plasma display device displays an image by utilizing light emission when a discharge cell constituting a pixel is discharged.

Plasma display devices are roughly classified into an AC type and a DC type according to a driving form.

Fig. 29 is a block diagram showing the basic composition of a conventional AC type plasma display device.

The plasma display device 900 of FIG. 29 has an analog-to-digital converter (hereinafter referred to as an analog-to-digital converter) 910, a video signal-subfield correspondent 920, a subfield processor 930, a data driver 940, a scan driver 950, a hold drive 960 and PDP970.

The analog-to-digital converter 910 is supplied with an analog video signal VD. The analog-to-digital converter 910 converts the video signal VD into digital image data, and supplies the digital image data to the video signal-subfield correspondent 920 . The video signal-subfield mapper 920 generates image data SP of each subfield from the image data of one field and supplies it to the subfield processor 930 so that one field is divided into a plurality of subfields for display.

The subfield processor 930 generates the data driver driving control signal DS, the scanning driver driving control signal CS and the sustaining driver driving control signal US from the image data SP of each subfield, and supplies them to the data driver 940, the scanning driver 950 and the sustaining driver respectively. 960.

PDP 970 includes a plurality of address electrodes (data electrodes) 911 , a plurality of scan electrodes 912 , and a plurality of sustain electrodes 913 . A plurality of address electrodes 911 are arranged in the vertical direction of the screen, and a plurality of scan electrodes 912 and a plurality of sustain electrodes 913 are arranged in the horizontal direction of the screen. Furthermore, a plurality of sustaining electrodes 913 are commonly connected together.

Power generation cells 914 are formed at intersections of address electrodes 911 , scan electrodes 912 , and sustain electrodes 913 , and each power generation cell 914 constitutes a pixel on the screen.

Data driver 940 is connected to a plurality of address electrodes 911 of PDP 970 . The scanning driver 950 has a driving circuit provided on each scanning electrode 912 inside, and each driving circuit is connected to a corresponding scanning electrode 912 of the PDP 970 . Sustain driver 960 is connected to a plurality of sustain electrodes 913 of PDP 970 .

The data driver 940 applies a data pulse to the corresponding address electrode 911 of the PDP 970 according to the data driver control signal DS in accordance with the image data SP during the writing period. Scan driver 950 sequentially applies a write pulse to a plurality of scan electrodes 912 of PDP 70 while shifting a shift pulse in the vertical scan direction in the write period according to scan driver control signal CS. Accordingly, address discharge is performed in the corresponding discharge cell 914 .

Scan driver 950 applies a periodic sustain pulse to scan electrodes 912 of PDP 970 in a sustain period according to scan driver control signal CS. On the other hand, sustain driver 960 applies sustain pulses shifted by 180 degrees from the sustain pulses to scan electrodes 912 to plural sustain electrodes 913 of PDP 70 during the sustain period according to sustain driver drive control signal US. Accordingly, sustain discharge is performed in the corresponding discharge cell 914 .

FIG. 30 is a timing chart showing an example of drive voltages for address electrodes, scan electrodes, and sustain electrodes in the PDP 7 of FIG. 29 .

In the initialization period, an initial setting pulse Pset is applied to a plurality of scan electrodes 912 at the same time. Then, in the address period, a data pulse Pda that is turned on or off according to a video signal is applied to each address electrode 911 , and an address pulse Pw is applied to a plurality of scan electrodes 912 in synchronization with the data pulse Pda. Accordingly, address discharges are sequentially generated in the selected discharge cells 914 of the PDP 970 .

Next, in the sustain period, the sustain pulse Psc is periodically applied to the plurality of scan electrodes 912 , and the sustain pulse Psu is periodically applied to the plurality of sustain electrodes. The phase of the sustain pulse Psu is shifted by 180 degrees from the sustain pulse Psc. Accordingly, sustain discharge occurs subsequent to the address discharge.

In such a plasma display device, the number of discharge cells 14 has significantly increased (increased number of pixels) due to the increase in screen size and high definition in recent years. As the number of discharge cells 14 increases, the peak current of the address discharge current flowing through one scan electrode 912 may increase during address discharge. When the peak current of the address discharge current increases, the write pulse Pw applied to the scan electrode 912 generates a large voltage drop. As a result, the address discharge becomes unstable. Therefore, it is necessary to set high voltage SH2 of address pulse Pw to be applied to scan electrode 912 in order to perform stable address discharge.

In view of this, as a method of reducing the peak current of the address discharge current, the plasma display device driving method shown in FIG. 29 is proposed. That is, the data driver 940 is divided into a plurality, and a phase difference is given to the data pulse Pda applied to the address electrode between the plurality of data drivers (for example, refer to Japanese Patent Laid-Open No. Hei 8-305319).

A method of driving such a plasma display device will be described.

FIG. 31 is a schematic view showing an example of a display state of a PDP 970 of a plasma display device composed of a plurality of data drivers. Fig. 32 is a diagram for explaining the dependence of the address discharge current on the data pulse phase difference. The data pulse phase difference is explained below.

In FIG. 31, the first and second data drivers 940a and 940b are connected to the subfield processor 930 in FIG. 29 . PDP 970 has the same composition as PDP 970 of FIG. 29 except including a plurality of address electrodes 911a, 911b.

Referring to FIG. 32 , the shift TR between the timing at which the first data driver 940a applies the data pulse Pda of FIG. 30 to the address electrode 911a and the timing at which the second data driver 940b applies the data pulse Pda of FIG. 30 to the address electrode 911b will be described.

In the following description, the timing at which each of the first and second data drivers 940a and 940b apply the data pulse Pda to the address electrodes 911a and 911b is referred to as a data pulse application timing. The offset TR between the timing of applying the data pulse to the address electrode 911 a and the timing of applying the data pulse to the address electrode 911 b is referred to as a data pulse phase difference TR.

In FIG. 31 , among discharge cells 914 on PDP 970 , all discharge cells 914 on scan electrode 912f in the first row from above emit light.

Assume a case where discharge cells 914 on scan electrodes 912f in the first row from above are made to emit light. As shown in FIG. 32(a), when there is no data pulse phase difference TR, the discharge cell 914 on the address electrode 911a and the discharge cell 914 on the address electrode 911b generate an address discharge at the same timing t1. Accordingly, scan electrode 912f generates discharge current DA2 having one peak.

At this time, the discharge current of the discharge cell 914 on the address electrode 911a and the discharge cell 914 on the address electrode 911b simultaneously flow through the scan electrode 912f, so the amplitude AM2 of the discharge current DA2 increases. Thus, a large voltage drop E2 occurs in the address pulse Pw applied to the scan electrode 912f. As a result, the address discharge becomes unstable as described above.

Conversely, as shown in FIG. 32(b), when there is a data pulse phase difference, the discharge cell 914 on the address electrode 911a generates an address discharge at timing t1, and the discharge cell 914 on the address electrode 911b generates an address discharge at timing t2. Accordingly, scan electrode 912f generates discharge current DA1 having two peaks.

At this time, the discharge current on the address electrode 911a and the discharge current on the address electrode 911b flow at different timings t1 and t2 in the scan electrode 912f, so the amplitude AM1 of the discharge current DA1 becomes smaller as the phase difference TR of the data pulse becomes larger. . Therefore, the voltage drop E1 generated by the write pulse Pw applied to the scan electrode 912f also becomes smaller as the data pulse phase difference TR increases. Therefore, even when the voltage of address pulse Pw to be applied to scan electrode 912f is set low, stable discharge can be ensured. In other words, by setting the data pulse phase difference TR large, it is possible to ensure stable discharge of the discharge cells 914 and reduce the voltage (drive voltage) of the write pulse Pw.

However, in plasma display device 900 of FIG. 29 , plural discharge cells 914 of PDP 970 function as capacitors. Hereinafter, the capacitance of the plurality of discharge cells 914 of the PDP 970 is referred to as a panel capacitance.

The circuit loss (power loss) of the data driver 940 when the data pulse Pda is applied to each address electrode 911 is proportional to the product of the plate capacitance and the square of the driving voltage applied to the address electrode 911 during the above-mentioned writing period. This relationship is expressed in a formula as follows.

P∝Cp×Vp ² …(1)

In the above formula (1), P is the circuit loss, Cp is the plate capacitance, and Vp is the driving voltage. At this time, the drive voltage Vp is the voltage of the data pulse Pda.

Therefore, the overall power consumption of plasma display device 900 during the writing period increases with the increase in size of PDP 970 (increase in panel capacitance) and increase in driving voltage. Therefore, in order to reduce the power consumption of the plasma display device 900 (reduce circuit loss), a power recovery circuit has been developed.

Fig. 33 is a circuit diagram showing an example of a conventional power recovery circuit. In FIG. 33, the power recovery circuit 980 is connected to the data driver integrated circuit built in the data driver 940 of FIG. 29. Referring to FIG. The data driver IC is in turn connected to a plurality of address electrodes 911 of the PDP970.

In FIG. 33, the capacitances of the plurality of discharge cells 914 formed by the address electrodes 911 are represented as address electrode capacitances Cp1 to Cpn, and the sum of these capacitances is represented as the plate capacitance Cp.

The power recovery circuit 980 includes a recovery capacitor C1, a recovery inductor L, N-channel field effect transistors (hereinafter simply referred to as transistors) Q1-Q4, and diodes D1 and D2.

The recovery capacitor C1 is connected between the node N3 and the ground terminal. The transistor Q4 and the diode D2 are connected in series between the node N3 and the node N2, and the diode D1 and the transistor Q3 are further connected in series between the node N2 and the node N3.

The recovery inductance L is connected between the node N2 and the node N1. The transistor Q1 is connected between the node N1 and the power supply terminal V1, and the transistor Q2 is connected between the node N1 and the ground terminal.

A power supply voltage Vda is supplied to the power supply terminal V1. Control signals S1 to S4 are supplied to gates of transistors Q1 to Q4, respectively. Transistors Q1 - Q4 are switched on and off according to control signals S1 - S4 .

FIG. 34 is a timing diagram illustrating the operation of the power recovery circuit 980 of FIG. 33 during programming. FIG. 34 shows the voltage NV1 at the node N1 in FIG. 33 and the waveforms of the control signals S1 to S4 applied to the respective transistors Q1 to Q4. When the control signals S1-S4 are at high level (H), Q1-Q4 are turned on, and when the control signals S1-S4 are at low level (L), Q1-Q4 are turned off.

During the TA period, the control signal S3 is at a high level, and the control signals S1 , S2 , and S4 are at a low level. Accordingly, the transistor Q3 is turned on, and the transistors Q1, Q2, and Q4 are turned off. In this case, the recovery capacitor C1 is connected to the recovery inductance L through the transistor Q3 and the diode D1, and the voltage NV1 of the node N1 is slowly increased by utilizing the LC resonance of the recovery inductance L and the plate capacitance Cp. At this time, the charge of the recovery capacitor C1 is discharged to the plate capacitance Cp through the transistor Q3, the diode D1 and the recovery inductance L.

During the TB period, the control signal S1 is at a high level, and the control signals S2-S4 are at a low level. Accordingly, the transistor Q1 is turned on, and the transistors Q2 to Q4 are turned off. At this time, the voltage NV1 of the node N1 rises sharply and then becomes fixed at the power supply voltage Vda.

During the TC period, the control signal S4 is at a high level, and the control signals S1-S3 are at a low level. Accordingly, the transistor Q4 is turned on, and the transistors Q1 to Q3 are turned off. In this case, the recovery capacitor C1 is connected to the recovery inductance L through the diode D2 and the transistor Q4, and the voltage NV1 of the node N1 is gradually decreased by utilizing the LC resonance of the recovery inductance L and the plate capacitance Cp. At this time, the charge stored in the plate capacitor Cp is stored in the recovery capacitor C1 through the recovery inductor L, the diode D2 and the transistor Q4. Thereby, power is recovered.

During the TD period, the control signal S2 is at a high level, and the control signals S1 , S3 , and S4 are at a low level. As a result, the transistor Q2 is turned on, and the transistors Q1, Q3, and Q4 are turned off. At this time, the node N1 is connected to the ground terminal, and the voltage NV1 of the node N1 is rapidly lowered, and then fixed at the ground potential.

In this way, by using the power recovery circuit 980, the charge stored in the plate capacitor Cp is recovered to the recovery capacitor C1, and at the same time, the recovered charge is supplied to the plate capacitor Cp. Hereinafter, the power based on the charge recovered from the plate capacitance Cp to the recovery capacitance C1 is referred to as recovered power.

Thereby, the above-mentioned circuit loss can be reduced. The overall power consumption of the plasma display device 900 can be reduced. In FIG. 34 , the voltage change indicated by the arrow RQ corresponds to recovered power, and the voltage change indicated by the arrow LQ corresponds to the circuit loss.

However, according to the power recovery circuit 980 described above, sufficient power recovery cannot necessarily be performed. The reason for this will be described with reference to FIGS. 35 and 36 .

FIG. 35 is a schematic diagram showing an example of the display state of the PDP 7, and FIG. 36 is a waveform diagram of data pulses applied to the address electrodes to obtain the display state of FIG. 35. Referring to FIG. FIG. 35 shows only a part of the PDP 970 of FIG. 29 .

FIG. 35( a ) shows an example in which four pixels (discharge cells) provided on each address electrode 911 display "black", "white", "black", and "black" sequentially from top to bottom. That is, in this example, only the pixels (discharge cells) in the second row above the PDP 970 perform address discharge.

When the power recovery circuit 980 of FIG. 33 is not used, the data pulse Pda is generated by the power supply from the power supply. FIG. 36(a) shows an example of the waveform of the data pulse Pda at this time. In FIG. 36( a ), a voltage change indicated by an arrow LQ corresponds to a circuit loss.

With the power recovery circuit 980, the data pulse Pda is generated by power supply and power recovery from the above-mentioned plate capacitance Cp. FIG. 36(b) shows an example of the waveform of the data pulse Pda at this time. In FIG. 36( b ), the voltage change indicated by the arrow RQ corresponds to recovered power.

According to FIG. 36(a) and FIG. 36(b), by using the power recovery circuit 980, the circuit loss of the data driver 940 when generating the data pulse Pda can be reduced by using the recovered power from the plate capacitance Cp.

On the other hand, FIG. 35(b) shows an example in which four pixels provided on each address electrode 911 display "white", "white", "white", "white" sequentially from top to bottom. That is, in this example, all the pixels of the PDP970 perform address discharge. At this time, a plurality of data pulses Pda are continuously applied to each address electrode 911 .

Here, a case is assumed in which the power recovery circuit 980 is not used, and successive data pulses are applied to the address electrodes 911 as one collective data pulse SPda.

Fig. 36(c) shows an example of the waveforms of the data pulses Pda, SPda. In FIG. 36(c), arrow LQ corresponds to circuit loss. In this case, a circuit loss of the data driver 940 occurs when the data pulse SPda rises, and no circuit loss of the data driver 940 occurs between each data pulse Pda.

Next, assume a case where the power recovery circuit 980 is used and a continuous data pulse Pda is applied to each address electrode 911 . FIG. 36(d) shows an example of the waveform of the continuous data pulse Pda in this case. In FIG. 36( d ), the voltage change indicated by the arrow LQ corresponds to circuit loss, and the voltage change indicated by the arrow RQ corresponds to recovered power. When the power recovery circuit 980 is used, successive data pulses Pda are generated by the power recovery of the plate capacitance Cp and the power supply. Thus, each rising edge of each data pulse Pda generates a circuit loss of the data driver 940 .

The waveforms of the data pulse Pda shown in FIG. 36(c) and FIG. 36(d) are compared. In Fig. 36(c), a large circuit loss occurs when the data pulse SPda rises. In Fig. 36(d), a small circuit loss occurs once for each data pulse Pda. Accordingly, when the number of continuously generated data pulses Pda further increases, even if power recovery by the power recovery circuit 980 is performed, the circuit loss cannot be sufficiently reduced. In this way, the conventional power recovery circuit 980 may not sufficiently reduce circuit loss.

In the driving method disclosed in Japanese Patent Publication No. 2002-156941, when all the pixels in the PDP970 shown in FIG. amplitude, thereby reducing circuit losses. However, further stabilization of address discharge and reduction of power consumption are required.

Contents of the invention

An object of the present invention is to provide a display device capable of sufficiently reducing power consumption and performing stable discharge and a driving method thereof.

A display device according to an aspect of the present invention includes a first electrode classified into a plurality of groups, a second electrode provided to intersect the first electrode, and a plurality of capacitors provided at the intersection of the first electrode and the second electrode. A display panel of a capacitive light-emitting element, and a driving circuit, the driving circuit respectively applies a data pulse for making a selected capacitive light-emitting element emit light to the first electrodes of a plurality of groups, so that a phase difference is generated between the plurality of groups, and the driving circuit The circuit includes a capacitive element for recovery, and a driving pulse for applying a data pulse is applied to the first electrode by discharging the first electrode from the capacitive element for recovery or recovering electric charges from the first electrode to the capacitive element for recovery. An application circuit, and a potential limiting circuit that limits the amount of charge recovered to the recovery capacitive element so that the potential of the recovery capacitive element does not exceed a predetermined value.

In this display device, the first electrodes of the display panel are classified into a plurality of groups. In the address period for making the selected capacitive light-emitting element of the display panel emit light, the drive circuit applies a data pulse for making the selected capacitive light-emitting element emit light to the first electrodes of the plurality of groups.

In the application circuit, electric charge is discharged from the recovery capacitive element to the first electrode or recovered from the first electrode to the recovery capacitive element during the address period, thereby reducing power consumption when driving pulses are generated.

The applying circuit is operated so that the voltage generated by the capacitive element for recycling changes with the switching times of the plurality of capacitive light-emitting elements in the display panel to emit light and not emit light within a specified time. At this time, the potential of the recovery capacitive element is limited by the potential limiting circuit so that the potential of the recovery capacitive element does not exceed a predetermined value lower than the first power supply voltage, thereby dividing the waveforms of the continuous driving pulses.

Accordingly, the data pulses can be applied from the drive circuit to the first electrodes of the plurality of groups so that the phase differences between the plurality of groups can be generated. In this case, the light emission timings of the capacitive light emitting elements provided on the first electrodes of the plurality of groups are different for each of the plurality of groups. Utilizing this point, the light emission current flowing through the second electrode is divided into a plurality of peaks, and the peaks are reduced. As a result, the voltage drop caused by the light emitting current in the driving voltage applied between the first electrode and the second electrode is reduced. Therefore, the capacitive light-emitting element can stably emit light with a low driving voltage.

Based on the above results, the power consumption can be reduced without compromising the driving tolerance of the display panel.

Here, the driving tolerance refers to the range of the driving voltage that is allowed to achieve stable light emission of the capacitive light-emitting element.

A display device according to another aspect of the present invention includes first electrodes classified into a plurality of groups, second electrodes provided to intersect the first electrodes, and an electrode provided at intersections of the first electrodes and the second electrodes. A display panel of a plurality of capacitive light-emitting elements, and a driving circuit, the driving circuit respectively applies data pulses for making selected capacitive light-emitting elements emit light to the first electrodes of the plurality of groups, so that each of the plurality of groups A phase difference is generated, and the driving circuit includes an inductive element and a capacitive element for recovery. By using the resonance operation of the capacitance of the display panel and the inductive element, the first electrode is discharged from the capacitive element for recovery, or the energy from the first electrode is discharged. Charges are recovered by the inductive element to the capacitive element for recovery, and a drive pulse for applying a data pulse to the first electrodes of the plurality of groups is applied to the first node application circuit and the potential limiting circuit. The potential limiting circuit limits the amount of charge recovered to the recovery capacitive element so that the potential of the recovery capacitive element does not exceed a predetermined value.

In this display device, the first electrodes of the display panel are classified into a plurality of groups. In the address period for making the selected capacitive light-emitting element of the display panel emit light, the drive circuit applies a data pulse for making the selected capacitive light-emitting element emit light to the first electrodes of the plurality of groups.

In the application circuit, electric charge is discharged from the recovery capacitive element to the first electrode or recovered from the first electrode to the recovery capacitive element during the address period, thereby reducing power consumption when driving pulses are generated.

The application circuit operates to make the voltage generated by the capacitive element for recycling change with the switching times of the plurality of capacitive light-emitting elements in the display panel to emit light and not emit light within a specified time. At this time, the potential of the recovery capacitive element is limited by the potential limiting circuit so that the potential of the recovery capacitive element does not exceed a predetermined value lower than the first power supply voltage, thereby dividing the waveforms of the continuous driving pulses.

Accordingly, the data pulses can be applied from the drive circuit to the first electrodes of the plurality of groups so that the phase differences between the plurality of groups can be generated. In this case, the light emission timings of the capacitive light emitting elements provided on the first electrodes of the plurality of groups are different for each of the plurality of groups. Utilizing this point, the light emission current flowing through the second electrode is divided into a plurality of peaks, and the peaks are reduced. As a result, the voltage drop caused by the light emitting current in the driving voltage applied between the first electrode and the second electrode is reduced. Therefore, the capacitive light-emitting element can stably emit light with a low driving voltage.

Based on the above results, the power consumption can be reduced without compromising the driving tolerance of the display panel.

Here, the driving tolerance refers to the range of the driving voltage that is allowed to achieve stable light emission of the capacitive light-emitting element.

A display device according to still another aspect of the present invention includes first electrodes classified into a plurality of groups, second electrodes arranged to intersect the first electrodes, and a plurality of electrodes arranged at intersections of the first electrodes and the second electrodes. a display panel of a capacitive light-emitting element, and a driving circuit that applies data pulses for making selected capacitive light-emitting elements emit light to the first electrodes of a plurality of groups, so that phase differences are generated among the plurality of groups, The drive circuit includes a first power supply terminal receiving a first power supply voltage, an inductive element, and a recovery capacitive element. Using the resonance operation of the capacitance of the display panel and the inductive element, the electric charge is released from the recovery capacitive element to make the first node After the potential of the first node and the first power supply terminal are connected, the connection between the first node and the first power supply terminal is cut off, and the charge is recovered from the first node through the inductive element to the capacitive element for recovery by resonant operation, The potential of the first node is lowered to apply a driving pulse for applying data pulses to the first electrodes of the plurality of groups to the application circuit of the first node and the potential limiting circuit, and the potential limiting circuit controls recovery to recovery. The charge amount of the capacitive element is limited so that the potential of the recovery capacitive element does not exceed a predetermined value lower than the first power supply voltage.

In this display device, the first electrodes of the display panel are classified into a plurality of groups. In the address period for making the selected capacitive light-emitting element of the display panel emit light, the drive circuit applies a data pulse for making the selected capacitive light-emitting element emit light to the first electrodes of the plurality of groups.

In the application circuit, electric charges are released from the recovery capacitive element by utilizing the resonance between the capacitance of the display panel and the inductive element during the address period, and the potential of the first node is raised. And, by connecting the first node and the first power supply terminal, the potential of the first node is raised to the first power supply voltage. Then, the connection between the first node and the first power supply terminal is disconnected, and the electric charge is recovered from the first node to the recovery capacitive element through the inductive element by resonant operation, and the potential of the first node is lowered. Accordingly, a driving pulse for applying a data pulse to the first electrodes of a plurality of groups is applied to the first node.

In this way, the charge is released from the recovery capacitive element to the first node by using the resonance operation of the capacitance of the display panel and the inductance element, and the resonance operation of the capacitance of the display panel and the inductance element is also used. Charges are recovered from the first node to the recovery capacitive element, thereby reducing power consumption when generating drive pulses.

The application circuit operates to make the voltage generated by the capacitive element for recycling change with the switching times of the plurality of capacitive light-emitting elements in the display panel to emit light and not emit light within a specified time. At this time, the potential of the recovery capacitive element is limited by the potential limiting circuit so that the potential of the recovery capacitive element does not exceed a predetermined value lower than the first power supply voltage, thereby dividing the waveforms of the continuous driving pulses.

Accordingly, the data pulses can be applied from the drive circuit to the first electrodes of the plurality of groups so that the phase differences between the plurality of groups can be generated. In this case, the light emission timings of the capacitive light emitting elements provided on the first electrodes of the plurality of groups are different for each of the plurality of groups. Utilizing this point, the light emission current flowing through the second electrode is divided into a plurality of peaks, and the peaks are reduced. As a result, the voltage drop caused by the light emitting current in the driving voltage applied between the first electrode and the second electrode is reduced. Therefore, the capacitive light-emitting element can stably emit light with a low driving voltage.

Based on the above results, the power consumption can be reduced without compromising the driving tolerance of the display panel.

Here, the driving tolerance refers to the range of the driving voltage that is allowed to achieve stable light emission of the capacitive light-emitting element.

The inductive element can be set between the first node and the second node, and the capacitive element for recovery can be connected to the third node. The potential limiting circuit limits the potential of the third node so that the potential of the capacitive element does not exceed Specified value; the application circuit includes a first switching element provided between the first power supply terminal and the first node, a second switching element provided between the ground terminal receiving the ground potential and the first node, and a second switching element provided between the second node and the first node. The 3rd switching element between the 3rd node, and the 4th switching element that is arranged between the 2nd node and the 3rd node; The element is turned on, so that the capacitive element releases charge to the first node through the inductive element, and after the potential of the first node rises, the third switching element is turned off, and the first switching element is turned on, so that the potential of the first node After rising to the first power supply voltage, the first switching element is turned off, and the fourth switching element is turned on, so that the charge is recovered from the first node to the recovery capacitive element through the inductive element, and the potential of the first node drops, thereby generating the the drive pulse.

At this time, in the application circuit, the third switching element is turned on during the address period, and the capacitance of the display panel and the inductive element perform a resonant operation, and charges are discharged from the recovery capacitive element to the first node through the inductive element. Also, when the third switching element is turned off and the first switching element is turned on, the potential of the first node rises to the first power supply voltage. Then, when the first switching element is turned off and the fourth switching element is turned on, the resonance operation between the capacitor and the inductive element of the display panel is performed, and charges are recovered from the first node through the inductive element to the recovery capacitive element. As a result, drive pulses are generated.

In this way, in the application circuit, by switching the on-off of the first switch element, the third switch element, and the fourth switch element, the resonance operation of the capacitance and the inductance element of the display panel can be performed, so that it can be conveniently controlled by switching each switch. Generation of drive pulses.

In addition, the electric potential of the third node connected to the recovery capacitive element is limited by the electric potential limiting circuit so that the electric potential does not exceed a predetermined value lower than the first power supply voltage. Thereby, successive drive pulse waveforms are separated.

The driving circuit can also include a first switch circuit arranged corresponding to the first electrode, and it can be operated. The first switch circuit is turned on, and the charge is recovered and released between the first node and the first electrode. The switch circuit is turned off, and the corresponding first electrode is set to the ground potential.

In this way, by switching the on and off of the first switching elements respectively, the light emitting and non-light emitting of the plurality of capacitive light emitting elements in the display panel can be controlled.

The smaller the total number of on-off switching of the first switch circuits, the higher the voltage generated by the recovery capacitive element. At the same time, the potential limit circuit is used to limit the voltage generated by the recovery capacitive element not to exceed the specified value.

The potential limiting circuit may include a division circuit for generating a potential approximately equal to a predetermined value by dividing the voltage between the first power supply voltage and the ground potential, and a second switch circuit connected between the third node and the ground potential. Meanwhile, it receives the potential generated by the dividing circuit as a control signal, and turns on when the potential of the third node exceeds a specified value.

At this time, the dividing circuit divides the voltage between the first power supply voltage and the ground potential so as to generate a potential substantially equal to a predetermined value. Furthermore, the second switch circuit connected between the third node and the ground terminal receives the potential generated by the division circuit as a control signal, and turns on when the potential of the third node exceeds a predetermined value, so that the current flows from the third node to the ground terminal. . Accordingly, the potential at the third node does not exceed a predetermined value, and the potential generated at one end of the recovery capacitive element does not exceed a predetermined value.

The potential limiting circuit can be made to include a second power supply terminal receiving a second power supply voltage approximately equal to a predetermined value, and a second switch circuit connected between the third node and the ground potential while receiving the second power supply terminal The received second power supply voltage is used as a control signal, and is turned on when the potential of the third node exceeds a predetermined value.

At this time, a second power supply voltage substantially equal to a predetermined value is supplied to the second power supply terminal. Furthermore, the second switch circuit connected between the third node and the ground terminal receives the second power supply voltage as a control signal, turns on when the potential of the third node exceeds a predetermined value, and causes a current to flow from the third node to the ground terminal. Accordingly, the potential of the third node does not exceed a predetermined value, and the voltage generated at one end of the recovery capacitive element does not exceed a predetermined value.

The second switch circuit may include a unidirectional conduction element provided between the third node and the fourth node to allow current to flow from the third node to the fourth node, and a unidirectional conduction element provided between the fourth node and the ground terminal. Between, and has the 5th switching element of the control terminal that receives control signal.

At this time, when the potential of the third node exceeds a predetermined value, the fifth switch is turned on, and a current flows from the third node to the ground terminal through the unidirectional conduction element and the fifth switching element. Accordingly, the potential of the third node does not exceed a predetermined value, and the voltage generated at one end of the recovery capacitive element does not exceed a predetermined value.

The potential limiting circuit may include a unidirectional conduction element provided between the third node and the ground terminal, and allowing a current to flow from the third node to the ground terminal when the potential of the third node exceeds a predetermined value.

At this time, the unidirectional conduction element provided between the third node and the ground terminal causes a current to flow from the third node to the ground terminal when the potential of the third node exceeds a predetermined value. Accordingly, the potential of the third node does not exceed a predetermined value, and the voltage generated at one end of the recovery capacitive element does not exceed a predetermined value. Moreover, it is easy to compose.

The unidirectional conduction element may be a Zener diode. Thus, composition is facilitated.

It may further include a charge excitation circuit that generates a potential higher than the potential of the first node to turn on the first switching element. At this time, a potential higher than the potential of the first node is generated by the charge excitation circuit, and the first switching element is turned on.

The charging excitation circuit can include a charging capacitive element arranged between the first node and the fifth node, arranged between the third power supply terminal receiving the third power supply voltage and the fifth node, and the current flows from the second power supply terminal A unidirectional conduction element to the fifth node, and a control signal output circuit that adds the potential of the fifth node to the potential of the first node and outputs the added potential as a control signal to the first switching element.

At this time, the unidirectional conduction element makes the current flow from the second power supply terminal to the fifth node, and the control signal output circuit adds the potential of the fifth node to the potential of the first node, and uses the added potential as a control The signal is output to the first switching element.

The specified value can be greater than one-half of the first power supply voltage and less than or equal to four-fifths of the first power supply voltage. Thus, stable light emission of the capacitive light-emitting element can be ensured. Furthermore, a sufficient driving margin can be obtained.

The phase difference can be greater than or equal to 200ns. Thus, stable light emission of the capacitive light-emitting element can be ensured. Furthermore, a sufficient driving margin can be obtained.

There may be a plurality of driving circuits, and the plurality of driving circuits are arranged to respectively correspond to the plurality of groups, and the plurality of driving circuits respectively apply data pulses for making the selected capacitive light-emitting elements emit light to the first electrodes of the plurality of groups, The plurality of groups are caused to have phase differences with each other.

At this time, the data pulses for making the selected capacitive light-emitting elements emit light are respectively applied to the first ones of the plurality of groups by the plurality of drive circuits respectively provided corresponding to the plurality of groups in accordance with the requirement of mutually generating phase differences in the plurality of groups. electrode. As a result, the light emission timings of the capacitive light emitting elements provided on the first electrodes of the plurality of groups are different for each of the plurality of groups, so that the light emission current flowing through the second electrodes is divided into a plurality of peaks, and the peaks are reduced. Small. As a result, the voltage drop caused by the light emitting current in the driving voltage applied between the first electrode and the second electrode is reduced. Therefore, the light emitting element can stably emit light with a low driving voltage.

A count detection circuit for detecting the rise count or fall count of the data pulse applied to the first electrode may also be included, and the drive circuit may also include a function for calculating the maximum rise count or the minimum fall count count of the data pulse detected by the count detection unit. A control unit that controls the operation of the applying circuit so that the potential of the first node is lowered to a prescribed voltage value when the ratio is greater than a prescribed ratio value, and then grounds the first node.

At this time, the number of rises or falls of the data pulses applied to the first electrodes classified into a plurality of groups is detected by the number detection unit. Then, the control unit calculates the ratio of the number of times detected by the number detection unit to the maximum possible number of rising times or the minimum possible number of falling times of data pulses, and compares the calculated ratio with a predetermined ratio value.

Furthermore, the operation of the application circuit is controlled such that when the calculated ratio is greater than a predetermined ratio value, the potential of the first node is lowered to a predetermined voltage value, and then the first node is grounded.

Here, the power consumption in the application circuit varies with the ratio of the number of times detected by the number detection unit to the maximum or minimum possible number of rises of the data pulse. That is, when the calculated ratio is greater than the predetermined ratio value, by grounding the first node, power consumption can always be reduced in an optimal state regardless of the light emitting states of the plurality of capacitive light emitting elements in the display panel.

A conversion unit for converting image data of one field into image data of each subfield may be provided so that one field is divided into a plurality of subfields, and the selected capacitive light-emitting element is discharged for each field, thereby performing grayscale display; The number detection part detects the number of times of each subfield according to the image data supplied by the conversion part; the control part calculates the ratio of the number of times detected by the number detection part to the maximum number of times that can be raised or the number of times that can be lowered by the data pulse of each subfield, and controls the application circuit The operation makes it ground the first node after the potential of the first node is lowered to the prescribed voltage value when the ratio is greater than the prescribed ratio value.

At this time, the image data of one field is converted into image data of each subfield by the conversion unit. In this way, one field can be divided into a plurality of subfields, and the selected capacitive light-emitting element can be discharged for each field to perform grayscale display.

In each of the plurality of subfields, the number of rises or falls of the data pulses applied to the first electrodes classified into a plurality of groups is detected by the number detection unit. Then, the control unit calculates the ratio of the number of times detected by the number detection unit to the maximum possible number of rising times or the minimum possible number of falling times of data pulses, and compares the calculated ratio with a predetermined ratio value.

Furthermore, the operation of the application circuit is controlled such that when the calculated ratio is greater than a predetermined ratio value, the potential of the first node is lowered to a predetermined voltage value, and then the first node is grounded. Therefore, regardless of the light-emitting state of the plurality of capacitive light-emitting elements in the display panel, the power consumption can always be reduced under the optimal state.

The specified ratio value can be made greater than or equal to 95%. Therefore, the power consumption can be always reduced under the optimal state regardless of the light-emitting state of the plurality of capacitive light-emitting elements in the display panel.

According to another aspect of the present invention, a display device driving method, the display device includes a first electrode classified into a plurality of groups, a second electrode provided to intersect the first electrode, and an electrode provided between the first electrode and the second electrode. In a display panel with a plurality of capacitive light-emitting elements at the intersection, the method applies data pulses for making the selected capacitive light-emitting elements emit light to the first electrodes of the plurality of groups, so that phase differences among the plurality of groups are mutually generated. The step of applying the data pulse includes: using the resonance operation of the capacitance of the display panel and the inductive element to discharge the charge from the recovery capacitive element, so that the potential of the first node is increased, and the first node is connected to the first power supply terminal. Afterwards, cut off the connection between the first node and the first power supply terminal, and use the resonant operation to recover the charge from the first node through the inductive element to the recovery capacitive element, so that the potential of the first node is lowered, so that multiple groups The step of applying a driving pulse for the data pulse to the first electrode of the first node, and limiting the amount of charge recovered to the recovery capacitive element so that the potential of the recovery capacitive element does not exceed the first power supply voltage The steps of the specified value.

In this display device driving method, a data pulse for making the selected capacitive light emitting element emit light is applied to the plurality of groups of first electrodes during an address period for making the selected capacitive light emitting element emit light.

When a data pulse is applied to the first electrodes of a plurality of groups in this way, charges are discharged from the recovery capacitive element by utilizing the resonance between the capacitance of the display panel and the inductive element during the address period, and the potential of the first node rises. And, by connecting the first node and the first power supply terminal, the potential of the first node is raised to the first power supply voltage. Then, the connection between the first node and the first power supply terminal is disconnected, and the electric charge is recovered from the first node to the recovery capacitive element through the inductive element by resonant operation, and the potential of the first node is lowered. Accordingly, a driving pulse for applying a data pulse to the first electrodes of a plurality of groups is applied to the first node.

In this way, the charge is released from the recovery capacitive element to the first node by using the resonance operation of the capacitance of the display panel and the inductance element, and the resonance operation of the capacitance of the display panel and the inductance element is also used. Charges are recovered from the first node to the recovery capacitive element, thereby reducing power consumption when generating drive pulses.

It is also operated to make the voltage generated by the capacitive element for recycling change with the switching times of multiple capacitive light-emitting elements in the display panel to emit light and non-light within a specified time, and limit it so that the potential of the capacitive element for recycling does not exceed the low At the specified value of the first power supply voltage, the waveforms of successive drive pulses are thus separated.

By applying data pulses to the first electrodes of the plurality of groups so that phase differences are generated in the plurality of groups, the timing of light emission of the capacitive light-emitting elements provided on the first electrodes of the plurality of groups is adjusted for each of the plurality of groups. all different. Utilizing this point, the light emission current flowing through the second electrode is divided into a plurality of peaks, and the peaks are reduced. As a result, the voltage drop caused by the light emitting current in the driving voltage applied between the first electrode and the second electrode is reduced. Therefore, the capacitive light-emitting element can stably emit light with a low driving voltage.

Based on the above results, the power consumption can be reduced without compromising the driving tolerance of the display panel.

Here, the driving tolerance refers to the range of the driving voltage that is allowed to achieve stable light emission of the capacitive light-emitting element.

There may also be a step of detecting the number of rises or falls of the data pulse applied to the first electrode, and calculating the ratio of the detected number of times to the maximum number of rises or the minimum number of falls of the data pulse and controlling the operation of the application circuit so that A step of lowering the potential of the first node to a predetermined voltage value and then grounding the first node when the ratio is greater than a predetermined ratio value.

At this time, the number of rises or falls of the data pulses applied to the first electrodes classified into a plurality of groups is detected. Then, the ratio of the number of times detected by the number detection unit to the maximum possible number of rising times or the minimum possible number of falling times of data pulses is calculated, and the calculated ratio is compared with a predetermined ratio value.

Furthermore, the operation of the application circuit is controlled such that when the calculated ratio is greater than a predetermined ratio value, the potential of the first node is lowered to a predetermined voltage value, and then the first node is grounded.

Here, the power consumption in the display device varies according to the ratio of the number of times detected by the number detection unit to the maximum number of rises or the minimum number of rises possible for the data pulse. That is, when the calculated ratio is greater than the predetermined ratio value, by grounding the first node, power consumption can always be reduced in an optimal state regardless of the light emitting states of the plurality of capacitive light emitting elements in the display panel.

It is possible to make the specified ratio value greater than or equal to 95%. Therefore, the power consumption can be always reduced under the optimal state regardless of the light-emitting state of the plurality of capacitive light-emitting elements in the display panel.

The specified value can be greater than one-half of the first power supply voltage and less than or equal to four-fifths of the first power supply voltage. Thus, stable light emission of the capacitive light-emitting element can be ensured. Furthermore, a sufficient driving margin can be obtained.

Description of drawings

FIG. 1 is a block diagram showing the basic configuration of a plasma display device according to Embodiment 1. As shown in FIG.

FIG. 2 is a timing chart showing an example of driving voltages supplied to address electrodes, scan electrodes, and sustain electrodes in FIG. 1 .

FIG. 3 is an explanatory diagram for explaining an ADS method used in the plasma display device of FIG. 1 .

FIG. 4 is a schematic diagram showing an example of a display state of the PDP shown in FIG. 1 .

Fig. 5 is a diagram for explaining the dependence of address discharge current on the phase difference of data pulses.

FIG. 6 is a circuit diagram of a first data driver group, a first power recovery circuit, and a PDP in FIG. 1 .

FIG. 7 is a timing chart showing the operation of the first and second power recovery circuits of FIG. 1 during writing.

Fig. 8 is a schematic diagram showing an example of a PDP display state.

9 is a timing chart showing the voltage of node N1 in FIG. 6, data pulses applied to address electrodes, and control pulses supplied to the first data driver group when the display state shown in FIG. 8 is obtained.

10 is a timing chart showing the voltage of node N1 in FIG. 6, data pulses applied to address electrodes, and control pulses supplied to the first data driver group when the display state shown in FIG. 8 is obtained.

11 is a timing chart showing the voltage at node N1 in FIG. 6, data pulses applied to address electrodes, and control pulses supplied to the first data driver group when the display state shown in FIG. 8 is obtained.

FIG. 12 is a diagram for explaining the operation of the recovery potential clamping circuit of FIG. 6 .

FIG. 13 is a diagram for explaining the operation of the recovered potential clamp circuit of FIG. 6 .

FIG. 14 is a waveform diagram showing changes in the recovery potential of the node N3 in FIG. 6 during the writing period.

FIG. 15 is a graph showing the relationship between the recovery potential of FIG. 14 and the cumulative rise number of control pulses per subfield.

FIG. 16 is a circuit diagram showing an example of a charge excitation circuit provided in the first power recovery circuit in FIG. 6 .

FIG. 17 is a graph for explaining the relationship between the driving margin and the data pulse phase difference of the plasma display device shown in FIG. 1. FIG.

FIG. 18 is a graph showing the relationship between the writing voltage and the phase difference when displaying a "full white" image.

FIG. 19 is a graph showing the relationship between the writing voltage and the limit voltage when displaying a "full white" image.

20 is a graph for comparing the power consumption of the plasma display device according to Embodiment 1 with the power consumption of a plasma display device having another configuration.

21 is a circuit diagram of a first data driver group, a first power recovery circuit, and a PDP according to Embodiment 2. FIG.

22 is a circuit diagram of a first data driver group, a first power recovery circuit, and a PDP according to Embodiment 3. FIG.

FIG. 23 is a block diagram showing the basic configuration of a plasma display device according to Embodiment 4. FIG.

FIG. 24 is a block diagram illustrating the configuration of a subfield processor in Embodiment 4. FIG.

FIG. 25 is a timing diagram showing the operation of the first and second power recovery circuits in FIG. 23 during writing when the power recovery mode is switched by the control signal.

26 is a graph showing the relationship between the recovery potential and the cumulative rising number of control pulses per subfield in the plasma display device according to Embodiment 4. FIG.

27 is a graph for comparing the power consumption of the plasma display device according to Embodiment 4 with the power consumption of a plasma display device having another configuration.

28 is a diagram for comparing the power consumption of the non-recovery type plasma display device, the conventional recovery type plasma display device, and the plasma display device of Embodiment 1 when the rising ratio of each subfield is 100% (in triple black and white). .

Fig. 29 is a block diagram showing the basic composition of a conventional AC type plasma display device.

FIG. 30 is a timing chart showing an example of driving voltages of address electrodes, scan electrodes, and sustain electrodes of the PDP shown in FIG. 29 .

FIG. 31 is a schematic diagram showing an example of a PDP display state of a plasma display device composed of a plurality of divided data drivers.

Fig. 32 is a diagram for explaining the dependence of the address discharge current on the data pulse phase difference.

33 is a circuit diagram showing an example of a conventional power recovery circuit.

FIG. 34 is a timing diagram illustrating the operation of the power recovery circuit of FIG. 33 during writing.

Fig. 35 is a schematic diagram showing an example of a display state of a PDP.

FIG. 36 is a waveform diagram of data pulses applied to address electrodes to obtain the display state of FIG. 35. FIG.

Detailed ways

Next, as an example of the display device and its driving method of the present invention, a plasma display device and its driving method will be described with reference to FIGS. 1 to 28 .

Embodiment 1

FIG. 1 is a block diagram showing a basic configuration of a plasma display device according to Embodiment 1. As shown in FIG.

The plasma display device 100 of Fig. 1 has an analog-to-digital converter (hereinafter referred to as an analog-to-digital converter) 1, a video signal-subfield corresponding device 2, a subfield processor 3, a first data driver group 4a, a second Data driver group 4b, scan driver 5, sustain driver 6, plasma display panel (hereinafter abbreviated as PDP) 7, first power recovery circuit 8a, and second power recovery circuit 8b.

An analog video signal VD is supplied to the analog-to-digital converter 1 . The analog-to-digital converter 1 converts the video signal VD into digital image data, and supplies it to the video signal-subfield correspondent 2 .

The video signal-subfield mapper 2 generates image data SP of each subfield from the image data of one field, and supplies it to the subfield processor 3 to divide one field into a plurality of subfields for display. In the plasma display device 100 of this embodiment, an address and display period separation method (abbreviated as an ADS method for phase) is employed as a gray scale display driving method. The details of the ADS method will be described later.

The subfield processor 3 generates data driver control signals DSa and DSb, power recovery circuit control signals Ha and Hb, scan driver control signal CS, and sustain driver control signal US from the image data SP of the subfield.

The data driver control signals DSa and DSb are supplied to the first data driver group 4a and the second data driver group 4b, respectively. Power recovery circuit control signals Ha, Hb are supplied to the first power recovery circuit 8a and the second power recovery circuit 8b, respectively. The scan driver control signal CS is supplied to the scan driver 5 , and the sustain driver control signal US is supplied to the sustain driver 6 .

Each of the first data driver group 4a and the second data driver group 4b is composed of a plurality of data driver integrated circuits and a plurality of modules not shown. The first data driver group 4a is connected to the subfield processor 3, the first power recovery circuit 8a, and the PDP 7, and the second data driver group 4b is connected to the subfield processor 3, the second power recovery circuit 8b, and the PDP7. Furthermore, a scan driver 5 and a sustain driver 6 are respectively connected to the PDP 7 .

PDP 7 includes a plurality of address electrodes (data electrodes) 41 ₁ to 41 _n and 42 ₁ to 42 _n , a plurality of scan electrodes 12 ₁ to 12 _m , and a plurality of sustain electrodes 13 ₁ to 13 _m . m and n are each an arbitrary integer. A plurality of address electrodes 41 ₁ to 41 _n and 42 ₁ to 42 _n are arranged in the vertical direction of the screen, and a plurality of scan electrodes 12 ₁ to 12 _m and a plurality of sustain electrodes 13 ₁ to 13 _m are arranged in the horizontal direction of the screen. The plurality of sustaining electrodes 13 ₁ to 13 _m are commonly connected together. In FIG. 1, the address electrodes 41 ₁ to 41 _n are arranged on the left side of the screen, and the address electrodes 42 ₁ to 42 _n are arranged on the right side of the screen.

Discharge cells 14 are formed at intersections of address electrodes 41 ₁ to 41 _n and 42 ₁ to 42 _n , scan electrodes 12 ₁ to 12 _m , and sustain electrodes 13 ₁ to 13 _m . Each discharge cell 14 constitutes a pixel on the screen. In FIG. 1, the discharge cells 14 on the screen are arranged in "m rows and 2n columns".

The plurality of address electrodes 41 ₁ to 41 _n are connected to the first data driver group 4a, and the plurality of address electrodes 42 ₁ to 42 _n are connected to the second data driver group 4b. The plurality of scan electrodes 12 ₁ to 12 _m are connected to the scan driver 5 , and the plurality of sustain electrodes 13 ₁ to 13 _m are connected to the sustain driver 6 .

Here, the scan driver 5 internally has a drive circuit provided for each of the scan electrodes 12 ₁ to 12 _m , and each drive circuit is connected to the corresponding scan electrodes 12 ₁ to 12 _m of the PDP 7 .

The first data driver group 4a applies data pulses to corresponding address electrodes 41 ₁ to 41 _n in the PDP 7 in accordance with the data driver control signal DSa in the writing period according to the image data SP. The output of the first power recovery circuit 8a is supplied to the power supply terminals of the plurality of data driver ICs of the first data driver group 4a to generate the data pulses. The first power recovery circuit 8a operates according to the power recovery circuit control signal Ha. The detailed operation of the first data driver group 4a and the first power recovery circuit 8a during the writing period will be described later.

The second data driver group 4b applies a data pulse to any one of the corresponding address electrodes 42 ₁ to 42 _n in the PDP 7 in accordance with the data driver control signal DSb in accordance with the image data SP in the writing period. The output of the second power recovery circuit 8b is supplied to the power supply terminals of the plurality of data driver ICs of the second data driver group 4b to generate the data pulses. The second power recovery circuit 8b operates according to the power recovery circuit control signal Hb. The detailed operations of the second data driver group 4b and the second power recovery circuit 8b during the writing period are the same as the detailed operations of the first data driver group 4a and the first power recovery circuit 8a described later.

Scan driver 5 simultaneously applies an initial setting pulse to all scan electrodes 12 ₁ to 12 _m in PDP 7 in the initialization period according to scan driver control signal CS. Then, in the address period, an address pulse is sequentially applied to the plurality of scan electrodes 12 ₁ to 12 _m while shifting the shift pulse in the vertical scanning direction. Thus, address discharge is performed in the selected discharge cell 14 .

Scan driver 5 applies a periodic sustain pulse to scan electrodes 12 ₁ to 12 _m of PDP 7 in a sustain period according to scan driver control signal CS. On the other hand, sustain driver 6 simultaneously applies a sustain pulse phase shifted by 180 degrees to sustain electrodes 13 ₁ to 13 _m of PDP 7 in accordance with sustain driver control signal US to sustain electrodes 13 ₁ to 13 _m of PDP 7 . Thus, sustain discharge is performed in discharge cells 14 that have undergone address discharge.

FIG. 2 is a timing chart showing an example of driving voltages supplied to address electrodes, scan electrodes, and sustain electrodes in FIG. 1 .

In FIG. 2 , an initial setting pulse Pset is simultaneously applied to a plurality of scanning electrodes 12 ₁ to 12 _m in the initialization period. Then, in the writing period, a data pulse Pda that is turned on or off according to a video signal is applied to address electrodes 41 ₁ to 41 _n 42 ₁ to 42 _n , and a plurality of scan electrodes are sequentially switched in synchronization with the data pulse Pda. 12 ₁ to 12 _m Apply the write pulse Pw. Accordingly, address discharges are sequentially generated in the selected discharge cells 14 of the PDP1.

In this embodiment, as shown in FIG. 2 , the timing at which the first data driver group 4a applies the data pulse Pda to the address electrodes 41 ₁ to 41 _n and the timing at which the second data driver group 4b applies the data pulse to the address electrodes 42 ₁ to 42 _n occur. The offset TR between the timings of Pda. Details of the offset TR will be described later.

Next, in the sustain period P3, the sustain pulse Psc is periodically applied to the plurality of scan electrodes 12 ₁ to 12 _m , and the sustain pulse Psu is periodically applied to the plurality of sustain electrodes 13 ₁ to 13 _m . The phase of the sustain pulse Psu is shifted by 180 degrees from the phase of the sustain pulse Psc. Accordingly, sustain discharge occurs subsequent to the address discharge.

As described above, in the plasma display device 100 of this embodiment, the ADS method is used as the grayscale display driving method. Here, the ADS method will be described. FIG. 3 is an explanatory diagram for explaining the ADS method used in the plasma display device 100 of FIG. 1 .

In the ADS method, one field (1/60 second=16.67 ms) is temporally divided into a plurality of subfields. For example, when displaying 256 gray scales with 8 bits, one field is divided into eight subfields SF1 to SF8. In addition, the subfields SF1 to SF8 are divided into an initializing period P1, a writing period P2, and a holding period P3. In the subfields SF1-SF8, as in the example of FIG. 2, each subfield is set in the initialization period P1, the address discharge for selecting the discharge cell 14 to be lit is performed in the write period P2, and the address discharge is performed in the hold period P3. A sustain discharge for display is performed.

In the sustain period P3 of the subfields SF1 to SF8 , the luminance (brightness) is weighted respectively. During the sustain period of each of the subfields SF1 to SF8 , the number of sustain pulses satisfying the weighted luminance is applied to the scan electrodes 12 ₁ to 12 _m and the sustain electrodes 13 ₁ to 13 _m . For example, in subfield SF1, a sustain pulse is applied to sustain electrodes 13 ₁ to 13 _m once, a sustain pulse is applied to scan electrodes 12 ₁ to 12 _m once, and the discharge cell 14 selected in address period P2 is subjected to two write cycles. Keep discharging. In subfield SF2, sustain pulses are applied to sustain electrodes 13 ₁ to 13 _m twice, sustain pulses are applied to scan electrodes 12 ₁ to 12 _m twice, and discharge cells 14 selected in write period P2 are sustained four times. discharge.

In this way, the luminance weighting of 1, 2, 4, 8, 16, 32, 64 and 128 is respectively completed in the subfields SF1～SF8, and these subfields SF1～SF8 are combined, so that the luminance can be adjusted in 256 levels from 0 to 255. size. The number of divisions and weighting values of the subfields are not limited to the above-mentioned examples, and various changes can be made. For example, in order to reduce the simulated contour of the moving image, the subfield SF8 can be divided into two, and the weighting values of the two subfields can be set for 64.

Next, the shift TR between the timing of applying the data pulse Pda to the address electrodes 41 ₁ to 41 _n in FIG. 2 and the timing of applying the data pulse Pda to the address electrodes 42 ₁ to 42 _n will be described.

In the following description, the _timing of applying the data pulse _Pda to the address electrodes 41 ₁ to 41 _n and 42 ₁ to 42 _n is called the data pulse application timing. The shift TR in the timing of applying the data pulse Pda to the electrodes 42 ₁ to 42 _n is called a data pulse phase difference TR.

FIG. 4 is a schematic diagram showing an example of the display state of PDP 7 in FIG. 1, and FIG. 5 is a diagram for explaining the dependence of address discharge current on the phase difference of data pulses.

In FIG. 4, among the discharge cells 14 on the PDP 7, all the discharge cells 14 on the scan electrode ₁₂₁ emit light.

Here, a case where there is no data pulse phase difference when realizing the display state shown in FIG. 4 will be described. As shown in FIG. 5( a ), when there is no data pulse phase difference, discharge cells 14 on address electrodes 411 to 41 n and discharge cells 14 on address electrodes 42 ₁ to 42 _n generate address discharge at the same timing t1. Accordingly, scan electrode ₁₂₁ generates discharge current DA2 having one peak.

At this time, in scan electrode 12 ₁ , discharge current flows through discharge cells 14 on address electrodes 41 ₁ to 41 _n and discharge cells 14 on address electrodes 42 ₁ to 42 _n at the same time, and amplitude AM2 of discharge current DA2 increases. As a result, a large voltage drop E2 occurs in the write pulse Pw applied to the scan electrode ₁₂₁ . As a result, the address discharge becomes unstable. Therefore, it is necessary to set high voltage SH2 of address pulse Pw to be applied to scan electrode ₁₂₁ in order to perform stable address discharge.

Next, the case where there is a data pulse phase difference TR when realizing the display state of the PDP 7 shown in FIG. 4 will be described. As shown in FIG. 5(b), when there is a data pulse phase difference TR, the discharge cells 14 on the address electrodes 41 ₁ to 41 _n generate an address discharge at timing t1, and the discharge cells 14 on the address electrodes 42 ₁ to 42 _n generate an address discharge at timing t1. Address discharge occurs at t2. Accordingly, discharge current DA1 having two peaks is generated in scan electrode ₁₂₁ .

At this time, in the scan electrodes ₁₂₁ , since the discharge cells 14 on the address electrodes ₄₁₁ to _41n and the discharge cells 14 on the address electrodes ₄₂₁ to _42n flow discharge currents at different timings, the amplitude AM1 of the discharge current DA1 varies with As the data pulse phase difference TR increases and becomes smaller. Accordingly, the voltage drop E1 generated by the write pulse Pw applied to the scan electrode ₁₂₁ also becomes smaller as the data pulse phase difference TR increases. Therefore, even if the voltage SH1 of the address pulse Pw to be applied to the scan electrode ₁₂₁ is set low, all can be stably discharged. In other words, by setting the data pulse phase difference TR large, the stable discharge of the discharge cells 14 can be ensured, the voltage of the write pulse Pw (driving voltage) can be reduced, and the driving margin described later can be increased.

Thus, in the plasma display device 100 of this embodiment, when the data pulse Pda is applied to the address electrodes 41 ₁ to 41 _n and 42 ₁ to 42 _n by the first data driver group 4 a and the second data driver group 4 b, a data pulse is generated. Phase difference TR. As a result, the stable discharge of the discharge cells 14 can be ensured, the voltage of the write pulse Pw (driving voltage) can be reduced, and the driving margin described later can be increased.

The detailed configuration and operation of the data driver group 4a, the first power recovery circuit 8a, and the PDP 7 in FIG. 1 during the writing period will be described with reference to FIGS. 6 to 16. FIG.

FIG. 6 is a circuit diagram of the first data driver group 4a, the first power recovery circuit 8a, and the PDP 7 in FIG. 1. Referring to FIG. As described above, the first power recovery circuit 8a is connected to the plurality of address electrodes 41 ₁ to 41 _n of the PDP 7 through the first data driver group 4a. In FIG. 6 , the capacitances of the plurality of discharge cells 14 provided on the address electrodes 41 ₁ to 41 _n in the PDP 7 are represented as Cp ₁ to Cp _n , and the sum of these capacitances is represented as the plate capacitance Cp.

According to FIG. 6 , the first power recovery circuit 8 a includes a recovery capacitor C1 , a recovery inductor L, N-channel field effect transistors (hereinafter simply referred to as transistors) Q1 to Q4 , diodes D1 and D2 , and a recovery potential clamping circuit 80 . The recovery potential clamping circuit 80 includes resistors R1 , R2 and R3 , diodes D3 and D4 , and a bipolar transistor (hereinafter simply referred to as transistor) Q5 .

A recovery capacitor C1 is connected between node N3 and the ground terminal. The transistor Q3 and the diode D1 are connected in series between the node N3 and the node N2, and the diode D2 and the transistor Q4 are connected in series between the node N2 and the node N3.

The recovery inductance L is connected between the node N2 and the node N1. The transistor Q1 is connected between the node N1 and the power supply terminal V1, and the transistor Q2 is connected between the node N1 and the ground terminal.

In the recovery potential clamping circuit 80, a diode D3 is connected between the node N3 and the node N4, the node N4 is also connected to the emitter of the transistor Q5, and the collector of the transistor Q5 is connected to the ground terminal through the resistor R3. A resistor R1 is connected between the power supply terminal V1 and the node N5, and a resistor R2 is connected between the node N5 and the ground terminal. Node N5 is connected to the base of transistor Q5. A diode D4 is connected between the node N5 and the node N4.

The first data driver group 4a includes a plurality of P-channel field effect transistors (hereinafter simply referred to as transistors) Q1 ₁ to Q1 _n and a plurality of N-channel field effect transistors (hereinafter simply referred to as transistors) Q2 ₁ to Q2 _n . Transistors Q1 ₁ to Q1 _n are connected between node N1 and nodes ND ₁ to ND _n of the first power recovery circuit 8 a, respectively. Transistors Q2 ₁ to Q2 _n are connected between the nodes ND ₁ to ND _n and the ground terminal, respectively. Control pulses Sa ₁ to _San generated based on the data driver control signal DSa of the subfield processor 3 in FIG. 1 are supplied to the gates of the plurality of transistors Q1 ₁ to Q1 _n and Q2 ₁ to Q2 _n .

Nodes ND1 to NDn of the first data driver group 4a are connected to address electrodes 41 ₁ to 41 _n of PDP 7, respectively. Address electrode capacitances Cp ₁ to Cp _n are formed between the address electrodes 41 ₁ to 41 _n and the ground terminal, respectively. A parasitic capacitance Cf exists between the node N1 of the first power recovery circuit 8a and the ground terminal.

The composition of the second data driver group 4b and the second power recovery circuit 8b is the same as that of the above-mentioned first data driver group 4a and the first power recovery circuit 8a. The gates of the plurality of transistors Q1 ₁ -Q1 _n , Q2 ₁ -Q2 _n in the second data driver group 4b are supplied with control pulses Sa ₁ -Sa _n generated according to the data driver control signal DSb of the subfield processor 3 in FIG. 1 .

The power supply voltage Vda is supplied to the power supply terminal V1. Control signals S1 to S4 are supplied to gates of transistors Q1 to Q4, respectively. Transistors Q1-Q4 are switched on and off according to control signals S1-S4. The control signals S1-S4 are generated according to the power recovery circuit control signal Ha supplied by the sub-field processor 3 in FIG. 1 . Control signals S1 to S4 generated based on the power recovery circuit control signal Hb are supplied to the transistors Q1 to Q4 of the second power recovery circuit 8b in FIG. 1 .

FIG. 7 is a timing chart showing the operation of the first and second power recovery circuits 8a, 8b in FIG. 1 during the writing period. In FIG. 7 , waveforms of voltage NV1 at node N1 in FIG. 6 and control signals S1 to S4 respectively supplied to transistors Q1 to Q4 are shown by solid lines. Signal waveforms of the voltage NV1 at the node N1 of the second data driver group 4b and the control signals S1 to S4 respectively supplied to the transistors Q1 to Q4 are shown by dotted lines.

In FIG. 7, the symbol 8a is marked with brackets after the voltage NV1 of the first power recovery circuit 8a and the control signals S1-S4, and the symbols are marked with brackets after the voltage NV1 of the second power recovery circuit 8b and the control signals S1-S4. 8b.

When the control signals S1-S4 are at a high level, the transistors Q1-Q4 are turned on, and when the control signals S1-S4 are at a low level, the transistors Q1-Q4 are turned off.

During the TA period, the control signal S3 is at a high level, and the control signals S1 , S2 , and S4 are at a low level. Accordingly, the transistor Q3 is turned on, and the transistors Q1, Q2, and Q4 are turned off. At this time, the recovery capacitor C1 is connected to the recovery inductance L through the transistor Q3 and the diode D1, and the voltage NV1 of the node N1 is slowly increased by utilizing the LC resonance of the recovery inductance L, the parasitic capacitance Cf and the plate capacitance Cp.

At this time, the charge of the recovery capacitor C1 is discharged to the parasitic capacitance Cf through the transistor Q3, the diode D1 and the recovery inductance L, and then discharged to the panel capacitance Cp of the PDP 7 through the first data driver group 4a.

During the TB period, the control signal S1 is at a high level, and the control signals S2-S4 are at a low level. Accordingly, the transistor Q1 is turned on, and the transistors Q2 to Q4 are turned off. At this time, the node N1 is connected to the power supply terminal V1 through the transistor Q1. As a result, the voltage NV1 at the node N1 rises rapidly, and is fixed at the power supply voltage Vda supplied to the power supply terminal V1 accordingly.

During the TC period, the control signal S4 is at a high level, and the control signals S1-S3 are at a low level. Accordingly, the transistor Q4 is turned on, and the transistors Q1 to Q3 are turned off. At this time, the recovery capacitor C1 is connected to the recovery inductance L through the transistor Q4 and the diode D2, and the voltage NV1 of the node N1 is slowly decreased by utilizing the LC resonance of the recovery inductance L and the transformer Cp. At this time, the charges of the parasitic capacitance Cf and the plate capacitance Cp are recovered to the recovery capacitor C1 through the recovery inductor L, the diode D2 and the transistor Q4.

The first power recovery circuit 8a repeats the operation during the period TA to TC to recover the charge stored in the plate capacitance Cp and the parasitic capacitance Cf to the recovery capacitor C1, and at the same time supply the recovered charge to the plate capacitance Cp and the parasitic capacitance Cf. Hereinafter, the power based on the recovered charge recovered from the plate capacitance Cp and the parasitic capacitance Cf to the recovery capacitor C1 is referred to as recovered power.

The voltage based on the charges recovered in the recovery capacitor C1 is the same as the voltage of the node N3 in FIG. 6 . Hereinafter, the voltage of the node N3 is referred to as recovery potential Vm. The recovery capacitor C1 and the recovery inductance L in FIG. 6 perform LC resonance based on the recovery potential Vm. As a result, as shown in FIG. 7 , voltage NV1 at node N1 in FIG. 6 generates variation AC. The variation AC of the voltage NV1 varies with the recovery potential Vm.

In the above description, during the period TA-TC, the control signal S2 is always at low level, so that the transistor Q2 is always turned off. However, the control signal S2 becomes high level when the writing period P2 ( FIG. 2 ) ends, and becomes low level when the writing period P2 is restarted. Accordingly, the transistor Q2 is always turned on except in the writing period P2, and the node N1 is connected to the ground terminal. This operation is performed to store a predetermined amount of electric charge in a charge excitation circuit described later.

During the period from TA to TC, the recovery potential clamping circuit 80 of the power recovery circuit 8 a in FIG. 6 performs the following operations.

In the recovery potential clamping circuit 80, resistors R1 and R2 are connected in series between the power supply terminal V1 and the ground terminal. Accordingly, a predetermined voltage NV5 is generated at a node N5 between the resistors R1 and R2. On the other hand, the recovery potential Vm of the node N3 is supplied to the node N4. Here, for simplicity of description, the voltage drop (for example, 0.7V) of the diode D3 is ignored. The recovery potential Vm fluctuates according to the operation of the first data driver group 4a described later.

The transistor Q5 is turned off when the voltage NV5 of the node N5 is greater than or equal to the voltage of the node N4, and is turned on when the voltage NV5 of the node N5 is less than or equal to the voltage of the node N4. That is, the transistor Q5 is turned off when the recovered potential Vm of the node N3 is equal to or lower than the voltage NV5, and is turned on when the recovered potential Vm of the node N3 is equal to or higher than the voltage NV5.

Therefore, when the recovery potential Vm is lower than or equal to the voltage NV5, the transistor Q5 is turned off, and thus the charge stored in the recovery capacitor C1 is kept and not released to the ground terminal.

When the recovery potential Vm is higher than or equal to the voltage NV5, the transistor Q5 is turned on, so the charge stored in the recovery capacitor C1 is discharged to the ground terminal through the node N3, the diode D3, the node N4, the transistor Q5 and the resistor R3. As a result, recovery potential Vm of node N3 does not exceed voltage NV5.

Hereinafter, the upper limit of recovery potential Vm limited by voltage NV5 set by resistors R1 and R2 in FIG. 6 and power supply voltage Vda applied to power supply terminal V1 is referred to as limit voltage Vr.

In the above description, considering the voltage drop of the diode D3, the voltage NV5 of the node N5 is set to be lower than the limit voltage Vr by the percentage of the voltage drop of the diode D3.

In this way, the recovery potential clamp circuit 80 performs the clamping operation when the recovery potential Vm of the node N3 exceeds the limit voltage Vr. Therefore, the recovery potential Vm does not exceed the limit voltage Vr. The reason why plasma display device 100 of this embodiment is provided with recovery potential clamping circuit 80 will be described later.

In FIG. 7, the voltage NV1 of the node N1 of the second power recovery circuit 8b and the waveforms of the control signals S1 to S4 are the same as the waveforms of the voltage NV1 of the node N1 of the first power recovery circuit 8a and the control signals S1 to S4, but the phase Offset TR. This timing offset TR is equivalent to the data pulse phase difference TR of FIG. 5 .

Next, the recovery potential Vm that changes every time the voltage NV1 rises in FIG. 7 will be described based on the operations of the first power recovery circuit 8a and the first data driver group 4a.

FIG. 8 is a schematic diagram showing an example of the change of the display state of PDP7. FIGS. 9 to 11 show the voltage NV1 of the node N1 in FIG. 6 and the data pulse Pda applied to the address electrode ₄₁₁ when the display state of FIG. and timing diagrams of control pulses Sa ₁ to Sa ₄ supplied to the first data driver group 4a. FIG. 8 shows only part of the PDP 7 of FIG. 1 .

FIG. 8(a) shows an example in which all the pixels of the PDP 7 in FIG. 1 display "white". Hereinafter, the display state in which all the pixels of the PDP 7 display "white" is referred to as "full white". At this time, all the discharge cells 14 constituting the pixels of the PDP 7 are discharged.

FIG. 8(b) shows an example in which all pixels in the PDP 7 of FIG. 1 display "black". Hereinafter, the display state in which all the pixels of the PDP 7 display "black" is referred to as "full black". At this time, all the discharge cells 14 constituting the pixels of the PDP 7 are not discharged.

FIG. 8( c ) shows an example in which pixels alternately display "white" and "black" in the up, down, left, and right directions of the PDP 7 in FIG. 1 . In Fig. 8 (c), the pixel formed by the discharge cell 14 on the address electrode 41 ₁ displays "white", "black", "white" and "black" from top to bottom, and the pixel formed by the discharge cell 14 on the address electrode 41 ₂ The pixels formed by 14 display "black", "white", "black" and "white" from top to bottom. Hereinafter, the state in which the pixels of the PDP7 alternately display "white" and "black" in the up, down, left, and right directions is called triple black and white. At this time, in the up, down, left, and right directions of the PDP 7, the discharge cells 14 constituting the pixel are discharged one by one apart, and the discharge cells 14 between these two cells are not discharged.

In the display state of the PDP7 of FIG. 8(a), the voltage NV1 _of the node N1 of _{FIG .} Change as shown in 9.

As shown in FIG. 9, when PDP 7 is "full white", variation AC of voltage NV1 at node N1 in FIG. 6 changes in response to recovery potential Vm at node N3 in FIG. The recovery potential Vm changes every time the voltage NV1 in FIG. 7 rises.

According to FIG. 9 , each time the voltage NV1 rises, the variation AC of the voltage NV1 decreases sequentially. At this time, the control pulses Sa ₁ to Sa ₄ are always at low level in the writing period P2. Therefore, when the PDP 7 is "full white", the transistors Q1 ₁ to Q1 ₄ are always on, and the transistors Q2 ₁ to Q2 ₄ are always off. As a result, voltage NV1 is applied to address electrode ₄₁₁ as data pulse Pda, so the voltage of address electrode ₄₁₁ changes in the same manner as voltage NV1.

During the PC period of FIG. 9, as described above, the LC resonance of the recovery inductance L of FIG. 6 and the parasitic capacitance Cf and the plate capacitance Cp increases the voltage NV1 of the node N1, and it is made by the voltage Vda applied to the power supply terminal V1. After fixing, the LC resonance of the recovery inductance L with the parasitic capacitance Cf and the plate capacitance Cp makes it lower.

Since the transistors Q1 ₁ -Q1 ₄ are always on and the transistors Q2 ₁ -Q2 ₄ are always off, when the voltage NV1 rises, the charge stored in the recovery capacitor C1 is released to the parasitic capacitance Cf and the plate capacitance Cp. Conversely, when the voltage NV1 decreases, the charges stored in the parasitic capacitance Cf and the plate capacitance Cp are recovered to the recovery capacitor C1.

When the PDP7 is "all white", the charge stored in the recovery capacitor C1 is gradually increased by repeating the above PC period. Therefore, recovery potential V m at node N3 in FIG. 6 increases sequentially as data pulse Pda is applied to address electrodes 41 ₁ to 41 ₄ . This reduces the circuit loss (arrow LQ in FIG. 9 ) of the first data driver group 4a. In the second data driver group 4b, the circuit loss is similarly reduced.

However, the recovery potential Vm does not rise higher than the limit voltage Vr in FIG. 7 due to the recovery potential clamp circuit 80 in FIG. 6 . As a result, since the recovery potential Vm is fixed at the limit voltage Vr, the variation AC of the above-mentioned voltage NV1 is constant. The detailed change of the recovery potential Vm will be described later.

As shown in FIG. 10, when the PDP 7 is "all black", the variation AC of the voltage NV1 of the node N1 in FIG. 6 changes in response to the recovery potential Vm of the node N3 in FIG. 6. The recovery potential Vm changes every time the voltage NV1 in FIG. 7 rises.

According to FIG. 10 , each time the voltage NV1 rises, the variation AC of the voltage NV1 gradually decreases. At this time, the control pulses Sa ₁ to Sa ₄ are always at a high level in the writing period P2. Therefore, when the PDP 7 is "all black", the transistors Q1 ₁ to Q1 ₄ are always turned off, and the transistors Q2 ₁ to Q2 ₄ are always turned on. As a result, the voltage NV1 is applied to the address electrode ₄₁₁ as the data pulse Pda, so that the voltage of the address electrode ₄₁₁ is always the ground potential Vg.

During the PC period of FIG. 10, as described above, the LC resonance of the recovery inductance L of FIG. 6 and the parasitic capacitance Cf and the plate capacitance Cp raises the voltage NV1 of the node N1, and it is made by the voltage Vda applied to the power supply terminal V1. After fixing, the LC resonance of the recovery inductance L with the parasitic capacitance Cf and the plate capacitance Cp makes it lower.

Since the transistors Q1 ₁ -Q1 ₄ are always off and the transistors Q2 ₁ -Q2 ₄ are always on, when the voltage NV1 rises, the charge stored in the recovery capacitor C1 is released to the parasitic capacitance Cf and the plate capacitance Cp. Conversely, when the voltage NV1 decreases, the charge stored in the parasitic capacitance Cf is recovered to the recovery capacitor C1.

When the PDP 7 is "all black", the charge stored in the recovery capacitor C1 is gradually increased by repeating the above PC period. Therefore, every time the voltage NV1 rises, the recovery potential Vm of the node N3 in FIG. 6 rises sequentially. This reduces the circuit loss (arrow LQ in FIG. 10 ) of the first data driver group 4a. In the second data driver group 4b, the circuit loss is similarly reduced.

However, the recovery potential Vm does not rise higher than the limit voltage Vr in FIG. 7 due to the recovery potential clamp circuit 80 in FIG. 6 . As a result, since the recovery potential Vm is fixed at the limit voltage Vr, the variation AC of the above-mentioned voltage NV1 is constant.

As shown in Fig. 11, when PDP7 is "triple black and white", except when the voltage NV1 rises for the first time, the variation AC of the voltage NV1 of the node N1 in Fig. 6 is constant. This is because the recovery potential Vm of the node N3 in FIG. 6 is constant except for the first rise of the voltage NV1.

At this time, in the writing period P2, the control pulses Sa ₁ and Sa ₃ repeat a low level and a high level every time the voltage NV1 rises. The control pulses Sa ₂ and Sa ₄ each time the voltage NV1 rises are opposite to the control pulses Sa ₁ and Sa ₃ and repeat high and low levels. Thus, the transistors Q1 ₁ -Q1 ₄ are switched on and off and the transistors Q2 ₁ -Q2 ₄ are switched on and off every PC period. As a result, the voltage of address electrode ₄₁₁ rises to voltage Vda in FIG. 7 when control pulses Sa ₁ and Sa ₃ are at low level, and becomes ground potential Vg when control pulses Sa ₂ and Sa ₄ are at low level.

During the PC period of FIG. 11, as described above, the LC resonance of the recovery inductance L of FIG. 6, the parasitic capacitance Cf and the plate capacitance Cp raises the voltage NV1 of the node N1, and it is made by the voltage Vda applied to the power supply terminal V1. After fixing, the LC resonance of the recovery inductance L with the parasitic capacitance Cf and the plate capacitance Cp makes it lower.

In the first PC period to the second PC period, after the recovery potential Vm changes to the minimum recovery potential Vs described later, it does not change from the minimum recovery potential Vs.

In the first PC period, when the voltage NV1 rises, the transistor Q1 ₁ is turned on, and the transistor Q2 ₁ is turned off, thereby releasing the charge stored in the recovery capacitor C1 to the parasitic capacitance Cf and the address electrode capacitance Cp ₁ . Here, the address electrode capacitance _Cp1 is connected to the transistor _Q11 which is in the on state. Then, by turning off the transistor _Q12 and turning on the transistor _Q22 , the charges stored in the recovery capacitor C1 are recovered to the parasitic capacitance Cf.

Then, when the voltage NV1 falls, the charges stored in the parasitic capacitance Cf and the address electrode capacitance _Cp1 are recovered to the recovery capacitor C1. Here, voltage NV1 falls to predetermined potential Vgx due to charges stored in parasitic capacitance Cf and address electrode capacitance _Cp1 , and does not fall to ground potential Vg. At this time, the recovery potential Vm of the node N3 is the minimum recovery potential Vs described later.

In this first PC period, data pulse Pda is applied to address electrode ₄₁₁ as shown in FIG. 11 . Also, no data pulse Pda is applied to address electrode ₄₁₂ .

In the second PC period, when the voltage NV1 rises, the transistor Q1 ₁ is turned off, and the transistor Q2 ₁ is turned on, thereby releasing the charge stored in the recovery capacitor C1 to the parasitic capacitance Cf. Also, by turning on the transistor Q12 and turning off the transistor _Q22 , the charges stored in the recovery capacitor C1 are discharged to _the parasitic capacitance Cf and the address electrode capacitance _Cp2 . Here, the address electrode capacitance _Cp1 is connected to the transistor _Q11 which is in the on state.

Then, when the voltage NV1 falls, the charges stored in the parasitic capacitance Cf and the address electrode capacitance _Cp1 are recovered to the recovery capacitor C1. Here, voltage NV1 falls to predetermined potential Vgx due to charges stored in parasitic capacitance Cf and address electrode capacitance _Cp1 , and does not fall to ground potential Vg. As described above, the recovery potential Vm of the node N3 is the minimum recovery potential Vs described later. The charge stored in the address electrode capacitance _Cp2 during the first PC period is discharged to the ground terminal through the address electrode ₄₁₁ and the transistor _Q11 .

In this PC2 period, as shown in FIG. 11, the data pulse Pda is applied to the address electrode ₄₁₂ . Also, the data pulse Pda is not applied to the address electrode ₄₁₂ .

The change in voltage NV1 in FIG. 7 has been described above based on the change in voltage of the two address electrodes 41 ₁ and 41 ₂ , but the same voltage changes as in address electrodes 41 ₁ and 41 ₂ also occur for the other address electrodes 41 ₃ to 41 _n . Therefore, the voltage NV1 changes according to the charges stored in the parasitic capacitance Cf and the address electrode capacitances Cp ₁ ˜Cp _n .

In this way, when PDP7 is "triple black and white", each address electrode 41 ₁ ~ 41 _n alternately repeats the operation of the above-mentioned PC period, so that there are no address electrode capacitances Cp ₁ ~ Cp _n connected to all address electrodes 41 ₁ ~ 41 _n Store the largest amount of charge. As a result, the recovery potential Vm becomes the minimum recovery potential Vs and does not increase. Arrow LQ in FIG. 11 shows the circuit loss of the first data driver group 4a at this time. This circuit loss is similarly consumed in the second data driver group 4b.

Next, the reason why the plasma display device 100 of this embodiment is provided with the recovery potential clamping circuit 80 will be described with reference to FIGS. 12 and 13 .

12 and 13 are diagrams for explaining the operation of the recovery potential clamping circuit 80 of FIG. 6 . As described above, the plasma display device 100 of this embodiment reduces circuit loss by using the first power recovery circuit 8a and the second power recovery circuit 8b of FIG. 6 .

For example, when the PDP 7 is "full white", as described above, the voltages of the address electrodes 41 ₁ to 41 _n and 42 ₁ to 42 _n in FIG. 1 are sequentially increased while the data pulse Pda is being applied (FIG. ) and Figure 13(a)). As a result, the recovery power (arrow RQ) based on the charge recovered from the plate capacitance Cp in FIG. 6 to the recovery capacitor C1 decreases sequentially as the data pulse Pda is applied to the address electrodes 41 ₁ to 41 _n and 42 ₁ to 42 _n . go down.

Here, the case where the first power recovery circuit 8a and the second power recovery circuit 8b in FIG. 6 are not provided with the recovery potential clamping circuit 80 will be described for comparison. In this case, when the data pulse _{Pda is continuously applied to the address electrodes 41 1 to 41 n , 42 1 to 42 n , as shown in FIG .} The voltage of 42 _n is fixed to the voltage Vda applied to the power supply terminal V1 of FIG. 6 .

In the plasma display device 100 of this embodiment, when the data pulse Pda is applied to the address electrodes 41 ₁ to 41 _n and 42 ₁ to 42 _n , a data pulse phase difference TR is generated, so that the data pulse Pda is applied to the address electrodes 41 ₁ to 41 _n . Timing t1 of 1 and timing t2 of applying data pulse Pda to address electrodes 42 ₁ to 42 _n are shifted (FIG. 12(b), (c)).

However, since the voltages of the address electrodes 41 ₁ to 41 _n and 42 ₁ to 42 _n are fixed at the voltage Vda, the rising portion of the data pulse Pda is not defined, and the data pulse phase difference TR cannot be reliably obtained. That is, the difference between the voltage of address electrodes 41 ₁ to 41 _n , 42 ₁ to 42 _n and the voltage of address pulse Pw in FIG. 2 applied to scan electrodes 121 to 12m always exceeds the voltage value required for address discharge.

Therefore, as shown in FIG. 12(b) and (c), corresponding to the data pulse Pda applied to the address electrodes 41 ₁ to 41 _n at the timing t1, the scan electrode 12 _k (where k is 1 to m) is supplied with the write pulse Pw. Any integer in ), the discharge currents of the discharge cells 14 on the address electrodes 41 ₁ to 41 _n and the discharge cells 14 on the address electrodes 42 ₁ to 42 _n flow simultaneously.

That is, since the rising edge of the data pulse Pda of the address electrodes 41 ₁ to 41 _n and 42 ₁ to 42 _n is not specified, the discharge cells 14 on the address electrodes 41 ₁ to 41 _n and the discharge cells 14 on the address electrodes 42 ₁ to 42 _n Discharge cell 14 generates an address discharge at the same timing corresponding to timing t3 at which address pulse Pw is applied to scan electrode _12k . Accordingly, scan electrode _12k generates discharge current DA3 having one peak.

At this time, the discharge currents of the discharge cells 14 on the address electrodes 41 ₁ to 41 _n and the discharge cells 14 on the address electrodes 42 ₁ to 42 _n flow through the scan electrodes 12 _k at the same time, so the amplitude AM3 of the discharge current DA3 becomes larger (Fig. 12(e)). Thus, a large voltage drop E3 occurs in the write pulse Pw applied to the scan electrode 12k (FIG. 12(d)). As a result, address discharge becomes unstable as described above.

In this way, when the first power recovery circuit 8a and the second power recovery circuit 8b in FIG. 6 do not have the recovery potential clamping circuit 80, the data pulse phase difference TR cannot be obtained, and address discharge stability cannot be ensured.

In contrast, in plasma display device 100 of the present embodiment, recovery potential clamping circuit 80 is provided in first power recovery circuit 8 a and second power recovery circuit 8 b in FIG. 6 .

The recovery potential clamp circuit 80 limits the reduction of the recovery power (arrow RQ) to a predetermined value. Therefore, even when the data pulses Pda are continuously applied to the address electrodes 41 ₁ to 41 _n and 42 ₁ to 42 _n , the voltages of the address electrodes 41 ₁ to 41 _n and 42 ₁ to 42 _n have a rise for each data pulse Pda. Part St, as shown in Figure 13(b), (c).

Similar to the above, in the plasma display device 100 of this embodiment, the timing t1 at which the data pulse Pda is applied to the address electrodes 41 ₁ to 41 _n is shifted from the timing t2 at which the data pulse Pda is applied to the address electrodes 42 ₁ to 42 _n . (Fig. 13(b), (c)).

Since the voltages of the address electrodes 41 ₁ to 41 _n , 42 ₁ to 42 _n have rising portions St for every data pulse Pda, a data pulse phase difference TR can be obtained. That is, _the difference between the voltage _of address electrodes 41 ₁ to 41 _n , 42 ₁ to 42 _n and the voltage of write pulse Pw in FIG. required voltage value.

Therefore, as shown in FIG. 13(b) and (c), among scan electrodes 12 _k (k is any integer from 1 to m) to which write pulses Pw are supplied, discharge cells 14 on address electrodes 41 ₁ to 41 _n are The discharge current of discharge cells 14 on address electrodes 42 ₁ to 42 _n flows corresponding to data pulse Pda applied to address electrodes 41 ₁ to 41 _n at timing t1 at timing staggered by data pulse phase difference TR.

Accordingly, discharge cells 14 on address electrodes 41 ₁ to 41 _n generate address discharge at timing t1, and discharge cells 14 on address electrodes 42 ₁ to 42 _n generate address discharge at timing t2. Accordingly, scan electrode _12k generates discharge current DA4 having two peaks.

At this time, in the scan electrode _12k , the discharge current of the discharge cells 14 on the address electrodes 41 ₁ to 41 _n and the discharge cells 14 on the address electrodes 42 ₁ to 42 _n flows at the timing of shifting the phase difference TR of the data pulse, thereby discharging The amplitude AM4 of the current DA4 becomes small (FIG. 13(e)). As a result, the voltage drop E4 caused by the write pulse Pw applied to the scan electrode 12k is reduced (FIG. 13(d)). As a result, the address discharge is stabilized.

In this way, in the plasma display _device 100 of this embodiment, by providing the recovery potential clamp circuit 80 in the first power recovery circuit 8a and the second power recovery circuit 8b _in FIG. _1˜42n apply a data pulse Pda having _a rising portion St. As a result, the data pulse phase difference TR can be obtained, and the stability of the address discharge can be ensured.

Next, changes in the recovery potential Vm at the node N3 in FIG. 6 will be described. FIG. 14 is a waveform diagram showing changes in the recovery potential Vm of the node N3 in FIG. 6 during the writing period.

In FIG. 14 , changes in the recovery potential Vm are shown together with changes in the voltage NV1 at the node N1 in FIG. 6 . In the following description, each pulse period Pa1 , Pa2 , Pa3 indicated by arrows Pa1 , Pa2 , Pa3 in the figure includes a TA period, a TB period, and a TC period, respectively.

In the TA period of the pulse period Pa1, the recovery potential Vm is lowered by the discharge of electric charges from the recovery capacitor C1 to the parasitic capacitance Cf and the plate capacitance Cp. Then, in the TB phase, the recovery potential Vm maintains a constant value. Next, in the TC period, the electric charges stored in the parasitic capacitance Cf and the plate capacitance Cp are recovered to the recovery capacitor C1, so that the value of the recovery potential Vm increases.

The increase in the recovery potential Vm varies depending on the amount of charge recovered from the parasitic capacitance Cf and the plate capacitance Cp.

In the TA period of the pulse period Pa2, the recovery potential Vm is lowered again due to the discharge of electric charges from the recovery capacitor C1 to the parasitic capacitance Cf and the plate capacitance Cp. Then, in the TB phase, the recovery potential Vm maintains a constant value. Next, in the TC period, the charges stored in the parasitic capacitance Cf and the plate capacitance Cp are recovered to the recovery capacitor C1 again, so that the value of the recovery potential Vm increases.

Here, when the recovery potential Vm rises above the limit voltage Vr, the recovery potential Vm is fixed at the limit voltage Vr by the action of the recovery potential clamp circuit 80 in FIG. 6 . The recovery potential Vm in the pulse period Pa2 is also changed in the same manner in the pulse period Pa3.

In each pulse period, when the state in which the charge recovered to the recovery capacitor C1 in the TC period is smaller than the charge released from the recovery capacitor C1 in the TA period continues, the recovery potential Vm decreases sequentially in each pulse period. The minimum value of the recovery potential Vm at this time is taken as the minimum recovery potential Vs. The value of the minimum recovery potential Vs is greater than one-half of the power supply voltage Vda applied to the power supply terminal V1 of FIG. 6 .

FIG. 15 is a graph showing the relationship between the recovery potential Vm in FIG. 14 and the cumulative number of rises of the control pulses Sa ₁ to _San in each subfield. In FIG. 15 , the vertical axis represents the recovery potential Vm of each subfield, and the horizontal axis represents the cumulative rising numbers of the control pulses Sa ₁ to _San in each subfield.

Here, the cumulative number of rises refers to the cumulative number of rises of the control pulses Sa ₁ -Sa _n . In other words, the cumulative rising number is the number of switching times of discharge and non-discharge of the plurality of discharge cells 14 in the PDP 7 of FIG. 1 . The recovery potential Vm varies with the number of accumulative rises of the control pulses Sa ₁ -Sa _n .

For example, when the PDP 7 displays "full white" or "full black", since the discharging or non-discharging of the discharge cell 14 is continuous without switching, the accumulative number of rises of the control pulses Sa ₁ -Sa _n is the least. In this way, when the number of cumulative rises of the control pulses Sa ₁ to _San is small, the recovery potential Vm converges to the power supply voltage Vda. As a result, the recovery potential Vm is increased, so that the circuit loss of the first and second data driver groups 4a, 4b decreases according to the cumulative increase.

In this embodiment, the recovery potential Vm is kept from exceeding the limit voltage Vr by utilizing the function of the recovery potential clamp circuit 80 in FIG. 6 . When the recovery potential Vm becomes the limit voltage Vr, as described above, the voltage NV1 has a variation AC centered on the limit voltage Vr.

The recovered potential clamp circuit 80 limits the recovered potential to the limit voltage Vr, so that the data pulse phase difference TR explained in FIGS. 12 and 13 can be obtained. Due to the effect of the data pulse phase difference, the peak of the discharge current flowing through scan electrodes 12 is reduced, so that each discharge cell 14 is stably discharged when data pulse Pda is continuously applied to address electrodes 41 ₁ to 41 _n .

When the PDP 7 displays "triple black and white", all the discharge cells 14 are switched between discharge and non-discharge, so the cumulative rising numbers of the control pulses Sa _{1 -San} are the largest. In this way, when the number of cumulative rises is large, the recovery potential Vm converges to the minimum recovery potential Vs having a predetermined value. As shown in FIG. 15 , the minimum recovery potential Vs exhibits a high value less than half of the power supply voltage Vda.

When the writing period P2 of each subfield in FIG. 3 ends, the power recovered by the first power recovery circuit 8a and the second power recovery circuit 8b is not recovered, but is used for the writing period of the next subfield. Therefore, except during the writing period P2, the recovery potential Vm of the recovery capacitor C1 is gradually discharged.

The charge excitation circuit incorporated in the first power recovery circuit 8a of FIG. 6 will be described. As described above, the first power recovery circuit 8a in FIG. 6 incorporates a charge excitation circuit.

FIG. 16 is a circuit diagram showing an example of a charge excitation circuit provided in the first power recovery circuit 8a. In FIG. 16 , the detailed configuration of charge excitation circuits CG1 and CG2 provided within the range of the dotted line NF in FIG. 6 is shown. The charging drive circuits CG1, CG2 are used to control the control signals S1, S3 applied to the gates of the transistors Q1, Q3.

In FIG. 16, the charge excitation circuit CG1 includes a diode Dp1, a capacitor CCp1 and a field effect transistor (hereinafter referred to as FET) driver FD1. The charging drive circuit CG2 includes a diode Dp2, a capacitor CCp2, and an FET driver FD2.

In FIG. 16, the FET driver FD1 is connected to the subfield processor 3 of FIG. 1, the power supply terminal Vp1, the ground terminal, the nodes N1 and Na, and the transistor Q1. The diode Dp1 is connected between the power supply terminal Vp2 and the node Na, and the capacitor CCp1 is connected between the node N1 and the node Na.

The FET driver FD2 is connected to the subfield processor 3 of FIG. 1, the power supply terminal Vp3, the ground terminal, the nodes Nb and Nc, and the transistor Q3. A diode Dp2 is connected between the power supply terminal Vp4 and the node Nc, and a capacitor CCp2 is connected between the node Nb and the node Nc.

Next, the operation of the charge excitation circuit CG1 will be described. In the following description, it is assumed that the transistor Q1 is turned on when a voltage about 15 V higher than that of the source is supplied to the gate of the transistor Q1. Further, a voltage of 5V is applied to the power supply terminal Vp1, and a voltage of 15V is applied to the power supply terminal Vp2.

To the FET driver FD1, the voltage of the power supply terminal Vp1 is applied as the power supply voltage Vcc, the voltage of the node N1 is applied as the reference voltage VZ, and the voltage of the node Na is applied as the bias voltage VB. Further, a power recovery circuit control signal Ha is supplied to the FET driver FD1 from the subfield processor 3 in FIG. 1 .

The operation of the charge excitation circuit CG1 in periods other than the writing period P2 in FIG. 2 will be described. At this time, the transistor Q2 of FIG. 6 is turned on. Thereby, the node N1 is connected to the ground terminal, and thus the voltage NV1 of the node N1 becomes the ground potential. As a result, the voltage at the node Na is higher than the voltage NV1 at the node N1, so that charges are stored in the capacitor CCp1 by the power supply voltage of 15V applied to the power supply terminal Vp2. As a result, a bias voltage VB of about 15V is generated on the node Na.

The operation of the charging drive circuit CG1 in the writing period P2 will be described. In the writing period P2, the voltage NV1 of the node N1 changes as shown in FIG. 7 .

At this time, the FET driver FD1 is supplied with the voltage NV1 from the node N1 as the reference voltage VZ, and also supplies the bias voltage VB of about 15V based on the charge stored in the capacitor CCp1 during periods other than the writing period P2.

FET driver FD1 raises control signal S1 to a level (high level) higher than reference voltage VZ by bias voltage VB based on power recovery circuit control signal Ha during TB in FIG. 7 . As a result, the gate voltage of transistor Q1 is about 15V higher than the source voltage, turning transistor Q1 on.

Next, the operation of the charge excitation circuit CG2 will be described. In the following description, it is assumed that the transistor Q3 is turned on when a voltage about 15 V higher than the source is supplied to the gate of the transistor Q3. Furthermore, a voltage of 5V is applied to the power supply terminal Vp3, and a voltage of 15V is applied to the power supply terminal Vp4.

To the FET driver FD2, the voltage of the power supply terminal Vp3 is applied as the power supply voltage Vcc, the voltage of the node Nb is applied as the reference voltage VZ, and the voltage of the node Nc is applied as the bias voltage VB. Further, a power recovery circuit control signal Ha is supplied to the FET driver FD2 from the subfield processor 3 in FIG. 1 .

The operation of the charge excitation circuit CG2 in periods other than the writing period P2 in FIG. 2 will be described. At this time, the transistor Q2 of FIG. 6 is turned on. Thereby, the node N1 is connected to the ground terminal, and thus the voltage NV1 of the node N1 becomes the ground potential. As a result, the voltage at the node N2 becomes the ground potential, and the potential NVb at the node Nb becomes the ground potential. The voltage of the node Nc is higher than the voltage NVb of the node Nb, so the charge is stored in the capacitor CCp2 by the power supply voltage of 15V applied to the power supply terminal Vp4. As a result, a bias voltage VB of about 15V is generated on the node Nc.

The operation of the charging drive circuit CG2 in the writing period P2 will be described. In writing period P2, voltage NVb of node Nb changes.

At this time, the voltage NVb is supplied from the node Nb as the reference voltage VZ to the FET driver FD2, and a bias voltage VB of about 15 V based on the charge accumulated in the capacitor CCp2 during periods other than the writing period P2 is also supplied.

FET driver FD2 raises control signal S3 to a level (high level) higher than reference voltage VZ by bias voltage VB based on power recovery circuit control signal Ha during TA in FIG. 7 . As a result, the gate voltage of transistor Q3 is about 15V higher than the source voltage, turning transistor Q3 on.

In this way, by using the charging drive circuits CG1 and CG2, even if the voltage of the nodes N1 and N2 changes, the transistors Q1 and Q3 can be reliably turned on.

Conditions for stable discharge of discharge cell 14 in FIG. 1 are determined from the relationship between the write voltage and the sustain voltage. The write voltage refers to the voltage applied between the address electrode selected for the address discharge and the selected scan electrode, which is applied to the address electrodes 41 ₁ to 41 _n , 42 ₁ to 42 of FIG. 1 during the write period P2 of FIG. 2 . The difference between the voltage of the data pulse Pda in FIG. 2 on _n and the voltage of the address pulse Pw in FIG. 2 on the scan electrodes 12 ₁ to 12 _m .

The sustain voltage refers to the voltage applied between each scan electrode and each sustain electrode for sustain discharge, and is the voltage of the sustain pulse Psc in FIG. 2 applied to the scan electrodes 12 ₁ to 12 _m in the sustain period P3 of FIG. 2 and The voltage difference between the sustain electrodes 13 ₁ to 13 _m and the voltage difference between the sustain pulse Psu in FIG. 2 applied to the sustain electrodes 13 ₁ to 13 _m and the voltage to the scan electrodes 12 ₁ to 12 _m .

Hereinafter, the range of the write voltage and the sustain voltage that allows the discharge cell 14 on the PDP 7 in FIG. 1 to achieve stable discharge is referred to as a driving margin. As illustrated in FIG. 5 , when the voltage drop E2 of the write pulse Pw is reduced by using the data pulse phase difference TR, the driving margin is increased. The relationship between the driving margin expansion and the magnitude of the data pulse phase difference TR will be described.

FIG. 17 is a graph for explaining the relationship between the driving margin and the data pulse phase difference of the plasma display device shown in FIG. 1. FIG. In the graph of FIG. 17 , the horizontal axis represents the write voltage, and the vertical axis represents the sustain voltage. The driving margin shown in FIG. 17 is the margin when the limit voltage Vr in FIG. 15 is set to 0.8 times the power supply voltage Vda.

In FIG. 17, when a write voltage and a sustain voltage exceeding curve L1 are applied to PDP 7 of FIG. 1, unselected discharge cells 14 may be erroneously discharged at the sustain voltage. The range of the write voltage and the hold voltage beyond the curve L1 is the range indicated by the arrow MO1. For example, when a "full black" image is displayed with a write voltage and a hold voltage exceeding the curve L1, the partial discharge cells 14 are erroneously discharged, resulting in poor image quality.

In FIG. 17, when a holding voltage lower than the curve L2 is applied to the PDP 7 of FIG. 1, the selected discharge cell 14 may be insufficiently discharged. The range of the writing voltage and the holding voltage lower than the curve L2 is the range indicated by the arrow MO2. For example, when a "full white" image is displayed at a holding voltage lower than the curve L2, some discharge cells are not discharged, and the image flickers.

The driving margin of plasma display device 100 in FIG. 1 is determined by these curves L1 and L2 and data pulse phase difference TR in FIG. 5 .

Here, curve L3 shows the result of measuring the minimum write voltage required to stabilize the discharge of the discharge cell 14 for each predetermined holding voltage when the data pulse phase difference TR is 0.

Curve L4 shows the result of measuring the minimum write voltage required to stabilize the discharge of the discharge cell 14 for each predetermined holding voltage when the data pulse phase difference TR is 150 ns.

Curve L5 shows the result of measuring the minimum write voltage required to stabilize the discharge of the discharge cell 14 for each predetermined holding voltage when the data pulse phase difference TR is 200 ns.

As shown in FIG. 17 , as the phase difference TR of the data pulse increases, the minimum write voltage required to achieve stable discharge of the discharge cell 14 decreases. That is, by increasing the data pulse phase difference TR, the peak of the discharge current flowing through the scan electrodes can be reduced, and thus the lower limit value of the write voltage required for discharge can be reduced. As a result, the write voltage range that allows the discharge cell 14 to stabilize the discharge is expanded.

From the results in FIG. 17, when the data pulse phase difference TR is set to 0, the driving margin is within the range surrounded by the curves L1, L2, and L3. When the data pulse phase difference TR is set to 150 ns, the driving tolerance is the range surrounded by the curves L1, L2, and L4. When the data pulse phase difference TR is set to 200 ns, the driving tolerance is the range surrounded by the curves L1, L2, and L5. From this, it is found that the larger the data pulse phase difference TR is, the larger the driving margin is. In this embodiment, the data pulse phase difference TR is preferably set to be greater than or equal to about 200 ns, which will be described later.

In FIG. 17, in the range indicated by the arrow MO3, a voltage sufficient for writing to the holding voltage may not be obtained, and the discharge cell 14 may be insufficiently discharged. For example, when a "full white" image is displayed at a writing voltage lower than the curve L5, the partial discharge cells 14 are not discharged, and the image flickers.

In this embodiment, it is preferable to set the data pulse phase difference TR in FIG. 5 as follows.

FIG. 18 is a graph showing the relationship between the writing voltage and the phase difference when displaying a "full white" image. The vertical axis represents the write voltage, and the horizontal axis represents the data pulse phase difference TR.

In Fig. 18, the solid line J1 shows that the discharge in Fig. 1 can be obtained when the holding voltage is set to a specified voltage value Ve (refer to Fig. 17) and the limit voltage Vr is set to 0.8Vda (Vda is the same as the power supply voltage Vda in Fig. 6). The lower limit value of the write voltage at which cell 14 discharges stably. Therefore, within the range of the hatched line in FIG. 18 , discharge stabilization of the discharge cell 14 can be achieved.

Focusing on the data pulse phase difference TR on the horizontal axis, when the phase difference exceeds about 200 ns, the lower limit value of the write voltage is very low compared to the conventionally generally used voltage value Vj (dotted line in FIG. 18 ). Therefore, in the plasma display device 100 of the present embodiment, it is preferable to set the data pulse phase difference TR to be equal to or greater than about 200 ns.

FIG. 19 is a graph showing the relationship between the writing voltage and the limit voltage Vr when displaying a "full white" image. The vertical axis represents the writing voltage, and the horizontal axis represents the limit voltage Vr.

In FIG. 19, the solid line J1 shows that when the hold voltage is taken as a predetermined voltage value Ve (refer to FIG. 17) and the phase difference TR of the data pulse in FIG. Voltage lower limit. Therefore, within the range of the hatched line in FIG. 19 , stable discharge of the discharge cell 14 can be obtained.

When focusing on the limit voltage Vr on the horizontal axis, when the limit voltage Vr is set to be lower than approximately 0.8 Vda, the lower limit value of the write voltage is significantly lower than the conventionally used voltage value Vj (dotted line in FIG. 18 ). Low.

Therefore, in the plasma display device 100 of this embodiment, it is preferable to set the limit voltage Vr to be less than about 0.8 Vda. It is preferable to set the limit voltage Vr to about 0.5 Vda to 0.8 Vda, and more preferably to set the limit voltage Vr to about 0.8 Vda.

In this way, by setting the phase difference TR of the data pulse and the limit voltage Vr, the lower limit value of the writing voltage required to obtain the stable discharge of the discharge cell 14 is enlarged, thereby ensuring the stable discharge of the discharge cell 14 and reducing the writing voltage.

Power consumption in the address period of plasma display device 100 according to this embodiment will be described. Here, the power consumption in this example refers to the power consumed by applying the data pulse Pda to the address electrodes 41 ₁ to 41 _n , 42 ₁ to 42 _n . This power consumption corresponds to the circuit loss indicated by the arrow LQ in FIGS. 9 to 11 .

FIG. 20 is a graph for comparing power consumption of plasma display device 100 according to Embodiment 1 with power consumption of a plasma display device having another configuration.

In this example, as a comparison object of the plasma display device 100 of this embodiment, an existing plasma display device that does not perform power recovery (referred to as a non-recovery type plasma display device) and a power recovery device as shown in FIG. 33 described in the background art are used. The plasma display device of the circuit 980 (referred to as a conventional recycling type plasma display device). In the following description, it is assumed that the plasma display device 100 of Embodiment 1, the non-recycling type plasma display device, and the conventional recycling type plasma display device have substantially the same configuration except for a part.

In FIG. 20 , the vertical axis represents the comparison of the data circuit losses of the data driver group 4 and the power recovery circuit 8 in the plasma display device 100 of Embodiment 1, the non-recycling type plasma display device, and the conventional recycling type plasma display device. This comparison of data circuit loss is based on the case where the "full white" display with the largest data circuit loss in the existing recycling type plasma display device is taken as 100%. The plasma display device 100, the non-recycling type plasma display device and Ratio of data circuit losses in existing recycling plasma display devices. The horizontal axis represents the rising ratio of the control pulses Sa ₁ to _San in each subfield. This rising ratio represents the ratio of the cumulative rising number of control pulses Sa ₁ ~Sa _n in each subfield to the maximum number of rising times in each subfield, and the cumulative rising number is the largest when displaying "triple black and white", so the ratio of the cumulative rising number is 100%.

According to Fig. 20, assume that the data circuit loss relative ratio of the existing recycling type plasma display device represented by the dotted line L2 is 100% (increasing rate is 0%: "full white" display), then the dotted line The maximum value of the relative loss ratio of the data circuit of the non-recycling type plasma display device represented by L1 is 200% (a rise ratio of 100%: "triple black and white" display). On the other hand, the maximum value of the relative data circuit loss ratio of the plasma display device 100 of the present embodiment indicated by the thick line is less than or equal to two-thirds of the 100% relative data circuit loss ratio of the conventional recycling type plasma display device (increase The ratio is 100%: "triple black and white" display), so that the maximum data circuit loss is greatly reduced.

The plasma display device 100 according to this embodiment can significantly reduce the loss of the data circuit even when the data pulse Pda is continuously applied to the address electrode during "full white" display, which is a problem of the loss of the data circuit of the conventional recovery type plasma display device. .

In the plasma display device 100 of this embodiment, the data pulse phase difference TR is generated by the first and second data driver groups 4a, 4b and the first and second power recovery circuits 8a, 8b. Thus, stable discharge of the discharge cells 14 can be ensured, the voltage of the write pulse Pw (drive voltage) can be reduced, and the drive margin can be increased.

In this embodiment, the data pulse phase difference TR is generated by using 2 data driver groups and 2 power recovery circuits, but it is not limited to this, as long as multiple data pulse phase differences TR can be generated, multiple data drivers can be further provided group and power recovery circuits.

As mentioned above, the recovery potential Vm of the node N3 in FIG. 6 increases with the number of discharge or non-discharge switching of the discharge unit 14 on the rising edge (rising edge of the data pulse) of the voltage NV1 of each node N1 (the cumulative number of rises in FIG. 15 ). )Variety. Specifically, when the number of accumulated increases is small, the recovery potential Vm increases. Accordingly, circuit loss is reduced, thereby sufficiently reducing power consumption of plasma display device 100 .

Plasma display device 100 of this embodiment is provided with recovery potential clamp circuit 80 shown in FIG. 6 . Thus, the recovery potential Vm of the node N3 in FIG. 6 is controlled by the recovery potential clamp circuit 80 so as not to exceed the limit voltage Vr, although the rising edge (data pulse rising edge) of the voltage NV1 of the node N1 varies. As a result, the recovery potential Vm does not rise to the power supply voltage Vda in FIG. 6 _, so that the timing of applying the data pulse _{Pda in} FIG _. The data pulse phase difference TR is generated between the timings.

As a result, the power consumption of the plasma display device 100 is reduced by the first and second power recovery circuits 8a, 8b, while ensuring stable discharge of the discharge cell 14 in FIG. 1, and reducing the voltage of the write pulse Pw ( drive voltage), and expand the drive tolerance.

To sum up, in this embodiment, the first and second data driver groups 4a, 4b generate data by staggering the output timing of applying the data pulse Pda to the address electrodes 41 ₁ to 41 _n and the address electrodes 42 ₁ to 42 _n , respectively. Pulse phase difference TR.

However, as long as the data pulse phase difference TR can be obtained, the timing of supplying the data driver control signal DSa to the first data driver group 4a and the timing of supplying the power recovery circuit to the first power recovery circuit 8a can also be staggered, for example, through the subfield processor 3. There is a data pulse phase difference TR between the timing of the control signal Ha, the timing of the data driver control signal DSb supplied to the second data driver group 4b, and the timing of the power recovery circuit control signal Hb supplied to the first power recovery circuit 8b.

In addition, in order to obtain the data pulse phase difference TR, delay circuits can also be provided in the first and second data driver groups 4a and 4b respectively, so that the data pulse Pda is applied to the address electrodes 41 ₁ to 41 _n and the address electrodes 42 ₁ to 42 _n The output timing is different.

In order to obtain the data pulse phase difference TR, delay circuits may be respectively provided in the first and second power recovery circuits 8a, 8b to delay the power supplied to the first and second data driver groups 4a, 4b.

The number of address electrodes 41 ₁ to 41 _n connected to the first data driver group 4a is not necessarily plural, and may be one. The same applies to the address electrodes 42 ₁ to 42 _n connected to the second data driver group 4b, and the number of address electrodes 42 ₁ to 42 _n connected to the second data driver group 4b does not necessarily have to be multiple, but may be one.

In this embodiment, the number of address electrodes 41 ₁ to 41 _n connected to the first data driver group 4 a is the same as the number of address electrodes 42 ₁ to 42 _n connected to the second data driver group 4 b, but it is not limited thereto. The number of address electrodes in the first and second data driver groups 4a, 4b may be different.

Embodiment 2

The plasma display device 100 of Embodiment 2 has the same composition and operation as the plasma display device 100 of Embodiment 1 except for the following points.

In plasma display device 100 according to Embodiment 2, recovery potential clamping circuit 81 provided in first power recovery circuit 8a and second power recovery circuit 8b is different from recovery potential clamping circuit 80 in FIG. 6 in configuration.

FIG. 21 is a circuit diagram of the first data driver group 4a, the first power recovery circuit 8a, and the PDP 7 according to the second embodiment. In FIG. 21, the recovery potential clamping circuit 81 includes a resistor R3, diodes D3 and D4, and a bipolar transistor (hereinafter simply referred to as a transistor) Q5.

In recovery potential clamping circuit 81, diode D3 is connected between node N3 and node N4, node N4 is connected to the emitter of transistor Q5, and the collector of transistor Q5 is connected to the ground terminal through resistor R3. The power supply terminal V2 is connected to the base of the transistor Q5. A diode D4 is connected between the power supply terminal V2 and the node N4.

During the TA period to the TC period in FIG. 7, the recovery potential clamp circuit 81 of the first power recovery circuit 8a operates as follows.

In the recovered potential clamp circuit 81, the limit voltage Vr of the first embodiment is applied to the power supply terminal V2 in advance. On the other hand, the recovery potential Vm of the node N3 is supplied to the node N4. The recovery potential Vm changes according to the operation of the first data driver group 4a described later. Here, for simplicity of description, the voltage drop of the diode D3 is ignored.

The transistor Q5 is turned off when the limit voltage Vr of the power supply terminal V2 is equal to or higher than the voltage of the node N4, and is turned on when the limit voltage Vr of the power supply terminal V2 is lower than the voltage of the node N4. That is, the transistor Q5 is turned off when the recovery potential Vm of the node N3 is equal to or lower than the limit voltage Vr, and is turned on when the recovery potential Vm of the node N3 is higher than the limit voltage Vr.

Accordingly, when the recovery potential Vm is lower than or lower than the limit voltage Vr, the transistor Q5 is turned off, and the charge stored in the recovery capacitor C1 is retained and not released to the ground terminal.

When the recovery potential Vm of the node N3 is higher than the limit voltage Vr, the transistor Q5 is turned on, so the charge stored in the recovery capacitor C1 is released to the ground terminal through the node N3, the diode D3, the node N4, the transistor Q5 and the resistor R3. As a result, the recovery potential Vm of the node N3 does not exceed the limit voltage Vr.

When considering the voltage drop of the diode D3 in the above description, the voltage applied to the power supply terminal V2 is set to be lower than the limit voltage Vr by the percentage of the voltage drop of the diode D3. The voltage drop of the diode D3 is, for example, 0.7V.

In this way, the recovery potential clamp circuit 81 performs a clamping operation when the recovery potential Vm of the node N3 exceeds the limit voltage Vr. Therefore, the recovery potential Vm does not exceed the limit voltage Vr.

In this way, in the recovery potential clamping circuit 81 of the first and second power recovery circuits 8a and 8b of the plasma display device 100 according to the second embodiment, the limit voltage Vr is directly applied to the power supply terminal V2, thereby making it easy to adjust the gate voltage of the transistor Q5. applied voltage.

Embodiment 3

The plasma display device 100 of Embodiment 3 has the same composition and operation as the plasma display device 100 of Embodiment 1 except for the following points.

In plasma display device 100 according to Embodiment 3, recovery potential clamping circuit 82 provided in first power recovery circuit 8 a and second power recovery circuit 8 b is different from recovery potential clamping circuit 80 in FIG. 6 in configuration.

FIG. 22 is a circuit diagram of the first data driver group 4a, the first power recovery circuit 8a, and the PDP 7 according to the third embodiment. In FIG. 22, the recovery potential clamp circuit 82 includes a Zener diode D5.

In the recovered potential clamp circuit 82, a Zener diode D5 is connected between the node N3 and the ground terminal. Node N3 is connected to the cathode of Zener diode D5. When a voltage exceeding the limit voltage Vr of the first embodiment is applied to the cathode of the Zener diode D5, a reverse current flows.

During the TA period to the TC period in FIG. 7, the recovery potential clamp circuit 82 of the first power recovery circuit 8a performs the operation shown below.

In the recovery potential clamp circuit 82, the cathode of the Zener diode D5 supplies the recovery potential Vm of the node N3. The recovery potential Vm changes according to the operation of the first data driver group 4a described later. As described above, when a voltage exceeding the limit voltage Vr is applied to the cathode of the Zener diode D5, a reverse current flows. Accordingly, the Zener diode D5 does not flow current when the recovery potential Vm of the node N3 is equal to or lower than the limit voltage Vr, and flows a reverse current when the recovery potential Vm of the node N3 is higher than the limit voltage Vr.

Accordingly, when the recovery potential Vm is lower than or lower than the limit voltage Vr, the charge stored in the recovery capacitor C1 is retained and not discharged to the ground terminal.

When the recovery potential Vm of the node N3 is higher than the limit voltage Vr, the charges stored in the recovery capacitor C1 are discharged to the ground terminal through the Zener diode D5. As a result, the recovery potential Vm of the node N3 does not exceed the limit voltage Vr.

In this way, the recovery potential clamp circuit 82 performs a clamping operation when the recovery potential Vm of the node N3 exceeds the limit voltage Vr. Therefore, the recovery potential Vm does not exceed the limit voltage Vr.

In the plasma display device 100 according to the third embodiment, the recovery potential Vm of the node N3 is controlled only by the Zener diode D5 in the recovery potential clamp circuit 82 of the first and second power recovery circuits 8a, 8b. Therefore, it is easy to compose.

Embodiment 4

The plasma display device 100 of Embodiment 4 has the same composition and operation as the plasma display device 100 of Embodiment 1 except for the following points.

FIG. 23 is a block diagram showing the basic configuration of plasma display device 100 according to Embodiment 4. As shown in FIG.

Plasma display device 100 according to Embodiment 4 further includes cumulative rise count detector 20 in addition to the composition of plasma display device 100 according to Embodiment 1.

The accumulated rising times detector 20 is connected to the video signal-subfield correspondent 2 and also connected to the subfield processor 3 at the same time. The accumulative rise count detector 20 calculates the rise count of the data pulse Pda applied to a plurality of address electrodes 41 ₁ to 41 _n , 42 ₁ to 42 _n based on the image data SP supplied from the video signal-subfield correspondent 2, that is, calculates and controls The rising times of the pulses Sa ₁ to _San are given to the sub-field processor 3 with a count signal SL indicating the times.

FIG. 24 is a block diagram illustrating the configuration of the subfield processor 3 according to the fourth embodiment.

As shown in FIG. 24 , the subfield processor 3 according to Embodiment 4 includes a rise count comparator 31 , a recovery switching determination unit 32 , and a control signal generator 33 .

In the subfield processor 3 , the count signal SL from the cumulative rising count detector 20 is supplied to the rising count comparator 31 .

The subfield processor 31 stores in advance the maximum number of times the control pulses Sa ₁ -Sa _n can rise in each subfield. The rise count comparator 31 calculates the rise rate based on the count signal SL.

Furthermore, the number-of-up comparison circuit 31 judges whether or not the calculated rise ratio is greater than or equal to the power consumption switching ratio β%, and supplies a judgment signal UC indicating the judgment result to the recovery switching determination unit 32 . Also in the rise count comparator 31, the power consumption switching ratio β% is stored in advance. The setting of the power consumption switching ratio β% will be described later.

The recovery switching determination unit 32 generates a switching signal CT for the switching control signal S2 based on the discrimination signal UC supplied from the rising frequency comparison circuit 31 .

The switching signal CT is at a high level when, for example, the calculated rising rate is greater than or equal to the power consumption switching rate β%, and is at a low level when the calculated rising rate is less than the power consumption switching rate β%. The generated switching signal CT is supplied to the control signal generator 33 .

The control signal generator 33 generates the data driver control signals DSa and DSb, the power recovery circuit control signals Ha and Hb, the scan driver control signal CS and the hold driver control signal CS according to the image data SP of the subfield supplied by the video signal-subfield corresponding device 2. The signal US also generates control signals S1-S4 according to the image data SP and the switching signal CT.

The control signal S2 is generated based on the switching signal CT supplied from the recovery switching determination unit 32, and supplied to the transistors Q2 of the first and second power recovery circuits 8a and 8b (FIG. 6). The control signal S2 switches the transistor Q2 on and off according to whether the rising ratio calculated by the rising times comparator 31 is greater than or equal to the power consumption switching ratio β%. Thus, the power recovery method of plasma display device 100 according to Embodiment 4 is switched. The details thereof will be described later.

In this embodiment, instead of the accumulative rising count detector 20, a cumulative falling count detector may be used. At this time, the cumulative falling count detector counts the falling counts of the control pulses Sa ₁ to _San , and supplies the count signal SL indicating the count to the subfield processor 3 . Then, in the subfield processor 3, the same processing as described above is performed based on the supplied reception signal SL.

FIG. 25 is a graph showing the operations of the first and second power recovery circuits 8a, 8b in FIG. 23 during the writing period when the power recovery mode is switched according to the switching signal CT when the calculated rising rate is equal to or greater than the power consumption switching rate β%. timing diagram. In FIG. 25 , the waveforms of the voltage NV1 at the node N1 in FIG. 6 and the control signals S1 to S4 respectively supplied to the transistors Q1 to Q4 are indicated by solid lines. Furthermore, signal waveforms of the voltage NV1 at the node N1 of the second data driver group 4b and the control signals S1 to S4 respectively supplied to the transistors Q1 to Q4 are indicated by dotted lines.

In FIG. 25 , the voltage NV1 of the first power recovery circuit 8a and the control signals S1 to S4 are marked with the symbol 8a in brackets, and the voltage NV1 of the second power recovery circuit 8b and the control signals S1 to S4 are followed by the symbols in brackets. 8b.

The transistors Q1-Q4 are turned on when the control signals S1-S4 are at a high level, and the transistors Q1-Q4 are turned off when the control signals S1-S4 are at a low level.

Changes in the control signals S1 to S4 and the voltage NV1 of the node N1 in the TA period and the TB period are the same as those in FIG. 7 of the first embodiment.

In the TC period, the control signal S4 is at a high level, and the control signals S1 to S3 are at a low level. Accordingly, the transistor Q4 is turned on, and the transistors Q1 to Q3 are turned off. At this time, the recovery capacitor C1 is connected to the recovery inductance L through the transistor Q4 and the diode D2, and the voltage NV1 of the node N1 is slowly decreased by utilizing the LC resonance of the recovery inductance L, the parasitic capacitance Cf and the plate capacitance Cp. At this time, the charges of the parasitic capacitance Cf and the plate capacitance Cp are recovered to the recovery capacitor C1 through the recovery inductor L, the diode D2 and the transistor Q4.

As described above, in the present embodiment, the switching of the power recovery method occurs by changing the control signal S2 in the TD period according to the switching signal CT.

At this time, in the TD period, the control signals S1 , S3 , and S4 are at low level, and the control signal S2 is at high level. As a result, the transistors Q1, Q3, and Q4 are turned off, and the transistor Q2 is turned on, thereby grounding the node N1.

As a result, the voltage NV1 of the node N1 that has dropped to a predetermined voltage value during the TC period drops sharply and is fixed at the ground potential Vg.

The first power recovery circuit 8a repeats the operation of the period TA to TD to recover the charge stored in the plate capacitance Cp and the parasitic capacitance Cf to the recovery capacitor C1, and at the same time supply the recovered charge to the plate capacitance Cp and the parasitic capacitance Cf.

At this time, the voltage NV1 of the node N1 is fixed at the power supply voltage Vda in the TB period, and the voltage NV1 of the node N1 is fixed at the ground voltage Vg in the TD period, so the value of the recovery potential Vm of the node N3 is half of the power supply voltage Vda One (variations AC of Figure 25).

In this way, in plasma display device 100 according to this embodiment, the power recovery method is switched according to the rising rate and the falling rate. This switching is performed to further reduce the power consumption in the address period of plasma display device 100 . The reduction in power consumption brought about by switching the power recovery mode will be described later.

26 is a graph showing the relationship between recovery potential Vm of plasma display device 100 according to Embodiment 4 and the cumulative number of rises of control pulses Sa ₁ to _San in each subfield. In FIG. 26 , the vertical axis represents the recovery potential Vm for each subfield, and the horizontal axis represents the cumulative rise numbers of the control pulses Sa ₁ to _San in each subfield.

In FIG. 26 , the relationship between the recovery potential Vm and the cumulative number of rises of the control pulses Sa ₁ to _San in each subfield is the same as that in FIG. 15 described in Embodiment 1 except for the points described below.

As described above, in the plasma display device 11 of the present embodiment, when the rising rate is equal to or greater than the power consumption switching rate β%, the TD period control signal S2 in FIG. 25 is at a high level. That is, the power recovery method is switched.

Here, the cumulative rising number or cumulative falling number of the control pulses Sa ₁ -Sa _n in each subfield when the rising ratio or falling ratio becomes the power consumption switching ratio β% is called the recovery mode switching number Ry.

In this embodiment, the power recovery mode is switched by forming the recovery mode switching number Ry by the cumulative rising number or cumulative falling number of the control pulses Sa _{1 -San} in each subfield. As a result, as shown in FIG. 25 and FIG. 26 , when the accumulated number of rises or accumulated drops is greater than or equal to the number Ry of switching the recovery mode, the value of the recovery potential Vm is one-half of the power supply voltage Vda.

The data circuit loss in the address period of plasma display device 100 of this embodiment will be described.

27 is a graph for comparing the power consumption of plasma display device 100 according to Embodiment 4 with the discharge of a plasma display device having another structure.

In this example, the plasma display device of Embodiment 1 and the existing recovery type plasma display device were used as comparison objects of the plasma display device 100 of the present embodiment.

In FIG. 27 , similar to FIG. 20 , the vertical axis represents a comparison of data circuit losses of the plasma display device 100 of Embodiment 4, the plasma display device of Embodiment 1, and the conventional recovery type plasma display device. The horizontal axis represents the rising ratio of the control pulses Sa ₁ to _San in each subfield.

In FIG. 27 , the relative change of the data circuit loss of the device, the plasma display device of Embodiment 1, and the existing recovery type plasma display device due to the rising ratio and falling ratio of the control pulses Sa1 to San of each subfield is compared with that of the embodiment. Figure 20 of 1 is the same. The dotted line L2 shows the relative loss of the data circuit of the conventional recycling type plasma display device, and the dotted line L3 shows the relative loss of the data circuit of the plasma display device according to the first embodiment.

The data circuit loss ratio of plasma display device 100 according to the present embodiment is shown by thick line L4.

Here, within the range of the arrow Bb in FIG. 27 , the relative data circuit loss ratio (dotted line L3) of the plasma display device according to Embodiment 1 is larger than the data circuit loss relative ratio (dotted line L2) of the conventional recovery type plasma display device. . The increase ratio of the data circuit loss relative to switching between the dashed-dotted line L3 and the dotted line L2 is defined as the power consumption switching ratio β%. This power consumption switching ratio β% is stored in advance in the rise count comparator 31 .

As shown in FIG. 27 , the data circuit loss relative ratio of plasma display device 100 is the same as that of the plasma display device of Embodiment 1 except for the range indicated by arrow Bb.

Within the range of the arrow Bb in FIG. 27 , the dotted line L2 overlaps with the thick line L4. That is, in the range where the rising ratio of each subfield is equal to or greater than the power consumption switching ratio β%, or the falling ratio of each subfield is greater than or equal to the range of the power consumption switching ratio β%, the plasma display device 100 of the present embodiment is switched to the same as the existing power consumption switching ratio. There is the same power recovery method as the recovery type plasma display device.

As a result, within the range of the arrow Bb, the relative data circuit loss ratio of the plasma display device 100 can be prevented from being larger than that of the conventional recycling type plasma display device. Furthermore, the plasma display device 100 of the present embodiment has a smaller maximum data circuit loss than the plasma display device of the first embodiment.

In this way, in plasma display device 100 according to Embodiment 4, the rising ratio of each subfield is equal to or greater than the power consumption switching ratio β% (the cumulative rising number is equal to or greater than the recovery mode switching number Ry) or the falling ratio of each subfield is equal to or greater than the power consumption In the range of switching ratio β% (accumulative drop number is greater than or equal to recovery mode switching number Ry), the same power recovery mode as that of the conventional recovery type plasma display device is switched. Therefore, the power consumption can be sufficiently reduced by using the optimal power recovery method in the entire range of the rising rate and the falling rate.

Here, the power consumption switching ratio β% is, for example, 95%. In this case, the plasma display device 100 according to the fourth embodiment is switched to the conventional recovery type plasma display in the range where the rising ratio of each subfield is equal to or greater than 95% or the falling ratio of each subfield is equal to or greater than 95%. The same power recovery method as the device.

Changes in the power consumption magnitude relationship between the non-recycling type plasma display device, the conventional recycling type plasma display device, and the plasma display device 100 of Embodiment 1 will be described with reference to FIG. 28 .

28 is a graph for comparing power consumption of a non-recovery type plasma display device, a conventional recovery type plasma display device, and the plasma display device 100 of Embodiment 1 when the rise rate of each subfield is 100% (in triple black and white).

28(a) shows the data pulse Pda applied to the address electrodes 41 ₁ to 41 _n and 42 ₁ to 42 _n of the non-recovery type plasma display device, and FIG. 28(b) shows the data pulse Pda applied to the conventional recovery type plasma display device. 28 _{(c) shows the data pulse Pda applied to the address electrodes 41 1 to 41 n and 42 1 to 42 n of the plasma display device according to} Embodiment 1. Data pulse Pda.

As shown in FIG. 28(a), when the rising rate is 100% (in triple black and white), the data pulses Pda and PDP7 applied to the address electrodes 41 ₁ to 41 _n and 42 ₁ to 42 _n of the non-recovery plasma display device are respectively The pixels rise and fall repeatedly, correspondingly. In this case, the power consumption of the non-recovery type plasma display device corresponds to a linear voltage change in the range indicated by the dotted line indicated by the arrow.

As shown in FIG. 28(b), when the rising rate is 100% (in the case of triple black and white), the data pulse Pda applied to the address electrodes 41 ₁ ~ 41 _n , 42 ₁ ~ 42 _n of the existing recovery type plasma display device and no recovery In the same way as the plasma display device of the PDP7, the rising and falling are repeated corresponding to each pixel of the PDP7. In this case, the power consumption of the conventional recycling type plasma display device corresponds to the linear voltage change in the dotted line range indicated by the arrow.

As shown in FIG. 28(c), when the rising rate is 100% (in triple black and white), the data pulses Pda and PDP7 applied to the address electrodes 41 ₁ to 41 _n and 42 ₁ to 42 _n of the plasma display device 100 according to the first embodiment are Each pixel of is repeated rising and falling correspondingly. In this case, the power consumption of plasma display device 100 according to Embodiment 1 corresponds to a linear voltage change in the range indicated by the dotted line indicated by the arrows.

The above-mentioned Fig. 28(a), (b) and (c) are compared. Compared with the degree of linear voltage change in Fig. 28(b) and (c), the degree of linear voltage change in Fig. 28(a) is very large. Therefore, the power consumption of the non-recovery type plasma display device is the largest when the rising ratio is 100% (in the case of triple black and white).

As shown in FIG. 28(c), in plasma display device 100 according to Embodiment 1, the voltage of each data pulse Pda changes linearly at the start of rising and the end of rising. Therefore, power consumption occurs when each data pulse Pda rises and rises and ends.

On the other hand, as shown in FIG. 28(b), in the conventional recycling type plasma display device, the voltage of each data pulse Pda changes linearly at the end of the rise. As a result, power consumption occurs at the end of the rise of each data pulse Pda.

Therefore, when the increase rate is 100% (in triple black and white), the power consumption generated in the plasma display device 100 of Embodiment 1 is larger than that generated in the conventional recycling type plasma display device (the range indicated by the arrow Bb in FIG. 20 ). .

On the other hand, plasma display device 100 according to Embodiment 4 switches the power recovery method in the same manner as in the conventional recovery type plasma display device when the boost ratio is 100% (in triple black and white). Therefore, even when the rising ratio is 100% (in triple black and white), the power consumption of the plasma display device 100 according to Embodiment 4 can be prevented from being increased compared with the power consumption of a plasma display device having another configuration (FIG. 27 ).

Thus, in plasma display device 100 according to Embodiment 4, when the rising rate or falling rate exceeds the power consumption switching rate β%, the power recovery method is switched to the power recovery method of the conventional recovery type plasma display device. As a result, according to plasma display device 100 of Embodiment 4, power consumption can be sufficiently reduced even when the rising rate or falling rate exceeds the power consumption switching rate β%.

That is, plasma display device 100 according to Embodiment 4 can sufficiently reduce power consumption regardless of the light emitting state.

The power recovery circuit 8a and the second power recovery circuit 8b included in the plasma display device 100 according to Embodiment 4 are not limited to the configuration shown in FIG. 6, and may have the configuration shown in FIG. 21 or FIG. 22.

The rising count comparator 31 of FIG. 24 included in the plasma display device 100 according to Embodiment 4 calculates the rising rate based on the count signal SL from the accumulated rising count detector 20, and judges whether the calculated rising rate is equal to or greater than the power consumption switching rate β%. The signal UC representing the result of the judgment is supplied to the recycling switching determination unit 32 in FIG. , and a signal UC indicating the result of the determination is supplied to the recovery switching determination unit 32 .

In Embodiments 1 to 4 above, the plasma display device 100 corresponds to a display device, the plurality of address electrodes 41 ₁ to 41 _n and 42 ₁ to 42 _n correspond to the first electrodes, and the plurality of scan electrodes 12 ₁ to 12 _m correspond to the first electrodes. The second electrode, the discharge unit 14 is equivalent to the capacitive light-emitting element, the PDP7 is equivalent to the display panel, the sub-field processor 3, the circuit composed of the first data driver group 4a and the first power recovery circuit 8a, and the second data driver group 4b and The circuit constituted by the second power recovery circuit 8b corresponds to a drive circuit.

Voltage NV1 at node N1 in FIG. 6 corresponds to a drive pulse, write period P2 in FIGS. 2 and 3 corresponds to an address period, data pulse phase difference TR corresponds to a phase difference, and data pulse Pda corresponds to a data pulse.

The power supply voltage Vda corresponds to the first power supply voltage, the power supply terminal V1 corresponds to the first power supply terminal, the node N1 in FIG. 6 corresponds to the first node, the N-channel field effect transistor Q1 corresponds to the first switching element, and the N-channel field effect transistor Q2 Corresponds to the second switching element.

The node N2 corresponds to the second node, the recovery inductance L corresponds to the inductive element, the node N3 corresponds to the third node, the N-channel field effect transistor Q3 corresponds to the third switching element, and the N-channel field effect transistor Q4 corresponds to the fourth switching element , the recovery capacitor C1 is equivalent to the capacitive element for recovery.

The limit voltage Vr is equivalent to a predetermined value, the recovery potential clamping circuits 80 and 81 are equivalent to potential limiting circuits, the P-channel field effect transistors Q1 ₁ to Q1 _n are equivalent to the first switch circuit, and the P-channel field effect transistors Q2 ₁ to Q2 _n are equivalent to In the second switch circuit, the voltage NV5 at the node N5 in FIG. 6 and the voltage applied to the power terminal V2 in FIG. 21 correspond to the control signal, the voltage applied to the power terminal V2 corresponds to the second power voltage, and the power terminal V2 corresponds to the second power supply voltage. 2 power terminals.

Diodes D3 and D4, bipolar transistor Q5 and resistor R3 are equivalent to the second switch circuit, node N4 is equivalent to the fourth node, bipolar transistor Q5 is equivalent to the fifth switching element, diode D3 and Zener diode D5 are equivalent to unidirectional conduction Components, charging excitation circuits CG1, CG2 correspond to charging excitation circuits.

The nodes Na and Nc correspond to the fifth node, the capacitors CCp1 and CCp2 correspond to charging capacitive elements, the power supply terminals Vp2 and Vp4 correspond to the third power supply terminals, and the voltage (15V) applied to the power supply terminals Vp2 and Vp4 corresponds to the third power supply voltage, diodes Dp1 and Dp2 are equivalent to unidirectional conduction elements, and FET drivers FD1 and FD2 are equivalent to control signal output circuits.

The first power recovery circuit 8a and the second power recovery circuit 8b are equivalent to the application circuit, the resistors R1, R2 and the node N5 are equivalent to the dividing circuit, the cumulative rising number detector 20 is equivalent to the number detection part, the sub-field processor 3, the rising number of times The comparator 31 , the recovery switching determination unit 32 and the control signal generator 33 correspond to a control unit. The rise ratio and the fall ratio correspond to the ratio of the number of times calculated by the count detection unit to the maximum number of possible rises or the maximum possible number of falls of the data pulse. The image data SP corresponds to image data, and the video signal-subfield mapper 2 corresponds to a conversion unit.

Claims (22)

1, a kind of display device is characterized in that, has

Comprise the 1st electrode that is categorized into a plurality of groups,

Be arranged to the 2nd electrode of described the 1st electrode crossing,

Possess the cross part that is arranged on described the 1st electrode and described the 2nd electrode a plurality of capacitive light emitting elements display board and

Driving circuit, this driving circuit apply the data pulse of the capacitive light emitting elements illuminating that makes selection respectively to the 1st described a plurality of groups electrode, make to produce phase differential mutually among the described a plurality of group,

Described driving circuit comprises

The recovery capacitive element,

By from described recovery with capacitive element to described the 1st electrode discharge or will be recovered to described recovery capacitive element from the electric charge of described the 1st electrode, make apply driving pulse that data pulse uses be applied to described the 1st electrode apply circuit and

The current potential restricting circuits, this current potential restricting circuits is recovered to described recovery by restriction and limits with the quantity of electric charge of capacitive element, makes described recovery be no more than setting with the current potential of capacitive element.

2, a kind of display device is characterized in that, has

Comprise the 1st electrode that is categorized into a plurality of groups,

Be arranged to the 2nd electrode of described the 1st electrode crossing,

Possess the cross part that is arranged on described the 1st electrode and described the 2nd electrode a plurality of capacitive light emitting elements display board and

Driving circuit, this driving circuit apply the data pulse of the capacitive light emitting elements illuminating that makes selection respectively to the 1st described a plurality of groups electrode, make to produce phase differential mutually among the described a plurality of group,

Described driving circuit comprises

Inductive element,

The recovery capacitive element,

Electric capacity by utilizing described display board and the running of the resonance of described inductive element, from described recovery with capacitive element to described the 1st electrode discharge, or will be recovered to described recovery capacitive element by described inductive element from the electric charge of described the 1st electrode, make to the 1st described a plurality of groups electrode apply driving pulse that data pulse uses be applied to described the 1st node apply circuit and

The current potential restricting circuits, this current potential restricting circuits is recovered to described recovery by restriction and limits with the quantity of electric charge of capacitive element, makes described recovery be no more than setting with the current potential of capacitive element.

3, a kind of display device is characterized in that, has

Comprise the 1st electrode that is categorized into a plurality of groups,

Be arranged to the 2nd electrode of described the 1st electrode crossing,

Possess the cross part that is arranged on described the 1st electrode and described the 2nd electrode a plurality of capacitive light emitting elements display board and

Driving circuit, this driving circuit apply the data pulse of the capacitive light emitting elements illuminating that makes selection respectively to the 1st described a plurality of groups electrode, make to produce phase differential mutually among the described a plurality of group,

Described driving circuit comprises

Accept the 1st supply voltage the 1st power supply terminal,

Inductive element,

The recovery capacitive element,

Utilize the resonance running of the electric capacity and the described inductive element of described display board, discharge electric charge from described recovery with capacitive element, the current potential of the 1st node is risen, after connecting described the 1st node and described the 1st power supply terminal, cut off being connected of described the 1st node and described the 1st power supply terminal, and utilize described resonance running by described inductive element electric charge to be recovered to described recovery capacitive element from described the 1st node, the current potential of described the 1st node is descended, thereby will apply the circuit that applies that driving pulse that data pulse uses is applied to described the 1st node the 1st described a plurality of groups electrode, and

The current potential restricting circuits, this current potential restricting circuits is recovered to described recovery by restriction and limits with the quantity of electric charge of capacity cell, makes described recovery be no more than the setting that is lower than described the 1st supply voltage with the current potential of capacitive element.

4, the display device described in claim 3 is characterized in that,

Described inductive element is arranged between described the 1st node and the 2nd node, described recovery is connected to the 3rd node with capacitive element,

Described current potential restricting circuits limits by the current potential that limits described the 3rd node, makes the current potential of described capacitive element be no more than setting;

The described circuit that applies comprises

Be arranged on the 1st on-off element between described the 1st power supply terminal and described the 1st node,

Be arranged on the ground terminal of accepting earthing potential and the 2nd on-off element between described the 1st node,

Be arranged between described the 2nd node and described the 3rd node the 3rd on-off element and

Be arranged on the 4th on-off element between described the 2nd node and described the 3rd node;

During the address of the selected described capacitive light emitting elements illuminating that makes described display board, described the 3rd on-off element conducting, thereby described capacitive element discharges electric charge by described inductive element to described the 1st node, after making the current potential rising of described the 1st node, described the 3rd on-off element disconnects, described the 1st on-off element conducting, after thereby the current potential of described the 1st node rises to described the 1st supply voltage, described the 1st on-off element disconnects, described the 4th on-off element conducting, make electric charge be recovered to reclaim by described inductive element and use capacity cell from described the 1st node, and the decline of the current potential of described the 1st node, thereby described driving pulse produced.

5, the display device described in claim 3 is characterized in that,

Described driving circuit also comprises the 1st on-off circuit that should be provided with described the 1st electrode pair, and

Operate, make, between described the 1st node and described the 1st electrode, carry out the recovery and the release of electric charge, disconnect, set described the 1st electrode of correspondence for earthing potential by described the 1st on-off circuit by described the 1st on-off circuit conducting.

6, the display device described in claim 4 is characterized in that,

Described current potential restricting circuits comprises

By dividing the voltage between described the 1st supply voltage and the earthing potential, produce the current potential that is substantially equal to described setting the division circuit and

The 2nd on-off circuit, the 2nd on-off circuit are connected between described the 3rd node and the described earthing potential, and the current potential that receives described division circuit generation simultaneously is as control signal, and conducting when the current potential of described the 3rd node surpasses described setting.

7, the display device described in claim 4 is characterized in that,

Described current potential restricting circuits comprises

Acceptance be substantially equal to described setting the 2nd supply voltage the 2nd power supply terminal and

The 2nd on-off circuit, the 2nd on-off circuit are connected between described the 3rd node and the described earthing potential, and the 2nd supply voltage that receives described the 2nd power supply terminal acceptance simultaneously is as control signal, and conducting when the current potential of described the 3rd node surpasses described setting.

8, the display device described in claim 6 is characterized in that,

Described the 2nd on-off circuit comprises

Be arranged between described the 3rd node and the 4th node, and make electric current from described the 3rd node flow to described the 4th node unidirectional breakover element and

Be arranged between described the 4th node and the described ground terminal, and have the 5th on-off element of the control terminal that receives described control signal.

9, the display device described in claim 4 is characterized in that,

Described current potential restricting circuits comprises

Be arranged between described the 3rd node and the described ground terminal, and when the current potential of described the 3rd node surpasses setting, make electric current flow to the unidirectional breakover element of described ground terminal from described the 3rd node.

10, the display device described in claim 9 is characterized in that,

Described unidirectional breakover element is a Zener diode.

11, the display device described in claim 4 is characterized in that,

Also have generation than the high current potential of the current potential of described the 1st node so that make the charging exciting circuit of described the 1st on-off element conducting.

12, the display device described in claim 11 is characterized in that,

Described charging exciting circuit comprises

Be arranged between described the 1st node and described the 5th node charging with capacity cell,

Be arranged between the 3rd power supply terminal and described the 5th node of accepting the 3rd supply voltage, make electric current from described the 2nd power supply terminal flow to described the 5th node unidirectional breakover element and

The current potential of described the 5th node is added on described the 1st node potential, and gained current potential after the addition is outputed to the control signal output circuit of described the 1st on-off element as control signal.

13, the display device described in claim 3 is characterized in that,

Described setting is greater than 1/2nd of described the 1st supply voltage, and smaller or equal to 4/5ths of described the 1st supply voltage.

14, the display device described in claim 3 is characterized in that,

Described phase differential is more than or equal to 200ns.

15, the display device described in claim 3 is characterized in that,

Have a plurality of described driving circuits,

Described a plurality of driving circuits are arranged to correspond respectively to described a plurality of group,

A plurality of described driving circuits apply the data pulse that makes selected capacitive light emitting elements illuminating to described a plurality of groups described the 1st electrode respectively, make to produce phase differential mutually among the described a plurality of group.

16, the display device described in claim 3 is characterized in that,

Also have the rising number of times that detects the data pulse be applied to described the 1st electrode or the number of times testing circuit of decline number of times,

Described driving circuit also comprises control part, this control part calculates the detected described number of times of described number of times test section to can the rise ratio of number of times or I decline number of times of data pulse maximum, and control the described running that applies circuit, make at described ratio during greater than the requirement ratio value, after the current potential of described the 1st node is reduced to the assigned voltage value, with described the 1st node ground connection.

17, the display device described in claim 16 is characterized in that,

Also have the transformation component that 1 view data is transformed into the view data of each son, so that be divided into a plurality of sons with 1, and every make selected described capacitive light emitting elements discharge, shows thereby carry out gray scale;

The view data that described number of times test section is supplied with according to described transformation component detects each described number of times of sub;

Described control part calculates the detected described number of times of described number of times test section to can the rise ratio of number of times or I decline number of times of data pulse maximum of each son, and control the described running that applies circuit, make at described ratio during greater than the requirement ratio value, after the current potential of described the 1st node is reduced to the assigned voltage value, with described the 1st node ground connection.

18, the display device described in claim 16 is characterized in that,

The rate value of described regulation is more than or equal to 95%.

19, a kind of display-apparatus driving method, this display device comprises and has the 1st electrode that is categorized into a plurality of groups, is arranged to and the 2nd electrode of described the 1st electrode crossing and the display board that possesses a plurality of capacitive light emitting elements of the cross part that is arranged on described the 1st electrode and described the 2nd electrode, it is characterized in that

Comprise the data pulse that respectively the 1st described a plurality of groups electrode is applied the capacitive light emitting elements illuminating that makes selection, make the step that produces phase differential among the described a plurality of group mutually,

The described step that applies data pulse comprises

Utilize the resonance running of the electric capacity and the inductive element of described display board, discharge electric charge from reclaiming with capacitive element, the current potential of the 1st node is risen, after connecting described the 1st node and the 1st power supply terminal, cut off being connected of described the 1st node and described the 1st power supply terminal, and utilize described resonance running by described inductive element electric charge to be recovered to described recovery capacitive element from described the 1st node, the current potential of described the 1st node is descended, thereby will apply the step that driving pulse that data pulse uses is applied to described the 1st node the 1st described a plurality of groups electrode, and

Be recovered to described recovery by restriction and limit, make described recovery be no more than the step of the setting that is lower than described the 1st supply voltage with the current potential of capacitive element with the quantity of electric charge of capacity cell.

20, the display-apparatus driving method described in claim 19 is characterized in that, also has

Detection be applied to the rising number of times of data pulse of described the 1st electrode or decline number of times step and

Calculate detected described number of times to can the rise ratio of number of times or I decline number of times of data pulse maximum, and control the described running that applies circuit, make at described ratio during greater than the requirement ratio value, after the current potential of described the 1st node is reduced to the assigned voltage value, with the step of described the 1st node ground connection.

21, the display-apparatus driving method described in claim 20 is characterized in that,

Described requirement ratio value is more than or equal to 95%.

22, the display-apparatus driving method described in claim 19 is characterized in that,

Described setting is greater than 1/2nd of described the 1st supply voltage, and smaller or equal to 4/5ths of described the 1st supply voltage.

Images