CN100550400C

CN100550400C - Active elements array substrates and manufacture method thereof

Info

Publication number: CN100550400C
Application number: CN 200710193829
Authority: CN
Inventors: 高逸群; 蔡文庆; 林俊男; 蔡东璋; 石明昌; 曾贵圣
Original assignee: AU Optronics Corp
Current assignee: AU Optronics Corp
Priority date: 2007-11-26
Filing date: 2007-11-26
Publication date: 2009-10-14
Anticipated expiration: 2027-11-26
Also published as: CN101179085A

Abstract

The invention provides a kind of active elements array substrates and manufacture method thereof that can be applicable to display floater.In part embodiment of the present invention, owing to have second pad between first pad on the active elements array substrates and the 3rd pad, so the too high problem of interface resistance that the present invention was caused in the time of can avoiding first pad directly to contact with the 3rd pad.In addition, in other embodiments of the invention,, therefore can effectively improve the reliability of product because first patterned conductive layer, second patterned conductive layer and the 3rd patterned conductive layer on the active elements array substrates can be electrically connected to each other.

Description

Active elements array substrates and manufacture method thereof

Technical field

The present invention relates to a kind of display floater and manufacture method thereof, and be particularly related to a kind of active elements array substrates and manufacture method thereof.

Background technology

Along with scientific and technological progress, LCD (liquid crystal display, LCD) and plasma display (plasma display panel, PDP) etc. flat-panel monitor (flat panel display) replaces early stage cathode-ray tube display gradually (cathode ray tube CRT) becomes the main flow of display commodity.Flat-panel monitor commodity now are mostly based on LCD, and at present LCD with Thin Film Transistor-LCD (Thin Film Transistor Liquid Crystal Display, TFT-LCD) general.The display panels of general colorful film transistor liquid crystal display (TFT-LCD) is made of thin-film transistor array base-plate, colored optical filtering substrates and liquid crystal layer.

Fig. 1 is the generalized section of the active elements array substrates of known thin-film transistor.Please refer to Fig. 1, known active elements array substrates 100 comprises substrate 110, a plurality of grid 120a, a plurality of first pad 120b, gate insulator 130, a plurality of channel layer 140, a plurality of source electrode 150, a plurality of drain electrode 152, protective layer 160 and transparency conducting layer 170.

The above-mentioned grid 120a and the first pad 120b are formed by first conductive layer, 120 patternings.Gate insulator 130 is covered on the grid 120a and the first pad 120b, and gate insulator 130 is between channel layer 140 and grid 120a, and channel layer 140 is positioned at the top of grid 120a.The

source electrode

150 and 152 both sides that are covered in channel layer 140 respectively that drain.Above-mentioned grid 120a, gate insulator 130, channel layer 140, source electrode 150 and the 152 formation thin-film transistors 101 that drain.Protective layer 160 cover grid insulating barriers 130, channel layer 140, source electrode 150 and drain 152.Protective layer 160 has contact hole 164, to expose part drain electrode 152.Gate insulator 130 has contact hole 162 with protective layer 160, to expose the part first pad 120b.Transparency conducting layer 170 can be divided into via contact hole 164 and the drain electrode 152 pixel electrode 170a that are electrically connected, and the transparent pad 170b that is electrically connected with the first pad 120b via contact hole 162.

The first pad 120b is usually located at the end of scan line, and it is also referred to as the scanning pad, and near the edge of display floater.The first pad 120b via transparent pad 170b and anisotropy conducting film (ACF) be electrically connected in order to the integrated circuit (IC) that drives panel.Generally speaking, the material of first conductive layer is an aluminium, and the material of transparency conducting layer 170 is indium tin oxide (ITO).Because the interface resistance between aluminium and the ITO is higher, so between the first pad 120b and the transparent pad 170b resistance problem of higher is arranged just.Therefore, there are problems such as electrical characteristic is poor, power consumption height, production reliability is low and lack useful life in these active elements array substrates 100 regular meetings.Though foregoing problems can be overcome by metals such as deposition one deck molybdenum or titanium on aluminium, because the price of molybdenum or titanium is than the aluminium costliness, so first pad of this multilayer can increase manufacturing cost.Moreover; because of still existing gate insulator 130 and protective layer 160 to make transparency conducting layer 170b be formed at this moment on the first pad 120b; be subject to the existence of this height fall and may make transparency conducting layer 170b can produce the crack in this contact hole 162, cause signal to transmit bad.

Summary of the invention

The invention provides a kind of active elements array substrates, it can solve pad and directly contact the excessive problem of interface resistance that is caused with first patterned conductive layer.

The invention provides a kind of active elements array substrates, its can solve that pad produces the crack in contact hole and the signal that causes transmit the problem of bad.

The present invention provides a kind of manufacture method of active elements array substrates in addition, and it can revised under the situation of existing technology not significantly, solves pad and directly contacts the excessive problem of interface resistance that is caused with first patterned conductive layer.

The present invention provides a kind of active elements array substrates and manufacture method thereof again, and it can solve pad and connect the excessive problem of pad resistance that two conductive layers are caused.

The present invention provides a kind of manufacture method of active elements array substrates again, and it can revised under the situation of existing technology not significantly, solves pad and connects the excessive problem of pad resistance that two conductive layers are caused.

The invention provides a kind of active elements array substrates, it comprises substrate, first patterned conductive layer, pattern dielectric layer, a plurality of channel layer, second patterned conductive layer, patterning protective layer and the 3rd patterned conductive layer.First patterned conductive layer is disposed on the substrate, and first patterned conductive layer comprises a plurality of grids and a plurality of first pad.Pattern dielectric layer is disposed on the substrate, and pattern dielectric layer comprises the first dielectric block that covers these these grids and the second dielectric block that exposes this these first pad, and the thickness of the first dielectric block is in fact greater than the thickness of the second dielectric block.A plurality of channel layers are disposed on the pattern dielectric layer of each grid top.Second patterned conductive layer is disposed on pattern dielectric layer and these channel layers, and second patterned conductive layer comprises a plurality of source electrode and drain electrodes that are positioned at top, each grid both sides, and a plurality of second pad that is positioned on each first pad.The patterning protective layer covers second patterned conductive layer, and wherein the patterning protective layer exposes these drain electrodes and these second pads.The 3rd patterned conductive layer is disposed on the patterning protective layer, and wherein the 3rd patterned conductive layer comprises a plurality of pixel electrodes that are connected with each drain electrode and a plurality of the 3rd pad that is positioned on each second pad.

According to active elements array substrates of the present invention, wherein said first patterned conductive layer also comprises the multi-strip scanning line, and wherein said multi-strip scanning line is electrically connected with described a plurality of first pads of described a plurality of grids and part.

According to active elements array substrates of the present invention, wherein said second patterned conductive layer also comprises many data wires, and wherein said many data wires are electrically connected with described a plurality of first pads of described a plurality of source electrodes and part.

The present invention provides a kind of manufacture method of active elements array substrates in addition, and it comprises the following steps.At first, provide substrate.Afterwards, form first patterned conductive layer on substrate, and first patterned conductive layer comprises a plurality of grids and a plurality of first pad.Then, form pattern dielectric layer on substrate, so that pattern dielectric layer comprises first dielectric block that covers these grids and the second dielectric block that exposes these first pads, and the thickness of the first dielectric block is greater than the thickness of the second dielectric block.Next, form a plurality of channel layers and second patterned conductive layer simultaneously on pattern dielectric layer, so that each channel layer is formed at each grid top, and second patterned conductive layer comprises a plurality of source electrode and drain electrodes that are positioned at each top, grid both sides, and a plurality of second pads that are positioned on each first pad, wherein grid, channel layer, source electrode and drain electrode constitute thin-film transistor.Then, form the patterning protective layer on pattern dielectric layer and each thin-film transistor, so that the patterning protective layer exposes these drain electrodes and these second pads.At last, form the 3rd patterned conductive layer on the patterning protective layer, wherein the 3rd patterned conductive layer comprises a plurality of pixel electrodes that are connected with each drain electrode and a plurality of the 3rd pad that is positioned on each second pad.

According to the manufacture method of active elements array substrates of the present invention, the method that wherein forms described pattern dielectric layer comprises: form dielectric layer and semiconductor layer on described first patterned conductive layer; On described semiconductor layer, form the first photoresist layer, the wherein said first photoresist layer is divided into first photoresist block that is positioned at described a plurality of thin-film transistors top and the second photoresist block that is adjacent to described first block, the described second photoresist block is positioned on the described semiconductor layer of described non-display area, the described second photoresist block has a plurality of openings that are positioned at described a plurality of first pads top, and the thickness of the described first photoresist block is in fact greater than the thickness of the described second photoresist block; With the described first photoresist layer is that mask carries out first etch process to described semiconductor layer and described pattern dielectric layer; Reduce the thickness of the described first photoresist layer, removed fully up to the described second photoresist block; And be that mask carries out second etch process to described semiconductor layer and described pattern dielectric layer with the remaining described first photoresist block, to expose described a plurality of first pad.

Manufacture method according to active elements array substrates of the present invention, the formation method of the wherein said first photoresist layer comprises: with first photomask is mask, the described first photo anti-corrosion agent material layer is exposed, and wherein said first photomask has transparent area corresponding to described a plurality of openings, corresponding to the shading region of the described first photoresist block and corresponding to the semi-opaque region of the described second photoresist block; And the described first photo anti-corrosion agent material layer carried out developing process.

According to the manufacture method of active elements array substrates of the present invention, wherein said first photomask comprises semi-modulation type photomask or tone photomask.

According to the manufacture method of active elements array substrates of the present invention, the method that wherein reduces the described first photoresist layer thickness comprises carries out cineration technics.

According to one pixel structure process method of the present invention, the method that wherein forms described a plurality of channel layer and described second patterned conductive layer simultaneously comprises: form second conductive layer on described pattern dielectric layer; Form the second photoresist layer on described second conductive layer; With the described second photoresist layer is that mask removes described second conductive layer of part and the described semiconductor layer of part, so that remaining described second conductive layer of each described grid top constitutes described source electrode and described drain electrode, and make the described semiconductor layer of each described grid top constitute described channel layer, and make remaining described second metal level on each described first pad constitute described second pad.

Manufacture method according to active elements array substrates of the present invention, the formation method of the wherein said second photoresist layer comprises: with second photomask is mask, the described second photoresist layer is exposed, and wherein said second photomask has transparent area and shading region; And the described second photo anti-corrosion agent material layer carried out developing process.

Manufacture method according to active elements array substrates of the present invention; wherein when forming described patterning protective layer; also comprise and form a plurality of first contact hole and a plurality of second contact holes that expose each described second pad that expose each described drain electrode; be connected with each described drain electrode so that each described pixel electrode passes through each described first contact hole, and each described the 3rd pad is connected with each described second pad by each described second contact hole.

The present invention provides a kind of active elements array substrates again, and it comprises substrate, first patterned conductive layer, pattern dielectric layer, a plurality of channel layer, a plurality of source electrode and drain electrode, a plurality of second pad, patterning protective layer and the 3rd patterned conductive layer.First patterned conductive layer is disposed on the substrate, and first patterned conductive layer comprises a plurality of grids and a plurality of first pad.Pattern dielectric layer is disposed on the substrate, and pattern dielectric layer covers these grids and these first pads, and pattern dielectric layer has a plurality of first contact holes, to expose each first pad of part.A plurality of channel layers are disposed on the pattern dielectric layer of each grid top.Second patterned conductive layer is disposed on pattern dielectric layer and these channel layers, and second patterned conductive layer comprises a plurality of source electrodes and drain electrode and a plurality of second pad.A plurality of source electrodes and drain electrode are positioned at each top, grid both sides.A plurality of second pads are electrically connected to these first pads via these first contact holes.The patterning protective layer covers second patterned conductive layer.The 3rd patterned conductive layer is disposed on the patterning protective layer; wherein the patterning protective layer has a plurality of second contact holes to expose each second pad of part; and pattern dielectric layer and patterning protective layer have the 3rd contact hole to expose each first pad of part; and the 3rd patterned conductive layer via these second contact hole electrical wirings to these second pads and these drain electrodes, and via these the 3rd contact hole electrical wirings to these first pads.

According to active elements array substrates of the present invention, wherein said the 3rd patterned conductive layer has the 3rd pad that pixel electrode that a plurality of and described drain electrode is electrically connected and a plurality of and described a plurality of first pad and described a plurality of second pad are electrically connected.

The present invention provides a kind of manufacture method of active elements array substrates again, and it comprises the following steps.At first, provide substrate.Then, form first patterned conductive layer on substrate, first patterned conductive layer comprises a plurality of grids and a plurality of first pad.Afterwards, form pattern dielectric layer on substrate, so that pattern dielectric layer covers these grids and these first pads.Next, formation is a plurality of on pattern dielectric layer simultaneously is arranged in the channel layer of each grid top and forms a plurality of first contact holes in pattern dielectric layer, and wherein these first contact holes expose each first pad of part.Then, form second patterned conductive layer on pattern dielectric layer, wherein second patterned conductive layer comprises a plurality of source electrode and drain electrode and a plurality of second pads that are positioned at each top, grid both sides, grid, channel layer, source electrode and drain electrode constitute thin-film transistor, and these second pads are electrically connected to these first pads via these first contact holes.Then; form the patterning protective layer on pattern dielectric layer, each thin-film transistor and these second pads; wherein the patterning protective layer has a plurality of second contact holes exposing each second pad of part, and pattern dielectric layer and patterning protective layer have the 3rd contact hole to expose partly each pad.At last, form the 3rd patterned conductive layer on the patterning protective layer, wherein the 3rd patterned conductive layer is electrically connected to these second pads and these drain electrodes via these second contact holes, and is electrically connected to these first pads via these the 3rd contact holes.

According to the manufacture method of active elements array substrates of the present invention, the method that wherein forms described channel layer and described a plurality of first contact holes simultaneously comprises: form dielectric layer and semiconductor layer on described first patterned conductive layer; On described semiconductor layer, form the photoresist layer, wherein said photoresist layer is divided into first photoresist block that is positioned at described a plurality of thin-film transistors top and the second photoresist block that is adjacent to described first block, the described second photoresist block is positioned on the described semiconductor layer of described non-display area, the described second photoresist block has a plurality of openings that are positioned at described first contact hole top, and the thickness of the described first photoresist block is greater than the thickness of the described second photoresist block; With described photoresist layer is that mask carries out first etch process to described semiconductor layer and described pattern dielectric layer; Reduce the thickness of described photoresist layer, removed fully up to the described second photoresist block; And be that mask carries out second etch process to described semiconductor layer and described pattern dielectric layer with the remaining described first photoresist block, form a plurality of first contact holes, to expose each described first pad of part.

Manufacture method according to active elements array substrates of the present invention, the formation method of wherein said photoresist layer comprises: be mask with the photomask, described photoresist layer is exposed, and wherein said photomask has corresponding to the transparent area of described a plurality of first contact holes, corresponding to the shading region of the described first photoresist block and corresponding to the semi-opaque region of the described second photoresist block; And the described first photo anti-corrosion agent material layer carried out developing process.

According to the manufacture method of active elements array substrates of the present invention, the method that wherein reduces described photoresist layer thickness comprises carries out cineration technics.

Because the pattern dielectric layer that part embodiment utilization of the present invention has two kinds of different-thickness allows first pad expose, so that follow-up second pad that is formed on the pattern dielectric layer can directly contact with first pad.By the connection of second pad, the interface resistance between the 3rd pad of first pad and follow-up formation can be lowered effectively.

Because part embodiment of the present invention forms a plurality of first contact holes when making channel layer, to allow first pad expose, so that follow-up second pad that is formed on the pattern dielectric layer can directly contact with first pad.By the connection of second pad, the interface resistance between the 3rd patterned conductive layer of first pad and follow-up formation can be lowered effectively.

For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.

Description of drawings

Fig. 1 is the generalized section of the active elements array substrates of known thin-film transistor.

Fig. 2 A to Fig. 2 J is the schematic flow sheet of manufacture method of the active elements array substrates of first embodiment of the invention.

Fig. 2 K be first embodiment of the invention active elements array substrates on look schematic diagram.

Fig. 3 A to Fig. 3 F is the schematic flow sheet of manufacture method of the active elements array substrates of second embodiment of the invention.

Wherein, description of reference numerals is as follows:

100,200,300: active elements array substrates

110,210,310: substrate

120a, 220a, 320a: grid

120b, 220b, 320b: first pad

130: gate insulator

140,240b, 340b: channel layer

150,260a, 360a: source electrode

152,260b, 360b: drain electrode

160,280: protective layer

162,164: contact hole

170: transparency conducting layer

170a, 290a, 390a: pixel electrode

170b: transparent pad

201,301: thin-film transistor

220,320: the first patterned conductive layers

222: scan line

230,330: dielectric layer

230 ', 330 ', 330 ": pattern dielectric layer

230a: the first dielectric block

230b: the second dielectric block

240,240a, 340,340a: semiconductor layer

250,350,270,380: the photoresist layer

250a, 350a, 380a: the first photoresist block

250b, 350b, 380b: the second photoresist block

252: opening

260,360: the second conductive layers

260 ': the second patterned conductive layer

260c, 360c: second pad

262: data wire

280 ', 370: the patterning protective layer

282,352: the first contact holes

284,382: the second contact holes

290,390: the three patterned conductive layers

290b, 390b: the 3rd pad

384: the three contact holes

D1, D2, D3, D4, D5, D6: thickness

L1, L4, L6: transparent area

L2, L5, L7: shading region

L3, L8: semi-opaque region

M1, M2, M3: photomask

Embodiment

(first embodiment)

Fig. 2 A to Fig. 2 J is the schematic flow sheet of manufacture method of the active elements array substrates of first embodiment of the invention.Please refer to Fig. 2 A, at first, on substrate 210, form first patterned conductive layer 220, and first patterned conductive layer 220 comprises a plurality of grid 220a and a plurality of first pad 220b.In the present embodiment, form that the method for first patterned conductive layer 220 is optional uses the photoengraving carving technology, but be not limited thereto, also can select screen printing technology, ink-jetting process, pattern sputtering process for use, cover depositing operation or other technology or above-mentioned combination.In the present embodiment, first patterned conductive layer 220 can be multi-layer metal structure, as multi-layer metal structures such as molybdenum/aluminium/molybdenum, titanium/aluminium/titanium, molybdenum/aluminium, aluminium/molybdenum, titanium/aluminium, aluminium/titaniums, and molybdenum, titanium, wherein at least one also can select for use following material to replace to aluminium, as: gold, silver, copper, iron, tin, lead, tantalum, tungsten, neodymium, hafnium or other material or other material or above-mentioned nitride or above-mentioned oxide or above-mentioned nitrogen oxide or above-mentioned alloy or above-mentioned combination.Certainly, first patterned conductive layer 220 also can be the single-layer metal structure, and its material for example is aluminium, gold, silver, copper, iron, tin, lead, molybdenum, titanium, tantalum, tungsten, neodymium, hafnium or other material or above-mentioned nitride or above-mentioned oxide or above-mentioned nitrogen oxide or above-mentioned alloy or above-mentioned combination.

Then please refer to Fig. 2 B, after forming first patterned conductive layer 220, form dielectric layer 230 and semiconductor layer 240 in regular turn, to be covered on the substrate 210 comprehensively.In the present embodiment, dielectric layer 230 for example is to form by chemical vapor deposition (CVD) or other modes with semiconductor layer 240.Generally speaking, dielectric layer 230 can be inorganic (as: silicon nitride, silica, silicon oxynitride, Yangization Han, class black diamond, Pyrex, other material or aforesaid combination), organic material (as: photoresist, Merlon, polyesters, polyalkylene oxide class, polyimide, polyphenyl phenol quinoline, benzocyclobutene,, polyalcohols, polyalkenes, polyphenyl class, poly-phenols, polyethers, polyketone class, polyamides class, carbene class or other material or above-mentioned combination) or above-mentioned combination.The material of semiconductor layer 240 can be amorphous silicon layer, polysilicon, monocrystalline silicon, microcrystal silicon or above-mentioned combination.In the present embodiment, semiconductor layer 240 is an example for amorphous silicon layer, and it for example is by intrinsic layer (intrinsic layer), the vertical direction that is also referred to as channel layer and is positioned at the ohmic contact layer (ohmic contact layer) on the intrinsic layer arrange constitute, wherein ohmic contact layer for example is N type doped amorphous silicon layer or P type doped amorphous silicon layer or above-mentioned combination, but be not limited thereto, intrinsic layer and ohmic contact layer can be arranged in and be horizontal framework with the semiconductor layer 230 of one deck.In addition, present embodiment also can additionally increase at least one doped layer between intrinsic layer and ohmic contact layer, and the doping content of doped layer is approximately less than the doping content of ohmic contact layer.Perhaps, intrinsic layer also can be the doped layer of single or multiple lift, and the concentration of being mixed is approximately less than the doping content of ohmic contact layer.

Please refer to Fig. 2 C, form the first photoresist layer 250 on semiconductor layer 240, wherein the first photoresist layer 250 is divided into first photoresist block 250a that is positioned at desire formation thin-film transistor top and the second photoresist block 250b that is adjacent to the first photoresist block.The second photoresist block 250b has a plurality of openings 252 that are positioned at first pad 220b top, and the thickness D1 of the first photoresist block 250a is in fact greater than the thickness D2 of the second photoresist block 250b.

In preferred embodiment of the present invention, the first photoresist layer 250 can adopt following method to make.At first; with the first photomask M1 (for example: the photomask of semi-modulation type photomask, slit pattern photomask, diffraction photomask, tone photomask or other same type or above-mentioned combination) is mask; the first photo anti-corrosion agent material layer is exposed, wherein the first photomask M1 have transparent area L1 corresponding to opening 252, corresponding to the shading region L2 of the first photoresist block 250a and corresponding to the semi-opaque region L3 of the second photoresist block 250b.Then, the first photo anti-corrosion agent material layer is carried out developing process.It should be noted that Fig. 2 B and the shown processing step of Fig. 2 C only are in order to illustrating, it is not in order to limit the present invention.

Please next, be that mask carries out first etch process to semiconductor layer 240 and dielectric layer 230 simultaneously with reference to Fig. 2 C and Fig. 2 D with the first photoresist layer 250.Reduce the thickness of photoresist layer 250 afterwards again, removed fully up to the second photoresist block 250b.In the present embodiment, can adopt the gas plasma treatment process, for example: cineration technics (ashing) reduces the thickness of photoresist layer 250.Then, be mask with the remaining first photoresist block 250a, semiconductor layer 240 and dielectric layer 230 are carried out second etch process, so that pattern dielectric layer 230 ' exposes the first pad 220b.

By Fig. 2 D as can be known, be formed at the second dielectric block 230b that the pattern dielectric layer 230 ' on the substrate 210 comprises the first dielectric block 230a of cover grid 220a and exposes the first pad 220b, and the thickness D3 of the first dielectric block 230a is in fact greater than the thickness D4 of the second dielectric block 230b.Moreover, preferably, the thickness that the thickness D4 of the second dielectric block 230b equals the first pad 220b in fact is example, but be not limited thereto, the thickness D4 of the second dielectric block 230b also can be different in essence in the thickness of the first pad 220b, for example: if etching speed is too fast or etching period is long, then the thickness D4 of the second dielectric block 230b equals the thickness of the first pad 220b in fact or if etching speed is slow or etching period is not enough a little, and then the thickness D4 of the second dielectric block 230b is in fact greater than the thickness of the first pad 220b.In other words, the second dielectric block 230b can't cover in fact on the surface of the first pad 220b tail end.

Please refer to Fig. 2 E, after finishing pattern dielectric layer 230, follow and form second conductive layer 260 comprehensively on pattern dielectric layer 230 '.In the present embodiment, second conductive layer 260 can be multi-layer metal structure, as multi-layer metal structures such as molybdenum/aluminium/molybdenum, titanium/aluminium/titanium, molybdenum/aluminium, aluminium/molybdenum, titanium/aluminium, aluminium/titaniums, and molybdenum, titanium, wherein at least one also can select for use following material to replace to aluminium, as: gold, silver, copper, iron, tin, lead, tantalum, tungsten, neodymium, hafnium or other material or other material or above-mentioned nitride or above-mentioned oxide or above-mentioned nitrogen oxide or above-mentioned alloy or above-mentioned combination.Certainly, second conductive layer 260 also can be the single-layer metal structure, and its material for example is aluminium, gold, silver, copper, iron, tin, lead, molybdenum, titanium, tantalum, tungsten, neodymium, hafnium or other material or above-mentioned nitride or above-mentioned oxide or above-mentioned nitrogen oxide or above-mentioned alloy or above-mentioned combination.

Please refer to Fig. 2 F, then, form the second photo anti-corrosion agent material layer in second conductive layer 260.Then, be mask with the second photomask M2, the second photo anti-corrosion agent material layer is exposed, wherein the second photomask M2 has transparent area L4 and shading region L5.Then, the second photo anti-corrosion agent material layer is carried out developing process, with the second photoresist layer 270 that forms patterning on second conductive layer 260.It should be noted that processing step that Fig. 2 E and Fig. 2 F are shown only is in order to illustrating, it is not in order to limit the present invention.

Please be simultaneously with reference to Fig. 2 F and Fig. 2 G, then, the second photoresist layer 270 with patterning is a mask, remove the semiconductor layer 240a of part second conductive layer 260 and part, to form source electrode 260a and drain electrode 260b in both sides, grid 220a top, and the semiconductor layer 240a that makes each grid 220a top constitutes channel layer 240b, and make remaining second conductive layer 260 ' on each first pad 220b constitute the second pad 260c, and remaining second conductive layer 260 ' is also referred to as second patterned conductive layer.By Fig. 2 G as can be known, the position can be removed in the process that forms second patterned conductive layer 260 ' in the lump at the part semiconductor layer 240a that above the grid 220a and is not covered by source electrode 260a and drain electrode 260b.In detail, semiconductor layer 240a arranges institute by intrinsic layer and the vertical direction that is positioned at the ohmic contact layer on the intrinsic layer to constitute, then can be removed in this step with the part ohmic contact layer that drain electrode 260b covers by source electrode 260a, to avoid short circuit between source electrode 260a and the drain electrode 260b, therefore, Ci Shi intrinsic layer is also referred to as channel layer.Above-mentioned grid 220a, channel layer 240b, source electrode 260a and drain electrode 260b constitute thin-film transistor 201.In the present embodiment, thin-film transistor 201 is that the bottom gate polar form with back of the body channel-etch framework is embodiment, but is not limited thereto, and also can be the bottom gate polar form of etch-stop framework or the bottom gate polar form or the top grid type of other framework.Moreover, form that the method for second patterned conductive layer 260 ' is optional uses the photoengraving carving technology, but be not limited to this, also can select screen printing technology, ink-jetting process, pattern sputtering process for use, cover depositing operation or other technology or above-mentioned combination.

Please refer to Fig. 2 H, then, form protective layer 280 on pattern dielectric layer 230 ' and each thin-film transistor 201 comprehensively.

Please refer to Fig. 2 I, then, protective layer 280 is carried out patterning, so that patterning protective layer 280 ' exposes part drain electrode 260b and the part second pad 260c.In the present embodiment, the method for formation patterning protective layer 280 ' is optional uses the photoengraving carving technology, but is not limited thereto, and also can select screen printing technology, ink-jetting process, pattern sputtering process for use, cover depositing operation or other technology or combinations thereof.

Please refer to Fig. 2 J; finish patterning protective layer 280 ' afterwards; then; form the 3rd patterned conductive layer 290 on patterning protective layer 280 ', the 3rd patterned conductive layer 290 comprises with each drain electrode pixel electrode 290a of being connected of 260b and is positioned at the 3rd pad 290b on second pad 260c respectively.In the present embodiment, form that the method for the 3rd patterned conductive layer 290 is optional uses the photoengraving carving technology, but be not limited thereto, also can select screen printing technology, ink-jetting process, pattern sputtering process for use, cover depositing operation or other technology or above-mentioned combination.Wherein, the material of described pixel electrode 290a of present embodiment and the 3rd pad 290b is all electrically conducting transparent material (as: indium tin oxide (indium tin oxide, ITO), indium-zinc oxide (indium zinc oxide, IZO), aluminium zinc oxide (aluminum zinc oxide, AZO), aluminium tin-oxide (aluminum tin oxide, ATO), cadmium tin-oxide (cadmium tin oxide, CTO), cadmium zinc oxide (cadmium zinc oxide, CZO), hafnium oxide (hafnium oxide, HfO), or other material, or the single layer structure of above-mentioned combination or sandwich construction) and a photoetching be etched to example.At this moment, the 3rd patterned conductive layer 290 and the 3rd pad 290b also can be described as patterned transparent conductive layer and transparent pad.Yet, embodiments of the invention are not limited to this, the 3rd patterned conductive layer 290 also can select for use electrically conducting transparent material (aforesaid material) in pad, and reflection conductive material and/or electrically conducting transparent material 290a in pixel electrode, and the reflection conductive material can be multi-layer metal structure, as molybdenum/aluminium/molybdenum, titanium/aluminium/titanium, molybdenum/aluminium, aluminium/molybdenum, titanium/aluminium, multi-layer metal structures such as aluminium/titanium, and molybdenum, titanium, wherein at least one also can select for use following material to replace to aluminium, as: gold, silver, copper, iron, tin, plumbous, tantalum, tungsten, neodymium, hafnium, or other material, or other material, or above-mentioned nitride, or above-mentioned oxide, or above-mentioned nitrogen oxide, or above-mentioned alloy, or above-mentioned combination.Certainly, also can be the single-layer metal structure, its material for example is aluminium, gold, silver, copper, iron, tin, lead, molybdenum, titanium, tantalum, tungsten, neodymium, hafnium or other material or above-mentioned nitride or above-mentioned oxide or above-mentioned nitrogen oxide or above-mentioned alloy or above-mentioned combination.In other words, the material of the pixel electrode 290a of the 3rd patterned conductive layer 290 can all be the electrically conducting transparent material, all be that reflection conductive material or part are the reflection conductive material for electrically conducting transparent material and another part, but the 3rd pad 290b uses the electrically conducting transparent material.If the material that pixel electrode uses comprises reflection conductive material and the 3rd pad is the electrically conducting transparent material, is example with the photoengraving carving technology, just need at least photoengraving carving technology basically, better simply mode is the above photoengraving carving technology of secondary or secondary.

Please continue J, second contact hole 284 that above-mentioned patterning protective layer 280 ' has first contact hole 282 that exposes the 260b that respectively drains and exposes each second pad 260c with reference to Fig. 2.Each pixel electrode 290a can be connected with each drain electrode 260b by each first contact hole 282, and each the 3rd pad 290b can be connected with each second pad 260c by each second contact hole 284.In other words, the upper surface of each first pad 220b of the lower surface of each second pad 260c contact, and the upper surface of each second pad 260c of the lower surface of each the 3rd pad 290b contact.

Because the pattern dielectric layer that part embodiment utilization of the present invention has two kinds of different-thickness allows first pad expose, so that follow-up second pad that is formed on the pattern dielectric layer can directly contact with first pad.First pad is usually located at the end of scan line, is also referred to as the scanning pad, and the edge of close display floater.First pad generally is electrically connected with integrated circuit (IC) in order to the driving panel via the 3rd pad and conducting film (as: have in anisotropy conducting film, anisotropic conductive, the adhesion in conducting particles, the adhesion glue and have conducting particles or other kind).Generally speaking, the material of first pad of first conductive layer for example is an aluminium, and the Facing material of second pad of second conductive layer is molybdenum and/or titanium for example, and the material of the 3rd pad for example is indium tin oxide (Indium Tin Oxide, ITO), be also referred to as transparent pad.Because the resistance of the interface of aluminium and ITO is higher, and the resistance of the interface of molybdenum (or titanium) and ITO is lower, the therefore connection by second pad, and present embodiment can be avoided the too high problem of interface resistance between the 3rd pad of first pad and follow-up formation.Moreover; the 3rd pad 290b is formed at protective layer 280 ' and goes up and contact on the second pad 260c; and the drop of matcoveredn 280 ' thickness only between the surface of second pad 260 and the 3rd pad 290b; make when the 3rd pad 290b contacts with the second pad 260c in contact hole 284, can avoid producing the crack and cause the not good problem of signal transmission.

Please continue the J with reference to Fig. 2, this active elements array substrates 200 comprises substrate 210, first patterned conductive layer 220, pattern dielectric layer 230 ', a plurality of channel layer 240b, second patterned conductive layer 260 ', patterning protective layer 280 ' and the 3rd patterned conductive layer 290.

Above-mentioned first patterned conductive layer 220 is disposed on the substrate 210, and first patterned conductive layer 220 comprises a plurality of grid 220a and a plurality of first pad 220b.Pattern dielectric layer 230 ' is disposed on the substrate, and pattern dielectric layer 230 ' comprises first dielectric block 230a that covers this grid 220a and the second dielectric block 230b that exposes this first pad 220b, and the thickness D3 of the first dielectric block 230a is in fact greater than the thickness D4 of the second dielectric block 230b.A plurality of channel layer 240b are disposed on the pattern dielectric layer 230 ' of each grid 220a top.Second patterned conductive layer 260 is disposed on pattern dielectric layer 230 ' and the channel layer 240b, and second patterned conductive layer 260 ' comprises a plurality of source electrode 260a and drain electrode 260b that are positioned at each top, grid 220a both sides, and a plurality of second pad 260c that is positioned on each first pad 220b.Patterning protective layer 280 ' covers second patterned conductive layer 260 ', and wherein patterning protective layer 280 ' exposes the drain electrode 260b and the second pad 290b.The 3rd patterned conductive layer 290 is disposed on the patterning protective layer 280 ', and wherein the 3rd patterned conductive layer 290 comprises a plurality of pixel electrode 290a and a plurality of the 3rd pad 290b that are positioned on each second pad 260c that are connected with each drain electrode 260b.

Fig. 2 K be first embodiment of the invention active elements array substrates on look schematic diagram.Please refer to Fig. 2 K, in the present embodiment, above-mentioned first patterned conductive layer 220 can comprise multi-strip scanning line 222, and scan line 222 is electrically connected with the first pad 220b of grid 220a and part, and first pad of this part is also referred to as the scanning pad.In addition, the second above-mentioned patterned conductive layer 260 ' can comprise many data wires 262 and staggered in fact with multi-strip scanning line 222, and data wire 262 is electrically connected with the first pad 220b of source electrode 260a and another part, the first pad 220b of this part also is referred to as data pads, wherein, scanning pad and data pads are to be electrically insulated.It should be noted that every arrangements of components the usefulness only among Fig. 2 K for illustrating, but not in order to restriction the present invention.The configuration of the scan line 222 among Fig. 2 K, data wire 262 and other each element can have multiple different design.In other words, the design of first embodiment can apply to scan pad and data pads wherein at least one.

With aforementioned, owing to have second pad between first pad of this active elements array substrates 200 and the 3rd pad, so the too high problem of interface resistance that the present invention was caused in the time of can avoiding first pad directly to contact with the 3rd pad.

(second embodiment)

Fig. 3 A to 3F is the schematic flow sheet of manufacture method of the active elements array substrates of second embodiment of the invention.Please refer to Fig. 3 A, at first, form first patterned conductive layer 320 on substrate 310.First patterned conductive layer 320 comprises a plurality of grid 320a and a plurality of first pad 320b.The method of formation first patterned conductive layer 320 of present embodiment is optional uses the photoengraving carving technology, but is not limited thereto, and also can select screen printing technology, ink-jetting process, pattern sputtering process for use, cover depositing operation or other technology or above-mentioned combination.In the present embodiment, first patterned conductive layer 320 can be multi-layer metal structure, as multi-layer metal structures such as molybdenum/aluminium/molybdenum, titanium/aluminium/titanium, molybdenum/aluminium, aluminium/molybdenum, titanium/aluminium, aluminium/titaniums, and molybdenum, titanium, wherein at least one also can select for use following material to replace to aluminium, as: gold, silver, copper, iron, tin, lead, tantalum, tungsten, neodymium, hafnium or other material or other material or above-mentioned nitride or above-mentioned oxide or above-mentioned nitrogen oxide or above-mentioned alloy or above-mentioned combination.Certainly, first patterned conductive layer 320 also can be the single-layer metal structure, and its material for example is aluminium, gold, silver, copper, iron, tin, lead, molybdenum, titanium, tantalum, tungsten, neodymium, hafnium or other material or above-mentioned nitride or above-mentioned oxide or above-mentioned nitrogen oxide or above-mentioned alloy or above-mentioned combination.

Please refer to Fig. 3 B, follow and form dielectric layer 330 and semiconductor layer 340 comprehensively on first patterned conductive layer 320.In the present embodiment, dielectric layer 330 for example is to form by chemical vapor deposition (CVD) or other modes with semiconductor layer 340.Generally speaking, dielectric layer 330 can be inorganic (as: silicon nitride, silica, silicon oxynitride, Yangization Han, class black diamond, Pyrex or other material or aforesaid combination), organic material (as: photoresist, Merlon, polyesters, polyalkylene oxide class, polyimide, polyphenyl phenol quinoline, benzocyclobutene, polyalcohols, polyalkenes, polyphenyl class, poly-phenols, polyethers, polyketone class, polyamides class, carbene class or other material or above-mentioned combination) or above-mentioned combination.The material of semiconductor layer 340 can be amorphous silicon layer, polysilicon, monocrystalline silicon, microcrystal silicon or above-mentioned combination.In the present embodiment, semiconductor layer 340 is an example for amorphous silicon layer, and it for example is to arrange institute by intrinsic layer and the vertical direction that is positioned at the ohmic contact layer on the intrinsic layer to constitute, wherein ohmic contact layer for example is N type doped amorphous silicon layer or P type doped amorphous silicon layer or above-mentioned combination, but be not limited thereto, intrinsic layer and ohmic contact layer can be arranged in and be horizontal framework with the semiconductor layer 340 of one deck.In addition, present embodiment also can additionally increase at least one doped layer between intrinsic layer and ohmic contact layer, and the doping content of doped layer is approximately less than the doping content of ohmic contact layer.Perhaps, intrinsic layer also can be the doped layer of single or multiple lift, and the concentration of being mixed is approximately less than the doping content of ohmic contact layer.Then on semiconductor layer 340, form photoresist layer 350, wherein photoresist layer 350 is divided into first photoresist block 350a that is positioned at desire formation thin-film transistor top and the second photoresist block 350b that is adjacent to the first photoresist block, the second photoresist block 350b is positioned on the semiconductor layer of non-display area, the second photoresist block 350b has a plurality of openings that are positioned at first contact hole, 352 tops, and the thickness D5 of the first photoresist block 350a is in fact greater than the thickness D6 of the second photoresist block 350b.

In preferred embodiment of the present invention, photoresist layer 350 can adopt following method to make.At first; with photomask M3 (for example: the photomask of semi-modulation type photomask, slit pattern photomask, diffraction photomask, tone photomask or other same type or above-mentioned combination) is mask; the photo anti-corrosion agent material layer is exposed, wherein photomask M3 have transparent area L6 corresponding to first contact hole 352, corresponding to the shading region L7 of the first photoresist block 350a and corresponding to the semi-opaque region L8 of the second photoresist block 350b.Then, the photo anti-corrosion agent material layer is carried out developing process.

Please then, be that mask carries out first etch process to semiconductor layer 340 and dielectric layer 330 simultaneously with reference to Fig. 3 B and Fig. 3 C with photoresist layer 350.Next, reduce the thickness of photoresist layer 350 again, removed fully up to the second photoresist block 350b.In the present embodiment, can adopt the gas plasma treatment process, for example: for example use cineration technics to reduce the thickness of photoresist layer 350.Then, be that mask carries out second etch process to semiconductor layer 340 and dielectric layer 330 with the remaining first photoresist block 350a, so that form a plurality of first contact holes 352 in the pattern dielectric layer 330 ', to expose each first pad 320b of part.It should be noted that processing step that Fig. 3 B and Fig. 3 C are shown only is in order to illustrating, it is not in order to limit the present invention.

By Fig. 3 C as can be known, be formed at pattern dielectric layer 330 ' the cover grid 320a and the first pad 320b on the substrate 310.Simultaneously, go up to form in pattern dielectric layer 330 ' and a plurality ofly be arranged in the channel layer 340a of each grid 320a top and form a plurality of first contact holes 352 in pattern dielectric layer 330 ', wherein first contact hole 352 exposes respectively first pad 320b of part.

Please refer to Fig. 3 D, then form second patterned conductive layer 360 on pattern dielectric layer 330 ', wherein second patterned conductive layer 360 comprises a plurality of source electrode 360a and drain electrode 360b and a plurality of second pad 360c that are positioned at each top, grid 320a both sides.In the present embodiment, second patterned conductive layer 360 can be multi-layer metal structure, as multi-layer metal structures such as molybdenum/aluminium/molybdenum, titanium/aluminium/titanium, molybdenum/aluminium, aluminium/molybdenum, titanium/aluminium, aluminium/titaniums, and molybdenum, titanium, wherein at least one also can select for use following material to replace to aluminium, as: gold, silver, copper, iron, tin, lead, tantalum, tungsten, neodymium, hafnium or other material or other material or above-mentioned nitride or above-mentioned oxide or above-mentioned nitrogen oxide or above-mentioned alloy or above-mentioned combination.Certainly, second patterned conductive layer 360 also can be the single-layer metal structure, and its material for example is aluminium, gold, silver, copper, iron, tin, lead, molybdenum, titanium, tantalum, tungsten, neodymium, hafnium or other material or above-mentioned nitride or above-mentioned oxide or above-mentioned nitrogen oxide or above-mentioned alloy or above-mentioned combination.By Fig. 3 D as can be known, the position can be removed in the process that forms second patterned conductive layer 360 in the lump at the part semiconductor layer 340a that above the grid 320a and is not covered by source electrode 360a and drain electrode 360b.In detail, if semiconductor layer 340a arranges institute by intrinsic layer and the vertical direction that is positioned at the ohmic contact layer on the intrinsic layer to constitute, then can be removed in this step with the part ohmic contact layer that drain electrode 360b covers by source electrode 360a, to avoid short circuit between source electrode 360a and the drain electrode 360b, therefore, Ci Shi intrinsic layer is also referred to as channel layer 340b.Above-mentioned grid 320a, channel layer 340b, source electrode 360a and drain electrode 360b constitute thin-film transistor 301, and the second pad 360c is electrically connected to the first pad 320b via first contact hole 352.In the present embodiment, thin-film transistor 201 is that the bottom gate polar form with back of the body channel-etch framework is embodiment, but is not limited thereto, and also can be the bottom gate polar form of etch-stop framework or the bottom gate polar form or the top grid type of other framework.Moreover, form that the method for second patterned conductive layer 360 is optional uses the photoengraving carving technology, but be not limited to this, also can select screen printing technology, ink-jetting process, pattern sputtering process for use, cover depositing operation or other technology or above-mentioned combination.

Please refer to Fig. 3 E, then form patterning protective layer 370 in pattern dielectric layer 330 ", on each thin-film transistor 301 and the second pad 360c.Patterning protective layer 370 has a plurality of second contact holes 382 to expose each second pad 360c of part and the 360b that partly respectively drains.And pattern dielectric layer 330 " have the 3rd contact hole 384 to expose each first pad 320b of part with patterning protective layer 370.In the present embodiment, the method for formation patterning protective layer 370 is optional uses the photoengraving carving technology, but is not limited thereto, and also can select screen printing technology, ink-jetting process, pattern sputtering process for use, cover depositing operation or other technology or above-mentioned combination.

Please refer to Fig. 3 F; then form the 3rd patterned conductive layer 390 on patterning protective layer 370, the 3rd patterned conductive layer 390 comprises the pixel electrode 390a that is connected with each drain electrode 360b and is positioned at the 3rd pad 390b last with each second pad 360c and that each first pad 320b is connected.In the present embodiment, form that the method for the 3rd patterned conductive layer 390 is optional uses the photoengraving carving technology, but be not limited thereto, also can select screen printing technology, ink-jetting process, pattern sputtering process for use, cover depositing operation or other technology or above-mentioned combination.Wherein, the material of described pixel electrode 390a of present embodiment and the 3rd pad 390b is all electrically conducting transparent material (as: indium tin oxide (indium tin oxide, ITO), indium-zinc oxide (indium zinc oxide, IZO), aluminium zinc oxide (aluminum zinc oxide, AZO), aluminium tin-oxide (aluminum tin oxide, ATO), cadmium tin-oxide (cadmium tin oxide, CTO), cadmium zinc oxide (cadmium zinc oxide, CZO), hafnium oxide (hafnium oxide, HfO), or other material, or the single layer structure of above-mentioned combination or sandwich construction) and a photoetching be etched to example.What at this moment, the 3rd patterned conductive layer 390 and the 3rd pad 390b also can claim is patterned transparent conductive layer and transparent pad.Yet, embodiments of the invention are not limited to this, the 3rd patterned conductive layer 390 also can select for use electrically conducting transparent material (aforesaid material) in pad, and reflection conductive material and/or electrically conducting transparent material 390a in pixel electrode, and the reflection conductive material can be multi-layer metal structure, as molybdenum/aluminium/molybdenum, titanium/aluminium/titanium, molybdenum/aluminium, aluminium/molybdenum, titanium/aluminium, multi-layer metal structures such as aluminium/titanium, and molybdenum, titanium, wherein at least one also can select for use following material to replace to aluminium, as: gold, silver, copper, iron, tin, plumbous, tantalum, tungsten, neodymium, hafnium, or other material, or other material, or above-mentioned nitride, or above-mentioned oxide, or above-mentioned nitrogen oxide, or above-mentioned alloy, or above-mentioned combination.Certainly, also can be the single-layer metal structure, its material for example is aluminium, gold, silver, copper, iron, tin, lead, molybdenum, titanium, tantalum, tungsten, neodymium, hafnium or other material or above-mentioned nitride or above-mentioned oxide or above-mentioned nitrogen oxide or above-mentioned alloy or above-mentioned combination.In other words, the material of the pixel electrode 390a of the 3rd patterned conductive layer 390 can all be the electrically conducting transparent material, all be that reflection conductive material or part are the reflection conductive material for electrically conducting transparent material and another part, but the 3rd pad 390b uses the electrically conducting transparent material.If the material that pixel electrode uses comprises reflection conductive material and the 3rd pad is the electrically conducting transparent material, is example with the photoengraving carving technology, at least photoengraving carving technology of needs just basically, better simply mode is the above photoengraving carving technology of secondary or secondary.

Please continue the F with reference to Fig. 3, above-mentioned patterning protective layer 370 has first contact hole 382 that exposes respectively drain 360b and each second pad 360c respectively and exposes respectively second contact hole 384 of first pad 320b.Each pixel electrode 290a can by each first contact hole 382 is connected with each drain electrode 260b and, and each the 3rd pad 290b can pass through respectively that each first contact hole 382 be connected with each second pad 360c and respectively second contact hole 384 be connected with each first pad 320b.In other words, the upper surface of each first pad 320b of the lower surface of each second pad 360c contact, and the upper surface of each second pad 360c of the lower surface of each the 3rd pad 390b contact and the upper surface of each first pad 320b.

Because part embodiment of the present invention forms a plurality of first contact holes when making channel layer, to allow part first pad expose, so that follow-up second pad that is formed on the pattern dielectric layer can contact with first pad.By contrast, known technology then makes first pad only directly connect second pad via transparency conducting layer, and first pad there is no directly with second pad and contacts.Because the resistance value of transparency conducting layer is far above the resistance value of first pad and the resistance value of second pad, so contact with the direct of second pad by first pad, the resistance value between first pad and second pad can be lowered effectively.Moreover, by the connected mode of this multiple stage type, can guarantee that also signal transmits the 3rd pad that quality is difficult for being touched in the window and produces brisement etc. factor influenced because of the thickness drop.

Please continue the F with reference to Fig. 3, this active elements array substrates 300 comprises substrate 310, first patterned conductive layer 320, pattern dielectric layer 330 ", a plurality of channel layer 340b, a plurality of source electrode 360a and drain electrode 360b, a plurality of second pad 360, patterning protective layer 370 and the 3rd patterned conductive layer 390.

The first above-mentioned patterned conductive layer 320 is disposed on the substrate 310, and first patterned conductive layer 320 comprises a plurality of grid 320a and a plurality of first pad 320b.Pattern dielectric layer 330 " be disposed on the substrate 310, and pattern dielectric layer 330 " the cover gate 320a and the first pad 320b, and pattern dielectric layer 330 " have a plurality of first contact holes 352, to expose each first pad 320b of part.A plurality of channel layer 340b are disposed on the pattern dielectric layer 330 of each grid 320a top.Second patterned conductive layer 360 is disposed at pattern dielectric layer 330 " with channel layer 340b on, and second patterned conductive layer 360 comprises a plurality of source electrode 360a and drain electrode 360b and a plurality of second pad 360c.A plurality of source electrode 360a and drain electrode 360b are positioned at each top, grid 320a both sides.A plurality of second pad 360c are electrically connected to the first pad 320b via first contact hole 352.Patterning protective layer 370 covers second patterned conductive layer 360.The 3rd patterned conductive layer 390 is disposed on the patterning protective layer 370; wherein patterning protective layer 370 has a plurality of second contact holes 382 to expose each second pad 360c of part and the 360b that partly respectively drains; and pattern dielectric layer 330 " have the 3rd contact hole 384 to expose each first pad 320b of part with patterning protective layer 370; and be electrically connected to drain electrode 360b via second contact hole 382 by the pixel electrode 390a of the 3rd patterned conductive layer 390, and the 3rd pad 390b of the 3rd patterned conductive layer is electrically connected to the first pad 320b via the 3rd contact hole 384 and second contact hole 382 is electrically connected to the second pad 360c.

Moreover, the above embodiments of the present invention, the photo anti-corrosion agent material in the photoengraving carving technology example of being used in serves as to implement example with positive photoresist all, but is not limited thereto, and also can use negative photoresist.Can say for example, if photo anti-corrosion agent material is positive photoresist, the photoresist thickness that then will remain (promptly expose and develop after photoresist thickness) and the relation in the zone at corresponding photomask place, and with semi-transparent mask is example, transmission region on the semi-transparent mask, its the corresponding photoresist thickness that will remain approach zero, with the rete before exposing, non-transmission region on the semi-transparent mask, its the corresponding photoresist thickness that will remain near unexposed and develop before photoresist thickness, and the semi-transparent zone on the semi-transparent mask, its the corresponding photoresist thickness that will the remain transmission region on semi-transparent mask in fact, its corresponding photoresist thickness that will remain and the non-transmission region on the semi-transparent mask, its between the correspondence photoresist thickness that will remain.If photo anti-corrosion agent material is a negative photoresist, the photoresist thickness that then will remain (promptly expose and develop after photoresist thickness) and the relation in the zone at corresponding photomask place be example with semi-transparent mask, transmission region on the semi-transparent mask, its the corresponding photoresist thickness that will remain near unexposed and develop before photoresist thickness, non-transmission region on the semi-transparent mask, its the corresponding photoresist thickness that will remain approach zero, with the rete before exposing, and the semi-transparent zone on the semi-transparent mask, its the corresponding photoresist thickness that will the remain transmission region on semi-transparent mask in fact, the non-transmission region on the photoresist thickness that its institute's correspondence will remain and the semi-transparent mask its between the corresponding photoresist thickness that will remain.

With above-mentioned,, and make the 3rd patterned conductive layer also simultaneously contact first pad and second pad via contact hole because present embodiment can make second pad contact first pad via contact hole.In comparison, known technology then makes first pad only directly connect second pad via transparency conducting layer, and first pad there is no directly with second pad and contacts.Because the resistance value of transparency conducting layer is far above the resistance value of first pad and the resistance value of second pad, so first pad of present embodiment and the resistance value between second pad can be lowered effectively.

In sum, owing to have second pad between the 3rd patterned conductive layer of the present invention and first pad, so the present invention can solve the too high problem of interface resistance of the 3rd patterned conductive layer and first pad.In addition, because the present invention can make first pad directly contact second pad via contact hole, so the present invention can significantly reduce the resistance value between first pad and second pad.

Though the present invention with embodiment openly as above; right its is not in order to qualification the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; when can doing a little variation and modification, so protection scope of the present invention is as the criterion when looking the accompanying Claim person of defining.

Claims

1. active elements array substrates comprises:

Substrate;

First patterned conductive layer is disposed on the described substrate, and described first patterned conductive layer comprises a plurality of grids and a plurality of first pad;

Pattern dielectric layer, be disposed on the described substrate, described pattern dielectric layer comprises first dielectric block that covers described a plurality of grids and the second dielectric block that exposes described a plurality of first pads, and the thickness of the described first dielectric block is greater than the thickness of the described second dielectric block;

A plurality of channel layers are disposed on the described pattern dielectric layer of each described grid top;

Second patterned conductive layer, be disposed on described pattern dielectric layer and the described a plurality of channel layer, described second patterned conductive layer comprises a plurality of source electrode and drain electrodes that are positioned at each top, described grid both sides, and a plurality of second pad that is positioned on each described first pad;

The patterning protective layer covers described second patterned conductive layer, and wherein said patterning protective layer exposes described a plurality of drain electrode and described a plurality of second pad; And

The 3rd patterned conductive layer is disposed on the described patterning protective layer, and wherein said the 3rd patterned conductive layer comprises a plurality of pixel electrodes that are connected with each described drain electrode and a plurality of the 3rd pad that is positioned on each described second pad.

2. active elements array substrates as claimed in claim 1, wherein said first patterned conductive layer also comprises the multi-strip scanning line, wherein said multi-strip scanning line is electrically connected with described a plurality of first pads of described a plurality of grids and part.

3. active elements array substrates as claimed in claim 1, wherein said second patterned conductive layer also comprises many data wires, wherein said many data wires are electrically connected with described a plurality of first pads of described a plurality of source electrodes and part.

4. the manufacture method of an active elements array substrates comprises:

Substrate is provided;

Form first patterned conductive layer on described substrate, described first patterned conductive layer comprises a plurality of grids and a plurality of first pad;

Form pattern dielectric layer on described substrate, so that described pattern dielectric layer comprises first dielectric block that covers described a plurality of grids and the second dielectric block that exposes described a plurality of first pads, and the thickness of the described first dielectric block is greater than the thickness of the described second dielectric block;

Form a plurality of channel layers and second patterned conductive layer simultaneously on described pattern dielectric layer, so that each described channel layer is formed at each described grid top, and described second patterned conductive layer comprises a plurality of source electrode and drain electrodes that are positioned at each top, described grid both sides, and a plurality of second pads that are positioned on each described first pad, wherein said grid, described channel layer, described source electrode and described drain electrode constitute thin-film transistor;

Form the patterning protective layer on described pattern dielectric layer and each described thin-film transistor, so that described patterning protective layer exposes described a plurality of drain electrode and described a plurality of second pad; And

Form the 3rd patterned conductive layer on described patterning protective layer, wherein said the 3rd patterned conductive layer comprises a plurality of pixel electrodes that are connected with each described drain electrode and a plurality of the 3rd pad that is positioned on each described second pad.

5. the manufacture method of active elements array substrates as claimed in claim 4, the method that wherein forms described pattern dielectric layer comprises:

Form dielectric layer and semiconductor layer on described first patterned conductive layer;

On described semiconductor layer, form the first photoresist layer, the wherein said first photoresist layer is divided into and is positioned at desire and forms first photoresist block of a plurality of thin-film transistors top and the second photoresist block that is adjacent to the described first photoresist block, the described second photoresist block is positioned on the described semiconductor layer of non-display area, the described second photoresist block has a plurality of openings that are positioned at described a plurality of first pads top, and the thickness of the described first photoresist block is greater than the thickness of the described second photoresist block;

With the described first photoresist layer is that mask carries out first etch process to described semiconductor layer and described dielectric layer;

Reduce the thickness of the described first photoresist layer, removed fully up to the described second photoresist block; And

With the remaining described first photoresist block is that mask carries out second etch process to described semiconductor layer and described dielectric layer, to expose described a plurality of first pad.

6. the manufacture method of active elements array substrates as claimed in claim 5, the formation method of the wherein said first photoresist layer comprises:

With first photomask is mask, the first photo anti-corrosion agent material layer is exposed, and wherein said first photomask has transparent area corresponding to described a plurality of openings, corresponding to the shading region of the described first photoresist block and corresponding to the semi-opaque region of the described second photoresist block; And

The described first photo anti-corrosion agent material layer is carried out developing process.

7. the manufacture method of active elements array substrates as claimed in claim 6, wherein said first photomask comprises semi-modulation type photomask or tone photomask.

8. the manufacture method of active elements array substrates as claimed in claim 5, the method that wherein reduces the described first photoresist layer thickness comprises carries out cineration technics.

9. the manufacture method of active elements array substrates as claimed in claim 4, the method that wherein forms described a plurality of channel layer and described second patterned conductive layer simultaneously comprises:

Form second conductive layer on described pattern dielectric layer;

Form the second photoresist layer on described second conductive layer;

With the described second photoresist layer is that mask removes described second conductive layer of part and the described semiconductor layer of part, so that remaining described second conductive layer of each described grid top constitutes described source electrode and described drain electrode, and make the described semiconductor layer of each described grid top constitute described channel layer, and make remaining described second conductive layer on each described first pad constitute described second pad.

10. the manufacture method of active elements array substrates as claimed in claim 9, the formation method of the wherein said second photoresist layer comprises:

With second photomask is mask, and the second photo anti-corrosion agent material layer is exposed, and wherein said second photomask has transparent area and shading region; And

The described second photo anti-corrosion agent material layer is carried out developing process.

11. the manufacture method of active elements array substrates as claimed in claim 4; wherein when forming described patterning protective layer; also comprise and form a plurality of first contact hole and a plurality of second contact holes that expose each described second pad that expose each described drain electrode; be connected with each described drain electrode so that each described pixel electrode passes through each described first contact hole, and each described the 3rd pad is connected with each described second pad by each described second contact hole.

12. an active elements array substrates comprises:

Substrate;

Pattern dielectric layer is disposed on the described substrate, and described pattern dielectric layer covers described a plurality of grid and described a plurality of first pad, and described pattern dielectric layer has a plurality of first contact holes, to expose each described first pad of part;

Second patterned conductive layer is disposed on described pattern dielectric layer and the described a plurality of channel layer, and described second patterned conductive layer comprises:

A plurality of source electrodes and drain electrode are positioned at each top, described grid both sides; And

A plurality of second pads are electrically connected to described a plurality of first pad via described a plurality of first contact holes;

The patterning protective layer covers described second patterned conductive layer; And

The 3rd patterned conductive layer; be disposed on the described patterning protective layer; wherein said patterning protective layer has a plurality of second contact holes to expose each described second pad of part; and described pattern dielectric layer and described patterning protective layer have the 3rd contact hole to expose each described first pad of part; and described the 3rd patterned conductive layer via described a plurality of second contact hole electrical wirings to described a plurality of second pads and described a plurality of drain electrode, and via described a plurality of the 3rd contact hole electrical wirings described a plurality of first pads extremely.

13. active elements array substrates as claimed in claim 12, wherein said the 3rd patterned conductive layer have the 3rd pad that pixel electrode that a plurality of and described drain electrode is electrically connected and a plurality of and described a plurality of first pad and described a plurality of second pad are electrically connected.

14. the manufacture method of an active elements array substrates comprises:

Substrate is provided;

Form pattern dielectric layer on described substrate, so that described pattern dielectric layer covers described a plurality of grid and described a plurality of first pad;

Formation is a plurality of on described pattern dielectric layer simultaneously is arranged in the channel layer of each described grid top and forms a plurality of first contact holes in described pattern dielectric layer, and wherein said a plurality of first contact holes expose each described first pad of part;

Form second patterned conductive layer on described pattern dielectric layer, wherein said second patterned conductive layer comprises a plurality of source electrode and drain electrode and a plurality of second pads that are positioned at each top, described grid both sides, described grid, described channel layer, described source electrode and described drain electrode constitute thin-film transistor, and described a plurality of second pad is electrically connected to described a plurality of first pad via described a plurality of first contact holes;

Form the patterning protective layer on described pattern dielectric layer, each described thin-film transistor and described a plurality of second pad, wherein said patterning protective layer has a plurality of second contact holes exposing each described second pad of part, and described pattern dielectric layer and described patterning protective layer have the 3rd contact hole to expose partly each described first pad; And

Form the 3rd patterned conductive layer on described patterning protective layer; wherein said the 3rd patterned conductive layer is electrically connected to described a plurality of second pad and described a plurality of drain electrode via described a plurality of second contact holes, and is electrically connected to described a plurality of first pad via described a plurality of the 3rd contact holes.

15. the manufacture method of active elements array substrates as claimed in claim 14, the method that wherein forms described channel layer and described a plurality of first contact holes simultaneously comprises:

On described semiconductor layer, form the photoresist layer, wherein said photoresist layer is divided into and is positioned at desire and forms first photoresist block of a plurality of thin-film transistors top and the second photoresist block that is adjacent to the described first photoresist block, the described second photoresist block is positioned on the described semiconductor layer of non-display area, the described second photoresist block has a plurality of openings that are positioned at described first contact hole top, and the thickness of the described first photoresist block is greater than the thickness of the described second photoresist block;

With described photoresist layer is that mask carries out first etch process to described semiconductor layer and described dielectric layer;

Reduce the thickness of described photoresist layer, removed fully up to the described second photoresist block; And

With the remaining described first photoresist block is that mask carries out second etch process to described semiconductor layer and described dielectric layer, forms a plurality of first contact holes, to expose each described first pad of part.

16. the manufacture method of active elements array substrates as claimed in claim 15, the formation method of wherein said photoresist layer comprises:

With the photomask is mask, the photo anti-corrosion agent material layer is exposed, and wherein said photomask has corresponding to the transparent area of described a plurality of first contact holes, corresponding to the shading region of the described first photoresist block and corresponding to the semi-opaque region of the described second photoresist block; And

Described photo anti-corrosion agent material layer is carried out developing process.

17. comprising, the manufacture method of active elements array substrates as claimed in claim 15, the method that wherein reduces described photoresist layer thickness carry out cineration technics.