CN100539453C - Data source and sink and method - Google Patents
Data source and sink and method Download PDFInfo
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- CN100539453C CN100539453C CNB2006101118650A CN200610111865A CN100539453C CN 100539453 C CN100539453 C CN 100539453C CN B2006101118650 A CNB2006101118650 A CN B2006101118650A CN 200610111865 A CN200610111865 A CN 200610111865A CN 100539453 C CN100539453 C CN 100539453C
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Abstract
The invention provides a kind of data source and sink and method, said apparatus is to comprise a deciphering module, one separates a deviation module and a control module, wherein deciphering module is to receive at least one package and package is deciphered back output, and according at least one significant character of package to produce a useful signal, separate the deviation module and be with deciphering module and electrically connect to receive the package deciphered and this package is separated deviation, control module is with deciphering module and separates the electric connection of deviation module, and receive useful signal to produce a gate clock signal, wherein separating the deviation module is according to the running of gate clock signal, to carry out the deviation of separating of package.Data source and sink of the present invention and method can be when the idle symbols of transmission logic, reduce required working power and keep the normal operation of data source and sink.
Description
Technical field
The invention relates to a kind of data source and sink, especially in regard to a kind of data serial R-T unit and method of using serial transmission.
Background technology
In known data source and sink, because parallel transmission speed is restricted, in order to overcome this restriction, the data source and sink of high speed serial transmission little by little is widely used in the communication system.
As shown in Figure 1, known data source and sink 1 is to be connected between a circuit entity layer (Electrical Physical Layer) 20 and one datalink layer connection (Data LinkLayer) 21, wherein data source and sink 1 comprises a plurality of channels 10 (first channel to the n channel), and each channel 10 comprises a decipher (de-scrambler) 11, and separates a deviator (de-skewer) 12 and a clock pulse generator 13.Wherein, clock pulse generator 13 produces a clock pulse signal CLK to decipher 11 and separate deviator 12, then decipher 11 and to separate deviator 12 be to move according to this clock pulse signal CLK.
With first channel 10 is example, circuit entity layer 20 sees through a serial parallel converters (Serial-to-Parallel converter) (not being shown in figure) with the package PAK that receives, after converting the serial data among the package PAK to parallel data, utilize one 8/10 bit decoders (not being shown in figure) 10 bit data among the package PAK to be decoded as the package PAK of one 8 bit data again, wherein package PAK can be a transport-layer encapsulations may (the transaction layer packet that the transport layer (Transaction layer) (not being shown among the figure) of a transmitting terminal in the PCI Express system is produced, TLP), in addition first channel 10 can also receive the datalink layer connection package that the datalink layer connection (Data Link layer) (not being shown among the figure) by transmitting terminal produced (Data link layer packet, DLLP).Decipher 11 is to electrically connect to receive package PAK with circuit entity layer 20, and with package PAK deciphering generation package PAK ', afterwards package PAK ' is exported to and separate deviator 12, separate deviator 12 then and separate deviation (de-skew) package PAK ' generation package PAK ＂, and according to departure delayed delivery package PAK ＂ suitably, and then guarantee that first channel 10 and package PAK ＂ in other channels 10 (as n channel 10) can export datalink layer connection 21 synchronously to; Wherein, factor has asymmetrical relation according to each channel in the R-T unit 1 when transmitting each package, so each channel when transmitting package the phenomenon (not being shown in figure) of deviation can take place, thereby produces a corresponding departure.Each channel can be separated deviation with package according to this corresponding departure, makes each package can deliver to datalink layer connection 21 simultaneously.
Yet, because separating must be with the package delayed delivery in the deviation process, therefore, separate and need enough buffering areas in the deviator 12 with the temporary package that postpones, thereby cause a large amount of losses of power, with PCI EXPRESS system, if first channel 10 is received the logic symbol " 00 " (Logic idle symbol) that leaves unused, because the idle symbol " 00 " of logic can't be handled by the circuit after the datalink layer connection 21, but in order to keep the normal operation of first channel 10, separate deviator 12 and still need continue running to handle the idle symbol of this logic, under the situation of mass data stream, the lasting running of separating deviator 12 can consume a large amount of power supplys.
Therefore, how a kind of data source and sink that the clock signal that is provided can be provided is provided, in the hope of can be, reduce required working power and keep the normal operation of data source and sink, just one of current important topic in response to when the idle symbol of data source and sink transmission logic.
Summary of the invention
The present invention provides a kind of idle symbol of logic of the package that is transmitted of can detecting to reduce the data source and sink of corresponding electrical source consumption.
Data source and sink of the present invention comprises an at least one channel and a control module, and each this channel comprises a deciphering module and and separates the deviation module.In the present invention, deciphering module receives at least one package and with package deciphering back output, and according at least one significant character of package with activation one useful signal.Separate the deviation module and be with deciphering module and electrically connect to receive the package deciphered and this package is separated deviation, control module is with deciphering module and separates the electric connection of deviation module, and receive this useful signal, a departure and a clock pulse signal to produce a gate clock signal, wherein separating the deviation module is according to gate clock signal running (operating), to carry out the deviation of separating of package.
In addition, data source and sink of the present invention, it comprises a plurality of channels and a control module.In the present invention, each channel is to have a deciphering module and to separate the deviation module, and deciphering module receives at least one package and with package deciphering back output, and according at least one significant character activation one useful signal of package.Separating deviation module and deciphering module electrically connects to receive the package deciphered and this package is separated deviation, control module is to separate the electric connection of deviation module with these deciphering modules and these, to receive these useful signals and to produce a gate clock signal, wherein respectively separating the deviation module is according to the running of gate clock signal, to carry out the deviation of separating of each package.
The present invention also provides a kind of data receiving-transmitting method, be used at least one interchannel and transmit at least one package, each this channel comprises a deciphering module and and separates the deviation module, and the step of this data receiving-transmitting method comprises: at least one significant character according to this package produces a useful signal; According to this useful signal, a departure and a clock pulse signal, to produce a gate clock signal; And this to separate the deviation module be respectively according to the running of this gate clock signal, to carry out the deviation of separating of this package.
Data source and sink of the present invention is the package symbol that detecting is received, when the significant character that detects package (be NOT logic idle symbol), control module just can provide the work time pulse signal, in other words, when the logic that detects package is left unused symbol, control module is suspended provides the work time pulse signal, so as to reducing corresponding electrical source consumption, and then can increase province's electrical efficiency of data source and sink effectively.
Description of drawings
Fig. 1 is a schematic diagram that shows the given data R-T unit;
Fig. 2 is a schematic diagram that shows according to the data source and sink of preferred embodiment of the present invention;
Fig. 3 is the clock pulse running schematic diagram that shows as the data source and sink transmitting-receiving package of Fig. 2;
Fig. 4 is another schematic diagram that shows according to the data source and sink of preferred embodiment of the present invention;
Fig. 5 A is the clock pulse running schematic diagram that shows as the data source and sink transmitting-receiving package of Fig. 4;
Fig. 5 B is another clock pulse running schematic diagram that shows as the data source and sink transmitting-receiving package of Fig. 4;
Fig. 5 C is another clock pulse running schematic diagram that shows as the data source and sink transmitting-receiving package of Fig. 4;
Fig. 6 is the flow chart of the data receiving-transmitting method of preferred embodiment of the present invention.
Embodiment
Hereinafter with reference to correlative type, the data source and sink according to preferred embodiment of the present invention is described.
With the single channel is example, and as shown in Figure 2, the data source and sink 3 of preferred embodiment of the present invention comprises a deciphering module 31, and separates a deviation module 32 and a control module 33.
As shown in Figure 3, it is the clock pulse running schematic diagram of package PAK ' in the data source and sink 3, for the data source and sink 3 easier quilts that make present embodiment are understood, below also please refer to Fig. 2 so that the embodiment of present embodiment to be described in detail.
At first, deciphering module 31 is to receive package PAK from a circuit entity layer 40, wherein package PAK can be in the pCI Express system transport-layer encapsulations may (TLP) that the transport layer (not being shown among the figure) by a transmitting terminal is produced, or a transport-layer encapsulations may (DLLP) that is produced by the datalink layer connection (not being shown among the figure) of transmitting terminal.Deciphering module 31 transmits package PAK ' to separating deviation module 32 after package PAK deciphering is become package PAK '.Whether deciphering module 31 and the content of detecting package PAK ' have the significant character of the idle symbol of NOT logic, the for example stp among Fig. 3,02,0E and end etc., wherein define each non-" 00 " symbol stp, 02,0E and end is a significant character at this, " 00 " symbol then is the idle symbol of logic.When deciphering module 31 detects package PAK ' when comprising significant character, promptly according to the significant character activation one useful signal VAL of package PAK ', and useful signal VAL is sent to control module 33, in the present embodiment, useful signal VAL is according to significant character stp, 02,0E and end and in time T
1, T
5, T
12And T
16Shi Zhineng.
In the present embodiment, control module 33 comprises a delay cell 331, a running control unit 332 and a door control unit 333.
Running control unit 332 (for example one or door OR gate) electrically connects with delay cell 331 and deciphering module 31, with receive delay signal DEL and useful signal VAL, in the present embodiment, running control unit 332 produces a control signal CTL according to inhibit signal DEL and useful signal VAL, as shown in Figure 3.Wherein when inhibit signal DEL and the two one of them activation of useful signal VAL, it is activation that running control unit 332 is set control signal CTL, so control signal CTL is in time T
1, T
2, T
5, T
6, T
12, T
13, T1
6And T
17Shi Zhineng; Then, running control unit 332 is sent to door control unit 333 with control signal CTL.
As shown in Figure 2, door control unit 333 (for example with a door AND gate and a door bolt Latch) receives the clock signal CLK that a clock pulse generation module 34 produces, and electrically connects with reception control signal CTL with running control unit 332.Door control unit 333 is according to control signal CTL and clock signal CLK and produce gate clock signal GCL.Door control unit 333 is at first fastened clock signal CLK and control signal CTL input to produce a gate-control signal CTL ' with a bolt or latch, then again gate-control signal CTL ' and clock signal CLK are seen through and door produces gate clock signal GCL, so gate clock signal GCL is in both all activations during activation of clock signal CLK and gate-control signal CTL ' as can be known.As shown in Figure 3, wherein gate-control signal CTL ' is in time T
2, T
3, T
6, T
7, T
13, T
14, T
17And T
18Shi Zhineng, so gate clock signal GCL is in time T
2, T
3, T
6, T
7, T
13, T
14, T
17And T
18Shi Zhineng is general clock signal, then suspends in all the other times; Then, door control unit 333 is sent to gate clock signal GCL and separates deviation module 32 is separated deviation module 32 with control running.
Separate deviation module 32 and receive package PAK ', and to holder, (be not shown among the figure) package PAK ' is temporary from deciphering module 31.Separate deviation module 32 and package PAK ' is separated deviation generation package PAK ＂, and export package PAK ＂ to datalink layer connection 41 according to gate clock signal GCL.As shown in Figure 3, separate deviation module 32 in time T
2, T
3, T
6, T
7, T
13, T
14, T
17With T
18Export the package PAK ＂ that separates deviation to datalink layer connection 41.
In addition, as shown in Figure 4, be the data source and sink 5 of another preferred embodiment of the present invention, it comprises four channels 501～504 and a control module 53, and wherein each channel has a deciphering module 511～514 and respectively and separates deviation module 521～524.Data source and sink 5 receives a package PAK from a circuit entity layer 60, wherein package PAK can be in the PCIExpress system transport-layer encapsulations may (TLP) that the transport layer (not being shown among the figure) by a transmitting terminal is produced, or a transport-layer encapsulations may (DLLP) that is produced by the datalink layer connection (not being shown among the figure) of transmitting terminal, and package PAK splits into a plurality of sub-package PAK
1To PAK
4
Deciphering module 511～514 receives at least one sub-package PAK respectively
1～PAK
4And with sub-package PAK
1～PAK
4Deciphering produces sub-package PAK
1'～PAK
4', afterwards with sub-package PAK
1'～PAK
4' export to respectively and separate deviation module 521～524.Deciphering module 511～514 is respectively according to sub-package PAK simultaneously
1'～PAK
4The significant character activation one sub-useful signal VAL of ' content
1～VAL
4, and with these sub-useful signal VAL
1～VAL
4Be sent to control module 53.Respectively separating deviation module 521～524 electrically connects to receive sub-package PAK with each deciphering module 511～514 respectively
1'～PAK
4', and with sub-package PAK
1'～PAK
4' separate deviation to produce sub-package PAK
1＂～PAK
4＂.
Control module 53 is with each deciphering module 511～514 and respectively separate 521～524 electric connections of deviation module, to receive the sub-useful signal VAL that each deciphering module 511～514 transmits
1～VAL
4Clock signal CLK according to these sub-useful signal VAL1～VAL4 and 54 outputs of clock pulse generation module produces a gate clock signal GCL then, control module 53 is sent to each with this gate clock signal GCL and separates deviation module 521～524 afterwards, and respectively separates deviation module 521～524th, according to gate clock signal GCL antithetical phrase package PAK
1'～PAK
4' separate deviation to produce sub-package PAK
1＂～PAK
4＂.
In detail, control module 53 comprises a delay cell 531, a running control unit 532 and a door control unit 533.Delay cell 531 electrically connects with the deciphering module 511～514 of each channel, and comprises delayer 5310 and one or door OR
1At first one or the door OR
0Be connected to receive each sub-useful signal VAL with each deciphering module 511～514
1～VAL
4, again according to each sub-useful signal VAL
1～VAL
4Produce a useful signal VAL
T, and with this useful signal VAL
TBe sent to delay cell 531 and running control unit 532, wherein useful signal VAL
TIn sub-useful signal VAL
1～VAL
4Wherein be activation during any activation.In the present embodiment, delayer 5310 transmits sub-package PAK according to 501～504 of each channels
1'～PAK
4' departure postpone useful signal VAL
T, to produce inhibit signal DEL, again by or door OR
1Export running control unit 532 to.The quantity of inhibit signal DEL is to be directly proportional with departure, is that the quantity of 1 inhibit signal DEL is 2 as departure, and the time of delay unit between each inhibit signal DEL is 1 T of chronomere.
The running control unit 532 (for example one or the door OR
2) electrically connect with delay cell 531, and see through or door OR
0Electrically connect with each channel deciphering module 511～514, so as to receive delay signal DEL and useful signal VAL
TRunning control unit 532 is according to inhibit signal DEL and useful signal VAL
TProduce a control signal CTL, and be sent to door control unit 533.As inhibit signal DEL and useful signal VAL
TDuring the two one of them activation, control signal CTL is activation.
Door control unit 533 (for example one with a door (AND) and a door bolt (Latch)) receives the clock signal CLK that a clock pulse generation module 54 produces, and electrically connects to receive control signal CTL with running control unit 532.And door control unit 533 is promptly according to control signal CTL and clock signal CLK and produce a gate clock signal GCL.Door control unit 533 is at first fastened clock signal CLK and control signal CTL input to produce a gate-control signal CTL ' with a bolt or latch, then again gate-control signal CTL ' and clock signal CLK are seen through and door generation gate clock signal GCL, so gate clock signal GCL is in both all activations during activation of clock signal CLK and gate-control signal CTL '.
Separate deviation module 521～524 at last and receive sub-package PAK from deciphering module 511～514 respectively
1'～PAK
4', and with sub-package PAK
1'～PAK
4' temporaryly respectively to holder, (be not shown among the figure).Separate deviation module 521～524 and respectively according to gate clock signal GCL with sub-package PAK
1'～PAK
4' separate deviation to produce sub-package PAK
1＂～PAK
4＂, and with sub-package PAK
1＂～PAK
4＂ exports datalink layer connection 61 to.
Shown in Fig. 5 A, Fig. 5 B and Fig. 5 C, it is at data source and sink 5 neutron package PAK
1'～PAK
4' clock pulse running schematic diagram, for the data source and sink 5 easier quilts that make present embodiment are understood, below also please refer to Fig. 4 so that the embodiment of present embodiment to be described in detail.
Present embodiment is to be example with data source and sink 5 with four channels, and shown in Fig. 5 A, deciphering module 511～514 sees through four channels 501～504 and receives sub-package PAK respectively
1To PAK
4, suppose that the bias phenomenon of transmission package, sub-package PAK all do not take place each channel
1～PAK
4In time T
1To T
4Transmission in these channels 501～504 respectively during this time.Sub-package PAK after deciphering module 511～514 detecting deciphering of these channels
1' to PAK
4' content, and according to the sub-useful signal VAL of significant character activation correspondence
1～VAL
4In detail, in time T
1The time, the deciphering module 511 and 512 of first channel 501 and second channel 502 respectively according to significant character " stp " with " 02 " the corresponding sub-useful signal VAL of activation
1With VAL
2, in time T
4The time the 3rd channel 503 and the 4th channel 504 deciphering module 513 and 514 respectively according to the corresponding sub-useful signal VAL of significant character " 0E " and " end " activation
3With VAL
4Then, the deciphering module 511～514 of each channel transmits each sub-useful signal VAL
1～VAL
4To control module 53.
Control module 53 is according to each sub-useful signal VAL
1～VAL
4Produce a useful signal VAL
TAgain and then produce inhibit signal DEL, shown in Fig. 5 A, factor useful signal VAL
1With VAL
2In T
1Shi Zhineng, and sub-useful signal VAL
3With VAL
4In T
4So Shi Zhineng is useful signal VAL
TIn T
1With T
4Shi Zhineng.Because each channel of hypothesis there is no the generation bias phenomenon, also represents that the departure of separating of each channel is to be 0, so delay cell 531 is 0 with useful signal VAL according to separating departure
TPostpone the T of chronomere, and produce an inhibit signal DEL; Say that as above-mentioned institute inhibit signal DEL is useful signal VAL
TPostpone 1T, so inhibit signal DEL is in time T
2And T
5Shi Zhineng.
Then, running control unit 532 is according to inhibit signal DEL and useful signal VAL
TProduce a control signal CTL, shown in Fig. 5 A, wherein as inhibit signal DEL and useful signal VAL
TThe two one of during activation, control signal CTL is activation, so control signal CTL is in time T
1, T
2, T
4And T
5The time be activation; Then, running control unit 532 is sent to door control unit 533 respectively with control signal CTL.
Door control unit 533 at first with clock signal CLK and control signal CTL input door bolt to produce a gate-control signal CTL ', then again gate-control signal CTL ' and clock signal CLK are seen through and door generation gate clock signal GCL.Control signal CTL is in time T from the above
1, T
2, T
4And T
5Shi Zhineng, gate-control signal CTL ' is in time T
2, T
3, T
5And T
6Shi Zhineng, so this gate clock signal GCL is in time T
2, T
3, T
5And T
6Shi Zhineng is general clock signal, but in time T
4The time for suspending.Then, door control unit 533 is sent to gate clock signal GCL deviation module 521～524 is respectively separated deviation module 521～524 with control the running of separating of each channel.
Each channel separate deviation module 521～524th, respectively according to gate clock signal GCL running, with sub-package PAK
1' to PAK
4' separate deviation and become sub-package PAK
1＂ to PAK
4＂ then shown in Fig. 5 A, separates deviation module 521～524 with sub-package PAK
1＂ to PAK
4＂ is in time T
2To T
5Export datalink layer connection 61 simultaneously to.
The another embodiment of the present invention hypothesis is worked as each channel and is transmitted sub-package PAK
1' to PAK
4At least one channel generation of ' time bias phenomenon is shown in Fig. 5 B.The 3rd channel 503 transmits sub-package PAK
3Bias phenomenon takes place in ' time, so that the deciphering module 531 of the 3rd channel is in time T
2Receive sub-package PAK
3', than the deciphering module 511,512 and 514 of other channels receive time of sub-package late 1T, the departure of also representing each interchannel is to be 1T, so postpone unit 531 with useful signal VAL
TPostpone 1T and 2T respectively to produce two inhibit signal DEL
1With DEL
2Shown in Fig. 5 B, sub-package PAK
1' with PAK
2' in time T
1The time comprise significant character, PAK
3' in T
5The time, and PAK
4' then in T
4The time, so useful signal VAL
TBe in T
1, T
4With T
5Shi Zhineng.Inhibit signal DEL
1With DEL
2Be respectively useful signal VAL
TPostpone 1T and 2T, so DEL
1In T
2, T
5With T
6Shi Zhineng, DEL
2In T
3, T
6With T
7Shi Zhineng.As two inhibit signal DEL
1With DEL
2And useful signal VAL
TDuring one of them activation of three, it is activation that running control unit 532 is set control signal CTL, so control signal CTL is in time T
1To T
7The time be activation, and door control unit 533 promptly produces gate clock signal GCL according to control signal CTL and clock signal CLK.As shown in Figure 4, gate clock signal GCL is that clock signal CLK and control signal CTL produce through the door bolt of door control unit 533 with door, so gate clock signal GCL is in time T
2To T
8The time be activation, and the deviation module 521～524 of separating that is sent to each channel is respectively separated the running of deviation module 521～524 with control.
Then, each channel separates deviation module 521～524 respectively according to gate clock signal GCL running, with sub-package PAK
1' to PAK
4' separate deviation to produce sub-package PAK
1＂ to PAK
4＂ because bias phenomenons take place in the 3rd channel 503, so other channels separate deviation module 521,522 and 524 respectively with sub-package PAK
1＂, PAK
2＂ and PAK
4＂ postpones 2T, and the 3rd channel 503 separate deviation module 52 with sub-package PAK
3＂ postpones 1T, so that make the sub-package PAK of each channel
1＂ to PAK
4＂ can export datalink layer connection 61 simultaneously to.In the present embodiment, each channel separates deviation module 521～524 in time T
3To T
6With sub-package PAK
1＂ to PAK
4＂ exports datalink layer connection 61 simultaneously to.
In addition, shown in Fig. 5 C, the 3rd channel 503 transmits sub-package PAK
3Bias phenomenon takes place in ' time, so that the deciphering module 513 of the 3rd channel 503 is in time T
3Receive sub-package PAK
3', than the deciphering module 51 of other channels receive time of sub-package late 2T, the departure of also representing each interchannel is to be 2T, then delay cell 531 is useful signal VAL that the deciphering module 511 to 514 with each channel is produced
TPostpone 1T, 2T and 3T respectively to produce three inhibit signal DEL
1～DEL
3Shown in Fig. 5 C, sub-package PAK
1' with PAK
2' in time T
1The time have a significant character, sub-package PAK
3' in T
6The time, and sub-package PAK
4' then in T
4The time, so useful signal VAL
TBe in T
1, T
4With T
6Shi Zhineng.Inhibit signal DEL
1～DEL
3Be respectively useful signal VAL
TPostpone 1T, 2T and 3T, so DEL
1In T
2, T
5With T
7Shi Zhineng, DEL
2In T
3, T
6With T
8Shi Zhineng, DEL
3In T
4, T
7With T
9Shi Zhineng.As three inhibit signal DEL
1～DEL
3And useful signal VAL
TDuring one of four activations, it is activations that running control unit 532 is set control signal CTL, so control signal CTL is in time T
1To T
9The time be activation, and door control unit 533 is according to control signal CTL and clock signal CLK and produce gate clock signal GCL, wherein gate clock signal GCL is in time T
2To T
10The time be activation.Door control unit 533 is also respectively separated the running of deviation module 521～524 with the deviation module 521～524 of separating that gate clock signal GCL is sent to each channel with control.
Then, each channel separates deviation module 521～524 according to gate clock signal GCL running, with sub-package PAK
1' to PAK
4' separate deviation to produce sub-package PAK
1＂ to PAK
4＂.Because bias phenomenons take place in the 3rd channel 503, other channels separate deviation module 521,522 and 524 respectively with sub-package PAK
1＂, PAK
2＂ and PAK
4＂ postpones 3T, and the 3rd channel 503 separate deviation module 52 with sub-package PAK
3＂ postpones 1T, makes the sub-package PAK of each channel
1＂ to PAK
4＂ can export datalink layer connection 61 simultaneously to.In the present embodiment, each channel separate deviation module 521～524th, in time T
4To T
7With sub-package PAK
1＂ to PAK
4＂ exports datalink layer connection 61 to.
Fig. 6 is the flow chart of the data receiving-transmitting method of a preferred embodiment, at first receives a package in step S01 data source and sink, and partition becomes a plurality of sub-packages, and each deciphering module is deciphered each sub-package respectively and seen through corresponding channel and is sent to and respectively separates the deviation module.
Then in step S02, the significant character that each deciphering module is comprised according to sub-its content of package of having deciphered produces corresponding sub-useful signal respectively, then again with the synthetic useful signal of each sub-useful signal.The synthesis mode of useful signal is in wherein activation during any activation of sub-useful signal.
The maximum deviation amount that step S03 takes place when then transmitting each sub-package according to each interchannel postpones useful signal to produce a plurality of inhibit signals.When each interchannel zero deflection, delay units delay useful signal 1T is to produce an inhibit signal; When each interchannel maximum delay amount is 1T, then postpone useful signal 1T and 2T respectively to produce two inhibit signals; When each interchannel maximum delay amount is 2T, then postpone useful signal 1T, 2T and 3T respectively to produce three inhibit signals, the rest may be inferred.In brief, delay cell is that the maximum deviation amount of each interchannel is added 1T with as its retardation, postpones useful signal to produce the equal inhibit signal of retardation number therewith according to this retardation again, and wherein sequential differs 1T between each inhibit signal.
In step S04, the running control unit promptly produces a control signal according to these a plurality of inhibit signals and the useful signal that produce among the step S03, and control signal is in wherein activation during any activation of these above-mentioned a plurality of inhibit signals and useful signal.
Step S05 then produces a gate clock signal according to the control signal of running control unit output and the clock signal of clock pulse generation module output.When control signal and clock signal all during activation, the gate clock signal is activation, but since control signal and clock signal need earlier through postponing, the therefore actual gate clock signal of exporting be than control signal and clock signal all the clock pulse of activation delay activation.
At last in step S06, respectively separate the sub-package that deciphering module transmitted that the deviation module is separated the deviation correspondence respectively, and separated the sub-package of deviation according to gate clock signal output, but make these sub-packages of each channel synchronous transmission to datalink layer connection, take place and there is any deviation.
In sum, because of data source and sink of the present invention is the content of detecting the package that is received, when the significant character that detects package (be NOT logic idle symbol), control module just can provide the work time pulse signal, in other words, when the logic that detects package is left unused symbol, control module is suspended provides the work time pulse signal, so as to reducing corresponding electrical source consumption, therefore suitably the control data R-T unit transmits the running of package, and then can increase province's electrical efficiency of communication device effectively.Except four channels, data source and sink of the present invention also can have the channel of other quantity, and corresponding have the deciphering module that equates with channel quantity and separate the deviation module, and the transmission of its package is also as the rule of above-mentioned embodiment.
Though the present invention by the preferred embodiment explanation as above, this preferred embodiment is not in order to limit the present invention.Those skilled in the art without departing from the spirit and scope of the present invention, should have the ability this preferred embodiment is made various changes and replenished, so protection scope of the present invention is as the criterion with the scope of claims.
Being simply described as follows of symbol in the accompanying drawing:
1,3,5: data source and sink
10: channel
11: decipher
12: separate deviator
13: the clock pulse generator
20,40,60: the circuit entity layer
21,41,61: datalink layer connection
31,511～514: deciphering module
32,521～524: separate the deviation module
33,53: control module
331,531: delay cell
332,532: the running control unit
333,533: door control unit
34,54: the clock pulse generation module
501: the first channels
502: second channel
503: the three channels
504: the four channels
5310: delayer
OR0～OR2: or door
PAK, PAK ', PAK ＂: package
PAK1～PAK4, PAK1 '～PAK4 ', PAK1 ＂～PAK4 ' ': sub-package
T1～T18: time
Stp, 02,0E, end, 00: symbol
CLK: clock signal
VAL, VALT: useful signal
VAL1～VAL4: sub-useful signal
DEL, DEL1～DEL3: inhibit signal
CTL: control signal
CTL ': gate-control signal
GCL: gate clock signal
S01～S06: the step of data receiving-transmitting method
Claims (14)
1. a data source and sink is characterized in that, described data source and sink comprises:
At least one channel, each this channel is to have a deciphering module and to separate the deviation module, this deciphering module receives at least one package and this package is deciphered, and according at least one significant character activation one useful signal of this package, this is separated deviation module and this deciphering module and electrically connects and this package is separated deviation; And
One control module is separated the electric connection of deviation module with this deciphering module and this, receives this useful signal, a departure and a clock pulse signal to produce a gate clock signal;
Wherein this to separate the deviation module be respectively according to the running of this gate clock signal, to carry out the deviation of separating of this package.
2. data source and sink according to claim 1 is characterized in that, more comprises:
One clock pulse generation module is to produce this clock signal, and this control module is this clock signal of gate producing this gate clock signal, and this gate clock signal is inputed to this separates the deviation module.
3. data source and sink according to claim 1 is characterized in that, activation when one of them comprises this significant character in this package of this useful signal.
4. data source and sink according to claim 2 is characterized in that, this control module comprises:
One delay cell is to electrically connect with this deciphering module, and postpones this useful signal to produce at least one inhibit signal;
One running control unit is to electrically connect with this deciphering module and this delay cell, and according at least one control signal of the corresponding generation with this inhibit signal of this useful signal; And
One door control unit is to receive this clock signal, and electrically connects with this running control unit, and according to this this clock signal of control signal gate to produce this gate clock signal.
5. data source and sink according to claim 4 is characterized in that, when this useful signal and one of them activation of this inhibit signal, this control signal is activation.
6. data source and sink according to claim 4 is characterized in that, this delay cell is to postpone this useful signal to produce this inhibit signal according to this departure.
7. data source and sink according to claim 6, it is characterized in that, this delay cell is to postpone this useful signal to produce this inhibit signal of a plurality of time of delay of inequality according to this departure, when this useful signal and one of them activation of this inhibit signal, this running control unit is that this control signal of setting is activation.
8. data source and sink according to claim 4 is characterized in that, this door control unit produces a gate-control signal according to this control signal and this clock signal, and when this gate-control signal and this clock signal activation, this gate clock signal is activation.
9. a data receiving-transmitting method is characterized in that, described data receiving-transmitting method is used at least one interchannel and transmits at least one package, and each this channel comprises a deciphering module and and separates the deviation module, and the step of this data receiving-transmitting method comprises:
At least one significant character according to this package produces a useful signal;
According to this useful signal, a departure and a clock pulse signal, to produce a gate clock signal; And
This separates the deviation module is respectively according to this gate clock signal running, to carry out the deviation of separating of this package.
10. data receiving-transmitting method according to claim 9 is characterized in that, the step that produces this useful signal according to this significant character of this package more comprises:
Distinguish the sub-useful signal of activation one correspondence according to this significant character of each this package that each this channel transmitted; And
This sub-useful signal wherein any when the activation, this useful signal of activation.
11. data receiving-transmitting method according to claim 9 is characterized in that, the step that produces this gate clock signal according to this useful signal and this clock signal more comprises:
Postpone this useful signal to produce at least one inhibit signal according to this departure;
According to this inhibit signal and this useful signal to produce a control signal; And
According to this control signal and this clock signal to produce this gate clock signal.
12. data receiving-transmitting method according to claim 11 is characterized in that, postpones this useful signal according to this departure and comprises with the step that produces this inhibit signal:
This useful signal is postponed this departure add a time of delay unit again, to produce this inhibit signal.
13. data receiving-transmitting method according to claim 11 is characterized in that, comprises with the step that produces this control signal according to this inhibit signal and this useful signal:
When this inhibit signal and this useful signal wherein during any activation, this control signal is activation.
14. data receiving-transmitting method according to claim 11 is characterized in that, comprises with the step that produces this gate clock signal according to this control signal and this clock signal:
With this control signal and this clock signal input one door bolt, to produce a gate-control signal; And
When this gate-control signal and this clock signal activation, this gate clock signal is activation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101118650A CN100539453C (en) | 2006-08-29 | 2006-08-29 | Data source and sink and method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101118650A CN100539453C (en) | 2006-08-29 | 2006-08-29 | Data source and sink and method |
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| Publication Number | Publication Date |
|---|---|
| CN1937428A CN1937428A (en) | 2007-03-28 |
| CN100539453C true CN100539453C (en) | 2009-09-09 |
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| CNB2006101118650A Active CN100539453C (en) | 2006-08-29 | 2006-08-29 | Data source and sink and method |
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| Country | Link |
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| CN (1) | CN100539453C (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003233434A (en) * | 2001-12-06 | 2003-08-22 | Matsushita Electric Ind Co Ltd | Electric power consumption management device |
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2006
- 2006-08-29 CN CNB2006101118650A patent/CN100539453C/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003233434A (en) * | 2001-12-06 | 2003-08-22 | Matsushita Electric Ind Co Ltd | Electric power consumption management device |
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| Publication number | Publication date |
|---|---|
| CN1937428A (en) | 2007-03-28 |
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