CN100536350C - Circuit and method for realizing the coding - Google Patents
Circuit and method for realizing the coding Download PDFInfo
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- CN100536350C CN100536350C CNB2007100075760A CN200710007576A CN100536350C CN 100536350 C CN100536350 C CN 100536350C CN B2007100075760 A CNB2007100075760 A CN B2007100075760A CN 200710007576 A CN200710007576 A CN 200710007576A CN 100536350 C CN100536350 C CN 100536350C
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Abstract
The invention relates to coding techniques, supplies a method to realize coding, the method based on the code circuit realization, in the code circuit including one or more than one same sub-encoder, the sub-encoder includes n middle result delay store unit, n is the numbers of the code word which input into the encoder, n is a integer which is more than one, the method also includes the following steps: The code combinatory logic unit coding treat with the received symbol stream and saved the testing code element in to the corresponging middle result delay store unit. The invention also provided a circuit to realize the coding, through used the code electric circuit method which the invention provided to reduce the coded circuit scale, meanwhile reduced the time which the code needed.
Description
Technical field
The present invention relates to coding techniques, the particularly a kind of circuit and method of encoding of realizing.
Background technology
Bo Si-Cha Dehuli-Huo Kun lattice nurse (BCH) sign indicating number is by rich this (Bose), Cha Dehuli (Chaudhuri) and Huo Kun lattice nurse (Hocquenhem) invention, so name with the beginning letter of these three inventor's names.
BCH code is a kind of cyclic code, utilizes division to carry out error correction.Reed-Solomon (RS) sign indicating number is a kind of of BCH code, and this yard is taken as a kind of special BCH code, do not distinguish BCH code and RS sign indicating number in the present invention, is referred to as BCH code.Error correcting capability and circuit easily realize because BCH code has preferably, therefore are widely used in communication system.Introduce the circuit of realizing the BCH code coding in the prior art below.
Fig. 1 is a structural representation of realizing first kind of circuit of BCH code coding in the prior art.As shown in Figure 1, this circuit comprises: sub-encoders 1, sub-encoders 2.... sub-encoders m.
Constitute total encoding and decoding if total m code word interweaves, a code word is a subcode of importing in the data, and the sign indicating number type of related code word is the sign indicating number type of same type in present specification.Fig. 2 is the structural representation of m code word in the data flow.As shown in Figure 2, this m code word adopts the mode that interleaves to sort, and first code element of m code word of discharging is second code element of m code word then earlier, is arranged in order down, up to p code element of m code word.
P+1 code element of this m code word is input to sub-encoders 1 respectively successively, sub-encoders 2... sub-encoders m.M sub-encoders carries out encoding process to m code word under the control of control circuit, then m code word of encoded processing outputed to decoding circuit and carry out decoding processing.This shows, because the sign indicating number type of m code word is identical, sub-encoders 1, sub-encoders 2... sub-encoders m are identical sub-encoders, therefore, this circuit design scheme is very simple, but has such problem: each sub-encoders only is responsible for handling a code word, therefore can cause the scale of circuit huger, in addition, the utilance of circuit resource is not high.
BCH code coding circuit resource utilization is not high as can be seen from such scheme, introduces second kind of circuit arrangement of realizing the BCH code coding after improving below.
Fig. 3 is a structural representation of realizing second kind of circuit of BCH code coding in the prior art.As shown in Figure 3, this circuit comprises: first data buffer storage unit 300, second data buffer storage unit 320 and sub-encoders 310.
Wherein, sub-encoders 310 comprises: sub-encoders 1, sub-encoders 2.... sub-encoders k.N among Fig. 3 represents the multiplexing number of sub-encoders 310, also is the number of the code word of each sub-encoders processing.M is the number that is input to the code word of coding circuit, the number of the code word that comprises in the data flow of expression input.N equals the value of Rin divided by the carry integer of Rd, and for example, Rin equals 9.6Mbps, and Rd equals 3Mbps, gets n so and equals 4, and wherein, Rin is the bandwidth of the data flow of input, and Rd represents the data bandwidth that each sub-encoders can be handled.
Because each sub-encoders 310 multiplexing number of times is n, so each sub-encoders will be successively to the 1st, the 2nd .... n code word carried out encoding process.As seen from Figure 2, because n code word interleaves ordering, if this n code word is encoded successively, at first need this n code word is stored in first data buffer storage unit 300, then according to (the 1st code element of subcode 0, the 2nd code element of subcode 0 .... p+1 code element of subcode 0), ... (the 1st code element of subcode n-1, the 2nd code element of subcode n-1 ... p+1 the code element of subcode n-1) order, therefrom reading this n subcode successively delivers to sub-encoders 310 and encodes, the one or more code elements of sub-encoders 310 each period treatment, and then the information code element of the code word after the encoding process put into second metadata cache 320.After sub-encoders 310 is finished the coding of this n code word, sub-encoders 310 is inserted into the code word of this n encoded processing in the data flow successively and exports, the method that the code word of encoded processing is inserted in the data flow successively is, information code element with each code word is inserted in the data flow earlier, and then the verification code element of each code word is inserted into successively the check digit of corresponding code word, for example, the verification code element of first code word is inserted into the check digit of this code word.
First data buffer storage unit 300 is used to receive and deposit the preceding code word of coding, and each code word is outputed to sub-decoder 310.
Second data buffer storage unit 320, be used to receive the information code element of each code word behind the coding of sub-encoders 310 outputs, after sub-encoders 310 carried out encoding process to this n code word, data buffer storage unit was inserted into the information code element of this n code word in the data flow successively.
Fig. 4 is the structural representation of sub-encoders in the encoder shown in Figure 3.As shown in Figure 4, this sub-encoders comprises: coded combination logical block 401 and scratch-pad register 402.
Coded combination logical block 401, be used for reading n code word from second data buffer storage unit 320, successively p+1 code element of n code word reading carried out encoding process, 401 each cycle of coded combination logical block are handled one or more code elements successively, the verification code element of p+1 code element of first code word after the encoded processing is put into scratch-pad register 402, the information code element of this p+1 code element is directly outputed to second data buffer storage unit 320.Coded combination logical block 401 is carried out the encoding process of second code word again, goes on successively, up to the p+1 that handles a n code word code element.
Scratch-pad register 402, the verification code element that is used for the code word of the encoded processing that received code combinatorial logic unit 401 sends, after 401 pairs of n code words of coded combination logical block were carried out encoding process, scratch-pad register 402 was inserted into this n code word verification code element after the information code element of this n code word.
By above-mentioned second kind of encoding scheme of the prior art as can be seen, compare to first kind of scheme, this scheme has improved the service efficiency of circuit resource.But need to interleave earlier the code word of discharging, the data buffer storage unit of depositing with the order of code word 1, code word 2..... code word n, this coding circuit is read the single code word of depositing one by one and is carried out encoding process, and the information code element of the code word after will encoding is stored in buffer once more, and the verification code element of code word is stored in the intermediate object program buffer unit.This shows, will occupy the regular hour to reading of code word and deposit operation, so can there be bigger time-delay in encoder.In addition, the data buffer storage unit in the encoder takies bigger circuit resource, thereby causes the circuit scale of encoder bigger.
This shows that in the prior art, the coding circuit of employing required scramble time when encoding is longer, and the circuit scale of coding circuit is bigger.
Summary of the invention
Embodiments of the invention provide a kind of realization Methods for Coding, and this coding method can reduce the scale of coding circuit.
Embodiments of the invention provide a kind of circuit of encoding realized, this coding circuit can reduce the scale of coding circuit.
In order to reach first purpose of the present invention, the embodiment of the invention provides a kind of realization Methods for Coding, this method realizes based on coding circuit, comprise the sub-encoders that one or more are identical in the coding circuit, it is characterized in that sub-encoders comprises n intermediate object program buffer unit, n is the number that is input to the code word of sub-encoders, n is the integer greater than 1, and this method may further comprise the steps:
The coded combination logical block receives code stream, the code word in the described code stream that receives is carried out Bose-Chaudhuri-Hocquenghem Code handle, and the verification code element of the code word of described encoded processing is stored in intermediate object program buffer unit with the corresponding ordering of described code word.
In order to reach second purpose of the present invention, the embodiment of the invention provides a kind of circuit of encoding realized, this circuit comprises: the sub-encoders that one or more are identical; It is characterized in that described sub-encoders comprises: coded combination logical block and n intermediate object program buffer unit, n is the number that is input to the code word of sub-encoders, and n is the integer greater than 1;
Described coded combination logical block is used to receive code stream, the code word in the described code stream that receives is carried out Bose-Chaudhuri-Hocquenghem Code handle, and is used for verification code element with the code word of described encoded processing and outputs to intermediate object program buffer unit with the corresponding ordering of described code word;
Described intermediate object program buffer unit is used to receive and deposit the verification code element of the code word of the described corresponding ordering with self that described coded combination logical block sends.
The technical scheme that provides by the embodiment of the invention, this method realizes based on coding circuit, comprise the sub-encoders that one or more are identical in the coding circuit, sub-encoders comprises n intermediate object program buffer unit, n is the number that is input to the code word of sub-encoders, wherein, n is the integer greater than 1; The coded combination logical block receives code stream, and the code word in the code stream that receives is carried out encoding process, the verification code element of the code word of encoded processing is stored in the intermediate object program buffer unit of corresponding ordering with this code word.
By above-mentioned scheme as can be seen, data buffer storage unit takies bigger circuit resource, does not comprise this data buffer storage unit in the coding circuit that the embodiment of the invention provided, but n intermediate object program buffer unit is set in each sub-encoders; The shared circuit resource of each intermediate object program buffer unit is very little, and the circuit scale of all intermediate object program buffer units is much smaller than the shared circuit scale of data buffer storage unit in this coding circuit, so the technical scheme of the embodiment of the invention has reduced the scale of coding circuit.
Description of drawings
Fig. 1 is a structural representation of realizing first kind of circuit of BCH code coding in the prior art;
Fig. 2 is the structural representation of m code word in the data flow;
Fig. 3 is a structural representation of realizing second kind of circuit of BCH code coding in the prior art;
Fig. 4 is the structural representation of sub-encoders in the encoder shown in Figure 3;
Fig. 5 is the schematic flow sheet of first preferred embodiment of method of the realization Bose-Chaudhuri-Hocquenghem Code of the embodiment of the invention;
Fig. 6 is the structural representation of second preferred embodiment of circuit of the realization BCH code coding of the embodiment of the invention.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, the present invention is described in further detail below in conjunction with accompanying drawing.
Embodiments of the invention provide circuit and the method that realizes coding, disposal ability and the number that is input to the code word of coding circuit according to sub-encoders, one or more identical sub-encoders are set in encoder, wherein, the number of sub-encoders is: the number of code word that is input to coding circuit is divided by the value of the disposal ability gained merchant's of sub-encoders carry integer, the number that wherein is input to the code word of coding circuit is meant, the number of code word, i.e. interleave depth in being input to one section interleaving data code stream of coding circuit.More than one intermediate object program buffer unit is set in sub-encoders, and the number of this intermediate object program buffer unit equals the number of the code word that this sub-encoders can handle.The coded combination logical block of sub-encoders is carried out encoding process to the code word that receives, and the verification code element of the code word after the encoded processing is stored in the intermediate object program buffer unit of corresponding ordering with this code word.After the coded combination logical block was finished encoding process to all code words, the intermediate object program buffer unit was inserted into the verification code element of these code words in the data flow successively and exports.
Fig. 5 is the schematic flow sheet of first preferred embodiment of method of the realization Bose-Chaudhuri-Hocquenghem Code of the embodiment of the invention.As shown in Figure 5, this method comprises:
Step 501: the intermediate object program buffer unit that number equals code word number is set in sub-encoders.
In this step, if each sub-encoders will be handled n code word, the number of intermediate object program buffer unit should equate with the number of the code word of its processing, promptly in the middle of the number of buffer unit also be that n is individual.
Step 502: the coded combination logical block in the sub-encoders receives code stream, and the code word in the code stream that receives is carried out encoding process.
In this step, the coded combination logical block receives n code word of code stream, and each code element of this n code word is carried out encoding process.That BCH code is carried out Methods for Coding is identical for the coded combination logical block in coding method that it is pointed out that here to be mentioned and the prior art, and the embodiment of the invention is not improved coding rule.
In this step, the coded combination logical block is carried out encoding process according to the order of the data flow of input to the code element of each code word, for example, the 1st clock cycle handles the 1st code element of subcode 0, the 2nd clock cycle handles the 1st code element of subcode 1, ... .., n clock cycle, encode to the 1st code element of subcode n-1.The rest may be inferred, and then successively the 2nd code element of n code word carried out encoding process, carries out encoding process up to p+1 the code element of finishing n code word.
Step 503: the coded combination logical block is stored in the verification code element of the code word of encoded processing the intermediate object program buffer unit of corresponding ordering with this code word.
In this step, the verification code element of the code word of encoded processing is stored in the intermediate object program buffer unit of corresponding ordering with this code word the most at last.Concrete steps are in the middle of it: the verification code element with the code word of encoded processing is stored in last intermediate object program buffer unit successively, when receiving the verification code element of a back code word, the verification code element of the code word deposited in advance in this intermediate object program buffer unit is displaced in the previous element of this intermediate object program buffer unit; If this intermediate object program buffer unit is an intermediate object program buffer unit 1, said so here unit is the coded combination logical block; If this intermediate object program buffer unit is not an intermediate object program buffer unit 1, said so here unit is the previous intermediate object program buffer unit of this intermediate object program buffer unit.
The verification code element of the 1st code element of subcode 0 is outputed among the intermediate object program buffer unit n, verification code element with the 1st code element of subcode 1 outputs among the intermediate object program buffer unit n then, verification code element with the 1st code element of the subcode 0 deposited among the intermediate object program buffer unit n is displaced among the intermediate object program buffer unit n-1 simultaneously, that is to say, what preserved among the intermediate object program buffer unit n-1 this moment is the verification code element of the 1st code element of subcode 0, what preserve among the intermediate object program buffer unit n is the verification code element of the 1st code element of subcode 1, verification code element with the 1st code element of subcode n-1 is stored in n intermediate object program buffer unit at last, verification code element with the 1st code element of the subcode n-2 that deposits among the middle buffer memory n is displaced among the intermediate object program buffer memory n-1 simultaneously, ...., the verification code element of the 1st code element of the subcode 0 deposited in the intermediate object program buffer unit 2 is displaced to intermediate object program buffer unit 1.At this moment, what preserve in the intermediate object program buffer unit 1 is the verification code element of the 1st code element of subcode 0, what preserve in the intermediate object program buffer memory 2 is the verification code element of the 1st code element of subcode 1 ..., what preserve among the intermediate object program buffer memory n is the verification code element of the 1st code element of subcode n-1.
When the 2nd code element of all code words encoded, elder generation outputs to the verification code element of the 2nd code element of subcode 0 among the intermediate object program buffer unit n, and the verification code element that will leave the 1st code element of the subcode n-1 among the intermediate object program buffer unit n then in advance in is displaced among the intermediate object program buffer unit n-1; To then the verification code element of the 1st code element of the subcode n-2 that deposits among the intermediate object program buffer unit n-1 be displaced among the intermediate object program buffer unit n-2 ... the verification code element of the 1st code element of the subcode 0 deposited in the intermediate object program buffer unit 1 is displaced to the coded combination logical block.The rest may be inferred, finishes the coding to all code elements of code word successively, last, what preserve in the intermediate object program buffer memory 1 is exactly the verification code element of subcode 0, what preserve in the intermediate object program buffer memory 2 is exactly the verification code element of subcode 1 ..., what preserve among the intermediate object program buffer memory n is exactly the verification code element of subcode n-1.
Because coded combination logical block, intermediate object program buffer unit 1, intermediate object program buffer unit 2...... intermediate object program buffer unit n is end to end, after a code element of n code word carried out encoding process, earlier the verification code element of all code elements is stored in the intermediate object program buffer unit of corresponding ordering with it, when a back code element of this n code word is carried out encoding process, need to leave in all the verification code elements in the intermediate object program buffer unit, be input to the coded combination logical block successively and participate in encoding operation, the coding of a promptly back code element needs the coding result of previous code element.It is to be noted, the coded combination logic is carried out encoding process to the code element that is input to the code word on it, what obtain is the intermediate object program of verification code element, after all being carried out encoding process, the code element of all code words just produces the verification code element of these code words, coding intermediate object program is the part of verification code element, for the purpose of unification, be referred to as the verification code element here.
In this step, what n intermediate object program buffer unit deposited is the verification code element of n code word, after the coded combination logical block is carried out encoding process to the information code element of n code word, does not preserve and directly exports.
Step 504: after all code words all are carried out encoding process, with the verification code element output of the code word of encoded processing.
In this step, after the coded combination logical block is all carried out encoding process to n code word, the intermediate object program buffer unit is inserted into the verification code element of this n code word successively in the code stream check digit of each code word and exports according to depositing order, and promptly intermediate object program buffer unit 1, intermediate object program buffer unit 2...... intermediate object program buffer unit n are inserted into the verification code element of stored code word in the data flow successively and export.
In the present embodiment, coding circuit comprises more than one identical sub-encoders, the number of sub-encoders equals to be input to the number of code word of coding circuit divided by the value of the disposal ability gained merchant's of sub-encoders carry integer, because being input to the number of the code word of coding circuit is the number of total code word of input, the disposal ability of sub-encoders is the number of the code word that can handle of each sub-encoders, so the shared bandwidth Rd of code word that the shared bandwidth Rin of total code word of the as many as input of number of sub-encoders can handle divided by sub-encoders, the value of gained merchant's carry integer.Related in the present embodiment code word is the code word of Bose-Chaudhuri-Hocquenghem Code, and the sign indicating number type of each code word is all identical, and related intermediate object program buffer unit 1～intermediate object program buffer unit n can be shift register, random access memory (RAM) and first-in first-out (FIFO) etc.
In the present embodiment, k identical sub-encoders is set in encoder in advance, wherein, the disposal ability n that the number k of sub-encoders multiply by sub-encoders equals to be input to the number m of the code word of coding circuit, promptly equals the number m of all code words in the input data bitstream stream.N intermediate object program buffer unit is set in each sub-encoders then, and promptly the number of intermediate object program buffer unit equals the number n of the code word that this sub-encoders can handle, and the size of intermediate object program buffer unit equals the size of the verification code element of code word.Need not in embodiments of the present invention in advance m code word that interleaves ordering to be stored in data buffer storage unit, and then from data buffer storage unit, read m code word successively, send to the coded combination logical block and carry out encoding process, therefore just reduced and in data buffer storage unit, deposited the required time of code word, required time with from data buffer storage unit, reading code word, thereby can reduce the required time of coding.
Embodiment shown in Figure 5 is the introduction to the BCH code Methods for Coding, below to introduce the structure of the coding circuit of realizing technical solution of the present invention.
This coding circuit comprises the sub-encoders that one or more are identical; And sub-encoders comprises: coded combination logical block and number equal to be input to the intermediate object program buffer unit of number of the code word of sub-encoders.
The coded combination logical block is used to receive code stream, and the code word in the code stream that receives is carried out encoding process, and the verification code element that is used for that encoding process is obtained outputs to the intermediate object program buffer unit of corresponding ordering with this code word.
The intermediate object program buffer unit is used to receive and deposit the verification code element of the code word of the corresponding ordering with self that the coded combination logical block sends.
Than prior art as can be seen, this coding circuit does not comprise data buffer storage unit; Only comprise one or more sub-encoders, each sub-encoders comprises several intermediate object program buffer units, and the number of intermediate object program buffer unit equals to be input to the number of the code word of this sub-decoder.Because data buffer storage unit occupies very big circuit resource, but the circuit resource that the intermediate object program buffer unit takies is very little, this shows the scale that can reduce coding circuit greatly.
The number n of intermediate object program buffer unit can be for greater than 1 integer, and number n=3 with the intermediate object program buffer unit are example below, introduce the structure of the circuit of realizing the BCH code coding.
Fig. 6 is the structural representation of second preferred embodiment of circuit of the realization BCH code coding of the embodiment of the invention.As shown in Figure 6, this coding circuit 600 comprises: the 1st sub-encoders the 610, the 2nd sub-encoders 620.... and k sub-encoders 630.Wherein, the 1st sub-encoders 610 comprises again: coded combination logical block the 611, the 1st intermediate object program buffer unit the 612, the 2nd intermediate object program buffer unit the 613, the 3rd intermediate object program buffer unit 614.
In the present embodiment, the internal structure of the 1st sub-encoders the 610, the 2nd sub-encoders 620.... and k sub-encoders 630 is identical, is the internal structure that example is introduced sub-encoders with the 1st sub-encoders 610 below.
Coded combination logical block 611 is used for receiving the code word of the code stream of input, and the code word that receives is carried out encoding process.Coded combination logical block 611 is used for the verification code element of the code word of encoded processing is outputed to the 3rd intermediate object program buffer unit 614, and the data code flow of the information code element of the code word of encoded processing is directly exported.
Code processing method that the embodiment of the invention relates to and code processing method of the prior art are identical, just do not do here and give unnecessary details.If the 1st sub-encoders 610 can be handled n=3 code word, the number of the intermediate object program buffer unit of the 1st sub-encoders 610 inside also is n=3 so.
The 1st intermediate object program buffer unit 612 when being used to receive the verification code element of the 2nd intermediate object program buffer unit 613 outputs, and outputs to coded combination logical block 611 with the verification code element of the current code word of depositing.
The 2nd intermediate object program buffer unit 613 be used to receive the verification code element that the 3rd intermediate object program buffer unit 614 is exported, and the verification code element that will deposit before outputs to the 1st intermediate object program buffer unit 612.
The 3rd intermediate object program buffer unit 614 is used for the verification code element that received code combinatorial logic unit 611 is exported, and the verification code element that will deposit before outputs to the 2nd intermediate object program buffer unit 613.
The 1st intermediate object program buffer unit the 612, the 2nd intermediate object program buffer unit 613 and the 3rd intermediate object program buffer unit 614, the verification code element that also is used for these 3 code words is inserted into after the information code element of these 3 code words successively, exports.
N is the integer greater than 1, when n=2, so just only comprises the 1st intermediate object program buffer unit and the 2nd intermediate object program buffer unit.At this moment, the 1st intermediate object program buffer unit when being used to receive the verification code element of the 2nd intermediate object program buffer unit output, and outputs to the coded combination logical block with the verification code element of the current code word of depositing.The 2nd intermediate object program buffer unit be used for the verification code element that the received code combinatorial logic unit is exported, and the verification code element that will deposit in advance outputs to the 1st intermediate object program buffer unit.The operation principle of each intermediate object program buffer unit is the same.
By embodiment shown in Figure 6 as can be seen, the technical scheme of the relevant BCH code coding circuit that the embodiment of the invention provided, k identical sub-encoders at first is set in coding circuit, each sub-encoders can be handled n code word, satisfy n*k=m, wherein, m is the number that is input to the code word of coding circuit, i.e. the number of the total code word in the data code flow.N intermediate object program buffer unit is set in each sub-encoders, and the intermediate object program buffer unit is deposited the verification code element of the code word after the encoded processing of corresponding ordering with it.As seen, in the coding circuit that this embodiment provided, comprise n intermediate object program buffer unit, and do not comprise data buffer storage unit.Because data buffer storage unit has bigger circuit scale, the size of intermediate object program buffer unit equals the size of verification code element, therefore take less circuit resource, compare to BCH code coding circuit of the prior art, the technical scheme that the embodiment of the invention provided can reduce the scale of circuit greatly.
Coding circuit that the embodiment of the invention provided and method mainly are circuit and the methods that designs at BCH code, have being equal to of same principle, the circuit that substitutes and method also within protection scope of the present invention for other.
In sum, more than be preferred embodiment of the present invention only, be not to be used to limit protection scope of the present invention.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1, a kind of realization Methods for Coding, this method realizes based on coding circuit, comprise the sub-encoders that one or more are identical in the coding circuit, it is characterized in that, sub-encoders comprises n intermediate object program buffer unit, n is the number that is input to the code word of sub-encoders, and n is the integer greater than 1, and described method specifically comprises:
Described sub-encoders receives code stream, the code word in the code stream that receives is carried out Bose-Chaudhuri-Hocquenghem Code handle, and the verification code element that described encoding process is obtained is stored in the intermediate object program buffer unit with the corresponding ordering of described code word.
2, method according to claim 1 is characterized in that, the code word in the described code stream that receives is carried out encoding process, and the verification code element that described encoding process is obtained is stored in the method for the intermediate object program buffer unit of the corresponding ordering of described code word and comprises:
The coded combination logical block is carried out encoding process to the code word in the described code stream that receives, and each verification code element that described encoding process is obtained outputs to n intermediate object program buffer unit successively,
When k intermediate object program buffer unit receives the verification code element, the verification code element of depositing is before outputed to k-1 intermediate object program buffer unit, and the verification code element that receives of storage, wherein k is greater than 1 and smaller or equal to the natural number of n;
When the 1st intermediate object program buffer unit receives the verification code element, the verification code element that storage receives, and the verification code element that will deposit before outputs to the coded combination logical block;
The coded combination logical block receives the verification code element of the 1st intermediate object program buffer unit output, according to the verification code element that receives, the code word that receives is carried out encoding process.
3, method according to claim 1 and 2 is characterized in that, the verification code element that described encoding process is obtained is stored in after the intermediate object program buffer unit with the corresponding ordering of described code word, further comprises:
After all code words that receive are finished encoding process, the verification code element of the code word of described encoded processing is inserted into successively the check digit of corresponding code word in the described code stream.
4, method according to claim 1 is characterized in that, described code word is the code word of Bo Si-Cha Dehuli-Huo Kun lattice nurse Bose-Chaudhuri-Hocquenghem Code.
5, method according to claim 1 is characterized in that, the sign indicating number type of described code word is identical.
6, method according to claim 1 and 2 is characterized in that, the number of described sub-encoders equals to be input to the number of code word of described coding circuit divided by described sub-encoders disposal ability gained merchant's carry integer value.
7, a kind of circuit of encoding realized, this circuit comprises the sub-encoders that one or more are identical;
It is characterized in that described sub-encoders comprises: coded combination logical block and n intermediate object program buffer unit, n is the number that is input to the code word of sub-encoders, and n is the integer greater than 1;
Described coded combination logical block is used to receive code stream, the code word in the described code stream that receives is carried out Bose-Chaudhuri-Hocquenghem Code handle, and the verification code element that described encoding process is obtained outputs to the intermediate object program buffer unit with the corresponding ordering of described code word;
Described intermediate object program buffer unit is used to receive and deposit the verification code element of the code word of the described corresponding ordering with self that described coded combination logical block sends.
8, circuit according to claim 7 is characterized in that, the number of described sub-encoders equals to be input to the number of code word of coding circuit divided by the value of described sub-encoders disposal ability gained merchant's carry integer.
9, circuit according to claim 7 is characterized in that, described sub-encoders comprises two intermediate object program buffer units;
Described first intermediate object program buffer unit when being used to receive the verification code element of second intermediate object program buffer unit output, is deposited described verification code element, and the verification code element that will deposit before outputs to the coded combination logical block;
Described second intermediate object program buffer unit is when being used to receive the verification code element of described coded combination logical block output; Deposit described verification code element, and the verification code element that will deposit before outputs to first intermediate object program buffer unit.
10, circuit according to claim 7 is characterized in that, described sub-encoders comprises: n intermediate object program buffer unit, n are the natural number greater than 2;
In described n the intermediate object program buffer unit:
The 1st intermediate object program buffer unit, when being used to receive the verification code element of the 2nd intermediate object program buffer unit output, deposit the verification code element of described the 2nd intermediate object program buffer unit output, and the verification code element that will deposit before outputs to the coded combination logical block;
N intermediate object program buffer unit, when being used to receive the verification code element of described coded combination logical block output, deposit the verification code element of described coded combination logical block output, and the verification code element that will deposit before outputs to n-1 intermediate object program buffer unit;
K intermediate object program buffer unit, when being used to receive the verification code element of k+1 intermediate object program buffer unit output, deposit the verification code element of described k+1 intermediate object program buffer unit output, and the verification code element that will deposit before outputs to k-1 intermediate object program buffer unit, wherein, k is greater than 1 and less than the natural number of n;
Described coded combination logical block, be further used for receiving the verification code element of the 1st intermediate object program buffer unit output, verification code element according to described the 1st intermediate object program buffer unit output, the code word that receives is carried out encoding process, the verification code element after the encoding process is outputed to n intermediate object program buffer unit.
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