CN102468902A - Method for Turbo coding of rate match/de-rate match in LTE (long term evolution) system - Google Patents
Method for Turbo coding of rate match/de-rate match in LTE (long term evolution) system Download PDFInfo
- Publication number
- CN102468902A CN102468902A CN201010532617XA CN201010532617A CN102468902A CN 102468902 A CN102468902 A CN 102468902A CN 201010532617X A CN201010532617X A CN 201010532617XA CN 201010532617 A CN201010532617 A CN 201010532617A CN 102468902 A CN102468902 A CN 102468902A
- Authority
- CN
- China
- Prior art keywords
- data
- address
- word
- matrix
- check
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
The invention provides a method for Turbo coding of rate match/de-rate match in an LTE (long term evolution) system. The method comprises the following steps of: confirming an interweaving mode according to the date length K of a code block; obtaining a system matrix according to a system bit stream, wherein a first check bit stream P1 and a second check bit stream P2 are alternately stored to obtain a check matrix, every eight lines from a first line of the system matrix is taken as a subsystem matrix, and every eight lines from a first line of the check matrix is taken as a subsystem check matrix; confirming a system matrix address and a check matrix address; putting the system bit stream in the address after the data is packed, and putting the check bit stream into the check matrix address after the data is packed; and outputting the data in the system matrix address and the check matrix address according to lines, so that the bit stream after the rate match/de-rate match can be obtained. After the method is used, the speed of rate match/de-rate match can be accelerated.
Description
Technical field
The present invention relates to communication technical field, more specifically, relate to the method that rate-matched is mated/separated to the Turbo of LTE system code rate.
Background technology
Long Term Evolution (LTE) is the Long Term Evolution of the 3G communication technology, and for the wireless communication system in future provides higher transmission rate, its code check has at a high speed brought white elephant for the Base-Band Processing at base station and terminal.For the Base-Band Processing in the LTE technology, how to accelerate the data processing speed of bit-level, especially the rate-matched processing speed of transmission channel is one of bottleneck of whole Base-Band Processing.
The transmission channel rate-matched process of existing Turbo coding is shown in accompanying drawing 1.The original sender Turbo coded bit stream obtained through systematic bit stream
first parity bit stream
The second parity bit stream
a total of three-way data.
is identical with the length of
three road bit streams; The length of bit stream equals K+4; K is the data length of encoding block, the 4th, and the tail bit.The tail bit is through the Turbo remaining bit of encoding.
and
three road bit streams are imported sub-block interleaver respectively; It is capable to be that bit stream is sent into a R; In the matrix of 32 row; Write line by line; Displacement between being listed as is again read line by line then and is obtained respectively getting into the bit collection module with
corresponding output bit flow
and
corresponding output bit flow
and
corresponding output bit flow
.In the bit collection module, the mode of collection is that systematic bits flows preceding, and first check bit stream is alternately deposited with second check bit stream, constitutes a complete bit stream w
kAccording to the original position of rate-matched and the length of rate-matched output, cutting perhaps repeats peek again, up to satisfying output length requirement output bit flow e
kTo the terminal.
According to above-mentioned overall flow analysis; Need not wait until that systematic bits stream
first check bit stream
second check bit stream
arrives simultaneously just begins rate adaptation operating, but carries out rate-matched respectively after each bit stream of encoding behind the Turbo encoded.Owing to need read the data in the bit stream in the internal memory repeatedly, therefore the processing speed of above-mentioned rate-matched is lower.
Summary of the invention
The embodiment of the invention proposes the method that rate-matched is mated/separated to Turbo code rate in a kind of LTE system, can accelerate rate-matched/separate rate matching speed.
The method of rate-matched is mated/separated to the Turbo code rate in a kind of LTE system, and this method comprises:
Data length K according to encoding block confirms interlace mode;
Obtain sytem matrix by systematic bits stream; First check bit stream P1 and second check bit stream P2 alternately deposit and obtain check matrix; Classify a sub-systems matrix as from the 1st row beginning per 8 of sytem matrix, classify a sub-check matrix as from the 1st row beginning per 8 of check matrix;
Begin and increase progressively from N=1 by 1; Until N=8; Extract the N row back of each subsystem matrix successively and calculate the sytem matrix address of this columns according to correspondence according to interlace mode; Begin and increase progressively by 1 from N=1,, extract the N row back of each sub-check matrix successively and calculate this columns according to the corresponding check matrix address according to interlace mode until N=8;
In each the extraction; Select the word packing back of 4 systematic bits streams to place said sytem matrix address according to pre-defined rule; The word packing back of the word of 4 P1 of selection and 4 P2 places the address of said check matrix according to pre-defined rule; This selection comprises S circulation, and the line number R that S equals the subsystem matrix subtracts 1 back and rounds downwards divided by 4, and R equals K and adds 4 backs and round up divided by 32;
Press in the row output system matrix address with the check matrix address in data, obtain the bit stream after rate-matched/the separate rate-matched.
Said data length K according to encoding block confirms that interlace mode comprises, K gets remainder to 32, confirms interlace mode by said remainder.
Said N row back of extracting each subsystem matrix successively comprises according to the sytem matrix address of this columns of interlace mode calculating according to correspondence; Confirm interleaving index according to interlace mode; Obtain the middle offset address of these each data of row by squint the successively address of each data in the N row of each subsystem matrix of interleaving index, obtain the sytem matrix address according to interlace mode and the said centre of N overall offset offset address again;
Said N row back of extracting each sub-check matrix is successively calculated this columns according to interlace mode and is comprised according to the corresponding check matrix address; Confirm interleaving index according to interlace mode; Obtain the middle offset address of these each data of row by squint the successively address of each data in the N row of each sub-check matrix of interleaving index, obtain the check matrix address according to interlace mode and the said centre of N overall offset offset address again.
The said skew successively by interleaving index further comprises before the offset address in the middle of the address of each data obtains in the N row of each subsystem matrix, the initial column position of computing system matrix, and the original position of sytem matrix equals k
0,
N
CbBe the soft Buffer size of rate-matched, RV is a redundancy version parameters.
Work as k
0Greater than 32, the initial column position of sytem matrix equals k '
0,
Said according to interlace mode and N overall offset said in the middle of offset address obtain the sytem matrix address and comprise, confirm the overall offset amount according to interlace mode and N, obtain the sytem matrix address according to the said centre of overall offset amount overall offset offset address then;
Said according to interlace mode and N overall offset said in the middle of offset address obtain the check matrix address and comprise, confirm the overall offset amount according to interlace mode and N, obtain the check matrix address according to the said centre of overall offset amount overall offset offset address then.
Saidly confirm that according to interlace mode and N the overall offset amount comprises, confirm filling bit by interlace mode, overall offset amount H equal 32 deduct behind the filling bit with N the data of P1 with.
Saidly confirm that according to interlace mode and N the overall offset amount comprises, confirm unnecessary bit by interlace mode, overall offset amount H equals N data and filling bit poor of P1.
The word packing back of 4 systematic bits streams of said selection places said sytem matrix address to comprise according to pre-defined rule,
Since the 0th system word, whenever take out the word of bit stream at a distance from 8 words, obtain first system word, second system word, tertiary system system word and Quaternary system system word; Get the maximum data of said four systems word respectively and form first system's output word, inferior high data are formed second system's output word, and inferior low data are formed tertiary system system output word, and minimum data is formed Quaternary system system output word;
Said first system's output word is positioned in the address of 4 data of capable the 1st data to the of said sytem matrix S; Said second system's output word is positioned in the address of 12 data of capable the 9th data to the of said sytem matrix S; Said tertiary system system output word is positioned in the address of 8 data of capable the 5th data to the of said sytem matrix S, said Quaternary system system output word is positioned in the address of 16 data of capable the 13rd data to the of said sytem matrix S.
The word of 4 P1 of said selection and the word of 4 P2 packing back place the address of said check matrix to comprise according to pre-defined rule,
Order is taken out the 0th word and the 8th word from P1, is designated as first check word and second check word successively, and order is taken out the 1st word and the 9th word from P2, is designated as the 3rd check word and the 4th check word successively;
Get the maximum data of first check word to the, four check words respectively and form the first verification output word, inferior high data are formed the second verification output word, and inferior low data are formed the 3rd verification output word, and minimum data is formed the 4th verification output word;
The said first verification output word is positioned in the address of 4 data of capable the 1st data to the of said check matrix S; The said second verification output word is positioned in the address of 12 data of capable the 9th data to the of said check matrix S; Said the 3rd verification output word is positioned in the address of 8 data of capable the 5th data to the of said check matrix S, said the 4th verification output word is positioned in the address of 16 data of capable the 13rd data to the of said check matrix S;
Then, order is taken out the 16th word and the 24th word from P1 again, is designated as the 5th check word and the 6th check word successively, and order is taken out the 17th data and the 25th data from P2, is designated as the 7th check word and the 8th check word successively;
Get the maximum data of the 5th check word to the eight check words respectively and form the 5th verification output word, inferior high data are formed the 6th verification output word, and inferior low data are formed the 7th verification output word, and minimum data is formed the 8th verification output word;
Said the 5th verification output word is positioned in the address of 4 data of capable the 1st data to the of said check matrix S+1; Said the 6th verification output word is positioned in the address of 12 data of capable the 9th data to the of said check matrix S+1; Said the 7th verification output word is positioned in the address of 8 data of capable the 5th data to the of said check matrix S+1, said the 8th verification output word is positioned in the address of 16 data of capable the 13rd data to the of said check matrix S+1.
When having remaining data after S the circulation, get a remaining data at every turn and be positioned in the address of said remaining data.
Further comprise when N equals 8,, fill the unnecessary bit of checking data according to interlace mode according to the unnecessary bit of interlace mode fill system data.
From technique scheme, can find out, in embodiments of the present invention, at first confirm interlace mode, then sytem matrix is divided into the subsystem matrix and check matrix is divided into sub-check matrix according to the data length of encoding block; Press column count sytem matrix address and check matrix address according to interlace mode; The systematic bits stream packing of per four words is positioned in the sytem matrix address; The P2 packing of the P1 of per four words and per four words is positioned in the address of check matrix, presses row output system matrix and check matrix.Data after the packing are positioned in the corresponding address, help the water operation of processor, thereby can accelerate rate matching speed.Identical technical scheme also can be applied to separate in the rate-matched, thereby can accelerate to separate rate matching speed.
Description of drawings
Fig. 1 is the rate-matched sketch map of Turbo coding in the prior art;
Fig. 2 is the method flow sketch map of Turbo code rate coupling in the LTE of the present invention system;
Fig. 3 is the sketch map of interlace mode 1 in the embodiment of the invention;
Fig. 4 is the sketch map of interlace mode 2 in the embodiment of the invention;
Fig. 5 is the sketch map of interlace mode 3 in the embodiment of the invention;
Fig. 6 is the sketch map of interlace mode 4 in the embodiment of the invention;
Fig. 7 is embodiment of the invention input storage sketch map;
Fig. 8 is a packing data operation chart in the embodiment of the invention.
Embodiment
For making the object of the invention, technical scheme and advantage express clearlyer, the present invention is remake further detailed explanation below in conjunction with accompanying drawing and specific embodiment.
In embodiments of the present invention; Systematic bits stream, first check bit stream (P1) and second check bit stream (P2) parallel processing simultaneously; And the data read-write operation of continuous 4 words constructs and is fit to the data access structure that the main flow processor is realized the packing data operation, and has reduced the read-write number of times to internal memory.Processing mode is simple, and loop structure is clear, do not exist to judge that redirect etc. interrupts the operation of streamline, and processor calculatings of can fetching data faster, and the data behind the bundle block interleaving map directly on the outgoing position, and then the quickening rate matching speed.
In the present invention, Turbo code rate coupling may further comprise the steps A to E:
Steps A, confirm interlace mode according to the data length K of encoding block.
Step B, obtain sytem matrix by systematic bits stream, P1 and P2 alternately deposit and obtain check matrix, classify a sub-systems matrix as from the 1st row beginning per 8 of sytem matrix, begin per 8 from the 1st row of check matrix and classify a sub-check matrix as.
It is identical that P1 and P2 alternately deposit the implementation that obtains check matrix and prior art, repeats no more at this.Sytem matrix is totally 32 row, is made up of four sub-systems matrixes; Check matrix is totally 32 row, and same is made up of four sub-check matrixes.
The sytem matrix address of this columns according to correspondence calculated according to interlace mode in step C, the N row back of extracting each subsystem matrix successively, extracts the N row back of each sub-check matrix successively and calculates this columns according to the corresponding check matrix address according to interlace mode.
Each N row that extract the subsystem matrix, the N row of sub-check matrix are until accomplishing 8 circulations, with data address in the computing system matrix and the data address in the check matrix.The N+1 that extract each submatrix less than 8 continuation as N are listed as, and the initial value of N is 1.
Step D, the word packing of selecting 4 systematic bits to flow are placed in the said sytem matrix address; Select the word of 4 P1 and the word packing of 4 P2 to be placed in the address of said check matrix; Said selection comprises S circulation; The line number R that S equals submatrix subtracts 1 and rounds downwards divided by 4, and R equals K and adds 4 backs and round up divided by 32.
Packing data processing to systematic bits stream is positioned in the data address of sytem matrix; Packing data processing to P1 and P2 is positioned in the data address of check matrix.Each word comprises 4 data, in technical scheme of the present invention, selects four words promptly to select 16 data.
Step e, press in the row output system matrix address and the data in the check matrix address, obtain the bit stream after the rate-matched.
Referring to accompanying drawing 2 are method flow sketch mapes of Turbo code rate coupling in the LTE system, specifically may further comprise the steps:
Because sub-block interleaving matrix is fixed as 32 row, gets remainder according to the data length K of encoding block to 32, remainder has four kinds of situation promptly 0,8,16 and 24, is directed to different remainders and need fills different bits.Remainder is that 0 this encoding block belongs to interlace mode 1; Remainder is that 8 these encoding blocks belong to interlace mode 2; Remainder is that 16 these encoding blocks belong to interlace mode 3; Remainder is that 24 these encoding blocks belong to interlace mode 4.4 kinds of interlace modes have determined the side-play amount of matrix data address
LTE has stipulated 188 kinds of fixing encoding block length, analyzes in the face of these 188 kinds of encoding block length down:
Step-length is that 8 encoding block length amounts to 60 kinds:
40，48，56，64，72，80，88，96，104，112，120，128，136，144，152，160，168，176，184，192，200，208，216，224，232，240，248，256，264，272，280，288，296，304，312，320，328，336，344，352，360，368，376，384，392，400，408，416，424，432，440，448，456，464，472，480，488，496，504，512。
Step-length is that 16 encoding block length amounts to 32 kinds
528，544，560，576，592，608，624，640，656，672，688，704，720，736，752，768，784，800，816，832，848，864，880，896，912，928，944，960，976，992，1008，1024。
Step-length is that 32 encoding block length amounts to 32 kinds
1056，1088，1120，1152，1184，1216，1248，1280，1312，1344，1376，1408，1440，1472，1504，1536，1568，1600，1632，1664，1696，1728，1760，1792，1824，1856，1888，1920，1952，1984，2016，2048。
Step-length is that 64 encoding block length amounts to 64 kinds
2112，2176，2240，2304，2368，2432，2496，2560，2624，2688，2752，2816，2880，2944，3008，3072，3136，3200，3264，3328，3392，3456，3520，3584，3648，3712，3776，3840，3904，3968，4032，4096，4160，4224，4288，4352，4416，4480，4544，4608，4672，4736，4800，4864，4928，4992，5056，5120，5184，5248，5312，5376，5440，5504，5568，5632，5696，5760，5824，5888，5952，6016，6080，6144。
Wherein, be 32 and 64 encoding block for step-length, it is 0 that K gets remainder to 32, all satisfies the requirement of interlace mode 1; Step-length is 16 encoding block, and 528 satisfy interlace mode 3,544 satisfies interlace mode 1, replaces successively; Step-length is that the existing encoding block that satisfies interlace mode 3 also has the encoding block that satisfies interlace mode 1 in 8 the encoding block.
Above-mentioned encoding block is got the surplus interlace mode under each encoding block that obtains to 32.
Interlace mode 1 corresponding codes block length: amount to 127 kinds
64，96，128，160，192，224，256，288，320，352，384，416，448，480，512，544，576，608，640，672，704，736，768，800，832，864，896，928，960，992，1024，1056，1088，1120，1152，1184，1216，1248，1280，1312，1344，1376，1408，1440，1472，1504，1536，1568，1600，1632，1664，1696，1728，1760，1792，1824，1856，1888，1920，1952，1984，2016，2048，2112，2176，2240，2304，2368，2432，2496，2560，2624，2688，2752，2816，2880，2944，3008，3072，3136，3200，3264，3328，3392，3456，3520，3584，3648，3712，3776，3840，3904，3968，4032，4096，4160，4224，4288，4352，4416，4480，4544，4608，4672，4736，4800，4864，4928，4992，5056，5120，5184，5248，5312，5376，5440，5504，5568，5632，5696，5760，5824，5888，5952，6016，6080，6144。
40，72，104，136，168，200，232，264，296，328，360，392，424，456，488。
48，80，112，144，176，208，240，272，304，336，368，400，432，464，496；
528，560，592，624，656，688，720，752，784，816，848，880，912，944，976，1008。
Interlace mode 4 corresponding codes block lengths: amount to 15 kinds
56，88，120，152，184，216，248，280，312，344，376，408，440，472，504。
Systematic bits stream is formed four sub-systems matrixes successively, and each subsystem matrix is totally 8 row, and preceding 7 row are whenever shown R data, and the 8th shows R-1 data; Check bit stream is formed four sub-check matrixes successively, and each sub-check matrix is totally 8 row, and preceding 7 row are whenever shown the individual data of 2 (R-1), and the 8th shows 2R data.Because check matrix is alternately deposited acquisition by P1 and P2, so the length of every columns certificate is longer than the length of the every columns certificate of sytem matrix in the check matrix.
Under regard to every kind of interlace mode and illustrate:
Interlace mode 1: corresponding filling bit N
D=28, promptly the encoding block length in the length of bit stream can be by 32 situation about dividing exactly.Example K=6144 is referring to accompanying drawing 3.
The corresponding sytem matrix of length that preceding 32 row are short, the corresponding check matrix of length that back 32 row are long.Systematic bits is made up of four sub-systems matrixes successively, and its short-and-medium rectangular strip is the row that do not contain unnecessary bit, and length is R-1, and long rectangular strip is the row that contain unnecessary bit, and length is R.Unnecessary bit is not satisfy the unnecessary bit of row length in the interleaver matrix.Check bit is made up of four sub-check matrixes successively, and its short-and-medium rectangular strip is the row that do not contain unnecessary bit, and length is 2 (R-1), and long rectangular strip is the row that contain unnecessary bit, and length is 2R.
Interlace mode 2: corresponding N
D=20, promptly to get surplus to 32 be 8 situation to the encoding block length in the length of bit stream.Example K=488 is referring to accompanying drawing 4.
Interlace mode 3: corresponding N
D=12, promptly to get surplus to 32 be 16 situation to the encoding block length in the length of bit stream.Example K=496 is referring to accompanying drawing 5.
Interlace mode 4: corresponding N
D=4, promptly to get surplus to 32 be 32 situation to the encoding block length in the length of bit stream.Example K=504 is referring to accompanying drawing 6.
Be similar to interlace mode 1, interlace mode 2,3,4 is the different of K with interlace mode 1 difference, and its sytem matrix is different with the corresponding row length of check matrix.
Extract the N row back of each subsystem matrix successively and calculate the sytem matrix address of this columns, extract the N row back of each sub-check matrix successively and calculate this columns according to the corresponding check matrix address according to interlace mode according to correspondence according to interlace mode.
Each subsystem matrix is totally 8 row, and a column data address of each subsystem matrix of cycle calculations is carried out eight circulations altogether and just can be calculated all sytem matrix addresses; Accordingly, each sub-check matrix also is 8 row, and a column data address of each sub-check matrix of cycle calculations is carried out eight circulations altogether and just can be calculated all check matrix addresses.Therefore the initial value of N is 1, and the maximum of N is 8.
Step 2031, calculating interleaving index.
Interleaving index is the tabulation according to the side-play amount of each data address in the determined matrix of interlace mode.To different interlace modes; Calculate the side-play amount of each data address in every kind of interlace mode; Offset address in the middle of each data address increase corresponding offset obtains in the corresponding sytem matrix, the middle offset address according to interlace mode and each data of N overall offset obtains the sytem matrix address then; Offset address in the middle of each data address increase corresponding offset obtains in the check matrix, the middle offset address according to interlace mode and each data of N overall offset obtains the check matrix address then.
Specify the calculating of interleaving index below:
At first according to redundancy version parameters RV and the soft Buffer N of rate-matched
CbSize, and the formula of LTE protocol description calculates initial row k
0:
In the following formula, R is the line number of subsystem matrix, N
CbBe the soft Buffer size of rate-matched, RV is a redundancy version parameters, scope: 0,1,2,3.Wherein, N
CbBe known parameters, RV is a known parameters.
In addition, because the particularity of arranged form, if k
0Greater than 32, then the initial column position of sytem matrix equals k '
0:
Formula (2) has guaranteed k '
0Span be 2 to 53.Because check matrix is that P1 and P2 combine, if the every columns of check matrix is identical according to the every columns certificate of number and sytem matrix, then check matrix should be 64 row.And for the LTE system, P1 and P2 calculate separately, and then check matrix 96 is listed as totally.If calculate according to former formula (1), then k
0Span be 2 to 74.After formula (2) calculating, be equivalent to be converted to the columns at check matrix place to an original corresponding columns.For example being originally 74 row, is at the 53rd row after calculating through formula (2).
The initial column position of sytem matrix calculates interleaving index respectively according to four kinds of interlace modes after confirming.
Length assignment to each row is the length of each row of initialization, and assignment possibly be R, and R-1 or 2R, 2 (R-1) amount to four kinds maybe.
The output index value of the beginning position of K row is that the output index value of the beginning position of 0, the K+1 row is that K is listed as the length that the output index value that starts the position adds the K row, by that analogy.Special, because the RV parameter, the 0th row can be put into the back all the time, and therefore the output index value of the beginning position of the 0th row is the length that the output index value of the beginning position of the 63rd row adds the 63rd row.
In addition, also need calculate the OPADD index of unnecessary bit, for sytem matrix, because the unnecessary bit of 1 bit is only arranged, the OPADD index that the OPADD of unnecessary bit is equivalent to the next column of these unnecessary bit place row subtracts 1; For check matrix, because the unnecessary bit of 2 bits is arranged, the OPADD index that the OPADD of unnecessary bit is equivalent to the next column of these unnecessary bit place row subtracts 2.
In conjunction with the number of filling bit, can obtain the characteristics of following 4 kinds of interlace modes.
Interlace mode 1, N
D=28, the interlace mode of systematic bits and P1 is following:
<4，20，12，28，8，24，16，0，6，22，14，30，10，26，18，2，5，21，13，29，9，25，17，1，7，23，15，31，11，27，19，3>
When systematic bits stream was got the 31st element with P1, promptly the 59th in Fig. 3 matrix was listed as, and P2 gets the 0th element.The saltus step of having fetched data this time; Therefore; In order to construct particular structural, need be the initial address of the output row of 59 to 64 row in the matrix of our definition 1 unit that squint backward successively, simultaneously the unnecessary bit initial address of respective column 1 unit that squints backward.
<12，28，20，4，16，0，24，8，14，30，22，6，18，2，26，10，13，29，21，5，17，1，25，9，15，31，23，7，19，3，27，11>
When systematic bits stream was got the 31st element with P1, promptly the 57th in Fig. 4 matrix was listed as, and P2 gets the 0th element.The saltus step of having fetched data this time; Therefore; In order to construct particular structural, need be the initial address of the output row of 57 to 64 row in the matrix of our definition 1 unit that squint backward successively, simultaneously the unnecessary bit initial address of respective column 1 unit that squints backward.
<20，4，28，12，24，8，0，16，22，6，30，14，26，10，2，18，21，5，29，13，25，9，1，17，23，7，31，15，27，11，3，19>
When systematic bits stream was got the 31st element with P1, promptly the 58th in Fig. 5 matrix was listed as, and P2 gets the 0th element.The saltus step of having fetched data this time; Therefore; In order to construct particular structural, need be the initial address of the output row of 58 to 64 row in the matrix of our definition 1 unit that squint backward successively, simultaneously the unnecessary bit initial address of respective column 1 unit that squints backward.
Interlace mode 4, N
D=4, the interlace mode of systematic bits and P 1 is following:
<28，12，4，20，0，16，8，24，30，14，6，22，2，18，10，26，29，13，5，21，1，17，9，25，31，15，7，23，3，19，11，27>
When systematic bits stream was got the 31st element with P1, promptly the 56th in the matrix was listed as, and P2 gets the 0th element.The saltus step of having fetched data this moment, therefore, in order to construct particular structural, need be with 56 in the matrix to the initial address of 64 row output row 1 unit that squint backward successively, simultaneously the unnecessary bit initial address of respective column 1 unit that squints backward.
The size of interleaving index is a 64+56=120 length.Preceding 64 index storage system matrixes, 32 row, check matrix 32 row amount to the initial address index of 64 row, the i.e. position of bit in output buffers of beginning; 56 index in back are unnecessary bit positions in output buffers of each special length row.Because two unnecessary bits are close-connected in the long line that contains unnecessary bit of check matrix, therefore only need to calculate an allocation index and get final product, the address of the unnecessary bit of another one can add according to this allocation index
The sytem matrix of interlace mode 1 and check matrix have 4 unnecessary bits delegation in the end respectively, why are that last column is to be put into last column to filling bit NULL here, therefore are called unnecessary bit, only need the index of 8 unnecessary bits.Likewise, interlace mode 2 needs the index of 24 remaining bits.Interlace mode 3 needs the index of 40 remaining bits, and interlace mode 4 needs the index of 56 remaining bits.Getting maximum length according to interlace mode 4 is 56, above-mentioned 120 index altogether.These 120 allocation indexs have determined the side-play amount that dateout is stored.
Before rate-matched, calculate good above-mentioned indexing parameter in advance.Because there is the identical situation of length of a plurality of encoding blocks in the LTE system, therefore only need calculates an interleaving index and get final product for identical encoding block.
Step 2032, obtain sytem matrix address and check matrix address respectively according to offset address in the middle of interlace mode and the N overall offset.
Because the block interleaver matrix in the sub-block interleaver has 32 row, then the filling bit of encoding block equals 32 and deducts K+4 and get surplus to 32.The length of systematic bits stream, P1 and P2 is equal to K+4.That is: the corresponding filling bit N of interlace mode 1
DEqual 28; The N of interlace mode 2 correspondences
DEqual 20; The N of interlace mode 3 correspondences
DEqual 12; The N of interlace mode 4 correspondences
DEqual 4.
According to N
DThe first eight data of the interlace mode of P 1 in the associative list one can obtain the overall offset amount of four kinds of each columns certificates of interlace mode.Deduct N when 32
DAfter, with N data of P1 and smaller or equal to 32, overall offset amount H equals 32 and deducts N
DThe back with N data of P1 and; Deduct N when 32
DAfter, with N the data of P1 and greater than 32, N the data that overall offset amount H equals P1 deduct N
D
Table 1 P1 check matrix interlace mode
<0，16，8，24，4，20，12，28，2，18，10，26，6，22，14，30，1，17，9，25，5，21，13，29，3，19，11，27，7，23，15，31>
Interlace mode 1:N
DThe H of=28 corresponding each row is respectively: 4,20,12,28,8,24,16,0;
Interlace mode 2:N
DThe H of=20 corresponding each row is respectively: 12,28,20,4,16,0,24,8;
Interlace mode 3:N
DThe H of=12 corresponding each row is respectively: 20,4,28,12,24,8,0,16;
Interlace mode 4:N
DThe H of=4 corresponding each row is respectively: 28,12,4,20,0,16,8,24.
Promptly for the encoding block of interlace mode 1, the overall offset amount of first row of its subsystem matrix and sub-check matrix is 4, and the overall offset amount of secondary series is 20, can obtain the overall offset amount of the 3rd row to the 8th row by that analogy.Overall offset amount among this paper is meant the side-play amount of the address of this columns certificate.
The data of step 204, S packaging system bit stream of circulation, the data of packing P1 and P2.
In step 203, calculated data corresponding address in sytem matrix and the check matrix.Packing data with systematic bits stream in the step 204 is positioned over the address in the sytem matrix; The packing data of P1 and P2 is positioned over the address in the check matrix.The line number R that cycle-index S equals the subsystem matrix subtracts 1 and rounds downwards divided by 4, and R equals K and adds 4 backs and round up divided by 32.
After S circulation,, then get a remaining data at every turn and be positioned in the address of remaining data if there is remaining data.
For the input data of systematic bits stream, P1 and P2 depositing shown in accompanying drawing 7 of totally three code streams.First word in systematic bits stream is by data S
0, data S
1, data S
2With data S
3Constitute, first word of P1 is by data P
0, data P
1, data P
2With data P
3Constitute, and first word of P2 is only by the data B in the 4th position
0Constitute.If the input data of systematic bits stream, P1 and P2 do not satisfy above-mentioned condition, the bit stream that then needs not satisfy condition is adjusted to above-mentioned condition.The adjustment mode is a prior art, just repeats no more at this.
Below the word packing introduced in detail systematic bits stream be positioned over the address in the sytem matrix.
Since the 0th word,, obtain the first system word A0, the second system word A8, tertiary system system word A16 and Quaternary system system word A24 whenever at a distance from the word of 8 word extraction system bit streams.Referring to accompanying drawing 8, to get the maximum data of four systems word respectively and form the first output word B0 of system, inferior high data are formed the second output word B8 of system, and inferior low data are formed tertiary system system output word B16, and minimum data is formed Quaternary system system output word B16.Said process is the packing data process.Wherein, a word is to be made up of four data.
B0 is positioned in the address of 4 data of capable the 1st data to the of sytem matrix S; B8 is positioned in the address of 12 data of capable the 9th data to the of sytem matrix S; B16 is positioned in the address of 8 data of capable the 5th data to the of sytem matrix S, B24 is positioned in 16 data of the 13rd data to the of capable the 4th row of sytem matrix S.
After carrying out S circulation, the word in the systematic bits stream is positioned over respectively in the address in the sytem matrix.
The packing data of P1 and P2 is positioned over the address in the check matrix; Be with packing data difference sytem matrix; Because the data number in the check matrix is the twice of data number in the sytem matrix; Therefore sytem matrix carries out packing data one time, and corresponding check matrix carries out the secondary data packing.
Order is taken out the 0th word and the 8th word from P1, is designated as first check word and second check word successively, and order is taken out the 1st word and the 9th word from P2, is designated as the 3rd check word and the 4th check word successively.
Get the maximum data of first check word to the, four check words respectively and form the first verification output word, inferior high data are formed the second verification output word, and inferior low data are formed the 3rd verification output word, and minimum data is formed the 4th verification output word.
The first verification output word is positioned in the address of 4 data of capable the 1st data to the of check matrix S; The second verification output word is positioned in the address of 12 data of capable the 9th data to the of check matrix S; The 3rd verification output word is positioned in the address of 8 data of capable the 5th data to the of check matrix S, the 4th verification output word is positioned in the address of 16 data of capable the 13rd data to the of said check matrix S.
Then, order is taken out the 16th word and the 24th word from P1 again, is designated as the 5th check word and the 6th check word successively, and order is taken out the 17th word and the 25th word from P2, is designated as the 7th check word and the 8th check word successively.
Get the maximum data of the 5th check word to the eight check words respectively and form the 5th verification output word, inferior high data are formed the 6th verification output word, and inferior low data are formed the 7th verification output word, and minimum data is formed the 8th verification output word.
The 5th verification output word is positioned in the address of 4 data of capable the 1st data to the of check matrix S+1; The 6th verification output word is positioned in the address of 12 data of capable the 9th data to the of check matrix S+1; The 7th verification output word is positioned in the address of 8 data of capable the 5th data to the of check matrix S+1, the 8th verification output word is positioned in the address of 16 data of capable the 13rd data to the of check matrix S+1.
Whether judge N smaller or equal to 8, if return step 103 after N less than 8, then makes N+1; Otherwise, execution in step 106.
Because sytem matrix is made up of four sub-systems matrixes, check matrix is made up of four sub-check matrixes.Subsystem matrix and sub-check matrix all have 8 columns certificates, when N=8 be in the subsystem matrix every columns according to all being positioned in the address of sytem matrix, and in the sub-check matrix every columns according to all being positioned in the address of check matrix.
So far, data in the sytem matrix address and the data in the check matrix address are the data after the rate-matched.
Be listed as to the 32nd row, the data in the output system matrix address successively from the 1st by row; Then, by row from the 33rd row to the 64th row, data in the output verification matrix address successively obtain the data after the rate-matched.
In addition, the technical scheme of step 201 to step 206 also is adapted in the LTE system Turbo coding and separates rate-matched.The implementation procedure of its technical scheme is identical with Turbo code rate coupling, and difference is in the step 2031 that the position of initial row equals 0.
The above is merely preferred embodiment of the present invention, is not to be used to limit protection scope of the present invention.All within spirit of the present invention and principle, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (12)
1. the method for rate-matched is mated/separated to the Turbo code rate in the LTE system, it is characterized in that this method comprises:
Data length K according to encoding block confirms interlace mode;
Obtain sytem matrix by systematic bits stream; First check bit stream P1 and second check bit stream P2 alternately deposit and obtain check matrix; Classify a sub-systems matrix as from the 1st row beginning per 8 of sytem matrix, classify a sub-check matrix as from the 1st row beginning per 8 of check matrix;
Begin and increase progressively from N=1 by 1; Until N=8; Extract the N row back of each subsystem matrix successively and calculate the sytem matrix address of this columns according to correspondence according to interlace mode; Begin and increase progressively by 1 from N=1,, extract the N row back of each sub-check matrix successively and calculate this columns according to the corresponding check matrix address according to interlace mode until N=8;
In each the extraction; Select the word packing back of 4 systematic bits streams to place said sytem matrix address according to pre-defined rule; The word packing back of the word of 4 P1 of selection and 4 P2 places the address of said check matrix according to pre-defined rule; This selection comprises S circulation, and the line number R that S equals the subsystem matrix subtracts 1 back and rounds downwards divided by 4, and R equals K and adds 4 backs and round up divided by 32;
Press in the row output system matrix address with the check matrix address in data, obtain the bit stream after rate-matched/the separate rate-matched.
2. mate/separate the method for rate-matched according to Turbo code rate in the said LTE of claim 1 system, it is characterized in that said data length K according to encoding block confirms that interlace mode comprises, K gets remainder to 32, confirms interlace mode by said remainder.
3. mate/separate the method for rate-matched according to Turbo code rate in the said LTE of claim 1 system; It is characterized in that; Said N row back of extracting each subsystem matrix successively comprises according to the sytem matrix address of this columns of interlace mode calculating according to correspondence; Confirm interleaving index according to interlace mode; Obtain the middle offset address of these each data of row by squint the successively address of each data in the N row of each subsystem matrix of interleaving index, obtain the sytem matrix address according to interlace mode and the said centre of N overall offset offset address again;
Said N row back of extracting each sub-check matrix is successively calculated this columns according to interlace mode and is comprised according to the corresponding check matrix address; Confirm interleaving index according to interlace mode; Obtain the middle offset address of these each data of row by squint the successively address of each data in the N row of each sub-check matrix of interleaving index, obtain the check matrix address according to interlace mode and the said centre of N overall offset offset address again.
4. mate/separate the method for rate-matched according to Turbo code rate in the said LTE of claim 3 system; It is characterized in that; The said skew successively by interleaving index further comprises before the offset address in the middle of the address of each data obtains in the N row of each subsystem matrix; The initial column position of computing system matrix, the original position of sytem matrix equals k
0,
N
CbBe the soft Buffer size of rate-matched, RV is a redundancy version parameters.
5. mate/separate the method for rate-matched according to Turbo code rate in the said LTE of claim 4 system, it is characterized in that, work as k
0Greater than 32, the initial column position of sytem matrix equals<,
6. mate/separate the method for rate-matched according to Turbo code rate in the said LTE of claim 3 system; It is characterized in that; Said according to interlace mode and N overall offset said in the middle of offset address obtain the sytem matrix address and comprise; Confirm the overall offset amount according to interlace mode and N, obtain the sytem matrix address according to the said middle offset address of overall offset amount overall offset then;
Said according to interlace mode and N overall offset said in the middle of offset address obtain the check matrix address and comprise, confirm the overall offset amount according to interlace mode and N, obtain the check matrix address according to the said centre of overall offset amount overall offset offset address then.
7. mate/separate the method for rate-matched according to Turbo code rate in the said LTE of claim 6 system; It is characterized in that; Saidly confirm that according to interlace mode and N the overall offset amount comprises; Confirm filling bit by interlace mode, overall offset amount H equal 32 deduct behind the filling bit with N the data of P1 with.
8. mate/separate the method for rate-matched according to Turbo code rate in the said LTE of claim 6 system; It is characterized in that; Saidly confirm that according to interlace mode and N the overall offset amount comprises, confirm unnecessary bit by interlace mode, overall offset amount H equals N data and filling bit poor of P1.
9. mate/separate the method for rate-matched according to Turbo code rate in the said LTE of claim 1 system, it is characterized in that, the word packing back of 4 systematic bits streams of said selection places said sytem matrix address to comprise according to pre-defined rule,
Since the 0th system word, whenever take out the word of bit stream at a distance from 8 words, obtain first system word, second system word, tertiary system system word and Quaternary system system word; Get the maximum data of said four systems word respectively and form first system's output word, inferior high data are formed second system's output word, and inferior low data are formed tertiary system system output word, and minimum data is formed Quaternary system system output word;
Said first system's output word is positioned in the address of 4 data of capable the 1st data to the of said sytem matrix S; Said second system's output word is positioned in the address of 12 data of capable the 9th data to the of said sytem matrix S; Said tertiary system system output word is positioned in the address of 8 data of capable the 5th data to the of said sytem matrix S, said Quaternary system system output word is positioned in the address of 16 data of capable the 13rd data to the of said sytem matrix S.
10. mate/separate the method for rate-matched according to Turbo code rate in the said LTE of claim 1 system, it is characterized in that, the word of 4 P1 of said selection and the word of 4 P2 packing back place the address of said check matrix to comprise according to pre-defined rule,
Order is taken out the 0th word and the 8th word from P1, is designated as first check word and second check word successively, and order is taken out the 1st word and the 9th word from P2, is designated as the 3rd check word and the 4th check word successively;
Get the maximum data of first check word to the, four check words respectively and form the first verification output word, inferior high data are formed the second verification output word, and inferior low data are formed the 3rd verification output word, and minimum data is formed the 4th verification output word;
The said first verification output word is positioned in the address of 4 data of capable the 1st data to the of said check matrix S; The said second verification output word is positioned in the address of 12 data of capable the 9th data to the of said check matrix S; Said the 3rd verification output word is positioned in the address of 8 data of capable the 5th data to the of said check matrix S, said the 4th verification output word is positioned in the address of 16 data of capable the 13rd data to the of said check matrix S;
Then, order is taken out the 16th word and the 24th word from P1 again, is designated as the 5th check word and the 6th check word successively, and order is taken out the 17th data and the 25th data from P2, is designated as the 7th check word and the 8th check word successively;
Get the maximum data of the 5th check word to the eight check words respectively and form the 5th verification output word, inferior high data are formed the 6th verification output word, and inferior low data are formed the 7th verification output word, and minimum data is formed the 8th verification output word;
Said the 5th verification output word is positioned in the address of 4 data of capable the 1st data to the of said check matrix S+1; Said the 6th verification output word is positioned in the address of 12 data of capable the 9th data to the of said check matrix S+1; Said the 7th verification output word is positioned in the address of 8 data of capable the 5th data to the of said check matrix S+1, said the 8th verification output word is positioned in the address of 16 data of capable the 13rd data to the of said check matrix S+1.
11. mate/separate the method for rate-matched according to Turbo code rate in the said LTE of claim 1 system, it is characterized in that, when having remaining data after S the circulation, get a remaining data at every turn and be positioned in the address of said remaining data.
12. mate/separate the method for rate-matched according to Turbo code rate in the said LTE of claim 1 system; It is characterized in that; Further comprise when N equals 8,, fill the unnecessary bit of checking data according to interlace mode according to the unnecessary bit of interlace mode fill system data.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010532617.XA CN102468902B (en) | 2010-11-01 | 2010-11-01 | Method for Turbo coding of rate match/de-rate match in LTE (long term evolution) system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010532617.XA CN102468902B (en) | 2010-11-01 | 2010-11-01 | Method for Turbo coding of rate match/de-rate match in LTE (long term evolution) system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102468902A true CN102468902A (en) | 2012-05-23 |
| CN102468902B CN102468902B (en) | 2014-04-16 |
Family
ID=46072131
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201010532617.XA Expired - Fee Related CN102468902B (en) | 2010-11-01 | 2010-11-01 | Method for Turbo coding of rate match/de-rate match in LTE (long term evolution) system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102468902B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109257146A (en) * | 2018-11-16 | 2019-01-22 | 武汉虹旭信息技术有限责任公司 | A kind of LTE based on DSP quickly decodes system and method |
| CN111630781A (en) * | 2017-12-08 | 2020-09-04 | 高通股份有限公司 | On-the-fly interleaving/rate matching and deinterleaving/de-rate matching for 5G NR |
| CN116015546A (en) * | 2022-12-13 | 2023-04-25 | 湖北公众信息产业有限责任公司 | Random length turbo code rate matching method based on FPGA |
| CN116388926A (en) * | 2023-03-15 | 2023-07-04 | 归芯科技(深圳)有限公司 | Rate matching method, device and chip |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101510819A (en) * | 2009-04-08 | 2009-08-19 | 华为技术有限公司 | Method and apparatus for matching velocity |
| CN101540654A (en) * | 2009-05-04 | 2009-09-23 | 普天信息技术研究院有限公司 | Method for interlacing rate matching and de-interlacing off-rate matching |
| CN101783719A (en) * | 2010-03-18 | 2010-07-21 | 华为技术有限公司 | Rate matching and rate de-matching method, device and communication system |
-
2010
- 2010-11-01 CN CN201010532617.XA patent/CN102468902B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101510819A (en) * | 2009-04-08 | 2009-08-19 | 华为技术有限公司 | Method and apparatus for matching velocity |
| CN101540654A (en) * | 2009-05-04 | 2009-09-23 | 普天信息技术研究院有限公司 | Method for interlacing rate matching and de-interlacing off-rate matching |
| CN101783719A (en) * | 2010-03-18 | 2010-07-21 | 华为技术有限公司 | Rate matching and rate de-matching method, device and communication system |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111630781A (en) * | 2017-12-08 | 2020-09-04 | 高通股份有限公司 | On-the-fly interleaving/rate matching and deinterleaving/de-rate matching for 5G NR |
| CN111630781B (en) * | 2017-12-08 | 2023-09-15 | 高通股份有限公司 | On-the-fly interleaving/rate matching and de-interleaving/de-rate matching for 5G NR |
| CN109257146A (en) * | 2018-11-16 | 2019-01-22 | 武汉虹旭信息技术有限责任公司 | A kind of LTE based on DSP quickly decodes system and method |
| CN109257146B (en) * | 2018-11-16 | 2020-11-24 | 武汉虹旭信息技术有限责任公司 | LTE (Long term evolution) rapid decoding system and method based on DSP (digital Signal processor) |
| CN116015546A (en) * | 2022-12-13 | 2023-04-25 | 湖北公众信息产业有限责任公司 | Random length turbo code rate matching method based on FPGA |
| CN116015546B (en) * | 2022-12-13 | 2023-10-20 | 湖北公众信息产业有限责任公司 | Random length turbo code rate matching method based on FPGA |
| CN116388926A (en) * | 2023-03-15 | 2023-07-04 | 归芯科技(深圳)有限公司 | Rate matching method, device and chip |
| CN116388926B (en) * | 2023-03-15 | 2023-09-22 | 归芯科技(深圳)有限公司 | Rate matching method, device and chip |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102468902B (en) | 2014-04-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101540654B (en) | Method for interlacing rate matching and de-interlacing off-rate matching | |
| CN101547064B (en) | Interleaving and rate matching and de-interleaving and rate de-matching methods | |
| CN109120276B (en) | The method of information processing, communication device | |
| CN101510819B (en) | Method and apparatus for matching velocity | |
| CN101986584A (en) | Rate de-matching device and method in 3GPP LTE | |
| CN102447521B (en) | A kind of dissociation rate matching method and device | |
| CN102468902A (en) | Method for Turbo coding of rate match/de-rate match in LTE (long term evolution) system | |
| CN112039535B (en) | Code rate compatible LDPC encoder based on quasi-cyclic generation matrix | |
| CN101800619A (en) | Interleaver or deinterleaver method and device thereof based on block interleaver | |
| CN101610089A (en) | Interweave a kind of second time and the method and apparatus of deinterleaving | |
| CN101944972B (en) | Coding and decoding method, device and communication system | |
| CN101764621A (en) | Method for realizing compatibility of short code and subcode in satellite-based (8176, 7156) LDPC coder | |
| CN103873188B (en) | A kind of parallel dissociation rate matching method and device | |
| CN102118219B (en) | Serial processing method and serial processing device for rate matching | |
| CN102594371B (en) | The method of a kind of Turbo code interleaving process and device | |
| CN102769506A (en) | De-interleaving method and device for rate de-matching | |
| CN102136888B (en) | Sub-block de-interleaving input data processing method and device | |
| CN104143992A (en) | LDPC encoding method based on bit stuffing | |
| CN102136878B (en) | Rate matching realization method and system | |
| CN103560797A (en) | Method and device for five times of iterative decoding of superstrong forward error correction | |
| CN102118217A (en) | Rate matching parallel processing method and device | |
| CN103929271A (en) | Parallel achieving method and device for LTE system rate matching | |
| CN101027860A (en) | An uplink coding and multiplexing implementation | |
| CN101534172B (en) | A realizing device and method of bit interleaving in china mobile multimedia broadcasting | |
| CN102340319A (en) | Turbo code rate matching method and device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| ASS | Succession or assignment of patent right |
Owner name: CHINA POTEVIO CO., LTD. Free format text: FORMER OWNER: PUTIAN IT TECH INST CO., LTD. Effective date: 20130916 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20130916 Address after: 100080, No. two, 2 street, Zhongguancun science and Technology Park, Beijing, Haidian District Applicant after: CHINA POTEVIO CO.,LTD. Address before: 100080 Beijing, Haidian, North Street, No. two, No. 6, No. Applicant before: PETEVIO INSTITUTE OF TECHNOLOGY Co.,Ltd. |
|
| ASS | Succession or assignment of patent right |
Owner name: PUTIAN IT TECH INST CO., LTD. Free format text: FORMER OWNER: CHINA POTEVIO CO., LTD. Effective date: 20131204 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20131204 Address after: 100080 Beijing, Haidian, North Street, No. two, No. 6, No. Applicant after: PETEVIO INSTITUTE OF TECHNOLOGY Co.,Ltd. Address before: 100080, No. two, 2 street, Zhongguancun science and Technology Park, Beijing, Haidian District Applicant before: CHINA POTEVIO CO.,LTD. |
|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20140416 Termination date: 20211101 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |