CN100530642C - Integrated circuit device and electronic instrument - Google Patents

Abstract

The invention provides a slim, thin and long integrated circuit device, and electronic equipment incorporating the same. The integrated circuit device includes a pad PDx and an electrostatic discharge protection element ESDx formed in a rectangular region and electrically connected with the pad PDx. The pad PDx is disposed in an upper layer of the electrostatic discharge protection element ESDx so that an arrangement direction of the pads is parallel to a long side direction of the region in which the electrostatic discharge protection element ESDx is formed, and the pad PDx overlaps part or the entirety of the electrostatic discharge protection element ESDx.

Description

Integrated circuit (IC) apparatus and electronic equipment

Technical field

The present invention relates to a kind of integrated circuit (IC) apparatus and electronic equipment.

Background technology

As the integrated circuit (IC) apparatus that drives display floaters such as liquid crystal panel display driver (lcd driver) is arranged.In this display driver, need dwindle the integrated circuit substrate size for cost degradation.

But the size of the display floater in the mobile phone of packing into etc. is almost fixing.Therefore,, shorten the integrated circuit (IC) apparatus of display driver simply and dwindle the integrated circuit substrate size, will cause being difficult to problems such as installation if adopt hand work.

Patent documentation 1: the spy opens the 2001-222249 communique

Summary of the invention

The present invention is the invention of carrying out in view of above-mentioned technical problem, and its purpose is, a kind of very thin elongated integrated circuit (IC) apparatus and the electronic equipment that comprises it are provided.

The present invention includes pad and form rectangular zone; the electrostatic protection element that is electrically connected with above-mentioned pad; with the orientation of above-mentioned pad and above-mentioned electrostatic protection element constituted the long side direction in zone parallel and with part or all overlapping mode of above-mentioned electrostatic protection element, at the above-mentioned pad of the upper-layer configured of above-mentioned electrostatic protection element.

And in the integrated circuit (IC) apparatus relevant with the present invention, above-mentioned pad has rectangular shape, and above-mentioned orientation also can be the short side direction of above-mentioned pad.

And, in the integrated circuit (IC) apparatus that the present invention is correlated with, also configurable above-mentioned second short brink in mutual opposed first and second minor face of above-mentioned electrostatic protection element at above-mentioned pad.

According to above-mentioned any one invention, not only can effectively utilize the zone between pad, and expand the zone that pad can dispose other elements down.Thus, dwindled the layout area of integrated circuit (IC) apparatus.And on the short side direction of the orientation of pad and pad, can change the zone of electrostatic protection element, such as carrying out inching with the current driving ability of the electrostatic protection element of transistor and usefulness, do not need to increase without rhyme or reason layout area with output.

In integrated circuit (IC) apparatus related to the present invention; comprise the transistor that is electrically connected with above-mentioned pad; to extend the mode of channel width at the short side direction of described pad; form and constitute above-mentioned transistor and the plurality of source regions of above-mentioned electrostatic protection element, a plurality of gate electrode and drain electrode; above-mentioned transistor is made of one or more source area, gate electrode and the drain electrode of above-mentioned first short brink, and above-mentioned electrostatic protection element also can be the grid controlled transistor that one or more source area, gate electrode and the drain electrode by above-mentioned transistor second short brink constitutes.

According to the present invention, not only electrostatic protection element can be configured in the lower floor of pad, and according to transistorized current driving ability, can easily adjust the size of transistor and grid controlled transistor, and helps to dwindle layout area.

In integrated circuit (IC) apparatus related to the present invention, if setting is a first direction from the direction of first limit towards opposed the 3rd limit of the minor face of said integrated circuit device, from the direction of second limit towards opposed the 4th limit on the long limit of integrated circuit (IC) apparatus is the words of second direction, then integrated circuit (IC) apparatus comprises: the first～the N circuit block (N is the integer more than or equal to 2), along above-mentioned first direction configuration; First interface area, the above-mentioned second direction side at above-mentioned the first～the N circuit block is provided with along the 4th limit; And second interface area, in the four directions opposite with the above-mentioned second direction of above-mentioned the first～the N circuit block to side, be provided with along above-mentioned second limit, above-mentioned the first～the N circuit block comprises at least one data driving block and the above-mentioned data driving block circuit block in addition that is used for driving data lines, be respectively W1 if be set in the width of the above-mentioned second direction of above-mentioned first interface area, above-mentioned the first～the N circuit block, above-mentioned second interface area, WB, the words of W2, integrated circuit (IC) apparatus in the width W of above-mentioned second direction is W1+WB+W2≤W＜W1+2 * WB+W2.

In the present invention, the first～the N circuit block comprises the circuit block outside data driving block and the data driving block.And for above-mentioned first interface area, above-mentioned the first～the N circuit block, each width W 1 of above-mentioned second interface area, WB, W2, W1+WB+W2≤W＜W1+2 * WB+W2 sets up.According to the integrated circuit (IC) apparatus that satisfies such relational expression, the width (making it can not form excessively flat layout) of circuit block in the second direction can not only be guaranteed, and the width on the second direction can be reduced, elongated integrated circuit (IC) apparatus is provided.Thus, the simplification that has promptly realized actual installation has realized the cost degradation that installs again.In addition, because circuit block is not excessively flat, layout designs is become easily, and can shorten the development time of device.

In integrated circuit (IC) apparatus related to the present invention, the width W on the above-mentioned second direction of integrated circuit (IC) apparatus also can be W＜2 * WB.

Like this, in the width on the second direction that can guarantee the first～the N circuit block significantly, make the width on the second direction of integrated circuit (IC) apparatus obtain reducing.And as the present invention, the lower floor's configuration electrostatic protection element by at pad makes the width of the second direction of integrated circuit (IC) apparatus obtain dwindling significantly.Therefore, make it possible to easily satisfy W＜2 * WB, and more elongated integrated circuit (IC) apparatus can be provided.

In integrated circuit (IC) apparatus related to the present invention, above-mentioned first interface area is in the above-mentioned second direction side of above-mentioned data driving block, can dispose without other circuit blocks, above-mentioned second interface area, can dispose without other circuit blocks to side in the above-mentioned four directions of above-mentioned data driving block.

Like this, be benchmark with the width on the second direction of data driving block, can set the width of the first～the N circuit block on second direction.And, there is the part of data driving block at least, in order in second direction, only there to be a circuit block (data driving block), and, realized elongated integrated circuit (IC) apparatus not with the excessive flattening of the layout of data driving block.

In integrated circuit (IC) apparatus related to the present invention, the data driver that above-mentioned data driving block comprises comprises Q the driver element of arranging along second direction, an above-mentioned Q driver element is exported respectively and the corresponding data-signal of the view data of 1 amount of pixels, if setting above-mentioned driver element is WD at the width of above-mentioned second direction, then above-mentioned the first～the N circuit block is WB at the width of above-mentioned second direction, also can be Q * WD≤WB＜(Q+1) * WD.

As mentioned above, if dispose a plurality of driver elements along second direction, then the signal of the view data that obtains from other the circuit block along first direction configuration can input to these driver elements effectively.And, can guarantee that the width of data driving block on second direction controls to minimum value, and can dwindle the width of integrated circuit (IC) apparatus on second direction.

In integrated circuit (IC) apparatus related to the present invention, when the pixel count of the horizontal scan direction of setting display floater is HPN, the piece number of setting data drive block is DBN, setting is IN to the input number of times of the view data imported in each horizontal scan period of above-mentioned driver element, then the number Q of the above-mentioned driver element of arranging along above-mentioned second direction also can be, and Q=HPN/ (DBN * IN).

So, can be with the width setup of the first～the N circuit block on second direction and the piece number of data driving block and the corresponding optimal width of input number of times of view data.

In integrated circuit (IC) apparatus related to the present invention, above-mentioned the first～the N circuit block comprises at least one memory block of storing image data, the data driver that above-mentioned data driving block comprises comprises Q the driver element of arranging along second direction, a described Q driver element is exported respectively and the corresponding data-signal of the view data of 1 amount of pixels, if setting the width of the above-mentioned second direction of above-mentioned driver element is WD, the included peripheral circuit of above-mentioned memory block part is WPC at the width of above-mentioned second direction, then also can be Q * WD≤WB＜(Q+1) * WD+WPC.

Like this, can be the width that benchmark is set the first～the N circuit block with the width of memory block.And, there is the part of memory block at least, because in second direction, only there is a circuit block (memory block), can realize elongated integrated circuit (IC) apparatus.Therefore, make the width of data driving block on second direction control to minimum value, and can dwindle the width of integrated circuit (IC) apparatus on second direction.

In integrated circuit (IC) apparatus related to the present invention, if setting the pixel count of the horizontal scan direction of display floater is HPN, the piece number of data driving block is DBN, the input number of times of the view data of in each horizontal scan period above-mentioned driver element being imported is IN, then the number Q of the above-mentioned driver element of arranging along above-mentioned second direction also can be, and Q=HPN/ (DBN * IN).

Like this, make the width of memory block on second direction control to minimum value, and can dwindle the width of integrated circuit (IC) apparatus on second direction.

In integrated circuit (IC) apparatus related to the present invention, along above-mentioned first direction, above-mentioned memory block and above-mentioned data driving block also can disposed adjacent.

Like this, and compare, dwindled the width of integrated circuit (IC) apparatus on second direction along the method for second direction configuration store piece and data driving block.And, if when the formation of memory block and data driving block etc. change, the influence that other circuit blocks are produced can be controlled to minimum value, realized the efficient activity of design.

In integrated circuit (IC) apparatus related to the present invention, in a horizontal scan period, repeatedly read the view data of storing the above-mentioned memory block to the above-mentioned data driving block of adjacency from above-mentioned memory block.

Like this, because the number of memory cells of memory block on second direction reduces, so the width of memory block on second direction can dwindle, the width of integrated circuit (IC) apparatus on second direction also can reduce.

And the invention still further relates to a kind of electronic equipment, this electronic equipment comprises the integrated circuit (IC) apparatus of the invention described above either side record and the display floater that is driven by the said integrated circuit device.

Description of drawings

Fig. 1 (A), (B), (C) are the key diagrams of the comparative example of present embodiment.

Fig. 2 (A), (B) are the key diagrams about the installation of integrated circuit (IC) apparatus.

Fig. 3 is the configuration example of the integrated circuit (IC) apparatus of present embodiment.

Fig. 4 is the example of polytype display driver and their built-in circuit blocks.

Fig. 5 (A), (B) are the plane figure examples of the integrated circuit (IC) apparatus of this form of implementation.

Fig. 6 (A), (B) are the examples of the profile of integrated circuit (IC) apparatus.

Fig. 7 is the circuit configuration example of integrated circuit (IC) apparatus.

Fig. 8 (A), (B), (C) are the configuration examples of data driver, scanner driver.

Fig. 9 (A), (B) are the configuration examples of power circuit, gray scale voltage generative circuit.

Figure 10 (A), (B), (C) are the configuration examples of D/A change-over circuit, output circuit.

Figure 11 (A), (B) are the key diagrams of the configuration of pad and electrostatic protection element.

Figure 12 (A), (B), (C) are the key diagrams that electrostatic protection is adjusted.

Figure 13 is electrostatic protection element and the transistorized configuration example under the pad.

Figure 14 (A), (B) are the transistorized structure example of output that is formed under the o pads.

Figure 15 is an example of the layout plane graph of electrostatic protection element.

Figure 16 is an example of the cross section structure of Figure 15.

Figure 17 is an example of transistorized cross-section structure that is formed at the lower floor of pad

Figure 18 (A), (B) are the key diagrams about the integrated circuit (IC) apparatus width.

Figure 19 (A)～(E) is the key diagram about the data driving block width.

Figure 20 (A), (B) are the key diagrams about the memory block width.

Figure 21 (A), (B) are the key diagrams of comparative example.

Figure 22 (A), (B) are the configuration examples of memory block.

Figure 23 is about W1, W2, the key diagram of the relation of WB.

Figure 24 (A), (B) are the configuration instruction figure of memory block, data driving block

Figure 25 is the key diagram of the method for reads image data repeatedly in a horizontal scan period.

Figure 26 is the configuration example of data driver, driver element.

Figure 27 (A), (B), (C) are the configuration examples of memory cell.

The configuration example of the memory block when Figure 28 is the lateral type unit, driver element.

The configuration example of the memory block when Figure 29 is the longitudinal type unit, driver element.

Figure 30 (A), (B) are the configuration examples of electronic equipment.

Embodiment

Below, the preferred embodiment of the present invention is at length described.Shuo Ming form of implementation is not the improper qualification for record content of the present invention in the claims below, and all that illustrate in this form of implementation constitute and not all are the necessary important documents that solves of the present invention.

1. comparative example

Integrated circuit (IC) apparatus 500 as the comparative example of present embodiment has been shown in Fig. 1 (A).The integrated circuit (IC) apparatus 500 of Fig. 1 (A) comprises memory block MB (video data RAM) and data driving block DB.And, along D2 direction configuration store piece MB and data driving block DB.In addition, memory block MB and data driving block DB form along the length of D1 direction and compare along the long super flat piece of the width of D2 direction.

View data from host computer side is written among the memory block MB.And the DID that data driving block DB will be written among the memory block MB converts analog data voltage to, thereby drives the data wire of display floater.Like this, in Fig. 1 (A), the signal flow of view data is to being the D2 direction.Therefore, in the comparative example of Fig. 1 (A), with this signal flow to being complementary, memory block MB and data driving block DB are disposed along the D2 direction.By aforesaid method, become short path between the input and output, can make the signal delay optimization, can carry out the high signal transmission of efficient.

But, the problem below in the comparative example of Fig. 1 (A), existing.

At first, in integrated circuit (IC) apparatus such as display driver, need dwindle the integrated circuit substrate size for cost degradation.But, if adopt hand work, shorten integrated circuit (IC) apparatus 500 simply and dwindle the integrated circuit substrate size, so,, also to dwindle at long side direction not only at short side direction.Therefore, shown in Fig. 2 (A), cause the problem that is difficult to install.That is, the output pitch for example is preferably greater than and equals 22 μ m, but for example becomes the pitch of 17 μ m in the simple shortening shown in Fig. 2 (A), is difficult to owing to pitch is narrow install.And the framework of the glass of display floater broadens, and the finished product number of glass reduces, and causes cost to increase.

Secondly, in display driver, according to the kind (amorphous TFT, low temperature polycrystalline silicon TFT) of display floater or the specification of pixel count (QCIF, QVGA, VGA) or product etc., the formation of memory and data driver changes.Therefore, in the comparative example of Fig. 1 (A), in some product, even the cell pitch of the cell pitch of pad pitch and memory and data driver is consistent shown in Fig. 1 (B), if but the change of the formation of memory and data driver, these pitches just become inconsistent shown in Fig. 1 (C).So, just shown in Fig. 1 (C), become inconsistently as pitch, just must between circuit block, be formed for absorbing the inconsistent unnecessary distribution zone of pitch.Particularly, piece piece on D 1 direction is in the comparative example of flat Fig. 1 (A), and the inconsistent unnecessary distribution zone that is used to absorb pitch becomes big.Its result, integrated circuit (IC) apparatus 500 width W on the D2 direction becomes big, and the integrated circuit substrate area increases, and causes cost to increase.

On the other hand, for fear of this problem, if change with the mode of pad pitch and the cell pitch alignment layout to memory and data driver, will prolong between development period, the result causes cost to increase.That is, in the comparative example of Fig. 1 (A) because the circuit of each circuit block is constituted and layout is carried out individual design, carry out afterwards matching section apart from etc. operation, thereby problems such as generation unnecessary dummy section, design efficiency are low appear.

2. the formation of integrated circuit (IC) apparatus

Fig. 3 shows and can solve the configuration example of the integrated circuit (IC) apparatus 10 of this form of implementation of problem as mentioned above.In this form of implementation, will from the minor face of integrated circuit (IC) apparatus 10 promptly the first limit SD1 towards the direction of opposed the 3rd limit SD3 as first direction D1, and with the rightabout of D1 as third direction D3.In addition, will be from the long limit of integrated circuit (IC) apparatus 10 promptly the second limit SD2 towards the direction of opposed the 4th limit SD4 as second direction D2, and with the rightabout of D2 as the four directions to D4.And the left side of integrated circuit (IC) apparatus 10 is the first limit SD1 in Fig. 3, and the right is the 3rd limit SD3, but also can be, the left side is the 3rd limit SD3, and the right is the first limit SD1.

As shown in Figure 3, the integrated circuit (IC) apparatus 10 of this form of implementation comprises the first～the N circuit block CB1～CBN (N is the integer more than or equal to 2) along the configuration of D1 direction.That is, circuit block is arranged on the D2 direction in the comparative example of Fig. 1 (A), but circuit block CB1～CBN is arranged on the D1 direction in this form of implementation.In addition, each circuit block does not form the such super flat piece of comparative example of Fig. 1 (A), and forms more square piece.

In addition, integrated circuit (IC) apparatus 10 comprises outlet side I/F zone 12 (broadly being first interface area), and its D2 direction side at the first～the N circuit block CB1～CBN is provided with along SD4.And, also comprising input side I/F zone 14 (broadly being second interface area), its D4 direction side at the first～the N circuit block CB1～CBN is provided with along SD2.More particularly, outlet side I/F zone 12 (an I/O zone) for example do not dispose by other circuit blocks etc. in the D2 of circuit block CB1～CBN direction side.And input side I/F zone 14 (the 2nd I/O zone) for example do not dispose by other circuit blocks etc. in the D4 of circuit block CB1～CBN direction side.That is, in the part that has data driving block at least, on the D2 direction, only there is a circuit block (data driving block).And, in that (Intellectual Property: intellectual property) nuclear is packed under the medium situation of other integrated circuit (IC) apparatus, also can form at least one the formation that I/ F zone 12,14 is not set as IP with integrated circuit (IC) apparatus 10.

Outlet side (display panel side) I/F zone 12 be become and display floater between the zone of interface, comprise pad, be connected output on the pad with multiple elements such as transistor, protection components.Specifically, comprise and being used for to the data wire outputting data signals or to transistor of scan line output scanning signal etc.And, be under the situation of touch panel etc. at display floater, also can comprise the input transistor.

Input side (host computer side) I/F zone 14 be become and main frame (MPU, image process controller, baseband engine) between the zone of interface, can comprise pad, be connected input on the pad with (input and output with) transistor, output with multiple elements such as transistor, protection components.Specifically, the input that comprises the signal (digital signal) that is used to import from main frame is with transistor or be used to export to the output of the signal of main frame with transistor etc.

And, also can be provided with along outlet side or input side I/F zone as limit SD1, the SD3 of minor face.In addition, the projection etc. that becomes external connection terminals can be arranged in I/F (interface) zone 12,14, also can be arranged in addition zone (among the first～the N circuit block CB1～CBN).Under the situation in the zone outside being arranged on I/ F zone 12,14, realize by the small-sized protruding technology except that gold bump (with the protruding technology of resin) as core.

In addition, the first～the N circuit block CB1～CBN can comprise the circuit block (circuit block with different functions) that at least two (or three) are different.With integrated circuit (IC) apparatus 10 is that the situation of display driver is an example, and circuit block CB1～CBN can comprise at least two in data driving block, memory block, turntable driving piece, logic circuit block, gray scale voltage generative circuit piece, the power circuit piece.More particularly, circuit block CB1～CBN can comprise data driving block, logic circuit block at least, can comprise gray scale voltage generative circuit piece again.In addition, under the situation of internal memory type, can comprise memory block again.

For example, Fig. 4 shows the example of polytype display driver and their built-in circuit blocks.Non-crystalline silicon tft (Thin Film Transistor) panel at internal memory (RAM) is used in the display driver, and circuit block CB1～CBN comprises memory block, data driver (source electrode driver) piece, scanner driver (gate drivers) piece, logical circuit (gate-array circuit) piece, gray scale voltage generative circuit (checking gamma circuit) piece and power circuit piece.On the other hand, the low temperature polycrystalline silicon of internal memory (LTPS) TFT panel is used in the display driver, owing to scanner driver can be formed on the glass substrate, thereby can omit the turntable driving piece.In addition, in the non-crystalline silicon tft panel of non-internal memory is used, memory block can be omitted, in the low temperature polycrystalline silicon TFT of non-internal memory panel is used, memory block and turntable driving piece can be omitted.In addition, in CSTN (Collar Super TwistedNematic) panel, TFD (Thin Film Diode) panel, can omit gray scale voltage generative circuit piece.

Fig. 5 (A), (B) show the plane figure example of integrated circuit (IC) apparatus 10 of the display driver of this form of implementation.Fig. 5 (A), (B) are the examples that the non-crystalline silicon tft panel of internal memory is used, and the display driver that Fig. 5 (A) for example uses QCIF, 32 rank is as target, and the display driver that Fig. 5 (B) for example uses QVGA, 64 rank is as target.

In Fig. 5 (A), (B), the first～the N circuit block CB1～CBN comprises first～the 4th memory block MB1～MB4 (broadly be the first～the I memory block, I is the integer more than or equal to 2).In addition, also comprise first～the 4th data driving block DB1～DB4 (broadly being the first～the I data driving block), they along the D1 direction respectively with each first～the 4th memory block MB1～MB4 in abutting connection with configuration.Specifically, memory block MB1 and data driving block DB1 along the D1 direction in abutting connection with configuration, memory block MB2 and data driving block DB2 along the D1 direction in abutting connection with configuration.And the view data that data driving block DB1 uses for driving data lines (video data) is stored by the memory block MB1 of adjacency, and the view data that data driving block DB2 uses for driving data lines is stored by the memory block MB2 of adjacency.

In addition, in Fig. 5 (A), the MB1 in memory block MB1～MB4 (broadly be the J memory block, the D3 direction side of 1≤J＜I), the DB1 (broadly being the J data driving block) in configuration data drive block DB1～DB4.In addition, in the D1 of memory block MB1 direction side, in abutting connection with configuration store piece MB2 (broadly being the J+1 memory block).And, in the D1 of memory block MB2 direction side, in abutting connection with configuration data drive block DB2 (broadly being the J+1 data driving block).The configuration of memory block MB3, MB4, data driving block DB3, DB4 is also identical.As mentioned above, in Fig. 5 (A), the boundary line of MB1, MB2 is with line symmetrical manner configuration MB1, DB1 and MB2, DB2 relatively, and the boundary line of MB3, MB4 is with line symmetrical manner configuration MB3, DB3 and MB4, DB4 relatively.In Fig. 5 (A), DB2 and DB3 be in abutting connection with configuration, but also can make these not in abutting connection with, dispose other circuit block therebetween.

On the other hand, in Fig. 5 (B), the D3 direction side of the MB1 in memory block MB1～MB4 (J memory block), the DB1 (J data driving block) in configuration data drive block DB1～DB4.In addition, at the D1 of MB1 direction side configuration DB2 (J+1 data driving block).And, at the D1 of DB2 direction side configuration MB2 (J+1 memory block).The configuration of DB3, MB3, DB4, MB4 is also identical.And in Fig. 5 (B), MB1 and DB2, MB2 and DB3, MB3 and DB4 be respectively by in abutting connection with configuration, but also can make these not in abutting connection with, dispose other circuit block therebetween.

According to the layout configurations of Fig. 5 (A), has the advantage that between memory block MB1 and MB2 or MB3 and MB4 (between J, the J+1 memory block) can the common column address decoder.On the other hand, according to the layout configurations of Fig. 5 (B), have the distribution pitch homogenizing that can make data output signal line, and can improve the advantage of wiring efficiency from data driving block DB1～DB4 to outlet side I/F zone 12.

And the layout configurations of the integrated circuit (IC) apparatus 10 of this form of implementation is not limited to Fig. 5 (A), (B).For example, the piece number of memory block or data driving block can be set at 2,3 or, also memory block or data driving block can be constituted in the mode of not carrying out piece and cutting apart more than or equal to 5.In addition, also can carry out the not distortion enforcement of adjacency of memory block and data driving block.In addition, also can constitute in the mode that memory block, turntable driving piece, power circuit piece or gray scale voltage generative circuit piece etc. are not set.In addition, also can between circuit block CB1～CBN and outlet side I/F zone 12 or input side I/F zone 14, be arranged on the very narrow circuit block (smaller or equal to the elongated circuit block of WB) of width on the D2 direction.In addition, circuit block CB1～CBN also can comprise the circuit block on the multistage D2 of the being arranged in direction of different circuit blocks.For example, also scanner driver circuit and power circuit can be constituted as a circuit block.

Fig. 6 (A) is the example along the profile of D2 direction of the integrated circuit (IC) apparatus of this form of implementation, and Fig. 6 (B) is the example of the profile of comparative example.In the comparative example of Fig. 1 (A), shown in Fig. 6 (B), two or more a plurality of circuit blocks dispose along the D2 direction.In addition, on the D2 direction, be formed with the distribution zone between the circuit block or between circuit block and the I/F zone.Therefore, it is big that the width W of the D2 direction (short side direction) of integrated circuit (IC) apparatus 500 becomes, and can not realize very thin elongated integrated circuit substrate.Therefore, even utilize hand work to shorten integrated circuit substrate, also become narrow pitch, thereby cause being difficult to installing owing to the length L D on D1 direction (long side direction) shown in Fig. 2 (A) shortens, exports pitch.

Relative therewith, in this form of implementation, shown in Fig. 3, Fig. 5 (A), (B), a plurality of circuit block CB1～CBN dispose along the D1 direction.In addition, shown in Fig. 6 (A), below pad (projection), can dispose transistor (circuit element) (active face projection).In addition, by global lines can form between the circuit block or circuit block and I/F zone between etc. in holding wire, this global lines is formed on as the upper strata of the local distribution of the distribution in the circuit block (lower floor of pad).Therefore, shown in Fig. 2 (B), under the state of keeping the length L D on the D1 direction of integrated circuit (IC) apparatus 10, the width W on the D2 direction can be dwindled, super very thin elongated integrated circuit substrate can be realized.Its result can make the output pitch for example be maintained more than or equal to 22 μ m, can install easily.

In addition, because a plurality of circuit block CB1～CBN dispose along the D1 direction in this form of implementation, thereby can easily tackle the specification change of product.That is, owing to can use the product of common design of Platform plurality of specifications, thereby can improve design efficiency.For example, in Fig. 5 (A), (B), even under the situation of the pixel count of display floater or the increase and decrease of grey exponent number, also the piece number by making memory block or data driving block or in the increases and decreases such as read-around number of the view data of a horizontal scan period only just can be tackled.In addition, Fig. 5 (A), (B) are the examples that the non-crystalline silicon tft panel of internal memory is used, but under the situation of the product that the low temperature polycrystalline silicon TFT panel of exploitation internal memory is used, it is just passable only to take off the turntable driving piece from circuit block CB1～CBN.In addition, under the situation of product of the non-internal memory of exploitation, as long as it is just passable to take off memory block.And,, in this form of implementation,, thereby can improve design efficiency because it is suppressed to Min. to the influence that other circuit blocks give even take off circuit block according to specification as described above.

In addition, in this form of implementation, can the width (highly) of the D2 direction of each circuit block CB1～CBN is unified with the width (highly) of for example data driving block or memory block.And, under the situation of the number of transistors of each circuit block increase and decrease, adjust, thereby can make and design more validation because the length of D1 direction that can be by making each circuit block increases and decreases.For example, even the gray scale voltage generative circuit piece in Fig. 5 (A), (B) or the formation of power circuit piece change, under the situation of increase and decrease number of transistors, the length of D1 direction that also can be by making gray scale voltage generative circuit piece or power circuit piece increases and decreases to be tackled.

And, as second comparative example, also can consider this method, that is, configuration data drive block slenderly on the D1 direction for example is in the D4 of data driving block direction side, along other a plurality of circuit blocks such as D1 direction configuration store pieces.But, in this second comparative example, between other a plurality of circuit blocks such as memory block and outlet side I/F zone, owing to insert the big data driving block of width, thereby the change of the width W of the D2 direction of integrated circuit (IC) apparatus is big, is difficult to realize very thin elongated integrated circuit substrate.In addition, form unnecessary distribution zone between data driving block and memory block, it is bigger that width W becomes.In addition, under the situation that the formation of data driving block or memory block changes, be created in inconsistent problem of pitch of explanation among Fig. 1 (B), (C), can not improve design efficiency.

In addition,, also can consider a kind of like this method, that is, only the circuit block (for example data driving block) of identical function be carried out piece and cuts apart, on the D1 direction and row arrangement as the 3rd comparative example of this form of implementation.But, in the 3rd comparative example, owing to can only make integrated circuit (IC) apparatus have identical function (for example function of data driver), thereby can not realize various product development.Relative therewith, in this form of implementation, circuit block CB1～CBN comprises the circuit block with at least two kinds of different functions.Therefore, shown in Fig. 4, Fig. 5 (A), (B), has the advantage that can provide corresponding to the integrated circuit (IC) apparatus of the multiple machine of polytype display floater.

3. circuit constitutes

Fig. 7 shows the circuit configuration example of integrated circuit (IC) apparatus 10.The circuit formation of integrated circuit (IC) apparatus 10 is not limited to Fig. 7, can carry out various deformation and implement.Memory 20 (video data RAM) store images data.Memory cell array 22 comprises a plurality of memory cell, stores the view data (video data) that is equivalent to 1 frame (1 picture) at least.At this moment, 1 pixel for example is made of three sub-pixel unit (3 point) of R, G, B, stores for example view data of 6 (k positions) for each sub-pixel unit.Row address decoder 24 (MPU/LCD row address decoder) carries out handling for the decoding of row address, and the selection of the word line of the line storage unit of going forward side by side array 22 is handled.Column address decoder 26 (MPU column address decoder) carries out handling for the decoding of column address, and the selection of the bit line of the line storage unit of going forward side by side array 22 is handled.Writing/Reading circuit 28 (MPU Writing/Reading circuit) carry out to writing of the view data of memory cell array 22 handle or from the view data of memory cell array 22 read handle.And the accessing zone of memory cell array 22 is with for example by initial address and terminal address are defined as the rectangle to the summit.That is, define accessing zone, carry out storage access by the column address of initial address and the column address and the row address of row address and terminal address.

Logical circuit 40 (for example disposing wiring circuit automatically) generates to be used to control and shows control signal constantly or be used for control data processing control signal constantly etc.This logical circuit 40 for example can be formed by automatic configuration distributions such as gate arrays (G/A).Control circuit 42 generates various control signals or carries out the control of whole device.Specifically, to the adjustment data (γ correction data) of gray scale voltage generative circuit 110 output gray-level characteristics (γ characteristic), or the voltage of control power circuit 90 generates.In addition, control is handled for the Writing/Reading of the memory that uses row address decoder 24, column address decoder 26, Writing/Reading circuit 28.Showing that control circuit 44 generates to be used to control constantly shows various control signals constantly, and control is from memory reading to the view data of display panel side.Main frame (MPU) interface circuit 46 is realized each access from main frame is generated internal pulses and to the host interface of storage access.Rgb interface circuit 48 is realized according to Dot Clock the RGB data of animation being write to rgb interface in the memory.And, also can be any the formation that only is provided with in host interface circuit 46, the rgb interface circuit 48.

In Fig. 7, carry out access with 1 pixel unit to memory 20 from host interface circuit 46, rgb interface circuit 48.On the other hand, according to showing constantly,, provide the view data of specifying and reading with the unit of going to data driver 50 by row address at each line period with host interface circuit 46, rgb interface circuit 48 are independently inner.

Data driver 50 is the circuit that are used to drive the data wire of display floater, in its configuration example shown in Fig. 8 (A).Data-latching circuit 52 latchs the DID from memory 20.D/A change-over circuit 54 (voltage selecting circuit) is latched at the D/A conversion of the DID in the data-latching circuit 52, generates analog data voltage.Specifically,, from these many gray scale voltages, select voltage, export as data voltage corresponding to DID from the gray scale voltage (reference voltage) of gray scale voltage generative circuit 110 acceptance a plurality of (for example 64 rank).Output circuit 56 (drive circuit, buffer circuit) cushions and exports to the data wire of display floater, driving data lines to the data voltage from D/A change-over circuit 54.And the part (for example output of operational amplifier) that also can constitute output circuit 56 is not included in the data driver 50, and is configured in other zones.

Scanner driver 70 is the circuit that are used to drive the scan line of display floater, and Fig. 8 (B) shows its configuration example.Shift register 72 comprises a plurality of triggers that are linked in sequence, with shift clock signal SCK shift enable input/output signal EIO successively synchronously.Level shifter 76 will be the high-voltage level that is used for scanning line selection from the voltage of signals level conversion of shift register 72.78 pairs of scanning voltages by level shifter 76 conversions and output of output circuit cushion, and export the scan line of display floater to, select the driven sweep line.And scanner driver 70 also can be the formation shown in Fig. 8 (C).In Fig. 8 (C), scan address generative circuit 73 generates the scan address and exports, and address decoder carries out the decoding of scan address to be handled.And, scanning voltage is exported to by the specific scan line of this decoding processing by level shifter 76, output circuit 78.

Power circuit 90 is the circuit that generate various supply voltages, and Fig. 9 (A) shows its configuration example.Booster circuit 92 is in the charge pump mode input supply voltage or internal power source voltage to be boosted and generate the circuit of booster voltage with transistor with boosting with capacitor or boosting, and can comprise 1 time～No. 4 booster circuits etc.According to this booster circuit 92, can generate the high voltage that scanner driver 70 or gray scale voltage generative circuit 110 use.Adjustment circuit (voltage stabilizing circuit) 94 carries out the level adjustment by the booster voltage of booster circuit 92 generations.VCOM generative circuit 96 generates the VCOM voltage of the opposite electrode that offers display floater and exports.Control circuit 98 is the circuit that carry out the control of power circuit 90, comprises various control registers etc.

Gray scale voltage generative circuit (checking gamma circuit) 110 generates the circuit of gray scale voltage, and Fig. 9 (B) shows its configuration example.Select with high-tension supply voltage VDDH, the VSSH of voltage generation circuit 112 (bleeder circuit) according to generation in power circuit 90, output is selected with voltage VS0～VS255 (broadly be R and select to use voltage).Specifically, select to comprise ladder resistor circuit with a plurality of resistive elements that are connected in series with voltage generation circuit 112.And, will carry out the voltage of dividing potential drop to VDDH, VSSH as selecting with this ladder resistor circuit with voltage VS0～VS255 output.Gray scale voltage selects circuit 114 according to be set in the adjustment data of adjusting the gray-level characteristic in the register 116 by logical circuit 40, for example under the situation on 64 rank, select 64 (broadly to be S voltage VS0～VS255 from selecting to use, the voltage of R＞S) is as gray scale voltage V0～V63 output.Like this, can generate the gray scale voltage of best gray-level characteristic (γ correcting feature) according to display floater.And, under the situation that polarity inversion drives, the ladder resistor circuit that ladder resistor circuit that positive polarity uses and negative polarity are used can be set in selecting with voltage generation circuit 112 also.In addition, the resistance value of each resistive element of ladder resistor circuit is changed according to being set in the adjustment data of adjusting in the register 116.In addition, also can constitute and selecting to select to be provided with in the circuit 114 impedance inverter circuit (operational amplifier of voltage follower connection) with voltage generation circuit 112 or gray scale voltage.

Figure 10 (A) shows the configuration example of included each DAC (Digital Analog Converter) of the D/A change-over circuit 54 of Fig. 8 (A).Each DAC of Figure 10 (A) for example can be arranged in each sub-pixel (or each pixel), is made of ROM decoder etc.According to from DID D0～D5 of 6 of memory 20 and its reversal data XD0～XD5, select any from the gray scale voltage V0～V63 of gray scale voltage generative circuit 110, thus view data D0～D5 is converted to aanalogvoltage.Then, the signal DAQ (DAQR, DAQG, DAQB) with the aanalogvoltage that obtains exports output circuit 56 to.

And, in display driver that low temperature polycrystalline silicon TFT uses etc., R is being carried out demultiplexing with, B with data-signal with, G and offering under the situation (situation of Figure 10 (C)) of display driver, can carry out D/A with view data and change with, B with, G R with a shared DAC.At this moment, each DAC of Figure 10 (A) is set in each pixel.

Figure 10 (B) shows the configuration example of included each efferent SQ of the output circuit 56 of Fig. 8 (A).Each efferent SQ of Figure 10 (B) can be arranged in each pixel.Each efferent SQ comprises R (red) usefulness, G (green) usefulness, B (indigo plant) impedance inverter circuit OPR, OPG, OPB (operational amplifier that voltage follower connects), carry out signal DAQR, the DAQG from DAC, the impedance conversion of DAQB, export data-signal DATAR, DATAG, DATAB to R usefulness, G usefulness, B data-signal output line.And, for example under the situation of low temperature polycrystalline silicon TFT panel, switch element shown in Figure 10 (C) (switch transistor) SWR, SWG, SWB also can be set, R be exported by the data-signal DATA of demultiplexing with data-signal with, B with, G by the OP of impedance inverter circuit.In addition, also can in a plurality of pixel coverages, carry out the demultiplexing of data-signal.In addition, the impedance inverter circuit shown in Figure 10 (B), (C) can be set in efferent SQ yet, and switch element etc. only is set.

4. the width of integrated circuit (IC) apparatus

4.1 the configuration relation of pad and electrostatic protection element

In the present embodiment, be positioned over the lower floor of this pad, make the D2 direction width of integrated circuit (IC) apparatus 10 further reduce by the electrostatic protection element that will be connected with the pad of the interface area that is arranged at integrated circuit (IC) apparatus 10.If the lower floor with other transistors outside the electrostatic protection element and resistive element are disposed at this pad by adjusting configuration mode, can make the width W of the D2 direction of integrated circuit (IC) apparatus 10 further reduce.

The example of the pad shown in Figure 11 (A) in the comparative example and the configuration relation of electrostatic protection element.For example along second limit SD2 of integrated circuit (IC) apparatus 10, the pad interval d0 of the designing requirement defined of being separated by is with pad PD _X-1, PD _x, PD _X+1Arrange along the D1 direction.Though pad is a rectangle among Figure 11 (A), pad is that square also can.Then shown in Figure 11 (A), with the short side direction configured in parallel in the formation zone of the configuration direction of pad and electrostatic protection element.And when pad was rectangular shape, the configuration direction of pad can be the short side direction of pad.

Withstand voltage when above-mentioned electrostatic protection element is carried out static can exist with ... for example structure of grid controlled transistor.

Figure 12 (A) shows the plane figure example of a grid controlled transistor.In Figure 27 (A), two source area SA1, SA2 are arranged, a drain region DA1.Gate electrode GA1 is configured in the upper strata of the channel region between source area SA1, the drain region DA1 across gate insulating film, and gate electrode GA2 is configured in the upper strata of the channel region between source area SA2, the drain region DA1 across gate insulating film.Low potential side supply voltage VEE offers source area SA1, SA2 by a plurality of contacts.Drain region DA1 is being electrically connected with pad PD by a plurality of contacts.

Pad, is necessary at drain region DA1 to the current path that forms homogeneous between source area SA1, the SA2 in addition during high voltage by static.For this reason, become key factor apart from d between each contact of drain region DA1 and gate electrode GA1, the GA2.If insufficient, then withstand voltage meeting is low apart from d for these, and element is easy to damage.And these apart from d if unequal, the flow direction that electric current will be concentrated a bit, element also can be easy to damage.So, be necessary for antistatic, each contact of drain region DA1 and the distance between gate electrode GA1, the GA2 are kept fully, and impartial each contact of configuration.So,, can allow the transistor of output buffering have functions such as electrostatic protection element simultaneously concurrently by noting considering the configuration of contact.

At this, when adjusting the current driving ability of the output buffer transistor that has the electrostatic protection element function simultaneously concurrently, shown in Figure 12 (B), (C), be necessary size is increased along the D2 direction, or the increase and decrease gate electrode.But if size is increased to the D2 direction, the length of the long side direction of pad is restricted, and has lost in pad lower floor and has disposed the transistorized benefit that destatics outside the protection component.For this reason, though can consider to increase and decrease measures such as gate electrode, the adjustment of current driving ability must be that unit regulates as a group with source area, gate electrode and drain region.Thus, can't realize the fine setting of transistor current driving force, invalidly increase layout area.

To this; in this example; shown in Figure 11 (B), it is parallel that the short side direction of rectangular pad and electrostatic protection element form the long side direction in zone, and to be disposed at the upper strata of this electrostatic protection element with the part or all of equitant mode of electrostatic protection element.And electrostatic protection element is disposed at the second minor face PSD2 side among opposed first and second minor face PSD1, the PSD2 with pad.When the distance in the second minor face PSD2 and nearest electrostatic protection element zone as d1; the distance in the first minor face PSD1 and nearest electrostatic protection element zone is during as d2; the second minor face PSD2 and nearest electrostatic protection element zone be d1＜d2 apart from the d1 and the second minor face PSD2 side.Thus, except effectively utilizing the zone between the pad, can make the zone that can be used for disposing other unit under the pad become big.In addition, even interval d0 is defined as stationary state in the designing requirement, but the width Delta WP of the D2 direction of the integrated circuit (IC) apparatus 10 of pad lower floor also has nargin.On the zone of width Delta WP, can dispose transistor and resistive element etc.And when regulating electrostatic withstand voltage, by the size of within the restriction of pad interval d0, regulating the electrostatic protection element long side direction, can the fine-adjusting current driving force.Its result can help to reduce expeditiously layout area.

The example of layout of the electrostatic protection element device of Figure 11 (B) is shown to Figure 13 pattern.In Figure 13, form transistorized plurality of source regions, gate electrode and drain electrode with the form of extending transistorized channel width at the short side direction of pad.Afterwards, according to one or more source areas of the first minor face PSD1x side of pad PDx, gate electrode and drain electrode constitute the transistor (example is transistor nDTrt as described later) that is configured in the imagination of pad PDx.Then, as the electrostatic protection element of grid controlled transistor, constitute by one or more source areas, gate electrode and the drain electrode of the second minor face PSD2x side of pad PDx.

By such distribution, not only can be easy to regulate the size of transistor and grid controlled transistor according to transistorized current driving ability, can also help to dwindle the configuration area.

4.1.1 be disposed at the example of the electrostatic protection element under the pad

The transistor that Figure 14 (A), (B) illustrate the output usefulness under the o pads that is formed on sweep signal constitutes example.The shift register 72 of Fig. 8 (B) comprises trigger FF1～FFn that each trigger corresponding with each scan line of scan line S1～Sn vertically connects, Figure 14 (A) shows the formation example that is equivalent among the scanner driver 70 shown in Fig. 8 (B) to the output of scan line St (1≤t≤n, t are integer).Equally, Figure 14 (B) shows the formation example that is equivalent among the scanner driver 70 among Fig. 8 (C) to the output of scan line St.

Shown in Figure 14 (A), the voltage level of the output signal of trigger FFt is changed by level displacement shifter 76t.Provide hot side voltage VDDHG and low potential side voltage VEE to level displacement shifter 76t, the voltage level conversion of the output signal of trigger FFt is become the voltage level of hot side voltage VDDHG or low potential side voltage VEE.The output of level displacement shifter 76t is as the transistorized signal of output that constitutes output circuit 78t.The output transistor, for example comprise interconnected P type metal acidifying film semiconductor (Metal OxideSemiconductor:MOS) transistor pDTrt of drain electrode and N type MOS transistor nDTrt, recommended connection by what is called between hot side power supply and the low potential side power supply.Then, at least one side of preferred crystal pipe pDTrt, nDTrt is formed at the lower floor of sweep signal o pads jointly with electrostatic protection element ESDt.Hot side voltage VDDHG is provided on the source electrode of transistor pDTrt, low potential side voltage VEE is provided on the source electrode of transistor nDTrt.Hot side voltage VDDHG and low potential side voltage VEE are generated by the booster circuit among Fig. 9 (A) of power circuit piece PB 92.

Among Figure 14 (A), electrostatic protection element ESDt is being connected.This electrostatic protection element ESDt is made of N type MOS transistor GCDTrt.The grid of transistor GCDTrt links to each other with its source electrode.Between the drain electrode and source electrode of transistor nDTrt, transistor GCDTrt and this transistor nDTrt are parallel to be provided with.When being applied in high voltage in the drain electrode of transistor GCDTrt,, electric current is derived to low potential side in order to prevent the destruction of transistor nDTrt.And, between the drain node DNDt of o pads PDt and transistor GCDTrt, in series insert and prevent from the resistive element RLt that locks from also can between drain node DNDt and transistor nDTrt, in series insert electrostatic protection usefulness protective resistance element RPt.

On the other hand, among Figure 14 (B), the voltage level of the output signal of the decoded result of address decoder 74 is changed by level displacement shifter 76t.And; at least one side's part or all of overlapping mode among the electrostatic protection element ESDt of the output circuit 78t that go up to be provided with each output with the scanner driver 70 shown in Figure 14 (B), transistor pDTrt, the nDTrt disposes o pads PDt at least one side's of electrostatic protection element ESDt, transistor pDTrt, nDTrt upper strata.

And among Figure 14 (A), (B); with with resistive element RLt that prevents to lock usefulness and protective resistance RPt among at least one side's part or all of overlapping mode, prevent to lock configuration pad PDt on the upper strata of at least one side among the resistive element RLt of usefulness and the protective resistance RPt at this.In addition, can allow transistor nDTrt have the function of electrostatic protection element concurrently.At this moment, can adopt the formation of omitting electrostatic protection element ESDt.

At this, can only the output circuit 78t in the scanner driver 70 shown in Fig. 8 (B), (C) be disposed on the outlet side I/F zone 12, the turntable driving piece that remaining circuit can be used as circuit block CB1～CBN disposes.Can as shown in Fig. 5 (A), turntable driving piece SB be disposed as a circuit block at the two ends of circuit block CB1～CBN, as shown in Fig. 5 (B), turntable driving piece SB1, SB2 are disposed as the circuit block at the two ends of circuit block CB1～CBN.

In scanner driver 70, as the supply voltage of output circuit 78t, need be than the voltage height of other circuit except level displacement shifter 76t.That is, the transistor that constitutes output circuit 78t need have and bears all high-tension tolerances, and size of component and thickness need be bigger than other circuit, and the thickness of wiring layer also need strengthen.If the holding wire of o pads PDt is supplied with the voltage of the drain node DNDt of transistor pDTrt, nDTrt in consideration, with will be supplied to high-tension holding wire relatively from the situation of turntable driving piece distribution, the distribution of this holding wire can be closed in the outlet side I/F zone 12, can significantly reduce the distribution zone of holding wire.So, close at the same area by element and the distribution that high voltage withstanding property will be arranged, expeditiously design element and element distribution.And, because scanner driver 70 is output as the number of scanning lines of expression panel, so it is bigger to close at the effect in a zone.Then, as shown in this embodiment, by the lower floor of the transistor arrangement that size and thickness is big at pad, can help further to dwindle the scale of circuit, the width of the D2 direction of integrated circuit (IC) apparatus 10 can further diminish.

Figure 15 shows the example of the layout vertical view of the transistor GCDTrt that forms as electrostatic protection element ESDt.Show to Figure 16 pattern example of cross-sectional configuration of the A-A line of Figure 15.

In Figure 15, form P type well area PWE in the N type well area NWL that on P type semiconductor substrate P SUB, forms.In P type well area PWE, in two zones of p type impurity diffusion zone PF, be provided with three N type diffusion of impurities zone NF of electrical separation respectively around formation.Between the NF of these N type diffusion of impurities zones, be provided with gate electrode GM, three N type diffusion of impurities zone NF comprise two source areas and a drain region.To p type impurity diffusion zone PF, N type diffusion of impurities zone NF and gate electrode GM, provide low potential side supply voltage VEE by contact CNT.

And as shown in figure 16, on the channel region of gate electrode GM bottom, the lower floor of LOCOS Acidulent film, LOCOS Acidulent film is provided with biasing layer OFT.Among the such a transistor GCDTrt as the set N type diffusion of impurities zone NF in drain region, by one or more through holes and wiring layer MTL, PDt is electrically connected with pad.

In Figure 16, be provided with the drain region of transistor GCDTrt under the pad PDt, be added in the voltage on the pad PDt, by having a plurality of circuits of roughly the same impedance, be applied on this drain region with beeline.Thus, can strengthen the electrostatic protection tolerance.

And in Figure 16,, can form transistor nDTrt, pDTrt equally in the pad lower floor though only the structure when forming transistor GCDTrt in the pad lower floor is illustrated.

In Figure 17, show the example of the cross-sectional configuration of the transistor nDTrt in the lower floor that is formed at pad PDt.In Figure 17, with respect to the structure among Figure 16, difference is that gate electrode is supplied with in the output of level displacement shifter.In addition, transistor pDTrt also can similarly be formed at the lower floor of pad PDt.

4.2 elongated integrated circuit (IC) apparatus

In this form of implementation, shown in Figure 18 (A), the first～the N circuit block CB1～CBN comprises at least one the data driving block DB that is used for driving data lines.In addition, the first～the N circuit block CB1～CBN comprises the circuit block (realizing the circuit block of the function different with DB) except data driving block DB.At this, the circuit block except data driving block DB for example is logic circuit block (Fig. 7 40).Perhaps, be gray scale voltage generative circuit piece (Fig. 7 110) or power circuit (Fig. 7 90).Perhaps under the situation of internal memory, be memory block (Fig. 7 20), under the situation that non-crystalline silicon tft is used, be turntable driving piece (Fig. 7 70).

In addition, in Figure 18 (A), W1, WB, W2 are respectively the width on the D2 direction of outlet side I/F zone 12 (first interface area), the first～the N circuit block CB1～CBN, input side I/F zone 14 (second interface area).

And in this form of implementation, shown in Figure 18 (A), under with the situation of width as W on the D2 direction of integrated circuit (IC) apparatus 10, W1+WB+W2≤W＜W1+2 * WB+W2 sets up.That is, in the comparative example of Fig. 6 (B), two or more a plurality of circuit blocks dispose along the D2 direction.Therefore, the width W on the D2 direction becomes W 〉=W1+2 * WB+W2.Relative therewith, in this form of implementation, outlet side I/F zone 12 is not to be configured in the D2 direction side of data driving block DB (or memory block) by the mode of other circuit blocks.That is, data driving block DB and outlet side I/F zone 12 is in abutting connection with configuration.In addition, input side I/F zone 14 is not to be configured in the D4 direction side of data driving block DB (or memory block) by the mode of other circuit blocks.That is, data driving block DB and input side I/F zone 14 is in abutting connection with configuration.And other circuit blocks of this moment for example are the main macrocircuit pieces (piece of gray scale voltage generative circuit, power circuit, memory or logical circuit etc.) that constitutes display driver.

In the comparative example of Fig. 1 (A), Fig. 6 (B), because W 〉=W1+2 * WB+W2, thereby the change of the width W on the D2 direction (short side direction) of integrated circuit (IC) apparatus 500 is big, so can not realize very thin elongated integrated circuit substrate.Therefore, even utilize hand work to shorten integrated circuit substrate, also become narrow pitch, thereby cause being difficult to installing owing to the length L D on D1 direction (long side direction) shown in Fig. 2 (A) also shortens, exports pitch.

Relative therewith, in this form of implementation, owing between data driving block DB and I/F zone 12,14, other circuit block is not set, thereby W＜W1+2 * WB+W2 sets up.Therefore, the width W of the integrated circuit (IC) apparatus on the D2 direction can be reduced, the very thin elongated integrated circuit substrate shown in Fig. 2 (B) can be realized.Specifically, can make, more particularly, can make W＜1.5mm as the width W＜2mm on the D2 direction of short side direction.Consider the inspection or the installation of integrated circuit substrate, be preferably W＞0.9mm.In addition, can make the length L D on the long side direction become 15mm＜LD＜27mm.In addition, can make the integrated circuit substrate shape become SP＞10, more particularly can make SP＞12 than SP=LD/W.Like this, according to specifications such as pin (PIN) numbers, for example can realize the elongated integrated circuit (IC) apparatus of W=1.3mm, LD=22mm, SP=16.9 or W=1.35mm, LD=17mm, SP=12.6.Thus, shown in Fig. 2 (B), can make the installation facilitation.In addition, owing to reduce the integrated circuit substrate area, thereby realize cost degradation.That is, can realize facilitation and the cost degradation installed simultaneously.

And, consider the flow direction of the signal of view data, the collocation method of the comparative example of Fig. 1 (A) is also reasonable.For this point, in this form of implementation, shown in Figure 18 (B), will from the output line DQL of the data-signal of data driving block DB in DB along D2 direction distribution.On the other hand, with data-signal output line DQL in outlet side I/F zone 12 (first interface area) along D1 (D3) direction distribution.Specifically,, be used in the lower floor of pad and in the global lines on the upper strata of local distribution (transistor distribution) in outlet side I/F zone 12, with data-signal output line DQL along D1 direction distribution.Like this, even the collocation method that other circuit block data driving block DB and I/F zone 12,14 between be not set of employing shown in Figure 18 (A) also can suitably export the data-signal from DB to display floater by pad.In addition, if with data-signal output line DQL with the mode distribution shown in Figure 18 (B), just can utilize outlet side I/F zone 12 that data-signal output line DQL is connected on pad etc., can prevent the increase of the width W on the D2 direction of integrated circuit (IC) apparatus.

And the width W 1 of Figure 18 (A), WB, W2 are respectively the width in the transistor formation region territory (memory bank zone, active region) in outlet side I/F zone 12, circuit block CB1～CBN, input side I/F zone 14.That is, in I/F zone 12,14, be formed with the transistor of output transistor, input transistor, input and output transistor, electrostatic protection element etc.In addition, in circuit block CB1～CBN, be formed with the transistor of forming circuit.And, be benchmark to form this transistorized well area or diffusion zone etc., determine W1, WB, W2.For example, in order to realize more very thin elongated integrated circuit (IC) apparatus, preferably on circuit block CB1～CBN transistorized, also form projection (active face projection).Specifically, go up formation resin core projection at transistor (active region), its core is formed by resin, and forms metal level on the surface of resin.And this projection (external connection terminals) is connected with pad on being configured in I/F zone 12,14 by metal wiring.The W1 of this form of implementation, WB, W2 are not the width in the formation zone of this projection, and are formed in the width in the following transistor formation region territory of projection.

In addition, the width on the D2 direction of each circuit block CB1～CBN for example can be unified into identical width.At this moment, as long as the width of each circuit block is identical in fact just passable, and for example the difference of counting about μ m～20 μ m (tens of μ m) belongs in the allowed band.In addition, in circuit block CB1～CBN, under the situation that has the different circuit block of width, can be with the Breadth Maximum in the width of circuit block CB1～CBN as width W B.For example can be with the Breadth Maximum of the width on the D2 direction of data driving block as this moment.Or under the situation of the integrated circuit (IC) apparatus of internal memory, can be used as the width on the D2 direction of memory block.And, between circuit block CB1～CBN and I/ F zone 12,14, the white space of 20～30 μ m left and right sides width for example can be set.

4.3 the width of data driving block

In this form of implementation, shown in Figure 19 (A), the data driver DR that data driving block DB is included can comprise Q the driver element DRC1～DRCQ that arranges along the D2 direction.At this, each driver element DRC1～DRCQ accepts to be equivalent to the view data of 1 pixel.And, be equivalent to the D/A conversion of the view data of 1 pixel, export and the corresponding data-signal of view data that is equivalent to 1 pixel.This each driver element DRC1～DRCQ can comprise the efferent SQ of the DAC (DAC that is equivalent to 1 pixel) of data-latching circuit, Figure 10 (A) or Figure 10 (B), (C).

And, under with the situation of width (pitch) on the D2 direction of driver element DRC1～DRCQ, shown in Figure 19 (A), can make width W B (Breadth Maximum) on the D2 direction of circuit block CB1～CBN become Q * WD≤WB＜(Q+1) * WD as WD.

That is, in this form of implementation, circuit block CB1～CBN disposes along the D1 direction.Therefore, other circuit blocks from circuit block CB1～CBN (for example logic circuit block, memory block) become along the distribution of D1 direction to the holding wire of the view data of data driving block DB input.And in order to be connected with holding wire along the view data of D1 direction, shown in Figure 19 (A), driver element DRC1～DRCQ is along the configuration of D2 direction, and each DRC1～DRCQ is connected on the holding wire of the view data that is equivalent to 1 pixel.

And, in integrated circuit (IC) apparatus of non-internal memory etc., can with the width on the D2 direction of data driving block DB benchmark for example, determine the width W B of circuit block CB1～CBN.Therefore, reduce the width W B of circuit block CB1～CBN for the width on the D2 direction that reduces data driving block DB, width W B is preferably with about driver element DRC1～DRCQ width Q * WD side by side.And if consider to be used for the tolerance limit in distribution zone etc., width W B becomes Q * WD≤WB＜(Q+1) * WD.Like this, because the width on the D2 direction of data driving block DB is suppressed also can reduce the width W B of circuit block CB1～CBN, thereby the elongated integrated circuit (IC) apparatus shown in Fig. 2 (B) can be provided for Min..

And, with the pixel count of the horizontal scan direction of display floater (under the situation of sharing the data wire that drives display floater by a plurality of integrated circuit (IC) apparatus, the pixel count of the horizontal scan direction that each integrated circuit (IC) apparatus is responsible for) as HPN, with the piece number (piece is cut apart number) of data driving block as DBN, and will be a horizontal scan period to the input number of times of the view data of driver element input as IN.And IN is identical with the read-around number RN of the view data of a horizontal scan period described later.At this moment, the number Q of the driver element DRC1～DRCQ that arranges along the D2 direction can use Q=HPN/ (DBN * IN) represent.For example under the situation of HPN=240, DBN=4, IN=2, become Q=240/ (4 * 2)=30.

In addition, shown in Figure 19 (B), also can make data driving block DB comprise a plurality of data driver DRa, DRb (the first～the m data driver) along D1 direction and row arrangement.If like this with a plurality of data driver DRa, DRb along D1 direction configuration (stack), just can prevent because the big situation of width W change on the D2 direction of the scale of data driver and integrated circuit (IC) apparatus.In addition, according to the type of display floater, data driver can adopt multiple formation.At this moment, also according to the method for a plurality of data drivers along D1 direction configuration, the data driver of the multiple formation of layout effectively just.Having illustrated in Figure 19 (B) along the configurable number of the data driver of D1 direction is 2 situation, but configurable number also can be more than or equal to 3.

Figure 19 (C) shows formation, the configuration example of driver element DRC.The driver element DRC that acceptance is equivalent to the view data of 1 pixel comprises R (red) usefulness, G (green) usefulness, B (indigo plant) data-latching circuit DLATR, DLATG, DLATB.If latch signal becomes state of activation, each data-latching circuit DLATR, DLATG, DLATB just latch view data.In addition, the driver element DRC R that is included in explanation among Figure 10 (A) with, G with, B with DACR, DACG, DACB.In addition, be included in (C) the efferent SQ of middle explanation of Figure 10 (B).

And the formation of driver element DRC, configuration are not subjected to the qualification of Figure 19 (C), can carry out various deformation and implement.For example, low temperature polycrystalline silicon TFT with display driver etc. in, shown in Figure 10 (C), R is transferred under the situation of display floater with the data-signal demultiplexing with, B with, G, can use a shared DAC to carry out R and change with the D/A of view data (view data that is equivalent to 1 pixel) with, B with, G.Therefore, at this moment, shown in Figure 19 (D), driver element DRC comprises that the shared DAC of formation of Figure 10 (A) is just passable.In addition, Figure 19 (C) (D) in, along D2 (D4) direction configuration R with circuit (DLATR, DACR), G with circuit (DLATG, DACG), B with circuit (DLATB, DACB).But, shown in Figure 19 (E), also can be at D1 (D3) direction configuration R with, G with, B circuit.

4.4 the width of memory block

In the integrated circuit (IC) apparatus of internal memory, shown in Figure 20 (A), can adjacency configuration on the D1 direction with data driving block DB and memory block MB.

About this point, in the comparative example of Fig. 1 (A), shown in Figure 21 (A), be complementary with the flow direction of signal, memory block MB and data driving block DB are along the D2 direction configuration as short side direction.Therefore, it is big that the width of the integrated circuit (IC) apparatus on the D2 direction becomes, and is difficult to realize very thin elongated integrated circuit substrate.In addition, if the specification of the pixel count of display floater, display driver, the changes such as formation of memory cell, width on the D2 direction of memory block MB or data driving block DB or the length on the D1 direction change, so, its influence also feeds through to other circuit block, makes the efficient of design low.

Relative therewith, in Figure 20 (A),, thereby can reduce the width W of the integrated circuit (IC) apparatus on the D2 direction because data driving block DB and memory block MB be along the configuration of D1 direction.In addition, under the situation that the pixel count of display floater etc. changes, because can be by cutting apart the replies such as method of memory block, thereby improve design efficiency.

In addition, in Figure 21 (A) comparative example, owing to word line WL disposes along the D1 direction as long side direction, thereby the change of the signal delay in word line WL is big, and the reading speed of view data is slack-off.Particularly, owing to the word line WL that is connected on the memory cell is formed by polysilicon layer, thereby the problem of this signal delay is serious.At this moment, in order to reduce this signal delay, have the method for the buffer circuit 520,522 that is provided with shown in Figure 21 (B).But if adopt this method, circuit scale will correspondingly become greatly, causes cost to increase.

Relative therewith, in Figure 20 (A), in memory block MB, word line WL is along the D2 direction configuration as short side direction, and bit line BL is along the D1 direction configuration as long side direction.In addition, in this form of implementation, the width W of the integrated circuit (IC) apparatus on the D2 direction is short.Therefore, can shorten the length of word line WL in the memory block MB, compare, can obviously be reduced in the signal delay among the WL with Figure 21 (A) comparative example.In addition, owing to also the buffer circuit 520,522 shown in Figure 21 (B) can be set, thereby circuit area also diminishes.In addition, in the comparative example of Figure 21 (A), from main frame when a part of accessing zone of memory carries out access, word line WL long and that parasitic capacitance is big is also selected for length on the D1 direction, thereby consumes electric power and become big.Relative therewith, as this form of implementation, on the D1 direction, cutting apart in the method for memory, during the main frame access,, thereby can realize the low consumption electrification owing to the word line WL that only selects corresponding to the memory block of accessing zone.

And, in this form of implementation, shown in Figure 20 (A), under the situation of width on the D2 direction of peripheral circuit that memory block MB is included part, can become Q * WD≤WB＜(Q+1) * WD+WPC as WPC.At this, peripheral circuit refers to the peripheral circuit (column address decoder, control circuit etc.) that is configured between the memory cell array or distribution zone etc., and this memory cell array is in the D2 or the configuration of D4 direction side of memory cell arrays and cut apart.

In the configuration of Figure 20 (A), preferably make width Q * WD of driver element DRC1～DRCQ consistent with the width of sense amplifier piece SAB.If these width are inconsistent, so, in the time will being connected on driver element DRC1～DRCQ, must change the distribution pitch of these holding wires from the holding wire of the view data of sense amplifier piece SAB, produce unnecessary distribution zone thus.

In addition, except memory cell arrays, memory block MB has peripheral circuit parts such as row address decoder RD.Therefore, in Figure 20 (A), the width of memory block MB is compared with width Q * WD of driver element DRC1～DRCQ, increases the width of the width W PC that is equivalent to the peripheral circuit part.

And, in integrated circuit (IC) apparatus of internal memory etc., can with the width on the D2 direction of memory block MB benchmark, determine the width W B of circuit block CB1～CBN.Therefore, reduce the width W B of circuit block CB1～CBN for the width on the D2 direction that reduces memory block MB, width W B preferably satisfies Q * WD≤WB＜(Q+1) * WD+WPC.Like this, because the width on the D2 direction of Min. ground inhibition data driving block DB also can reduce width W B, thereby the elongated integrated circuit (IC) apparatus shown in Fig. 2 (B) can be provided.

Figure 20 (B) shows the configuration relation between driver element DRC1～DRCQ and the sense amplifier piece SAB.Shown in Figure 20 (B), the driver element DRC1 that is equivalent to the view data of 1 pixel to acceptance, connect the sense amplifier that be equivalent to 1 pixel corresponding with it (R with sense amplifier SAR10～SAR15, G with sense amplifier SAG10～SAG15, B with sense amplifier SAB10～SAB15).Connection between other driver elements DRC2～DRCQ and the sense amplifier is also identical.

Shown in Figure 20 (B), the width on the D2 direction of peripheral circuit that memory block is included part (row address decoder RD) as WPC, and will be equivalent under the situation of figure place as PDB of view data of 1 pixel, the width W B (Breadth Maximum) on the D2 direction of circuit block CB1～CBN can represent with P * WS≤WB＜(P+PDB) * WS+WPC.At this, be under 6 the situation, to become PDB=18 at each of R, G, B.

And, with the pixel count of the horizontal scan direction of display floater as HPN, the figure place of view data that will be equivalent to 1 pixel is as PDB, with the piece number of memory block as MBN (=DBN), the read-around number of the view data of will be in a horizontal scan period reading from memory block is as RN.At this moment, the number P of the sense amplifier of arranging along the D2 direction in sense amplifier piece SAB can use P=(HPN * PDB)/(MBN * RN) represent.

And number P is the effective sense amplifier number corresponding to the effective storage unit number, does not comprise the number of the invalid sense amplifiers such as sense amplifier that virtual memory cell is used.In addition, number P is a number of exporting the sense amplifier of the view data that is equivalent to 1.For example, switching by first, second sense amplifier and the selector that is connected with its output under the situation of view data that output is equivalent to 1, the combination of these first, second sense amplifiers and selector is equivalent to export the sense amplifier of the view data that is equivalent to 1.

Figure 22 (A), (B) show the detailed layout configurations example of memory block MB.Figure 22 (A) is the configuration example under the situation of lateral type described later unit.Word line when MPU/LCD row address decoder RD carries out the main frame access selects control and the word line when data driving block (LCD) is exported to select control.Sense amplifier piece SAB is when data driving block is exported, and the signal that carries out the view data of reading from memory cell arrays amplifies, and exports view data to data driving block.MPU Writing/Reading circuit WR is when the main frame access, and the memory cell (accessing zone) of carrying out becoming access object in memory cell arrays writes view data or reads the control of view data.This MPU Writing/Reading circuit WR can comprise the sense amplifier that is used to read view data.MPU column address decoder CD carries out the selection control corresponding to the bit line of the memory cell that becomes access object when the main frame access.Control circuit CC carries out the control of each circuit block in the memory block MB.

Figure 22 (B) is the configuration example under the situation of longitudinal type described later unit.In Figure 22 (B), memory cell array comprises first memory cell arrays 1 and second memory cell arrays 2.And, MPU/LCD row address decoder RD is set between memory cell arrays 1 and MA2.In addition, MPU/LCD row address decoder RD carries out the selection of the word line of any among memory cell arrays 1, the MA2 when carrying out access by host computer side.In addition, to the output of the view data of data driving block the time, carry out the two the selection of word line of memory cell arrays 1, MA2.Like this, owing to can when the main frame access, only be selected to the word line of the memory cell array of access object, thereby compare, can be reduced in the signal delay in the word line or consume electric power with the method for the word line of the memory cell array of selecting both all the time.

And, be arranged on D2 (or D4) the direction side of memory cell arrays under the situation of Figure 22 (A), becoming the peripheral circuit part in MPU/LCD row address decoder RD, the control circuit CC or its distribution zone that are arranged under the situation of Figure 22 (B) between memory cell arrays 1 and the MA2, its width becomes WPC.

And, in this form of implementation,, describe as prerequisite, but also can carry out implementing as the distortion of the configuration of each sub-pixel unit with the configuration of each pixel for the configuration of driver element or sense amplifier unit.In addition, sub-pixel also is not limited to R, G, these 3 sub-pixels of B constitute, and can be that 4 sub-pixels of RGB+1 (for example white) constitute.

4.5WB and the relation of W1, W2

In this form of implementation, as shown in figure 23, can make the width W 1 on the D2 direction in outlet side I/F zone 12 become 0.13mm≤W1≤0.4mm.In addition, can make the width W B of circuit block CB1～CBN become 0.65mm≤WB≤1.2mm.In addition, can make the width W 2 in input side I/F zone 14 become 0.1mm≤W2≤0.2mm.

For example, in outlet side I/F zone 12, the number on the configuration D2 direction is one or more pad.And, shown in Fig. 6 (A), by configuration below pad output with transistor, electrostatic protection element with transistor etc., make the width W 1 in outlet side I/F zone 12 become Min..Therefore, consider pad width (for example 0.1mm) or pad pitch, become 0.13mm≤W1≤0.4mm.

On the other hand, in input side I/F zone 14, the number on the configuration D2 direction is one a pad.And, shown in Fig. 6 (A), by configuration below pad input with transistor, electrostatic protection element with transistor etc., make the width W 2 in input side I/F zone 14 become Min..Therefore, consider pad width or pad pitch, become 0.1mm≤W2≤0.2mm.And, in outlet side I/F zone 12, make the number of the pad on the D2 direction become a plurality of reasons to be, the transistorized quantity that need below pad, dispose (or size), outlet side I/F zone 12 is than input side I/F zone more than 14.

In addition, as explanation in Figure 19 (A), Figure 20 (A), be benchmark with the width on the D2 direction of data horse district motion block DB or memory block MB, determine the width W B of circuit block CB1～CBN.In addition, in order to realize elongated integrated circuit (IC) apparatus, on circuit block CB1～CBN, must form logical signal with global lines from logic circuit block, from the gray scale voltage signal or the power supply wiring of gray scale voltage generative circuit piece.And these distribution width for example become about 0.8～0.9mm altogether.Therefore, consider these, the width W B of circuit block CB1～CBN becomes 0.65mm≤WB≤1.2mm.

And even W1=0.4mm, W2=0.2mm, also owing to 0.65mm≤WB≤1.2mm, thereby WB＞W1+W2 sets up.In addition, be under the situation of minimum value at W1, WB, W2, become W1=0.13mm, WB=0.65mm, W2=0.1mm, the width of integrated circuit (IC) apparatus becomes about W=0.88mm.Therefore, W=0.88mm＜2 * WB=1.3mm sets up.In addition, be under the peaked situation at W1, WB, W2, become W1=0.4mm, WB=1.2mm, W2=0.2mm, the width of integrated circuit (IC) apparatus becomes about W=1.8mm.Therefore, W=1.8mm＜2 * WB=2.4mm sets up.That is, W＜2 * WB sets up.So,, just can realize the elongated integrated circuit (IC) apparatus shown in Fig. 2 (B) if W＜2 * WB sets up.

By at least one in usefulness transistor and electrostatic protection element are boosted in lower floor's configuration of pad as this form of implementation, can significantly dwindle the width of the W1 of integrated circuit (IC) apparatus 10.Therefore, W＜2 * WB is set up.Its result can provide more very thin integrated circuit (IC) apparatus.

5. memory block, data driving block is detailed

5.1 piece is cut apart

Suppose that display floater is that the pixel count at vertical scanning direction (data wire direction) shown in Figure 24 (A) is VPN=320, is the QVGA panel of HPN=240 at the pixel count of horizontal scan direction (scan-line direction).In addition, the figure place PDB that supposes to be equivalent to image (demonstration) data of 1 pixel is that each of R, G, B is 6, the PDB=18 position.At this moment, the figure place of the required view data of the demonstration that is equivalent to 1 frame of display floater becomes VPN * HPN * PDB=320 * 240 * 18.Therefore, the memory of integrated circuit (IC) apparatus stores at least and is equivalent to 320 * 240 * 18 view data.In addition, data driver is at each horizontal scan period (each bar data wire be scanned during), and the data-signal (with the corresponding data-signal of the view data that is equivalent to 240 * 18) that will be equivalent to the HPN=240 bar exports display floater to.

And in Figure 24 (B), data driver is split into DBN=4 data drive block DB1～DB4.In addition, memory also is split into MBN=DBN=4 memory block MB1～MB4.Therefore, each data driving block DB1～DB4 is in each horizontal scan period, and the data-signal that will be equivalent to the HPN/DBN=240/4=60 bar exports display floater to.In addition, each memory block MB1～MB4 stores and is equivalent to (VPN * HPN * PDB)/MBN=(320 * 240 * 18)/4 view data.And, in Figure 24 (B), common column address decoder CD12 in memory block MB1 and MB2, common column address decoder CD34 in memory block MB3 and MB4.

5.2.1 repeatedly read a horizontal scan period

In Figure 24 (B), each data driving block DB1～DB4 is equivalent to 60 data-signal a horizontal scan period output.Therefore, must be from memory block MB1～MB4 corresponding to DB1～DB4, read and be equivalent to 240 the corresponding view data of data-signal in each horizontal scan period.

But,, must increase the number of the memory cell (sense amplifier) that is arranged on the D2 direction so if be increased in the figure place that each horizontal scan period is read view data.Its result, the width W on the D2 direction of integrated circuit (IC) apparatus become big, very thinization that hinders integrated circuit substrate.In addition, word line WL is elongated, also causes the problem of the signal delay of WL.

So, in this form of implementation, adopt a kind of like this method, that is,, read repeatedly (RN time) from each memory block MB1～MB4 to each data driving block DB1～DB4 a horizontal scan period with the view data that is stored among each memory block MB1～MB4.

For example, in Figure 25, shown in A1, A2, it is state of activation (high level) that storage access signal MACS (word line selection signal) has only RN=2 time a horizontal scan period.Thus, view data is read RN=2 time to each data driving block from each memory block a horizontal scan period.So, be arranged on the included data-latching circuit of data driver DRa, DRb of the Figure 26 in the data driving block, latch the view data of reading according to latch signal LATa, the LATb shown in A3, the A4.And, the D/A conversion of the view data that the included D/A change-over circuit of DRa, DRb is latched, the included output circuit of DRa, DRb will export the data-signal output line to according to data-signal DATAa, the DATAb that the D/A conversion obtains shown in A5, A6.Afterwards, shown in A7, the sweep signal SCSEL that inputs to the TFT grid of each pixel of display floater becomes state of activation, and data-signal inputs in each pixel of display floater and is held.

And, in Figure 25, read view data 2 times in first horizontal scan period, first horizontal scan period identical exports data-signal DATAa, DATAb to the data-signal output line.But, also can read 2 view data and latch in first horizontal scan period, after second horizontal scan period, will export the data-signal output line to corresponding to data-signal DATAa, the DATAb of the view data that is latched.In addition, in Figure 25, show the situation of read-around number RN=2, but also can be RN 〉=3.

According to the method for Figure 25, as shown in figure 26, to read and be equivalent to 30 the corresponding view data of data-signal from each memory block, each data driver DRa, DRb output is equivalent to 30 data-signal.Thus, be equivalent to 60 data-signal from each data driving block output.Like this, in Figure 30, from each memory block, as long as read when reading 1 time with the corresponding view data of data-signal that is equivalent to 30 just passable.Therefore, compare, can reduce the memory cell on the D2 direction of Figure 26, the number of sense amplifier with the method for only reading once a horizontal scan period.Its result can reduce the width on the D2 direction of integrated circuit (IC) apparatus, can realize the super very thin elongated integrated circuit substrate shown in Fig. 2 (B).Particularly, the length of a horizontal scan period is being about 52 μ sec under the situation of QVGA.On the other hand, for example be about 40nsec between the reading duration of memory, compare much shorter with 52 μ sec.Therefore, even will be at the read-around number of a horizontal scan period from once increasing to repeatedly, the influence that display characteristic is brought be so not big yet.

In addition, Figure 24 (A) is the display floater of QVGA (320 * 240), if but will just also can be adapted to the display floater of VGA (640 * 480) at the read-around number of a horizontal scan period for example as RN=4, can increase the degree of freedom of design.

In addition, repeatedly reading of a horizontal scan period, can also can pass through in each memory block, to select second method of repeatedly identical word line to realize a horizontal scan period by in each memory block, selecting first method of many different word lines to realize a horizontal scan period by row decoder (word line selection circuit) by row decoder (word line selection circuit).Perhaps, also can realize by both combinations of first, second method.

5.3 the configuration of data driver, driver element

Figure 26 shows the configuration example of the included driver element of data driver and data driver.As shown in figure 26, data driving block comprises a plurality of data driver DRa, the DRb along D1 direction and row arrangement.In addition, each data driver DRa, DRb comprise the driver element DRC1～DRC30 of 30 of many groups (broadly being Q).

If the word line WL1a of memory block is selected and shown in the A1 of Figure 25 primary view data be read out from memory block, data driver DRa just latchs the view data that is read out according to the latch signal LATa shown in the A3.Then, the D/A of the view data that is latched conversion, and will shown in A5, export the data-signal output line to corresponding to the primary data-signal DATAa that reads view data.

On the other hand, if the word line WL1b of memory block is selected and shown in the A2 of Figure 25 secondary view data be read out from memory block, data driver DRb just latchs the view data that is read out according to the latch signal LATb shown in the A4.Then, the D/A of the view data that is latched conversion, and will shown in A6, export the data-signal output line to corresponding to secondary data-signal DATAb that reads view data.

Like this, by be equivalent to 30 the data-signal of each data driver DRa, DRb output, can export 60 the data-signal of being equivalent to altogether corresponding to 60 pixels corresponding to 30 pixels.

And as mentioned above, the number Q of the driver element DRC1～DRC30 that arranges along the D2 direction can use Q=HPN/ (DBN * IN) represent.Under the situation of Figure 26, owing to HPN=240, DBN=4, IN=2, thereby Q=240/ (4 * 2)=30.In addition, as mentioned above, in sense amplifier piece SAB, the sense amplifier number P that arranges along the D2 direction can use P=(HPN * PDB)/(MBN * RN) represent.Under the situation of Figure 26, because HPN=240, PDB=18, MBN=4, RN=2, thereby P=(240 * 18)/(4 * 2)=540.

5.4 memory cell

Figure 27 (A) shows the configuration example of the included memory cell of memory block (SRAM).This memory cell comprises transmission transistor T RA1, TRA2, load transistor TRA3, TRA4 and driving transistors TRA5, TRA6.If word line WL becomes state of activation, transmit transistor T RA1, TRA2 and be switched on, can carry out to writing of the view data of node NA1, NA2 or reading from the view data of node NA1, NA2.In addition, the view data that is written into is maintained among node NA1, the NA2 by the flip-flop circuit that is made of transistor T RA3～TRA6.And the memory cell of this form of implementation is not limited to the formation of Figure 27 (A), for example can carry out implementing as the distortion that load transistor TRA3, TRA4 use resistive element or append other transistors etc.

Figure 27 (B) (C) shows the layout example of memory cell.Figure 27 (B) is the layout example of lateral type unit, and Figure 27 (C) is the layout example of longitudinal type unit.At this, the lateral type unit is the word line WL unit longer than bit line BL, XBL in each memory cell shown in Figure 27 (B).On the other hand, the longitudinal type unit is bit line BL, the XBL unit longer than word line WL in each memory cell shown in Figure 27 (C).And, the WL of Figure 27 (C) be be formed on polysilicon layer on transmission transistor T RA1, the local word line that TRA2 is connected, but the signal delay that also can be provided for WL again prevents, the word line of the metal level of current potential stabilisation.

Memory block when Figure 28 shows as the lateral type unit shown in memory cell use Figure 27 (B), the configuration example of driver element.And Figure 28 at length shows the part corresponding to 1 pixel in driver element, the memory block.

As shown in figure 28, acceptance is equivalent to the driver element DRC of the view data of 1 pixel, comprises R usefulness, G usefulness, B data-latching circuit DLATR, DLATG, DLATB.If latch signal LAT (LATa, LATb) becomes state of activation, each data-latching circuit DLATR, DLATG, DLATB just latch view data.In addition, the driver element DRC R that is included in explanation among Figure 10 (A) with, G with, B with DACR, DACG, DACB.In addition, be included in (C) the efferent SQ of middle explanation of Figure 10 (B).

The part corresponding to 1 pixel among the sense amplifier SAB comprises R sense amplifier SAR0～SAR5, G sense amplifier SAG0～SAG5 and B sense amplifier SAB0～SAB5.And bit line BL, the XBL along the memory cell MC of D1 direction arrangement is connected on the SAR0 in the D1 of sense amplifier SAR0 direction side.In addition, be connected on the SAR1 at bit line BL, the XBL of the D1 of sense amplifier SAR1 direction side along the memory cell MC of D1 direction arrangement.For other sense amplifier and the relation of memory cell too.

If word line WL1a is selected, read view data from memory cell MC to bit line BL, XBL, connect on the WL1a of this memory cell MC and transmit transistorized grid, sense amplifier SAR0～SAR5, SAG0～SAG5, SAB0～SAB5 carry out the amplification action of signal.And DLATR latchs 6 R view data D0R～D5R from SAR0～SAR5, the D/A conversion of the view data that DACR is latched, efferent SQ outputting data signals DATAR.In addition, DLATG latchs 6 G view data D0G～D5G from SAG0～SAG5, the D/A conversion of the view data that DACG is latched, efferent SQ outputting data signals DATAG.In addition, DLATB latchs 6 B view data D0B～D5B from SAB0～SAB5, the D/A conversion of the view data that DACB is latched, efferent SQ outputting data signals DATAB.

And under the situation of the formation of Figure 28, repeatedly reading of the view data of a horizontal scan period shown in Figure 25 can realize as described below.That is,, at first select word line WL1a and first time of carrying out view data reads, shown in the A5 of Figure 25, export primary data-signal DATAa in first horizontal scan period (during the selection of first scan line).Then,, select word line WL1b and second time of carrying out view data reads, shown in the A6 of Figure 25, export secondary data-signal DATAb in the first identical horizontal scan period.In addition, after second horizontal scan period (during the selection of second scan line), at first select word line WL2a and first time of carrying out view data reads, export primary data-signal DATAa.Then,, select word line WL2b and second time of carrying out view data reads, export secondary data-signal DATAb in the second identical horizontal scan period.Like this, under the situation of using the lateral type unit,, can realize repeatedly reading of a horizontal scan period by in memory block, selecting different many word lines (WL1a, WL2a) a horizontal scan period.

Memory block when Figure 29 shows as the longitudinal type unit shown in memory cell use Figure 27 (C), the configuration example of driver element.In the longitudinal type unit, can make the width on the D2 direction shorter than lateral type unit.Therefore, can make the number of the memory cell on the D2 direction become 2 times of lateral type unit.And, in the longitudinal type unit, use array selecting signal COLa, COLb, the row that are connected the memory cell on each sense amplifier are switched.

For example, in Figure 29, if array selecting signal COLa becomes state of activation, so, in the memory cell MC of the D1 of sense amplifier SAR0～SAR5 direction side, the memory cell MC of row Ca side is selected, is connected on sense amplifier SAR0～SAR5.And the signal that is stored in the view data among these selecteed memory cell MC is exaggerated, and is output as D0R～D5R.On the other hand, if array selecting signal COLb becomes state of activation, so, in the memory cell MC of the D1 of sense amplifier SAR0～SAR5 direction side, the memory cell MC of row Cb side is selected, is connected on sense amplifier SAR0～SAR5.And the signal that is stored in the view data among these selecteed memory cell MC is exaggerated, and is output as D0R～D5R.Be connected the memory cell on other sense amplifiers view data read also identical.

And under the situation of the formation of Figure 29, repeatedly reading of the view data of a horizontal scan period shown in Figure 25 can realize as described below.That is,, at first select word line WL1, make array selecting signal COLa become state of activation, carry out the first time of view data and read, shown in the A5 of Figure 25, export primary data-signal DATAa in first horizontal scan period.Then, in the first identical horizontal scan period, select identical word line WL1 and second time of carrying out view data reads, make array selecting signal COLb become state of activation, carry out the second time of view data and read, shown in the A6 of Figure 25, export secondary data-signal DATAb.In addition, after second horizontal scan period, select word line WL2, make array selecting signal COLa become state of activation, carry out the first time of view data and read, export primary data-signal DATAa.Then,, select identical word line WL2, make array selecting signal COLb for activating, and read the second time of carrying out view data, exports secondary data-signal DATAb in the second identical horizontal scan period.Like this, under the situation of using the longitudinal type unit,, can realize repeatedly reading of a horizontal scan period by in memory block, selecting many identical word lines a horizontal scan period.

6. electronic equipment

Figure 30 (A), (B) show the example of the electronic equipment (electro-optical device) of the integrated circuit (IC) apparatus 10 that comprises this form of implementation.And electronic equipment also can comprise except the inscape the parts shown in Figure 30 (A), (B) (for example camera, operating portion or power supply etc.).In addition, the electronic equipment of present embodiment is not limited to mobile phone, also can be digital camera, PDA, electronic memo, electronic dictionary, projector, rear-projection TV or carrying type information terminal etc.

In 30 (A), (B), host apparatus 410 for example is MPU (Micro ProcessorUnit), baseband engine (baseband processor) etc.This host apparatus 410 carries out the control as the integrated circuit (IC) apparatus 10 of display driver.Or also can carry out as the processing as graphics engine such as the processing of application engine or baseband engine or compression, expansion, calibration.In addition, the image process controller (display controller) 420 of Figure 30 (B) replaces that host apparatus 410 compress, expansion, calibration etc. are as the processing of graphic machine.

Display floater 400 has many data wires (source electrode line), multi-strip scanning line (gate line) and by data wire and the specific a plurality of pixels of scan line.And,, realize display action by changing the optical characteristics of the electrooptic cell (being liquid crystal cell narrowly) in each pixel region.This display floater 400 can be made of the panel of the active matrix mode of using switch elements such as TFT, TFD.And display floater 400 also can be the panel except the active matrix mode, also can be the panel except liquid crystal panel.

Under the situation of Figure 30 (A), can use the device of internal memory as integrated circuit (IC) apparatus 10.That is, this moment, integrated circuit (IC) apparatus 10 will be written in the internal memory earlier from the view data of host apparatus 410, and read the view data that writes from internal memory, drove display floater.Under the situation of Figure 30 (B), can use the not device of internal memory as integrated circuit (IC) apparatus 10.That is, be written in the internal memory of image process controller 420 from the view data of host apparatus 410 this moment.And integrated circuit (IC) apparatus 10 drives display floater 400 under the control of image process controller 420.

The above is the preferred embodiments of the present invention only, is not limited to the present invention, and for a person skilled in the art, the present invention can have various changes and variation.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.For example, in specification or accompanying drawing, at least once the term (outlet side I/F zone, input side I/F zone etc.) of using the different term (first interface area, second interface area etc.) of broad sense more or synonym to put down in writing simultaneously also can be replaced into this different term Anywhere at specification or accompanying drawing.In addition, the formation of integrated circuit (IC) apparatus or electronic equipment, configuration, action also are not limited to the content that illustrates in this form of implementation, can carry out various deformation and implement.

Symbol description

CB1～CBN the 1st～the N circuit block

10 IC apparatus, 12 outlet side I/F zones

14 input side I/F zone, 20 memories

22 memory cell arrangements, 24 row address decoder

26 column address decoder, 28 Writing/Reading circuit

40 logic circuits, 42 control circuits

44 show constantly control circuit 46 host interface circuits

48RGB interface circuit 50 data drivers

52 data-latching circuit 54D/A change-over circuits

56 output circuits, 70 scanner drivers

72 shift registers, 73 scan address generative circuits

74 address decoders, 76 level displacement shifters

78 output circuits, 90 power circuits

92 booster circuits, 94 Circuit tunings

96VCOM generative circuit 98 control circuits

110 gray scale voltage generative circuits 112 select to use voltage generation circuit

114 gray scale voltages select circuit 116 to adjust register

Claims (12)

1. an integrated circuit (IC) apparatus is characterized in that, comprising:

Pad;

Electrostatic protection element forms rectangular zone, and is electrically connected with described pad; And

Other elements beyond the described electrostatic protection element,

Described pad is parallel with the long side direction that the orientation of described pad and described electrostatic protection element form the zone, and is disposed at the upper strata of described electrostatic protection element with part or all overlapping mode of described electrostatic protection element,

Described electrostatic protection element is disposed at described second short brink in mutual opposed first and second minor faces of described pad.

2. integrated circuit (IC) apparatus according to claim 1 is characterized in that: described pad has rectangular shape, and the orientation of described pad is the short side direction of described pad.

3. integrated circuit (IC) apparatus according to claim 1 is characterized in that:

When will be from first limit of the minor face of described integrated circuit (IC) apparatus towards the direction on opposed the 3rd limit as first direction, will be from second limit on the long limit of integrated circuit (IC) apparatus towards the direction on opposed the 4th limit during as second direction,

Integrated circuit (IC) apparatus comprises:

The first～the N circuit block, along described first direction configuration, wherein N is the integer more than or equal to 2;

First interface area, the described second direction side at described the first～the N circuit block is provided with along the 4th limit; And

Second interface area, is provided with along described second limit to side in the four directions opposite with the described second direction of described the 1st～the N circuit block,

The 1st～the N circuit block comprises at least one data driving block and the described data driving block circuit block in addition that is used for driving data lines;

When the width of the described second direction of setting described first interface area, described the first～the N circuit block, described second interface area was respectively W1, WB, W2, integrated circuit (IC) apparatus in the width W of described second direction was,

W1+WB+W2≤W＜W1+2×WB+W2。

4. integrated circuit (IC) apparatus according to claim 3 is characterized in that: the width W in the described second direction of integrated circuit (IC) apparatus is W＞2 * WB.

5. integrated circuit (IC) apparatus according to claim 3 is characterized in that:

Described first interface area is in the described second direction side of described data driving block, dispose without other circuit blocks,

Described second interface area, disposes without other circuit blocks to side in the described four directions of described data driving block.

6. integrated circuit (IC) apparatus according to claim 3 is characterized in that:

The included data driver of described data driving block comprises Q the driver element of arranging along second direction, and a described Q driver element is exported respectively and the corresponding data-signal of the view data of 1 pixel,

When setting described driver element when the width of described second direction is WD, described the first～the N circuit block at the width W B of described second direction is, Q * WD≤WB＜(Q+1) * WD.

7. integrated circuit (IC) apparatus according to claim 6 is characterized in that:

When the pixel count of the horizontal scan direction of setting display floater is HPN, the piece number of setting data drive block is DBN, be set in the horizontal scan period when the input number of times of the view data of described driver element input is IN, then the number Q of the described driver element of arranging along described second direction is, and Q=HPN/ (DBN * IN).

8. integrated circuit (IC) apparatus according to claim 3 is characterized in that:

The first～the N circuit block comprises at least one memory block of storing image data,

The included data driver of described data driving block comprises Q the driver element of arranging along second direction, and a described Q driver element is exported respectively and the corresponding data-signal of the view data of 1 pixel,

Is WD when setting described driver element at the width of described second direction, sets the included peripheral circuit part of described at least one memory block when the width of described second direction is WPC, Q * WD≤WB＜(Q+1) * WD+WPC.

9. integrated circuit (IC) apparatus according to claim 8 is characterized in that:

When the pixel count of the horizontal scan direction of setting display floater is HPN, the piece number of setting data drive block is DBN, be set in the horizontal scan period when the input number of times of the view data of described driver element input is IN, the number Q of the described driver element of arranging along described second direction is, and Q=HPN/ (DBN * IN).

10. integrated circuit (IC) apparatus according to claim 8 is characterized in that: described at least one memory block and described data driving block are along described first direction disposed adjacent.

11. integrated circuit (IC) apparatus according to claim 8 is characterized in that:

In a horizontal scan period, repeatedly read the view data of storing the described memory block to the described data driving block of adjacency from described at least one memory block.

12. an electronic equipment is characterized in that, comprising:

According to each described integrated circuit (IC) apparatus in the claim 1 to 11, and

Display floater by described integrated circuit (IC) apparatus driving.

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