CN100523850C - System plate and method for testing chip with high pressure - Google Patents
System plate and method for testing chip with high pressure Download PDFInfo
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- CN100523850C CN100523850C CNB2006101195587A CN200610119558A CN100523850C CN 100523850 C CN100523850 C CN 100523850C CN B2006101195587 A CNB2006101195587 A CN B2006101195587A CN 200610119558 A CN200610119558 A CN 200610119558A CN 100523850 C CN100523850 C CN 100523850C
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Abstract
The invention discloses a high-voltage test system board of the chip. A high-voltage channel to be detected is connected to the high-voltage test unit. A channel to be exerted the high voltage is connected to the output of the amplifier. A controllable relay positioned on the idle test channel selects the high-voltage test unit to connect to a plurality of high-voltage channels to be tested via the idle test channel. The invention also discloses a high-voltage test method comprising the following procedures. The high-voltage channel to be tested is connected to the high-voltage test unit via the controllable relay and the high-voltage test is carried out, and the channel to be exerted the high voltage is connected to the output of the amplifier via the controllable relay. Secondly, the connection between a plurality of high-voltage channels and the high-voltage test unit is switched via the controllable relay positioned on the idle test channel, and the high-voltage test unit is utilized to carry out the high-voltage test on other high-voltage channels to be tested via the high-voltage test unit. The invention can carry out the test on the plurality of high-voltage test channels in turn, promote the test development efficiency and accelerate the product debugger process.
Description
Technical field
The present invention relates to large scale integrated circuit dc parameter Hi-pot test field, especially a kind of chip high voltage testing system board, also design utilizes this chip high voltage testing system board chip to be carried out the method for Hi-pot test.
Background technology
Existing large scale integrated circuit dc parameter Hi-pot test system is formed by hardware testing system and software testing system organic assembling.Wherein hardware testing system is made of hardware such as large-scale logic tester, automatic prober platform, application specific probe card, dedicated system plates, and software testing system is made of operating system, special test program and special test vector etc.
As shown in Figure 1, the test channel 74 of the dedicated system plate of existing large test instrument is connected with amplifier by relay, and test channel 79 is connected with amplifier by relay, and test channel 81 is connected with the Hi-pot test unit by relay.When utilizing existing large test instrument to carry out the Hi-pot test of chip, existing systems plate peripheral circuit makes and can only utilize the Hi-pot test unit to test, and is to connect just and can test at system board.
And be limited in the Hi-pot test element resources of existing large test instrument, can not carry out high pressure to many arbitrarily high-pressure channels and apply and test.In Fig. 1, test channel 81 is connected with the Hi-pot test unit and therefore can carries out Hi-pot test, and test channel 79 is to be connected with test channel 74 by relay and amplifier, therefore can not directly carry out Hi-pot test.If desired it is carried out Hi-pot test, then need at first to disconnect Hi-pot test unit and test channel 81, then test channel 79 is connected with the Hi-pot test unit, could realize Hi-pot test this 79 test channel.
Under the existing large scale integrated circuit dc parameter Hi-pot test system condition, unless frequently change peripheral circuit, otherwise can't rotate test to two high-pressure channels of EEPROM, not only make troubles to test, also increased the time, reduced testing efficiency.
Summary of the invention
Technical matters to be solved by this invention provides a kind of chip high voltage testing system board, it can not need to revise under the situation of system board peripheral circuit, a plurality of high-pressure channels of test that need are carried out Hi-pot test, thereby improve testing efficiency, reduce testing cost.For this reason, the present invention also provides a kind of Hi-pot test method, and it utilizes said chip Hi-pot test system board that chip is carried out Hi-pot test, can make full use of test resource.
For solving the problems of the technologies described above, the technical scheme that chip high voltage testing system board of the present invention is adopted is, it needs tested high-pressure channel to be connected with the Hi-pot test unit by the may command relay that is arranged on the idle test channel that can be connected with the Hi-pot test unit, the passage that need apply high pressure is connected with amplifier out by the may command relay that is arranged on the idle test channel that can be connected with amplifier, and the may command relay that is arranged on the idle test channel can be selected the Hi-pot test unit is connected with a plurality of high-pressure channels of test that need by idle test channel.
The technical scheme that Hi-pot test method of the present invention is adopted is, may further comprise the steps: at first, the high-pressure channel of needs test is connected with the Hi-pot test unit by the may command relay that is arranged on the idle test channel, and the passage that need apply high pressure is connected with amplifier out by the may command relay that is arranged on the idle test channel, and utilizes the Hi-pot test unit that the high-pressure channel of needs test is carried out Hi-pot test; Secondly, switch being connected between a plurality of high-pressure channels and the Hi-pot test unit by being arranged on may command relay on the idle test channel, and utilize the Hi-pot test unit that other required testing high voltage passages are carried out Hi-pot test.
Chip high voltage testing system board of the present invention by being arranged on the may command relay on the idle test channel, making full use of idle test channel the high-pressure channel of needs test is tested.Hi-pot test method of the present invention, need the high-pressure channel of test to be connected with the Hi-pot test unit by control by the may command relay that is arranged on the idle test channel, and the passage that need apply high pressure is connected with amplifier output by the may command relay that is arranged on the idle test channel, can carry out test by turns to a plurality of Hi-pot test passages.The present invention improves test development efficient, the debug procedures of expedite product.
Description of drawings
The present invention is further detailed explanation below in conjunction with the drawings and specific embodiments:
Fig. 1 is an existing system plate peripheral circuit diagram;
Fig. 2 is a chip high voltage testing system board peripheral circuit diagram of the present invention;
Fig. 3 is an embodiment of the invention test macro synoptic diagram;
Fig. 4 is a Hi-pot test method flow synoptic diagram of the present invention.
Embodiment
As shown in Figure 3, the test macro that utilizes the present invention to test comprises by the data line software testing system and the hardware testing system of line data transmission of going forward side by side that be connected.Wherein, software systems are made of operating system, special test program and special test vector etc.Hardware system is made of hardware such as logic tester, probe station, probe, system boards.When carrying out the chip high voltage test, chip under test is fixed on the probe station, and logic tester is connected with measuring head by data line, and measuring head is connected with system board, and software testing system control hardware test macro is tested chip.
As shown in Figure 2, the test channel 74 of chip high voltage testing system board is connected with amplifier by relay, test channel 79 is connected with test channel 74 by relay and amplifier, test channel 81 is connected with the Hi-pot test unit by relay, idle test channel 80 is connected with the may command relay, this may command relay one end is connected with the Hi-pot test unit, the other end is connected with test channel 79, idle test channel 82 is connected with the may command relay, this may command relay one end is connected with amplifier out, and the other end is connected with test channel 81.
As shown in Figure 4, when utilizing chip high voltage testing system board of the present invention to carry out chip testing, at first, the high-pressure channel of needs test is connected with the Hi-pot test unit by the may command relay that is arranged on the idle test channel, and the passage that need apply high pressure is connected with amplifier output by the may command relay that is arranged on the idle test channel, and utilizes the Hi-pot test unit that the high-pressure channel of needs test is carried out Hi-pot test; Secondly, switch being connected between a plurality of high-pressure channels and the Hi-pot test unit by being arranged on may command relay on the idle test channel, and utilize the Hi-pot test unit that other required testing high voltage passages are carried out Hi-pot test.
In conjunction with Fig. 2 and Fig. 4, test channel 79 is connected with the Hi-pot test unit by the may command relay that is arranged on the idle channel 80, and the test channel 81 that need apply high pressure is connected with amplifier out by the may command relay that is arranged on the idle test channel 82, and can utilize the Hi-pot test unit that test channel 79 is carried out Hi-pot test this moment.By switching the connection between may command relay change high-pressure channel and the Hi-pot test unit, test channel 81 is connected with the Hi-pot test unit then, test channel 81 is carried out Hi-pot test.
Chip high voltage testing system board of the present invention by being arranged on the may command relay on the idle test channel, making full use of idle test channel a plurality of high-pressure channels of needs tests is carried out switch test.Hi-pot test method of the present invention needs the high-pressure channel of test to be connected with the Hi-pot test unit with may command relay on being arranged on idle test channel by control, can carry out the test of rotating to a plurality of Hi-pot test passages.The present invention can reduce the test duration, improves test development efficient.
Claims (3)
1, a kind of chip high voltage testing system board, it is characterized in that, it needs tested high-pressure channel to be connected with the Hi-pot test unit by the may command relay that is arranged on the idle test channel that can be connected with the Hi-pot test unit, the passage that need apply high pressure is connected with amplifier out by the may command relay that is arranged on the idle test channel that can be connected with amplifier, and the may command relay that is arranged on the idle test channel is selected the Hi-pot test unit is connected with a plurality of high-pressure channels of test that need by idle test channel.
2, chip high voltage testing system board as claimed in claim 1 is characterized in that, described idle test channel is a plurality of.
3, a kind of Hi-pot test method of utilizing the described chip high voltage testing system board of claim 1, it is characterized in that, may further comprise the steps: at first, the high-pressure channel of needs test is connected with the Hi-pot test unit by the may command relay that is arranged on the idle test channel, and the passage that need apply high pressure is connected with amplifier output by the may command relay that is arranged on the idle test channel, and utilizes the Hi-pot test unit that the high-pressure channel of needs test is carried out Hi-pot test; Secondly, switch being connected between a plurality of high-pressure channels and the Hi-pot test unit by being arranged on may command relay on the idle test channel, and utilize the Hi-pot test unit that other required testing high voltage passages are carried out Hi-pot test.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101195587A CN100523850C (en) | 2006-12-13 | 2006-12-13 | System plate and method for testing chip with high pressure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101195587A CN100523850C (en) | 2006-12-13 | 2006-12-13 | System plate and method for testing chip with high pressure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101201384A CN101201384A (en) | 2008-06-18 |
| CN100523850C true CN100523850C (en) | 2009-08-05 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB2006101195587A Active CN100523850C (en) | 2006-12-13 | 2006-12-13 | System plate and method for testing chip with high pressure |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110376504B (en) * | 2019-06-27 | 2022-06-17 | 瑞芯微电子股份有限公司 | IC high-voltage damage simulation system and method |
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| CN101201384A (en) | 2008-06-18 |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20140108 |
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Free format text: CORRECT: ADDRESS; FROM: 201206 PUDONG NEW AREA, SHANGHAI TO: 201203 PUDONG NEW AREA, SHANGHAI |
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Effective date of registration: 20140108 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Patentee before: Shanghai Huahong NEC Electronics Co., Ltd. |