CN100521163C - Method for etching silicon groove on insulator - Google Patents

Abstract

The invention relates to a producing method for an integrated circuit, in particular to a silicon trench etching process used in CMOS/SOI (silicon-on-insulator) materials. The silicon trench etching process used in insulators comprises a buried oxide layer2 which is positioned on substrate silicon 1 and is provided with top silicon 3 and is characterized in that the first step is to carry out traditional thermal oxidation on the top silicon 3 to form a SiO2 layer 4 and to deposit SiN on the SiO2 layer 4 to form a SiN layer 5; the second step is to coat common optical resist 6 on the SiN layer 5 to form a silicon trench etching window; the third step is to carry out plasma reaction etching on the silicon trench etching window to expose the top silicon 3; the fourth step is to carry out isotropic silicon trench etching on the exposed top silicon 3 with mixed acids; the fifth step is to continue to carry out plasma reaction etching on the top silicon 3 which is eroded by the mixed acid to form silicon trenches; the sixth step is to carry out traditional LOCOS oxidation on the silicon trenches. The invention can relieve the condition of over steep appearance of silicon trenches in the processing of complete drying silicon trench etching +LOCOS oxidative separation.

Description

Be used for the silicon groove etching method on the insulator

Technical field

The present invention relates to the production method of integrated circuit, specifically a kind of silicon groove etching process that is used for CMOS/SOI (silicon-on-insulator) material, the present invention can solve the full dielectric isolation problem in the compatible SOI CMOS of the high-low pressure technology.

Background technology

In power integrated circuit, the charge carrier that is injected into substrate by the device on the same substrate can be collected by contiguous large area power device, may cause that opening by mistake of power device open, this also is the extensive integrated principal element of power device that the restriction knot is isolated.And along with the reaching its maturity of SOI technology, its comparatively ideal isolation structure that can provide just is being applied in the design of high tension apparatus increasingly extensively.

In the SOI technology, device can (refer to the selective oxidation technology by silicon groove etching and LOCOS oxidation, promptly shelter the combination layer that etches silicon nitride/rebasing oxide layer with anisotropic dry etching with resist, make the technology that active device can be not oxidized in the subsequent fields oxidation technology) realize the full dielectric isolation of silicon island, thus realize the integrated of power device well.

Dry method silicon groove etching+LOCOS oxidation isolation technology flow process is shown in Fig. 1-1～1-4 fully:

(1) the 1st step, the SOI material formed SiO through thermal oxidation earlier as Figure 1-1 ₂ Layer 4 adopts LPCVD deposit (low-pressure chemical vapor phase deposition) to form SiN layer 5 then;

(2) the 2nd steps carried out photoetching and form the silicon groove etching window, shown in Fig. 1-2;

(3) the 3rd steps were carried out dry etching to silicon groove window as Figure 1-3, eroded SiN layer 5, SiO ₂Layer 4 and part silicon fiml 3 (etching depth of silicon fiml is about 0.7～1.2 μ m) form the silicon groove;

(4) the 4th steps were carried out the LOCOS oxidation to the silicon groove shown in Fig. 1-4, the SiO that this process forms ₂Link to each other with the oxygen buried layer 2 full dielectric isolation of formation SOI silicon groove of layer 7.

At top silicon surface is the SOI material of 1～1.5 μ m, there is distinct disadvantage in said method: for fear of long LOCOS oxidizing process, the inevitable etching ground of silicon groove shown in Fig. 1-3 very dark (0.7～1.2 μ m), this will cause through after the LOCOS oxidation shown in Fig. 1-4, the perpendicular steps in silicon groove district and non-silicon groove district is not only very big but also pattern is very steep, this can increase the deposit of follow-up polycrystalline and metal and the difficulty of etching, and whole flow technology is had a negative impact.

Goal of the invention

The objective of the invention is to seek a kind of silicon groove etching method that is used on the insulator, to slow down in complete dry method silicon groove etching+LOCOS oxidation isolation technology the too steep situation of silicon flute profile looks;

Reduce the LOCOS oxidizing process in silicon groove etching+LOCOS oxidation isolation technology simultaneously;

And develop a kind of full dielectric isolation scheme that is applicable to the SOI material of 1～1.5um top silicon surface, this scheme goes for not possessing the processing line of CMP or silicon groove pad device, replaces STI technology to realize full dielectric isolation.

Process program provided by the present invention is seen Fig. 2-1～2-6, replaces conventional complete dry method silicon groove etching with silicon groove wet etching+dry method silicon groove etching.

Concrete technological process of the present invention is as described below, and details are seen accompanying drawing 2-1～2-6:

Be used for the silicon groove etching method on the insulator, comprise the oxygen buried layer 2 that is positioned on the substrate silicon 1, top layer silicon 3 is arranged on oxygen buried layer 2, it is characterized in that:

Step 1, elder generation carry out traditional thermal oxidation on top layer silicon 3, form SiO ₂Layer 4 is again at SiO ₂Layer 4 deposit SiN form SiN layer 5; Shown in Fig. 2-1;

Step 2, on SiN layer 5, be coated with photoresist commonly used 6, and reserve a zone that does not have resist coating 6, traditional photoetching is carried out in this zone, form the silicon groove etching window, shown in Fig. 2-2;

Step 3, again the silicon groove etching window is carried out the plasma reaction etching, erode SiN layer 5 and SiO ₂Layer 4 exposes top layer silicon 3, and the main component of described plasma gas is SF ₆(90sccm), He (50sccm); Shown in Fig. 2-3; Sccm is meant at standard atmosphere and depresses, the gas volume that per minute flows through, and volume unit is a cubic centimetre;

Step 4, with mixed acid the top layer silicon of exposing 3 is carried out isotropic silicon groove corrosion, corrosion depth 0.3～0.6 μ m; Described mixed acid comprises 5.59 parts HNO ₃, 0.134 part HF, 2.27 parts H ₂O, unit are parts by volume; Shown in Fig. 2-5;

Step 5, above-mentioned top layer silicon 3 of corroding through mixed acid is proceeded the plasma reaction etching, form the silicon groove, etching depth 0.3～0.6 μ m, the main gas componant of plasma comprises Cl ₂(70sccm), He (150sccm); Shown in Fig. 2-6;

Step 6, the silicon groove is carried out traditional LOCOS oxidation, the oxide layer 7 of formation links to each other with oxygen buried layer 2 and forms the full dielectric isolation of SOI silicon groove.

At top silicon surface thickness is in the full dielectric isolation technology of SOI material of 1～1.5 μ m, if there is not condition to do the STI isolation technology, can select silicon groove etching+LOCOS oxidation isolation technology.If silicon groove etching adopts dry method fully, may form very steep silicon groove step (as Fig. 1-4) after the LOCOS oxidation so, subsequent technique is had a negative impact.And introduce the mixed acid wet corrosion technique, and can effectively slow down silicon groove step, this is because the composition of mixed acid mainly is HNO ₃+ HF+H ₂O, it is isotropic to the corrosion of silicon, vertically can produce horizontal corrosion in the corrosion silicon, thereby can effectively slow down silicon groove step.

Advantage of the present invention is: 1, the present invention can slow down in complete dry method silicon groove etching+LOCOS oxidation isolation technology the too steep situation of silicon flute profile looks; 2, the present invention goes for not possessing the processing line of CMP or silicon groove pad device, replaces STI technology to realize the full dielectric isolation of SOI; 3, technology of the present invention is simple, has very strong operability.

Description of drawings

Fig. 1-1,1-2,1-3,1-4 are complete dry etching silicon concentrated flow journey schematic diagram, wherein:

Fig. 1-the 1st, masking layer SiN/SiO ₂The deposit schematic diagram.

Fig. 1-2 is a channel separating zone photoetching schematic diagram.

Fig. 1-the 3rd, groove dry etching schematic diagram.

Fig. 1-the 4th, schematic diagram is isolated in the LOCOS oxidation.

Fig. 2-1,2-2,2-3,2-4,2-5,2-6 are etch silicon groove schematic diagram of the present invention, wherein:

Fig. 2-the 1st, masking layer SiN/SiO ₂The deposit schematic diagram.

Fig. 2-the 2nd, channel separating zone photoetching schematic diagram.

Fig. 2-the 3rd, dry etching fall masking layer SiN and SiO ₂Schematic diagram.

Fig. 2-the 4th, mixed acid wet etching groove schematic diagram.

Fig. 2-the 5th, dry etching groove schematic diagram.

Fig. 2-the 6th, channel separating zone LOCOS oxidation schematic diagram.

Embodiment

Institute's reference numbers zone explanation among Fig. 1-1,1-2,1-3, the 1-4: 1, the substrate silicon in the SOI material, thickness is about the SEMI standard thickness; 2, the oxygen buried layer in the SOI material, thickness are 1～2 μ m; 3, the top silicon surface of SOI material, thickness are 1～1.5 μ m; 4, the SiO that forms in the technology ₂Layer, thickness is about

5, the SiN layer that forms in the technology, thickness is about

6, photoresist, thickness is about

7, the SiO2 layer of LOCOS oxidation formation, thickness is about

Adopt the present invention can slow down in complete dry method silicon groove etching+LOCOS oxidation isolation technology the too steep situation of silicon flute profile looks.As being the SOI material of 1.5 μ m at top silicon surface thickness, adopt the silicon groove of complete dry etching 1.1 μ m, its section angle is more than 80 degree; And adopt technology of the present invention, and reach 0.5um (lateral encroaching 0.5um) with mixed acid corrosion silicon groove earlier, use dry etching silicon groove 0.6um then, its section angle is about 65 degree, helps the deposit and the corrosion of polycrystalline and metal.

Claims (1)

1, be used for silicon groove etching method on the insulator, comprise the oxygen buried layer (2) that is positioned on the substrate silicon (1), top layer silicon (3) is arranged on oxygen buried layer (2), it is characterized in that:

Step 1, elder generation carry out thermal oxidation on top layer silicon (3), form SiO ₂Layer (4) is again at SiO ₂Layer (4) deposit SiN forms SiN layer (5);

Step 2, go up resist coating (6), carry out photoetching again, form the silicon groove etching window at SiN layer (5);

Step 3, again the silicon groove etching window is carried out the plasma reaction etching, erode SiN layer (5) and SiO ₂Layer (4) exposes top layer silicon (3), and the main component of described plasma gas is the SF of 90sccm ₆, 50sccm He;

Step 4, with mixed acid the top layer silicon of exposing (3) is carried out isotropic silicon groove corrosion, corrosion depth 0.3～0.6 μ m; Described mixed acid comprises 5.59 parts HNO ₃, 0.134 part HF, 2.27 parts H ₂O; Unit is a parts by volume;

Step 5, the above-mentioned top layer silicon (3) of corroding through mixed acid is proceeded the plasma reaction etching, form the silicon groove, etching depth 0.3～0.6 μ m, the main gas componant of plasma comprises the Cl of 70sccm ₂, 150sccm He;

Step 6, the silicon groove is carried out the LOCOS oxidation, the oxide layer of formation (7) links to each other with oxygen buried layer (2) and forms the full dielectric isolation of SOI silicon groove.

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