CN100511666C - Circuit board and circuit structure - Google Patents
Circuit board and circuit structure Download PDFInfo
- Publication number
- CN100511666C CN100511666C CNB2007101398961A CN200710139896A CN100511666C CN 100511666 C CN100511666 C CN 100511666C CN B2007101398961 A CNB2007101398961 A CN B2007101398961A CN 200710139896 A CN200710139896 A CN 200710139896A CN 100511666 C CN100511666 C CN 100511666C
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- China
- Prior art keywords
- opening
- chip
- line layer
- wiring board
- substrate
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Abstract
This invention relates to a CB carrying a chip icluding a base board, a circuit layer and a protection layer, in which, the circuit layer is matched on the base board, the protection layer set on the base board and the circuit layer includes a chip area, a first open-end and a second open-end, the chip is matched in the chip area, the two open-ends are located outside of two adjacent sides of the chip area separately and expose part of the circuit layer to decide the relative position between the chip and the base board.
Description
Technical field
The invention relates to a kind of wiring board and circuit structure, and particularly have specifically labelled wiring board and a circuit structure relevant for a kind of.
Background technology
Continue in the progressive modern life in science and technology, electronic product is being played the part of indispensable role in people's life.Along with people day by day increase the demand of electronic product, the producer of these electronic products also increases for the demand of the chip packing-body in the electronic product thereupon.Be with, the qualification rate and the production efficiency that how to increase chip packing-body just become one of present urgent problem.
With regard to the chip packing-body processing procedure that brilliant chip is electrically connected at wiring board with routing joint (wire bonding) processing procedure; the producer usually can be at the relative position of the preceding first measuring chip of carrying out line connection process with respect to wiring board, exactly lead is electrically connected between chip and the wiring board.
Fig. 1 comes the schematic diagram that chip is positioned for the telltale mark on the wiring board of utilizing of known techniques.Please refer to Fig. 1, a wiring board 100 at first is provided.Wiring board 100 has a plurality of contacts 110 and a location mark 120, and wherein these contacts 110 are to be positioned on the surperficial 100a of wiring board 100 with telltale mark 120, and these contacts 110 are electrically insulated with telltale mark 120.
One chip 200 is provided afterwards.Chip 200 has an active surface 200a and a back side (not illustrating), and wherein the back side is relative with active surface 200a.Chip 200 also comprises a plurality of weld pads 210 in addition, and wherein these weld pads 210 are positioned on the active surface 200a.Then chip 200 is disposed on the wiring board 100, the back side of its chips 200 (not illustrating) is towards the surperficial 100a of wiring board 100.
In these weld pads 210, select a benchmark weld pad 210 ' then.Then utilize a measurement equipment to come the relative position of measuring basis weld pad 210 ' with respect to telltale mark 120, its step as described later.At first with measurement equipment alignment fiducials weld pad 210 '.Be starting point with benchmark weld pad 210 ' afterwards, move along directions X and Y direction in regular turn, to find out between telltale mark 120 and the benchmark weld pad 210 ' distance respectively in directions X and Y direction.Thus, known techniques just can measure the relative position of benchmark weld pad 210 ' with respect to telltale mark 120 via above-mentioned step.That is to say that known techniques can measure the relative position of chip with respect to wiring board via above-mentioned step.
It should be noted that known techniques need reserve enough areas to hold telltale mark 120 usually when designed lines plate 100 on surperficial 100a.Yet the design of this telltale mark 120, the wiring space that is positioned at other circuit on its surperficial 100a that tends to reduce wiring board 100.
In addition, come in the process of measuring basis weld pad 210 ' with respect to the relative position of telltale mark 120 at above-mentioned utilization measurement equipment, measuring equipment need move along directions X, moves the measurement flow process that just can finish once along the Y direction more afterwards.Yet be noted that known techniques can't just measure the relative position of benchmark weld pad 210 ' with respect to telltale mark 120 exactly single time measurement flow process usually.That is to say that known techniques need just can measure the relative position of benchmark weld pad 210 ' with respect to telltale mark 120 through after the measurement flow process repeatedly usually, is that the production efficiency with the chip packing-body processing procedure just is not easy to promote.
Summary of the invention
Purpose of the present invention is exactly that a kind of circuit structure that has specifically labelled wiring board and have this wiring board is being provided, and wherein this telltale mark can not have influence on the wiring space of other circuit that is positioned at PCB surface.
The present invention proposes a kind of wiring board, and it is suitable for carrying a chip.Wiring board comprises a substrate, a line layer and a protective layer.Line layer is disposed on the substrate.Protective layer is disposed on substrate and the line layer.Protective layer has a chip region, one first opening and one second opening, and its chips is suitable for being disposed at chip region.First opening and second opening lay respectively at the outside of the adjacent dual-side of chip region, and expose the part of line layer.The part of the line layer that is exposed out is in order to determine the relative position between chip and the substrate.
According to the described wiring board of one embodiment of the invention, above-mentioned line layer comprises many first traces.First opening exposes in these first traces the part of one of them at least.
According to the described wiring board of one embodiment of the invention, above-mentioned line layer comprises many second traces.Second opening exposes in these second traces the part of one of them at least.
According to the described wiring board of one embodiment of the invention, the first above-mentioned opening is a rectangle.
According to the described wiring board of one embodiment of the invention, the second above-mentioned opening is a rectangle.
The present invention proposes a kind of circuit structure, and it comprises a wiring board and a chip.Wiring board comprises a substrate, a line layer and a protective layer.Line layer is disposed on the substrate.Protective layer is disposed on substrate and the line layer.Protective layer has one first opening and one second opening, and wherein first opening and second opening expose the part of line layer respectively.Chip configuration is on substrate, and a back side of chip is towards substrate.First opening and second opening lay respectively at the outside of two adjacent sides of chip.The part of the line layer that is exposed out is in order to determine the relative position between chip and the substrate.
According to the described circuit structure of one embodiment of the invention, above-mentioned line layer comprises many first traces.First opening exposes in these first traces the part of one of them at least.
According to the described circuit structure of one embodiment of the invention, above-mentioned line layer comprises many second traces.Second opening exposes in these second traces the part of one of them at least.
According to the described circuit structure of one embodiment of the invention, the first above-mentioned opening is a rectangle.
According to the described circuit structure of one embodiment of the invention, the second above-mentioned opening is a rectangle.
According to the described circuit structure of one embodiment of the invention, dispose a benchmark weld pad on the active surface of above-mentioned chip.Chip has a first side adjacent one another are and a second side.First opening is positioned on the bearing of trend of first side, and second opening is positioned on the bearing of trend of second side.
Because first opening of the present invention and second opening expose the part of line layer respectively, so the present invention can utilize the part of these line layers that are exposed out as telltale mark.Be with compared to known techniques, telltale mark of the present invention is not easy to influence the wiring space of other circuit that is positioned at PCB surface.
Description of drawings
For above and other objects of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below:
Fig. 1 comes the schematic diagram that chip is positioned for the telltale mark on the wiring board of utilizing of known techniques.
Fig. 2 is the schematic diagram of the circuit structure of one embodiment of the invention.
The primary clustering symbol description
100: wiring board
100a: surface
110: contact
120: telltale mark
200: chip
200a: active surface
210: weld pad
210 ': the benchmark weld pad
300: wiring board
310: substrate
320: line layer
322a: first inner contact
322b: second inner contact
324a: first trace
324b: second trace
326a: the first outer contact
326b: the second outer contact
330: protective layer
332a: first opening
332b: second opening
334: chip region
400: chip
402: the first side
404: the second side
410: weld pad
410 ': the benchmark weld pad
500: circuit structure
Embodiment
Fig. 2 is the schematic diagram of the circuit structure of one embodiment of the invention.Please refer to Fig. 2, circuit structure 500 comprises a wiring board 300 and a chip 400.Wiring board 300 comprises a substrate 310, a line layer 320 and a protective layer 330.Line layer 320 is disposed on the substrate 310.In the present embodiment, line layer 320 comprises a plurality of first inner contact 322a, a plurality of second inner contact 322b, many first trace 324a, many second trace 324b, a plurality of first outer contact 326a and a plurality of second outer contact 326b.The first trace 324a is electrically connected between the first inner contact 322a and the first outer contact 326a, and the second trace 324b is electrically connected between the second inner contact 322b and the second outer contact 326b.
Based on above-mentioned circuit structure 500, present embodiment can be with the part of the line layer 320 that exposed by the first opening 332a and the second opening 332b, i.e. the part that is exposed out of the first trace 324a and the second trace 324b is as telltale mark.And utilize these telltale marks to measure the relative position of wiring board 300 with respect to chip 400.
Below will introduce and measure the step of wiring board 300 with respect to the relative position of chip 400.At first in a plurality of weld pads 410 of the active surface of chip 400 a selected weld pad 410 as benchmark weld pad 410 '.Then via a measurement equipment, and with benchmark weld pad 410 ' is starting point, and measuring basis weld pad 410 ' is to the distance of the line layer 320 that is exposed by the first opening 332a.Be starting point with benchmark weld pad 410 ' more afterwards, measuring basis weld pad 410 ' is to the distance of the line layer 320 that is exposed by the second opening 332b.Thus, present embodiment just can measure the relative position of wiring board 300 with respect to chip 400.In case after having determined the relative position of wiring board 300 with respect to chip 400, present embodiment just can be electrically connected at the first inner contact 322a and the second inner contact 322b with these weld pads 410 via line connection process.
More preferably, present embodiment more can suitably be adjusted the relative position between the first opening 332a and the chip 400, and adjust relative position between the second opening 332b and the chip 400, survey the efficient of wiring board 300 with lifting capacity with respect to the relative position of chip 400.
For example, present embodiment can be adjusted the position of the first opening 332a and the second opening 332b, so that on the bearing of trend of the first side 402 that the first opening 332a and the second opening 332b lay respectively at chip 400 and second side 404.Thus, present embodiment can be an initial point with benchmark weld pad 410 ' just, and along the first side 402 bearing of trend amount of movement measurement equipment, come the distance of measuring basis weld pad 410 ' and the part of the line layer 320 that is exposed by the first opening 332a.Be initial point with benchmark weld pad 410 ' afterwards, and along the second side 404 bearing of trend amount of movement measurement equipment, come the distance of measuring basis weld pad 410 ' and the part of the line layer 320 that is exposed by the second opening 332b.
In sum, because first opening of the present invention and second opening expose the part of line layer respectively, so the present invention can utilize the part of these line layers that are exposed out as telltale mark.Be with compared to known techniques, telltale mark of the present invention is not easy to influence the wiring space of other circuit that is positioned at PCB surface.
In addition, because the present invention can make first opening and second opening lay respectively on the bearing of trend of the first side of chip and second side, so compared to known techniques, the present invention can measure the relative position of wiring board with respect to chip more quickly.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limiting the present invention, anyly has the knack of this skill person, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking the claim person of defining.
Claims (11)
1. a wiring board is suitable for carrying a chip, it is characterized in that, this wiring board comprises:
One substrate;
One line layer is disposed on this substrate; And
One protective layer; be disposed on this substrate and this line layer; this protective layer has a chip region, one first opening and one second opening; this chip is suitable for being disposed at this chip region; this first opening and this second opening lay respectively at this chip region adjacent dual-side the outside and expose the part of this line layer, the part that is exposed out of this line layer is in order to determine the relative position between this chip and this substrate.
2. wiring board as claimed in claim 1 is characterized in that, this line layer comprises many first traces, and this first opening exposes in those first traces the part of one of them at least.
3. wiring board as claimed in claim 1 is characterized in that, this line layer comprises many second traces, and this second opening exposes in those second traces the part of one of them at least.
4. wiring board as claimed in claim 1 is characterized in that, this first opening is a rectangle.
5. wiring board as claimed in claim 1 is characterized in that, this second opening is a rectangle.
6. a circuit structure is characterized in that, comprising:
One wiring board comprises:
One substrate;
One line layer is disposed on this substrate; And
One protective layer is disposed on this substrate and this line layer, and this protective layer has one first opening and one second opening, and wherein this first opening and this second opening expose the part of this line layer respectively; And
One chip, be disposed on this substrate, and a back side of this chip is towards this substrate, and this first opening and this second opening lay respectively at the outside of two adjacent sides of this chip, and the part that is exposed out of this line layer is in order to determine the relative position between this chip and this substrate.
7. circuit structure as claimed in claim 6 is characterized in that, this line layer comprises many first traces, and this first opening exposes in those first traces the part of one of them at least.
8. circuit structure as claimed in claim 6 is characterized in that, this line layer comprises many second traces, and this second opening exposes in those second traces the part of one of them at least.
9. circuit structure as claimed in claim 6 is characterized in that, this first opening is a rectangle.
10. circuit structure as claimed in claim 6 is characterized in that, this second opening is a rectangle.
11. circuit structure as claimed in claim 6, it is characterized in that, dispose a benchmark weld pad on one active surface of this chip, and this chip has a first side adjacent one another are and a second side, this first opening is positioned on the bearing of trend of this first side, and this second opening is positioned on the bearing of trend of this second side.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007101398961A CN100511666C (en) | 2007-07-26 | 2007-07-26 | Circuit board and circuit structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007101398961A CN100511666C (en) | 2007-07-26 | 2007-07-26 | Circuit board and circuit structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101090105A CN101090105A (en) | 2007-12-19 |
| CN100511666C true CN100511666C (en) | 2009-07-08 |
Family
ID=38943361
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2007101398961A Expired - Fee Related CN100511666C (en) | 2007-07-26 | 2007-07-26 | Circuit board and circuit structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100511666C (en) |
-
2007
- 2007-07-26 CN CNB2007101398961A patent/CN100511666C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN101090105A (en) | 2007-12-19 |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090708 Termination date: 20170726 |
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| CF01 | Termination of patent right due to non-payment of annual fee |