CN100472772C - Circuit board and circuit structure - Google Patents
Circuit board and circuit structure Download PDFInfo
- Publication number
- CN100472772C CN100472772C CN 200710103942 CN200710103942A CN100472772C CN 100472772 C CN100472772 C CN 100472772C CN 200710103942 CN200710103942 CN 200710103942 CN 200710103942 A CN200710103942 A CN 200710103942A CN 100472772 C CN100472772 C CN 100472772C
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- Prior art keywords
- chip
- line
- opening
- layer
- substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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Abstract
The present invention discloses a circuit board, suitable for carrying chips. The circuit board includes a substrate, a cicuit layer and a welding mask layer. The cicuit layer is mounted in the substrate. The cicuit layer includes cutting line drawings, which are defined in a cutting region. The welding mask layer is mounted in the substrate and the cicuit layer. The welding mask layer has a chip area, a first opening and a second opening. The chip area is located in the cutting region. The chip is suitable for disposing in the chip area, wherein the chips are superposition with the chip area. The first opening and the second opening are respectively located on the lateral edge of the adjacent two sides in the chip area, and exposes a part of the cutting line drawings. The exposed part of the cutting line drawings are used to measure the relative position between chip and substrate.
Description
Technical field
The invention relates to a kind of wiring board and circuit structure, and particularly have specifically labelled wiring board and a circuit structure relevant for a kind of.
Background technology
Continue in the progressive modern life in science and technology, electronic product is being played the part of indispensable role in people's life.Along with people day by day increase the demand of electronic product, the producer of these electronic products for the demand of the chip packing-body in the electronic product also with increase.Be with, the rate of finished products and the production efficiency that how to increase chip packing-body just become one of problem of needing solution at present badly.
With regard to the Chip Packaging body technology that chip is electrically connected at wiring board with wire-bonded (wire bonding) technology; the producer usually can be before carrying out wire bonding technique first measured chip with respect to the relative position of wiring board, exactly lead is electrically connected between chip and the wiring board.
Fig. 1 comes the schematic diagram that chip is positioned for the telltale mark on the wiring board of utilizing of known technology.Please refer to Fig. 1, wiring board 100 at first is provided.Wiring board 100 has a plurality of contacts 110 and telltale mark 120, and wherein these contacts 110 are to be positioned on the surperficial 100a of wiring board 100 with telltale mark 120, and these contacts 110 are electrically insulated with telltale mark 120.
Chip 200 is provided afterwards.Chip 200 has active surperficial 200a and the back side (not illustrating), and wherein the back side is relative with active surperficial 200a.Chip 200 also comprises a plurality of weld pads 210 in addition, and wherein these weld pads 210 are positioned on the active surperficial 200a.Then chip 200 is disposed on the wiring board 100, the back side of its chips 200 (not illustrating) is towards the surperficial 100a of wiring board 100.
Selected reference weld pad 210 ' in these weld pads 210 then.Then utilize measuring equipment to come the relative position of measuring basis weld pad 210 ' with respect to telltale mark 120, its step as described later.At first with measuring equipment alignment fiducials weld pad 210 '.Be starting point with benchmark weld pad 210 ' afterwards, move along directions X and Y direction in regular turn, to find out between telltale mark 120 and the benchmark weld pad 210 ' distance respectively in directions X and Y direction.Thus, known technology just can be measured the relative position of benchmark weld pad 210 ' with respect to telltale mark 120 via above-mentioned step.That is to say that known technology can be measured the relative position of chip with respect to wiring board via above-mentioned step.
It should be noted that known technology need reserve enough areas to hold telltale mark 120 usually when designed lines plate 100 on surperficial 100a.Yet the design of this telltale mark 120, the wiring space that is positioned at the All other routes on its surperficial 100a that tends to reduce wiring board 100.
In addition, come in the process of measuring basis weld pad 210 ' with respect to the relative position of telltale mark 120 at the above-mentioned measuring equipment that utilizes, measurement mechanism need move along directions X, moves the measurement flow process that just can finish once along the Y direction more afterwards.Yet be noted that known technology can't just be measured the relative position of benchmark weld pad 210 ' with respect to telltale mark 120 exactly single time measurement flow process usually.That is to say that known technology need just can be measured the relative position of benchmark weld pad 210 ' with respect to telltale mark 120 through after the measurement flow process repeatedly usually, is that the production efficiency with the Chip Packaging body technology just is not easy to promote.
Summary of the invention
Purpose of the present invention is exactly that a kind of circuit structure that has specifically labelled wiring board and have this wiring board is being provided, and wherein this telltale mark can not have influence on the wiring space of the All other routes that are positioned at PCB surface.
The present invention proposes a kind of wiring board, and it is suitable for carries chips.Wiring board comprises substrate, line layer and welding cover layer.Line layer is disposed on the substrate.Line layer comprises the line of cut pattern, and this line of cut pattern defines cutting zone.Welding cover layer is disposed on substrate and the line layer.Welding cover layer has chip region, first opening and second opening.Chip region is positioned at cutting zone.Chip is suitable for being disposed at chip region, and its chips overlaps with chip region.First opening and second opening lay respectively at the outside of the adjacent dual-side of chip region, and expose the part of line of cut pattern.The part of the line of cut pattern that is exposed out is in order to determine the relative position between chip and the substrate.
According to the described wiring board of the preferred embodiments of the present invention, also comprise protective layer, it is disposed on the part of the line of cut pattern that is exposed out, and wherein this protective layer for example is a gold.
The present invention proposes a kind of circuit structure, and it comprises wiring board and chip.Wiring board comprises substrate, line layer and welding cover layer.Line layer is disposed on the substrate.Line layer comprises the line of cut pattern, and the line of cut pattern defines cutting zone.Welding cover layer is disposed on substrate and the line layer, and wherein welding cover layer has first opening and second opening.Chip configuration is on welding cover layer, and the back side of chip is towards substrate.Chip is positioned at cutting zone, and wherein first opening and second opening lay respectively at the outside of two adjacent sides of chip, and exposes the part of line of cut pattern.The part of the line of cut pattern that is exposed out is in order to determine the relative position between chip and the substrate.
According to the described circuit structure of the preferred embodiments of the present invention, also comprise protective layer, it is disposed on the part of the line of cut pattern that is exposed out, and wherein the material of this protective layer for example is a gold.
According to the described circuit structure of the preferred embodiments of the present invention, its chips has first side adjacent one another are and second side.First opening is positioned on the bearing of trend of first side, and second opening is positioned on the bearing of trend of second side.
Because the present invention utilizes the part of existing line of cut pattern to be used as telltale mark, therefore telltale mark of the present invention can not influence the wiring space of the All other routes that are positioned at PCB surface.
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
Description of drawings
Fig. 1 comes the schematic diagram that chip is positioned for the telltale mark on the wiring board of utilizing of known technology.
Fig. 2 is the schematic top plan view of the wiring board of one embodiment of the invention.
Fig. 3 is the generalized section along hatching AA ' of Fig. 2.
Fig. 4 is the schematic top plan view of the wiring board of another embodiment of the present invention.
Fig. 5 is the schematic diagram of the circuit structure of one embodiment of the invention.
Description of reference numerals
100: wiring board 100a: surface
110: contact 120: telltale mark
200: chip 200a: active surface
210: weld pad 210 ': the benchmark weld pad
300: wiring board 300 ': wiring board
310: substrate 320: line layer
322: circuit pattern 322a: interior connection pad
322a ': protective layer 322b: outer connection pad
322b ': protective layer 322c: trace
324 ': protective layer 324: the line of cut pattern
330: 332: the first openings of welding cover layer
336: the three openings of 334: the second openings
Opening 400 in 338: the four: chip
402: first side 404: second side
410: weld pad 410 ': the benchmark weld pad
500: circuit structure direction: X
Direction: Y D: chip region
C: cutting zone
Embodiment
Fig. 2 is the schematic top plan view of the wiring board of one embodiment of the invention.Fig. 3 is the generalized section along hatching AA ' of Fig. 2.Please jointly with reference to Fig. 2 and Fig. 3, wiring board 300 comprises substrate 310, line layer 320 and welding cover layer 330.In the present embodiment, substrate 310 can be a simple layer core dielectric layer.In addition, substrate 310 also can be by the multilayer line layer and multilayer dielectric layer is staggered in regular turn is formed by stacking, and wherein has one deck line layer between two adjacent dielectric layers.
Preferably; the part of interior connection pad 322a, outer connection pad 322b and the line of cut pattern 324 that exposed by first opening 332 and second opening 334 more can comprise protective layer 322a ', protective layer 322b ' and protective layer 324 ' respectively, and the part of the line of cut pattern 324 that is exposed with connection pad 322a, outer connection pad 322b in avoiding and by first opening 332 and second opening 334 is subjected to the erosion of external environment.The material of protective layer 322a ', protective layer 322b ' and protective layer 324 ' for example is a gold.
In addition, the wiring board 300 of present embodiment more can a plurality of cutting area C of tool except can having single cutting area C.Fig. 4 looks schematic diagram on the wiring board of another embodiment of the present invention.Wiring board 300 ' is similar to wiring board 300, and wherein both difference is that the line of cut pattern 324 of wiring board 300 ' defines a plurality of cutting area C.Preferably, all have opening between the arbitrary two adjacent cutting area C, and these cutting areas C is the arrangement mode that is matrix form.
Based on above-mentioned wiring board 300, the present invention can be with chip configuration on wiring board 300, to form circuit structure.Afterwards with the part of the line of cut pattern 324 that exposed by first opening 332 and second opening 334 as telltale mark, come the relative position of measurement circuitry plate 300 with respect to chip.Below will be described in detail circuit structure.
Fig. 5 is the schematic diagram of the circuit structure of one embodiment of the invention.Circuit structure 500 comprises wiring board 300 and chip 400.Chip 400 is disposed on the welding cover layer 330, and the back side of chip 400 is towards wiring board 300.Chip 400 is configured in the chip region D, and chip 400 overlaps with chip region D.Thus, first opening 332 and second opening 334 will lay respectively at the outside of two adjacent sides of chip 400.
Based on above-mentioned circuit structure 500, present embodiment can be with the part of the line of cut pattern 324 that exposed by first opening 332 and second opening 334 as telltale mark, and utilizes these telltale marks to come the relative position of measurement circuitry plate 300 with respect to chip 400.At first in a plurality of weld pads 410 of chip 400, select a weld pad 410 as benchmark weld pad 410 '.Then via measuring equipment, and with benchmark weld pad 410 ' is starting point, and measuring basis weld pad 410 is to the distance of the part of the line of cut pattern 324 that is exposed by first opening 332.Be starting point with benchmark weld pad 410 ' more afterwards, measuring basis weld pad 410 is to the distance of the part of the line of cut pattern 324 that is exposed by second opening 334.Thus, present embodiment just can be measured the relative position of wiring board 300 with respect to chip 400.In case after having determined the relative position of wiring board 300 with respect to chip 400, connection pad 322a in present embodiment just can be electrically connected at weld pad 410 via wire bonding technique.
Preferably, present embodiment more can suitably be adjusted the relative position between the chip 400 and first opening 332, and the relative position between the adjustment chip 400 and second opening 334, to promote the efficient of measurement circuitry plate 300 with respect to the relative position of chip 400.For example, present embodiment can be adjusted the position of first opening 332 and second opening 334, so that on the bearing of trend of the first side 402 that first opening 332 and second opening 334 lay respectively at chip 400 and second side 404.Thus, present embodiment can be an initial point with benchmark weld pad 410 ' just, and along the first side 402 bearing of trend mobile measuring equipment, come the distance of measuring basis weld pad 410 ' and the part of the line of cut pattern 324 that is exposed by first opening 332.Be initial point with benchmark weld pad 410 ' afterwards, and along the second side 404 bearing of trend mobile measuring equipment, come the distance of measuring basis weld pad 410 ' and the part of the line of cut pattern 324 that is exposed by second opening 334.
In sum, because the present invention utilizes the part of existing line of cut pattern to be used as telltale mark, the therefore telltale mark of the present invention wiring space that can not reduce the circuit pattern that is positioned at PCB surface.
In addition, because the present invention can make first opening and second opening lay respectively on the bearing of trend of the first side of chip and second side, so compared to known technology, the present invention can measure the relative position of wiring board with respect to chip more quickly.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; any those skilled in the art; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking appended the claim person of defining.
Claims (7)
1. a wiring board is suitable for carries chips, and this wiring board comprises:
Substrate;
Line layer is disposed on this substrate, and this line layer comprises the line of cut pattern, and this line of cut pattern defines cutting zone; And
Welding cover layer, be disposed on this substrate and this line layer, this welding cover layer has chip region, first opening and second opening, this chip region is positioned at this cutting zone, this chip is suitable for being disposed at this chip region and overlaps with this chip region, this first opening and this second opening lay respectively at the outside of the adjacent dual-side of this chip region, and expose the part of this line of cut pattern, and the part of this line of cut pattern that is exposed out is in order to determine the relative position between this chip and this substrate.
2. wiring board as claimed in claim 1 also comprises protective layer, is disposed on the part of this line of cut pattern that is exposed out.
3. wiring board as claimed in claim 1, wherein the material of this protective layer is a gold.
4. circuit structure comprises:
Wiring board comprises:
Substrate;
Line layer is disposed on this substrate, and this line layer comprises the line of cut pattern, and this line of cut pattern defines cutting zone;
Welding cover layer is disposed on this substrate and this line layer, and this welding cover layer has first opening and second opening; And
Chip, be disposed on this welding cover layer, and the back side of this chip is towards this substrate, this chip is positioned at this cutting zone, this first opening and this second opening lay respectively at the outside of two adjacent sides of this chip, and expose the part of this line of cut pattern, the part of this line of cut pattern that is exposed out is in order to determine the relative position between this chip and this substrate.
5. circuit structure as claimed in claim 4 also comprises protective layer, is disposed on the part of this line of cut pattern that is exposed out.
6. circuit structure as claimed in claim 5, wherein the material of this protective layer is a gold.
7. circuit structure as claimed in claim 4, wherein this chip has first side adjacent one another are and second side, and this first opening is positioned on the bearing of trend of this first side, and this second opening is positioned on the bearing of trend of this second side.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200710103942 CN100472772C (en) | 2007-05-15 | 2007-05-15 | Circuit board and circuit structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200710103942 CN100472772C (en) | 2007-05-15 | 2007-05-15 | Circuit board and circuit structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101055863A CN101055863A (en) | 2007-10-17 |
| CN100472772C true CN100472772C (en) | 2009-03-25 |
Family
ID=38795598
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200710103942 Expired - Fee Related CN100472772C (en) | 2007-05-15 | 2007-05-15 | Circuit board and circuit structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100472772C (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102065643B (en) * | 2009-11-17 | 2012-10-17 | 富葵精密组件(深圳)有限公司 | Method for making circuit board |
| KR20190014993A (en) * | 2017-08-04 | 2019-02-13 | 에스케이하이닉스 주식회사 | Semiconductor package including indicating pattern |
-
2007
- 2007-05-15 CN CN 200710103942 patent/CN100472772C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN101055863A (en) | 2007-10-17 |
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|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090325 Termination date: 20170515 |
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| CF01 | Termination of patent right due to non-payment of annual fee |