CN100511664C - Chip encapsulation structure - Google Patents
Chip encapsulation structure Download PDFInfo
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- CN100511664C CN100511664C CNB2006100902932A CN200610090293A CN100511664C CN 100511664 C CN100511664 C CN 100511664C CN B2006100902932 A CNB2006100902932 A CN B2006100902932A CN 200610090293 A CN200610090293 A CN 200610090293A CN 100511664 C CN100511664 C CN 100511664C
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49112—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting a common bonding area on the semiconductor or solid-state body to different bonding areas outside the body, e.g. diverging wires
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
The invention discloses a chip encapsulating structure, which comprises a carrier, a chip, a plurality of the first bond wires, a plurality of the second bond wires and an encapsulating colloid, wherein the carrier has a plurality of the first joints and at least one second joint, and the chip has at least one first pad and at least one second pad. Besides, the first bond wires are electrically connected with the first pads and the first joins, while the second bond wires are electrically connected with the second pads and the second joints, wherein the first pad is electrically connected with at least two first joints via at least two first bond wires, while the second pad is electrically connected with one second joint via one second bond wire. Besides, the encapsulating colloid is equipped on the carrier to wrap the chip, a plurality of the first bond wires and a plurality of the second bond wires.
Description
Technical field
The present invention relates to a kind of chip-packaging structure (Chip package structure), the chip-packaging structure of particularly a kind of lead-in wire bonding (Wire bonding).
Background technology
In recent years, along with making rapid progress and the rise of semiconductor industry of electronic technology, make electronic product more humane, with better function constantly weed out the old and bring forth the new, and design towards light, thin, short, little trend.In semiconductor industry, (Integrated Circuits, production IC) mainly is divided into three phases to integrated circuit: the encapsulation (package) of the design of integrated circuit, the making of integrated circuit and integrated circuit etc.In the encapsulation of integrated circuit, bare chip is made via wafer (wafer) earlier, circuit design, step such as light shield manufacture and cutting crystal wafer and finishing, and each cuts formed bare chip by wafer, electrically connect via weld pad on the bare chip (bonding pad) and encapsulation base material (substrate), with packing colloid (encapsulant) bare chip is coated again, its purpose is to prevent that bare chip is subjected to extraneous humidity effect and assorted dust pollution, and the media that electrically connects between bare chip and the external circuit is provided, to constitute a Chip Packaging (Chip Package) structure.
Please also refer to Figure 1A and Figure 1B, Figure 1A is the schematic diagram of existing a kind of chip-packaging structure, and Figure 1B is the vertical view of the chip-packaging structure of Figure 1A.Chip-packaging structure 100a comprises a carrier 110, a chip 120, many bonding wires 130 and a packing colloid 140, its chips 120 is arranged on the surface of carrier 110, and a plurality of weld pads 122 on the chip 120 are electrically connected to a plurality of contacts 112 on the carrier 110 by bonding wire 130 in the mode of lead-in wire bonding respectively.In addition; packing colloid 140 also is arranged on the surface of carrier 110; and packing colloid 140 covers a plurality of contacts 112, the chip 120 of carrier 110 and many bonding wires 130 that connect contact 112 and weld pad 122; in order to preventing that chip 120 is subjected to ectocine (as moisture, assorted dirt etc.), and can protect bonding wire 130 to avoid being subjected to damage of external force.In addition, have many leads 102 at carrier 110, wherein lead 102 is electrically connected between contact 112a and contact 112b.Yet, make a mistake during when lead 102 fractures or at configuration, will cause the electric connection between contact 112a and contact 112b to disappear, promptly contact 112b can't obtain the signal that chip 120 is exported from contact 112a again.Therefore, load bearing seat 110 will thereby lose original effect.
Please then refer to Fig. 2, it is the vertical view of existing another kind of chip-packaging structure.By Figure 1B and Fig. 2 as can be known, chip-packaging structure 100b and above-mentioned chip-packaging structure 100a are similar, and its main difference is: the equipping position of a plurality of weld pads 122 on a plurality of contacts 112 on the carrier 110 and the chip 120 different (for example do not set the contact 112b among the chip-packaging structure 100a and set the contact 112c of another location).In this chip-packaging structure 100b,, must electrically connect contact 112a and contact 112c by a lead 104 because answer must asking of configuration.Yet contact 112a and contact 112c are equipped on the carrier 110 respectively and correspond to the both sides of chip 120, and promptly lead 104 is than lead 102 difficult higher layout circuits.In other words, fracture is more easily arranged lead 104 or situation about making a mistake when configuration takes place, and make load bearing seat 110 to use.Therefore, how when the configuration of wire fracture or lead makes a mistake, make that still to possess electrical connection between contact be an important topic.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of chip-packaging structure, when the configuration of its wire fracture in load bearing seat inside or lead makes a mistake, still possesses effect originally.
For solving the problems of the technologies described above, the present invention proposes a kind of chip-packaging structure, it comprises a carrier, a chip, many first bonding wires, many second bonding wires and a packing colloid, wherein carrier has a plurality of first contacts and at least one second contact, and chip has at least one first weld pad and at least one second weld pad.In addition, first bonding wire electrically connects first weld pad and first contact, and second bonding wire electrically connects second weld pad and second contact, wherein first weld pad electrically connects by at least two first bonding wires and two first contacts at least, electrically connect by lead between these at least two first contacts, and second weld pad electrically connects by one second bonding wire and one second contact.In addition, packing colloid then is to be arranged on the carrier, with coating chip, many first bonding wires and many second bonding wires.
Described according to one embodiment of the invention, carrier for example is a circuit base plate, and these first contacts and these second contacts for example are a plurality of connection gaskets.
Described according to one embodiment of the invention, carrier for example is a lead frame, and these first contacts and these second contacts for example are a plurality of pins.
Described according to one embodiment of the invention, these first bonding wires for example comprise a figure spike projection and a bonding wire body, and wherein the bonding wire body for example is connected on the figure spike projection.In addition, the figure spike projection in first bonding wire for example is to be stacked in each other on first weld pad, and the material of bonding wire body and figure spike projection for example is a gold.
The present invention also proposes a kind of chip-packaging structure, and it comprises many bonding wires and above-mentioned carrier, chip and packing colloid.Bonding wire electrically connects the contact of carrier and the weld pad of chip, and wherein at least one weld pad electrically connects with at least two contacts by at least two bonding wires, electrically connects by lead between these at least two contacts.
In sum, in chip-packaging structure of the present invention, be electrically connected to a few weld pad and at least two contacts by at least two bonding wires, electrically connect by lead between these at least two contacts, make when the configuration of wire fracture in the load bearing seat inside or lead makes a mistake, can make still have electric connection between weld pad and a plurality of contact by bonding wire, so chip-packaging structure still has effect originally.
After adopting structure of the present invention and technology, because in chip-packaging structure of the present invention, can electrically connect the different contact of many bonding wires to the load bearing seat on the weld pad of chip, wherein each bonding wire is to be connected with weld pad with its figure spike projection.Than prior art, the present invention has following advantage:
1. when the configuration of wire fracture that connects two contacts in the load bearing seat or lead makes a mistake, the bonding wire connected mode in the chip-packaging structure of the present invention can make the relation that still has electric connection between two contacts.
2. in load bearing seat, during difficult higher configuration, the electric connection between two contacts is oversimplified when the lead between two contacts on the load bearing seat by the bonding wire connected mode in the chip-packaging structure of the present invention.
3. in chip-packaging structure of the present invention, the figure spike projection of each bar bonding wire is stacked on the weld pad each other so that wire bonder can successfully be avoided chip or the bonding wire finished of routing when routing.
Description of drawings
Figure 1A is the schematic diagram of existing a kind of chip-packaging structure.
Figure 1B is the vertical view of the chip-packaging structure of Figure 1A.
Fig. 2 is the vertical view of existing another kind of chip-packaging structure.
Fig. 3 A is the schematic diagram of the chip-packaging structure of first embodiment of the invention.
Fig. 3 B is the vertical view of the chip-packaging structure of Fig. 3 A.
Fig. 4 is the vertical view of the chip-packaging structure of second embodiment of the invention.
Fig. 5 is the schematic diagram of the chip-packaging structure of third embodiment of the invention.
Wherein, description of reference numerals is as follows:
100a, 100b, 300a, 300b, 500: chip-packaging structure
102,104,302,304: lead
110,310,510: carrier
112,112a, 112b, 112c, 512: contact
120,320,520: chip
122,522: weld pad
130,530: bonding wire
140,350: packing colloid
312,312a, 312b, 312c: first contact
314: the second contacts
322: the first weld pads
324: the second weld pads
330,330a, 330b, 330c, 330d: first bonding wire
332: the bonding wire body
334: figure spike projection
340: the second bonding wires
Embodiment
Please also refer to Fig. 3 A and Fig. 3 B, Fig. 3 A is the schematic diagram of the chip-packaging structure of first embodiment of the invention, and Fig. 3 B is the vertical view of the chip-packaging structure of Fig. 3 A.As seen from the figure; chip-packaging structure 300a comprises a carrier 310; one chip 320; many first bonding wires 330 (for example being 330a and 330b); many second bonding wires 340 and a packing colloid 350; its chips 320 for example is to be arranged on the carrier 310; and packing colloid 350 also is arranged on the carrier 310; packing colloid 350 is in order to coating chip 320; many first bonding wires 330 and many second bonding wires 340; to prevent that chip 320 is subjected to ectocine, 350 whiles of packing colloid can protect first bonding wire 330 and second bonding wire 340 to avoid being subjected to damage of external force.
In addition, the carrier 310 of present embodiment has a plurality of first contacts 312 (for example being the first contact 312a and the first contact 312b) and one or more second contact 314, and chip 320 has one or more first weld pads 322 and one or more second weld pad 324.In addition, first bonding wire 330 is in order to electrically connecting first weld pad 322 and first contact 312, and second bonding wire 340 is in order to electrically connect second weld pad 324 and second contact 314.In the present embodiment, have many leads 302 in the carrier 210, wherein lead 302 is electrically connected at the first contact 312a and the first contact 312b, and have the first bonding wire 330a on first weld pad 322 simultaneously and 330b is electrically connected at the first contact 312a and the first contact 312b respectively, promptly first weld pad 322 electrically connects with two or more first contacts 312 by two or many first bonding wires 330 respectively.324 of second weld pads are to electrically connect by one second bonding wire 340 and one second contact 314.
Therefore, by above learning, when the configuration of 302 fractures of the lead between the electric connection first contact 312a and the first contact 312b or lead 302 makes a mistake, still can be respectively and the electric connection between the first contact 312a and the first contact 312b by the first bonding wire 330a and 330b, making wins continues to possess the relation of electric connection between the contact 312a and the first contact 312b.In addition, carrier 310 of the present invention also can be a circuit base plate, and a plurality of first contacts 312 on the carrier 310 then can be a plurality of connection gaskets with a plurality of second contacts 314.
In sum, for understanding the connection relationship of 322 of the first above-mentioned bonding wire 330 and first weld pads, so will be in hereinafter elaborating.Please refer to Fig. 3 A, routing mode of the present invention for example is to form a figure spike projection 334 earlier on first weld pad 322, then utilize wire bonder with a bonding wire body 332 routings on first contact 312, the then wire bonder segment distance that upwards stretches, and then turn to backguy to the figure spike projection 334 that is pre-formed on first weld pad 322, wherein bonding wire body 332 for example is a gold with the material of figure spike projection 334.Thus, when the wire bonder desire repeats routings in 312 of first weld pad 322 and first contacts with first bonding wire 330, the figure spike projection 334 of each bar first bonding wire 330 will be stacked on first weld pad 322 each other.Above-mentioned routing mode will make wire bonder when routing, and the routing function is successfully avoided other bonding wire or chip 320 of finishing of routing.
Please then refer to Fig. 4, it is the vertical view of the chip-packaging structure of second embodiment of the invention.Please also refer to Fig. 3 B and Fig. 4, present embodiment chip-packaging structure 300b and above-mentioned chip-packaging structure 300a are similar, and its main difference is the equipping position of a plurality of weld pads on a plurality of contacts and the chip 320 on the carrier 310 different (for example chip-packaging structure 300b does not set the first contact 312b of chip-packaging structure 300a and is equipped with the first contact 312c of another location).In chip-packaging structure 300b, for example be to cooperate must asking of configuration and electrically connect the first contact 312a and the first contact 312c by a lead 304.The first contact 312a and the first contact 312c are equipped on the carrier 310 respectively and correspond to the both sides of chip 320, i.e. the lead 302 difficult higher configurations of lead 304 in the chip-packaging structure 300a.In the present embodiment, first weld pad 322 can electrically connect first contact 312c and the 312a respectively by the first bonding wire 330c and the first bonding wire 330d.In other words, as the lead between the first contact 312c and the first contact 312a 304 fracture or or the configuration of lead 304 when making a mistake, still can make to win to continue to possess the relation of electric connection between the contact 312c and the first contact 312a by the first bonding wire 330c and the first bonding wire 330d.
Above-mentioned chip- packaging structure 300a and 300b electrically connect first contact 312 and first weld pad 322 by first bonding wire 330, and electrically connect second contact 314 and second weld pad 324 by second bonding wire 340.It should be noted that in the chip-packaging structure of other kind, can electrically connect contact on the carrier and the weld pad on the chip by a kind of bonding wire.Fig. 5 is the schematic diagram of the chip-packaging structure of third embodiment of the invention.Please also refer to Fig. 3 and Fig. 5, the chip-packaging structure 300a of the chip-packaging structure 500 and first embodiment is similar, precisely because main difference is: the chip-packaging structure 500 of present embodiment only electrically connects weld pad 522 on contact 512 and the chip 520 on the carrier 510 by a kind of bonding wire 530.Therefore, chip-packaging structure 500 has simpler chip package process.
The above only is the present invention's preferred embodiment wherein, is not to be used for limiting practical range of the present invention; Be that all equalizations of doing according to claim of the present invention change and modification, be all claim of the present invention and contain.
Claims (10)
1. a chip-packaging structure is characterized in that, this chip-packaging structure comprises: a carrier has a plurality of first contacts and at least one second contact;
One chip has at least one first weld pad and at least one second weld pad;
Many first bonding wires, it electrically connects this first weld pad and this first contact, and wherein this first weld pad electrically connects by at least two first bonding wires and two first contacts at least, electrically connects by lead between these at least two first contacts;
Many second bonding wires, it electrically connects this second weld pad and this second contact, and wherein this second weld pad electrically connects by one second bonding wire and one second contact; And
One packing colloid, it is arranged on this carrier, to coat this chip, described first bonding wire and described second bonding wire.
2. chip-packaging structure as claimed in claim 1 is characterized in that, this carrier is a circuit base plate, and described first contact and described second contact are a plurality of connection gaskets (connecting pad).
3. chip-packaging structure as claimed in claim 1 is characterized in that, this carrier is a lead frame, and described first contact and described second contact are a plurality of pins (lead).
4. chip-packaging structure as claimed in claim 1 is characterized in that, described each first bonding wire comprises:
One figure spike projection; And
One bonding wire body is connected on this figure spike projection.
5. chip-packaging structure as claimed in claim 4 is characterized in that, the described figure spike projection in described first bonding wire is stacked on this first weld pad each other.
6. chip-packaging structure as claimed in claim 4 is characterized in that, the material of this figure spike projection comprises gold.
7. chip-packaging structure as claimed in claim 4 is characterized in that the material of this bonding wire body comprises gold.
8. a chip-packaging structure is characterized in that, this chip-packaging structure comprises:
One carrier has a plurality of contacts;
One chip has a plurality of weld pads;
Many bonding wires, it electrically connects described weld pad and described contact, and wherein at least one weld pad electrically connects with at least two contacts by at least two bonding wires, electrically connects by lead between these at least two contacts; And
One packing colloid, it is arranged on this carrier, to coat this chip and described bonding wire.
9. chip-packaging structure as claimed in claim 8 is characterized in that, this carrier is a circuit base plate, and described contact is a plurality of connection gaskets (connecting pad).
10. chip-packaging structure as claimed in claim 8 is characterized in that, this carrier is a lead frame, and described contact is a plurality of pins (lead).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100902932A CN100511664C (en) | 2006-07-11 | 2006-07-11 | Chip encapsulation structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100902932A CN100511664C (en) | 2006-07-11 | 2006-07-11 | Chip encapsulation structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101106118A CN101106118A (en) | 2008-01-16 |
| CN100511664C true CN100511664C (en) | 2009-07-08 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006100902932A Active CN100511664C (en) | 2006-07-11 | 2006-07-11 | Chip encapsulation structure |
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| CN (1) | CN100511664C (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103904207A (en) * | 2014-04-04 | 2014-07-02 | 利亚德光电股份有限公司 | Wafer circuit |
| CN115312393A (en) * | 2022-07-12 | 2022-11-08 | 天芯互联科技有限公司 | Packaging method and package |
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2006
- 2006-07-11 CN CNB2006100902932A patent/CN100511664C/en active Active
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| Publication number | Publication date |
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| CN101106118A (en) | 2008-01-16 |
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