CN100505250C - Semiconductor packaging device - Google Patents

Semiconductor packaging device Download PDF

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Publication number
CN100505250C
CN100505250C CNB2004100424147A CN200410042414A CN100505250C CN 100505250 C CN100505250 C CN 100505250C CN B2004100424147 A CNB2004100424147 A CN B2004100424147A CN 200410042414 A CN200410042414 A CN 200410042414A CN 100505250 C CN100505250 C CN 100505250C
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China
Prior art keywords
chip
semiconductor encapsulation
encapsulation device
fulcrum ball
supporting body
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Expired - Fee Related
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CNB2004100424147A
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Chinese (zh)
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CN1700465A (en
Inventor
孙国洋
杨家铭
吕宏源
蔡纬瑾
林益正
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HUATAI ELECTRONICS CO Ltd
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HUATAI ELECTRONICS CO Ltd
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Priority to CNB2004100424147A priority Critical patent/CN100505250C/en
Priority to KR1020050039741A priority patent/KR100709695B1/en
Priority to JP2005142388A priority patent/JP2005333132A/en
Publication of CN1700465A publication Critical patent/CN1700465A/en
Application granted granted Critical
Publication of CN100505250C publication Critical patent/CN100505250C/en
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    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Semiconductor Memories (AREA)

Abstract

This invention relates to semi-conductor sealing device, which comprises one baseboard, one first chip, one non-conductive glue, one second chip and multiple supportive sphere, wherein, the first chip has relative upper and down surfaces fixed on the baseboard; the non-conductive glue is set on the top surface of the first chip; the second chip has relative top and down surfaces, wherein, the said down surface is fixed on the top surface of the first chip through non-conductive glue with adherent area between the non-conductive glue and the second chip is larger than the down surface area; the multiple supportive sphere located on the non-conductive glue to support the second chip.

Description

Semiconductor encapsulation device
Technical field
The present invention relates to a kind of packaging system, be particularly related to a kind of semiconductor encapsulation device, dispose fulcrum ball in the non-conductive adhesive between two stack chips, to define the required space of bonding wire, and make non-conductive adhesive and upper strata chip chamber stick together area greater than 90% of the following table area of upper strata chip, concentrate with the structural stress of minimizing after sealing is handled, and then avoid yields that chip splits (die crack) and increase encapsulates.
Background technology
Along with the increase of microminiaturization and high running speed requirement, multi-chip module packaging system (Multi-Chip Module Package; MCM Package) more and more attractive at many electronic installations.This multicore chip package can minimize the volume of whole system, and have higher memory capacity with two or more chip portfolios in single packaging system.For example, the two DRAM storage chips with 8M memory capacity are made up in single packaging system and obtain a packaging system with 16M memory capacity.Moreover this multicore chip package has the higher speed of service, can reduce the length of chip chamber connection line and reduces signal delay and access time.In addition, with the chip of various difference in functionalitys, as chip portfolios such as storage chip, logic chip or microprocessors in single packaging system, to have complete operating function.
At present, two chip stacks in single packaging system, are mainly contained following known packaging system.At first, in the first known packaging system 2, this packaging system 2 comprises a substrate 10, lower floor's storage chip 20, one illusory chip (dummy die) 30 and one upper strata storage chip 40.With reference to figure 1, this lower floor's storage chip 20 is fixed on this substrate 10 by a viscose 22, and the both sides of the edge of the upper surface 28 of this lower floor's storage chip 20 are provided with a plurality of aluminium connection pads 24, are electrically connected at a plurality of connection pads 12 of this substrate 10 by these a plurality of first bonding wire 26.With reference to figure 2, this illusory chip 30 is fixed on this lower floor's storage chip 20 by a viscose 32, and defines the required space of first bonding wire 26, according to appointment the above height H of 5 mils (mils).With reference to figure 3, this upper strata storage chip 40 is fixed on this illusory chip 30 by a viscose 42, and the upper surface 48 of this upper strata storage chip 40 is provided with a plurality of aluminium connection pads 44, a plurality of aluminium connection pads 44 are electrically connected at these a plurality of connection pads 12 of this substrate 10 by a plurality of second bonding wires 46, and two storage chips, 20,40 storehouses like this are on this substrate 10.Yet, the higher and encapsulation of the cost of this packaging system to manufacture process time longer.Moreover the coefficient of expansion of illusory chip and this viscose does not match, and therefore after sealing was handled, the structural stress of the combination interface of illusory chip and viscose increased, and then produces the yields that chip splits (die crack) and reduces encapsulation.The yields of this encapsulation generally is about between 30% and 40%.
Moreover the second known packaging system 50 is similar to this first known packaging system 2 substantially.In the second known packaging system 50, packaging system 50 comprises a substrate 60, lower floor's storage chip 70 and a upper strata storage chip 90.With reference to figure 4,74 of a plurality of aluminium connection pads are configured on the same side edge of upper surface 78 of this lower floor's storage chip 70.With reference to figure 5, this lower floor's storage chip 70 is fixed on this substrate 60 by a viscose 72, and the aluminium connection pad 74 of this lower floor's storage chip 70, and it is electrically connected at a plurality of connection pads 62 of this substrate 10 by a plurality of first bonding wires 76.Then, this upper strata storage chip 90 is fixed on this lower floor's storage chip 70 by a viscose 92, and with the step-wise manner storehouse on this lower floor's storage chip 70.At last, the upper surface 98 of this upper strata storage chip 90 is provided with a plurality of aluminium connection pads 94, and it is electrically connected at these a plurality of connection pads 62 of this substrate 60 by a plurality of second bonding wires 96, so with two storage chips, 70,90 storehouses on this substrate 60.Yet, this chip palpus process particular design, and different with general chip, so this chip is obtained the cost that is difficult for and increases chip.Moreover, if another newly-increased chip by storehouse on this upper strata chip 90, size that then should newly-increased chip can be reduced, therefore preferably can only storehouse two chips in this packaging structure, so will limit its product function.
In addition, No. the 442876th, Taiwan patent gazette Announcement Number, title discloses a kind of semiconductor encapsulation device for " multichip package structure ", this semiconductor encapsulation device mainly comprise a carries chips device, plural conductive projection, a plurality of bonding wires, a plurality of storage chip (as, a upper strata storage chip and lower floor's storage chip), an and glue-line.This lower floor's storage chip is configured on this carries chips device.This plural conductive projection is configured on this lower floor's storage chip.This upper strata storage chip is configured on this lower floor's storage chip by this glue-line, and each conductive projection has a column protuberance, in order to support this upper strata storage chip.Yet this glue-line is that non-conductive viscose and column protuberance are that electric conducting material is manufactured, and this stack architecture will cause glue-line to lose the purpose of insulation.Moreover its column protuberance may injure the surface of upper strata storage chip.
In addition, No. the 510573rd, Taiwan patent gazette Announcement Number, title discloses a kind of semiconductor encapsulation device for " semiconductor package of multi-chip stack ", and it comprises an adhesive body, a plurality of chip, a device in order to carries chips, a plurality of plain conductor and at least one glass fiber-reinforced resin bed.This chip is sealed in the adhesive body, and each chip has a upper surface and a lower surface, and has a plurality of weld pads that are formed at upper surface.Should be in order to the device of carries chips, as substrate or lead frame, and this carries chips device is cemented for chip stack.This plain conductor is sealed in the adhesive body, and its weld pad that electrically connects chip is to the device that is somebody's turn to do in order to carries chips.These glass fiber-reinforced resin series of strata are between two chips, in order to the chip of cemented mutual storehouse.Yet this glass fiber-reinforced resin bed is that soft materials is made, and therefore this glass fiber-reinforced resin bed can't define the required space of bonding wire fully, the height that all 5 mils according to appointment (mils) are above.
In addition, american documentation literature US2003/0160311A1 discloses a kind of semiconductor package body, comprise top integrated circuit lead and bottom integrated circuit lead, the lower surface of top integrated circuit lead is connected by the upper surface of binding material with the bottom integrated circuit lead, binding material comprises that a plurality of wherein particles of being blended in are to keep the predetermined space between top integrated circuit lead and the bottom integrated circuit lead, to avoid harness damage, particle can be Any shape, but misaligned, tight.
Therefore, just having to provide a kind of semiconductor encapsulation device, to solve aforesaid problem.
Summary of the invention
The purpose of this invention is to provide a kind of semiconductor encapsulation device, it comprises a plurality of fulcrum balls and is disposed in the non-conductive adhesive, and supports a chip, in order to defining the required space of bonding wire, large scale fulcrum ball wherein have neat with arrange closely.
Technical scheme of the present invention is as follows:
Semiconductor encapsulation device provided by the invention, it comprises a substrate, one first chip, a non-conductive adhesive, one second chip and a plurality of fulcrum ball; This first chip has relative upper surface and lower surface, and this lower surface is fixed on this substrate; This non-conductive adhesive is configured on the upper surface of this first chip; This second chip has relative upper surface and lower surface, wherein said lower surface is fixed on the upper surface of described first chip by non-conductive adhesive, and sticks together area greater than 90% of the lower surface area of described second chip between described non-conductive adhesive and described second chip; Described a plurality of fulcrum ball is configured in the described non-conductive adhesive, and comprise the large scale fulcrum ball and the small size fulcrum ball of two kinds of different-diameters, wherein this large scale fulcrum ball is in order to supporting this second chip, and the diameter of this small size fulcrum ball is less than the distance between this first and second chip.
Compare with known packaging system, the large scale fulcrum ball in the semiconductor encapsulation device of the present invention has neat and arranges closely; The area that sticks together between the non-conductive adhesive and second chip increases, therefore manufacture follow-up that the thermal stress of sticking together in the interface between the non-conductive adhesive and second chip is scattered in whole sticking together on the area in the process, can reduce concentrating of thermmohardening processing back thermal stress, and then avoid yields that chip splits (die crack) and increase encapsulates.
Description of drawings
Fig. 1 to Fig. 3 is the generalized section of the first known packaging system;
Fig. 4 to Fig. 5 is the generalized section of the second known packaging system;
Fig. 6 to Figure 11 is the generalized section of semiconductor packaging structure of the present invention;
The figure number explanation:
Packaging structure 2 substrates 10 connection pads 12
Lower floor's storage chip 20 viscoses 22 aluminium connection pads 24
First bonding wire, 26 upper surfaces, 28 illusory chips 30
Viscose 32 upper strata storage chips 40 viscoses 42
Aluminium connection pad 44 second bonding wires 46 upper surfaces 48
Packaging structure 50 substrates 60 connection pads 62
Lower floor's storage chip 70 viscoses 72 aluminium connection pads 74
First bonding wire, 76 upper surfaces, 78 upper strata storage chips 90
Viscose 92 aluminium connection pads 94 second bonding wires 96
Upper surface 98 packaging structures 100 substrates 110
Connection pad 112 first chips 120 viscoses 122
Connection pad 124 first bonding wires 126 upper surfaces 128
Lower surface 129 non-conductive adhesives 130 fulcrum balls 132
Large scale fulcrum ball 132a small size fulcrum ball 132b second chip 140
Connection pad 144 second bonding wires 146 upper surfaces 148
Lower surface 149 the 3rd chip 150 four-core sheets 160
Lower surface 169 the 5th chip 170 viscoses 172
Passive component 180 tin creams 182 adhesive bodies 190
Embodiment
In order to make above-mentioned purpose of the present invention, feature and advantage more obvious, below by embodiment, and conjunction with figs., be described in detail below:
To Figure 11, it shows the semiconductor encapsulation device 100 of one embodiment of the invention with reference to figure 6.This semiconductor encapsulation device 100 comprises a substrate 110, one first chip 120 and one second chip 140; This first and second chip 120,140 is storage chip, microprocessor, logicality chip or the radio frequency chip of DRAM (Dynamic Random Access Memory) (DRAM), static random internal memory (SRAM), flash memory (Flash), double data storage (DDR) or Rambus internal memory etc.
With reference to figure 6, this substrate 110 is provided with a plurality of connection pads 112; First chip 120 has relative upper surface 128 and lower surface 129, lower surface 129 usefulness one viscose 122 is fixed on the substrate 110, and the edge of described upper surface 128 (as, the both sides of the edge of upper surface 128) be provided with a plurality of connection pads 124 and a plurality of first bonding wires 126, be electrically connected at the connection pad 112 of described substrate 110 in order to connection pad 124 described first chip 120; The connection pad 124 of described first chip 120 can be the aluminium connection pad.
With reference to figure 7a, a non-conductive adhesive 130 is configured on the upper surface 128 of first chip 120; A plurality of fulcrum balls 132 are inserted in the described non-conductive adhesive 130 by means of stirring, and support second chip 140, as shown in Figure 8.Described fulcrum ball 132 has a predetermined diameter, in order to define the required space of this first bonding wire, and the above height H of 5 mils (mils) according to appointment.Described fulcrum ball 132 can be elasticity, heat-resisting material such as rubber and makes.In another embodiment, with reference to figure 7b, a plurality of fulcrum balls 132 can be the fulcrum ball of two kinds of different-diameters, are large scale fulcrum ball 132a and small size fulcrum ball 132b.This large scale fulcrum ball 132a is in order to define the required space of this first bonding wire 126, the above height H of 5 mils (mils) according to appointment, and this small size fulcrum ball 132b can cause this large scale fulcrum ball 132a to have neat and arrangement closely in order to interval this large scale fulcrum ball 132a.Preferably, the number of this small size fulcrum ball 132b is less than 20% of whole fulcrum ball numbers.
Again with reference to figure 8, second chip 140 has relative upper surface 148 and lower surface 149, these lower surface 149 usefulness non-conductive adhesives 130 are fixed on the upper surface 128 of first chip 120, and this upper surface 149 is provided with a plurality of connection pads 144 and a plurality of second bonding wires 146, is electrically connected at the connection pad 112 of described substrate 110 in order to the connection pad 144 with described second chip 140.Preferably, stick together area greater than 90% of the second chip lower surface area between described non-conductive adhesive 130 and described second chip 140.
Those skilled in the art as can be known, packaging system 100 of the present invention can comprise a plurality of newly-increased chip (not shown) in addition, its similar is in this second chip 140, and be stacked in regular turn on this second chip with plural layer non-conductive adhesive and a plurality of fulcrum ball, in order to increase the core number of packaging structure 100.Simultaneously, what the size of this newly-increased chip can be with second chip 140 is measure-alike, and can the size of this newly-increased chip be dwindled because of piling up.In addition, the substrate of packaging system 100 of the present invention can substitute with a lead frame (not shown).
With reference to figure 9, this packaging system comprises one the 3rd and four-core sheet 150,160 in addition, and its structure is similar to first and second chip 120,140 respectively.The 3rd and four-core sheet 150,160 be stacked in regular turn on the substrate 110 by non-conductive adhesive 130 and fulcrum ball 132, in order to increase the core number of packaging system 100.Stick together area greater than 90% of four-core sheet lower surface area between described non-conductive adhesive 130 and the described four-core sheet 160.
With reference to Figure 10, this packaging system 100 comprises one the 5th chip 170 and a plurality of passive component 180 in addition.The 5th chip is fixed on this substrate 110 by a viscose 172, and is connected in described substrate 110 with the routing juncture.The 5th chip 170 can be a control chip.Passive component 180 is welded on this substrate 110 by tin cream 182, and is electrically connected at this substrate 110.
With reference to Figure 11, an adhesive body 190, as epoxy resin by model as described on the substrate 110, in order to seal this first, second, third, fourth and the 5th chip 120,140,150,160 and 170, passive component 180, and whole bonding wires.At last, this adhesive body 190 is cut, and an enclosing cover (not shown) is by using hot melt adhesive or ultrasonic waves mode to be combined on this adhesive body, to form a complete package device.This packaging system 100 can be a flash memory cards packaging system.
Compare with known packaging system, the large scale fulcrum ball has neat and arranges closely in packaging system of the present invention, the area that sticks together between the non-conductive adhesive 130 and second chip 140 increases, therefore in follow-up manufacturing process, the thermal stress of sticking together in the interface between the non-conductive adhesive 130 and second chip 140 is scattered in whole sticking together on the area, the thermal stress that can reduce after thermmohardening is handled is concentrated, and then avoids the yields that chip splits (die crack) and increase encapsulates.According to packaging structure encapsulation of the present invention, its yields is generally greater than 92%.
Though the present invention discloses with previous embodiment, so it is not in order to limiting the present invention, anyly is familiar with those skilled in the art, without departing from the spirit and scope of the present invention, and when doing various changes and modification.Therefore protection scope of the present invention is as the criterion with the protection range of claim.

Claims (18)

1, a kind of semiconductor encapsulation device is characterized in that comprising:
One supporting body;
One first chip, this first chip has relative a upper surface and a lower surface, and described lower surface is fixed on the described supporting body;
One non-conductive adhesive, this non-conductive adhesive are configured on the upper surface of described first chip;
One second chip, this second core has relative a upper surface and a lower surface, wherein said lower surface is fixed on the upper surface of described first chip with non-conductive adhesive, and sticks together area greater than 90% of the second chip lower surface area between described non-conductive adhesive and described second chip; And
A plurality of fulcrum balls, be configured in this non-conductive adhesive, and comprise the large scale fulcrum ball and the small size fulcrum ball of two kinds of different-diameters, wherein this large scale fulcrum ball is in order to supporting described second chip, and the diameter of this small size fulcrum ball is less than the distance between this first and second chip.
2, by the described semiconductor encapsulation device of claim 1, it is characterized in that, described supporting body is provided with a plurality of first connection pads, the upper surface of described first chip is provided with a plurality of second connection pads and a plurality of first bonding wires, is electrically connected at a plurality of first connection pads of described supporting body in order to a plurality of second connection pads with described first chip; And the upper surface of this second chip is provided with a plurality of the 3rd connection pads and a plurality of second bonding wires, in order to will be electrically connected at a plurality of first connection pads of described supporting body at a plurality of the 3rd connection pads of described second chip.
3, by the described semiconductor encapsulation device of claim 2, it is characterized in that described fulcrum ball has a predetermined diameter, in order to define the required space of described first bonding wire.
By the described semiconductor encapsulation device of claim 1, it is characterized in that 4, described large scale fulcrum ball is in order to define the required space of described first bonding wire, described small size fulcrum ball is in order to the described large scale fulcrum ball in interval.
By the described semiconductor encapsulation device of claim 1, it is characterized in that 5, the number of described small size fulcrum ball is less than 20% of whole fulcrum ball numbers.
6, by the described semiconductor encapsulation device of claim 1, it is characterized in that described fulcrum ball is the fulcrum ball that elasticity, heat-resisting material are manufactured.
7, by the described semiconductor encapsulation device of claim 6, it is characterized in that described fulcrum ball is the rubber ball.
8, by the described semiconductor encapsulation device of claim 1, it is characterized in that described first and second chip is a storage chip.
9, by the described semiconductor encapsulation device of claim 1, it is characterized in that, also comprise:
One the 3rd chip, the 3rd chip have relative a upper surface and a lower surface, and described lower surface is fixed on the described supporting body; And
One four-core sheet, the four-core sheet has relative a upper surface and a lower surface, wherein lower surface is fixed on the upper surface of described the 3rd chip with non-conductive adhesive, and sticks together area greater than 90% of four-core sheet lower surface area between described non-conductive adhesive and the four-core sheet.
10, by the described semiconductor encapsulation device of claim 9, it is characterized in that, the described the 3rd and the four-core sheet be storage chip.
11, by the described semiconductor encapsulation device of claim 9, it is characterized in that further comprise: one the 5th chip, the 5th chip is fixed on the described supporting body.
12, by the described semiconductor encapsulation device of claim 11, it is characterized in that described the 5th chip is a control chip.
13, by the described semiconductor packaging structure of claim 11, it is characterized in that further comprise: a plurality of passive components, these a plurality of passive components are fixed on the described supporting body again.
14, by the described semiconductor encapsulation device of claim 13, it is characterized in that also comprise: an adhesive body, this adhesive body are sealed the described first, second, third, fourth and the 5th chip, passive component and whole bonding wire.
15, by the described semiconductor encapsulation device of claim 14, it is characterized in that: this semiconductor encapsulation device is a storage card package device.
16, by the described semiconductor encapsulation device of claim 1, it is characterized in that also comprise: an adhesive body, this adhesive body are sealed described first and second chip, first and second bonding wire.
17, by the described semiconductor encapsulation device of claim 1, it is characterized in that described supporting body is a substrate.
18, by the described semiconductor encapsulation device of claim 1, it is characterized in that described supporting body is a lead frame.
CNB2004100424147A 2004-05-18 2004-05-18 Semiconductor packaging device Expired - Fee Related CN100505250C (en)

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JP2005142388A JP2005333132A (en) 2004-05-18 2005-05-16 Semiconductor package

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