CN100505210C - Method for fabricating storage node contact hole of semiconductor device - Google Patents
Method for fabricating storage node contact hole of semiconductor device Download PDFInfo
- Publication number
- CN100505210C CN100505210C CNB200610152834XA CN200610152834A CN100505210C CN 100505210 C CN100505210 C CN 100505210C CN B200610152834X A CNB200610152834X A CN B200610152834XA CN 200610152834 A CN200610152834 A CN 200610152834A CN 100505210 C CN100505210 C CN 100505210C
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- China
- Prior art keywords
- layer
- storage node
- hard mask
- contact hole
- node contact
- Prior art date
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
Abstract
A method for fabricating a storage node contact hole of a semiconductor device includes: forming an inter-layer insulation layer over a substrate; forming a hard mask over the inter-layer insulation layer; etching the inter-layer insulation layer to form a storage node contact hole; forming a passivation layer to fill the storage node contact hole; removing the hard mask with an etch rate of the hard mask faster than that of the inter-layer insulation layer; and removing the passivation layer.
Description
Technical field
The present invention relates to make the method for semiconductor device, more specifically relate to the method for making storage node contact hole.
Background technology
Because the design rule of dynamic random access memory (DRAM) device reduces, also reduce as the thickness of mask with the photoresist layer of formation contact hole.Therefore, implementing to lack photoresist layer during the etching process.Recently, utilize hard mask to form contact hole to overcome this restriction.
In the etching process of the storage node contact hole in the capacitor forming process of DRAM, mainly utilize polysilicon layer to form hard mask.Connect depression (landing) plug that forms in the storage node contact hole bottom and fill storage node contact hole with the storage node contact plug of capacitor storage node.
But, in the process that forms follow-up storage node contact plug, cause mask alignment as the polysilicon layer of hard mask, therefore need open the additional process of storage node contacts keyway (key box).And the polysilicon membrane that is exposed to the whole surface of wafer can be used as sources of particles in the cleaning process that repeats to implement.In addition, the moisture (H that comprises the hydrogen component
2O) be present in intermediate insulating layer inside.Forming as polysilicon layer residual during the polysilicon layer of follow-up storage node contact plug as stoping H
2O flees from the barrier layer of outside.As a result, H
2O expands to substrate, changes transistorized threshold voltage characteristic.Therefore, after forming storage node contact hole, need to remove hard mask.
Figure 1A-1C is the sectional view that graphic extension is used to make the typical method of storage node contact hole.
Shown in Figure 1A, intermediate insulating layer 12 forms above the top of substrate 11, is formed with transistor, depression plug and bit line BL in the substrate.Hard mask polysilicon layer is formed on intermediate insulating layer 12 tops.
Storage node contacts mask 14 is formed on hard mask polysilicon layer top.Storage node contacts mask 14 comprises photoresist layer.
Utilize storage node contacts mask 14 to come the etch hard mask polysilicon layer, obtain hard mask 13 as etch stop layer.Hard mask 13 comprises polysilicon.
Shown in Figure 1B, come etching intermediate insulating layer 12 with storage node contacts mask 14 and hard mask 13 as etch stop layer, to form a plurality of storage node contact holes 15.When storage node contact hole 15 forms, can remove storage node contacts mask 14, and hard mask 13 plays a part etch stop layer.After storage node contact hole 15 forms, the hard mask 13 of loss predetermined thickness in the unit area.Hereinafter, residual hard mask will be represented with Reference numeral 13A after storage node contact hole 15 forms.
But the thickness D1 of residual hard mask 13A is different with the thickness D2 of residual hard mask 13A in the neighboring area in the unit area that forms storage node contact hole 15.
Shown in Fig. 1 C, remove residual hard mask 13A.
If after forming storage node contact hole 15, remove formed residual hard mask 13A in uneven thickness, then the intermediate insulating layer in the unit area 12 may be impaired.The impaired part of intermediate insulating layer 12 is represented (referring to Fig. 1 C) with Reference numeral 12A.
For example, if the hard mask 13 initial thickness that form are about 1200
, then the thickness D1 of residual hard mask 13A is about 600 in the unit area
, in the neighboring area residual hard mask 13A thickness D2 be about 900
After removing residual hard mask 13A, the impaired part 12A of intermediate insulating layer 12 is about 300
Or it is bigger.And when removing residual hard mask 13A, the inside of storage node contact hole 15 and top may be impaired.
As mentioned above, the impaired part 12A of intermediate insulating layer 12 can increase the parasitic capacitance between bit line and the memory node or cause bit line and storage node contact plug between electrical short.
Summary of the invention
Therefore, the method that the purpose of this invention is to provide the storage node contact hole of making semiconductor device, this method can remove hard mask and remove that feasible excessive damage to middle insulating barrier minimizes in the process of hard mask after storage node contact hole forms.
According to an aspect of the present invention, provide the method for the storage node contact hole of making semiconductor device, comprising: on substrate, form intermediate insulating layer; On intermediate insulating layer, form hard mask; The etching intermediate insulating layer is to form storage node contact hole; Form passivation layer to fill storage node contact hole; The etch-rate that utilizes hard mask removes hard mask sooner than the etch-rate of intermediate insulating layer; And remove passivation layer.
According to another aspect of the present invention, provide the method for the storage node contact hole of making semiconductor device, comprising: on the substrate that is defined as unit area and neighboring area, form oxide skin(coating); On oxide skin(coating), form silicon-rich oxy-nitride (SRON) layer that comprises a large amount of silicon; Utilize the SRON layer to come the etching oxide layer, in the unit area, to form storage node contact hole as hard mask; Form the passivation layer of filling storage node contact hole; The etch-rate that utilizes the SRON layer removes the SRON layer sooner than the etch-rate of oxide skin(coating); And remove passivation layer.
Description of drawings
[18], will understand above-mentioned and other purposes and feature of the present invention better by the hereinafter explanation of given in conjunction with the accompanying drawings exemplary.
[19] Figure 1A-1C is the sectional view that the typical method of storage node contact hole is made in graphic extension; With
[20] Fig. 2 A-2F is the sectional view that the method for storage node contact hole is made in graphic extension according to an embodiment of the present invention.
Embodiment
[21] Fig. 2 A-2F is the sectional view that the method for storage node contact hole is made in graphic extension according to an embodiment of the present invention.
[22] shown in Fig. 2 A, on the substrate 21 that is defined as unit area and neighboring area, form intermediate insulating layer 22.Intermediate insulating layer 22 comprises the oxide-base material.The oxide-base material can be a kind of in high density plasma oxide layer and boron phosphorus silicate glass (BPSG) layer.Substrate 21 has been formed with the transistor that comprises word line, depression plug and bit line, and can think the depression plug.Therefore, can think that intermediate insulating layer 22 is that sandwich construction and bit line BL are formed in the intermediate insulating layer 22.
[23] hard mask layer is formed on the intermediate insulating layer 22.Hard mask layer comprises and is selected from oxide skin(coating), silicon nitride (Si
3N
4) layer, polysilicon layer and comprise a kind of in silicon-rich oxy-nitride (SRON) layer of a large amount of silicon.Particularly, hard mask layer mainly comprises the SRON layer.The SRON layer has the Si of ratio
3N
4Layer and the more substantial silicon of nitride layer make the SRON layer have the Si of ratio
3N
4Layer and the better self-aligned contacts of nitride layer (SAC) etch features.And, utilize the SRON layer as hard mask layer, make the selectivity of Billy with the easier control intermediate insulating layer 22 of polysilicon layer.Therefore, remove in the process, can be minimized the damage of middle insulating barrier 22 follow-up.
[24] storage node contacts mask 24 is formed on the hard mask layer.Storage node contacts mask 24 comprises photoresist layer.
Afterwards, utilize storage node contacts mask 24 to come the etch hard mask layer, to obtain hard mask 23 as etch stop layer.
Shown in Fig. 2 B, utilize storage node contacts mask 24 and hard mask 23 to come etching intermediate insulating layer 22, to form a plurality of storage node contact holes 25 that expose substrate 21 surfaces as etch stop layer.When storage node contact hole 25 forms, can remove storage node contacts mask 24; But hard mask 23 plays a part etch stop layer.During forming storage node contact hole 25, hard mask 23 uses the SRON layer that comprises a large amount of polysilicons, and therefore has excellent SAC etching characteristic.Therefore, the damage to hard mask 23 tops is minimized.If hard mask 23 has bad SAC etching characteristic, but then implementing the top of etching process with etch hard mask 23 during forming storage node contact hole 25.As a result, can cause the defective of storage node contact hole 25 in the damage of the over top of hard mask 23.
When storage node contact hole 25 formed, the hard mask 23 of part also was damaged, and makes hard mask 23 keep predetermined thickness on intermediate insulating layer 22.Hereinafter, residual hard mask will be represented with Reference numeral 23A.Therefore, the thickness D11 of residual hard mask 23A is different with the thickness D12 of residual hard mask 23A in the neighboring area in the unit area.Because storage node contact hole 25 only is formed in the unit area, therefore the damage to hard mask 23 mainly occurs in the unit area.As a result, the thickness D11 of residual hard mask 23A becomes littler than the thickness D12 of residual hard mask 23A in the neighboring area in the unit area.
Shown in Fig. 2 C, form passivation layer 26 to fill storage node contact hole 25, simultaneously residual hard mask 23A keeps.During removing residual hard mask 23A, passivation layer 26 plays a part to prevent that etch residues from flowing in the storage node contact hole 25.And, during removing residual hard mask 23A, the damage that passivation layer 26 reduces storage node contact hole 25 tops.
Shown in Fig. 2 D, remove residual hard mask 23A by the etch-back method.When removing residual hard mask 23A, keep the etch-rate of residual hard mask 23A liken to into the etch-rate of the intermediate insulating layer 22 of oxide base layer faster, to reduce excessive damage to middle insulating barrier 22.If keep the etch-rate of residual hard mask 23A faster than the etch-rate of intermediate insulating layer 22, then can make on intermediate insulating layer 22, to produce to damage to minimize, also be like this even on residual hard mask 23A, excessively implement etching.For example, the etch-rate of residual hard mask 23A and intermediate insulating layer 22 remains the intermediate insulating layer to 1 part at least about 2 parts residual hard mask 23A, and perhaps higher, the residual hard mask 23A of promptly about 2-3 part is to about 1 part intermediate insulating layer.
Hereinafter will study the etching process of the residual hard mask 23A that forms by the SRON layer that comprises a large amount of silicon in great detail.
The engraving method that removes residual hard mask 23A uses the etch-back method.Utilize by joining difluoromethane (CH as argon (Ar) gas of diluent gas
2F
2), methane (CH
4) and oxygen (O
2) mist in and the gas that obtains is implemented the etch-back method in reactive ion etching type plasma chamber.CH
2F
2Gas: CH
4Gas: the mixing ratio of oxygen is about 2: about 1: about 1.CH
2F
2, CH
4And O
2The total flow of mist be about 80sccm or littler, the about 80sccm of promptly about 50sccm-.The flow of Ar gas is the about 1000sccm of about 100sccm-.If CH
2F
2, CH
4And O
2The total flow of mist surpass about 80sccm, then intermediate insulating layer 22 can be by over etching.If O in the mist
2The flow of gas is less than CH
2F
2The flow of gas, then intermediate insulating layer 22 may less etching.
If adopt above-mentioned prescription, then make the SRON layer that comprises a large amount of silicon and the etch-rate of intermediate insulating layer 22 remain about 2-3 part SRON layer: the ratio of about 1 part of intermediate insulating layer 22.Therefore, the damage on the intermediate insulating layer 22 that is created in the unit area is minimized, be removed fully up to the SRON layer.
As mentioned above, after removing residual hard mask 23A, the surface damage on the intermediate insulating layer 22 is minimized.And, implement the etch-back method with the process of removing residual hard mask 23A in because passivation layer 26 and do not damage the inside and the top of storage node contact hole 25.
Shown in Fig. 2 E, remove the passivation layer 26 of filling storage node contact hole 25.Because passivation layer 26 comprises photoresist layer, therefore can utilize oxygen plasma to implement stripping process and remove passivation layer 26.Near the 22 pairs of oxygen plasmas of intermediate insulating layer that form passivation layer 26 have high selectivity.Therefore, when removing passivation layer 26, can not damage the top of intermediate insulating layer 22.
Shown in Fig. 2 F, after removing passivation layer 26, form polysilicon layer 27, up to the storage node contact hole 25 that fills up exposure.Because before polysilicon layer 27 formed, residual hard mask 23A was removed, so the moisture of intermediate insulating layer 22 inside can be fled from the outside.Therefore, transistorized threshold voltage does not change because of moisture.
Though do not illustrate, selective etch polysilicon layer 27 in subsequent process is so that form storage node contact hole.
As mentioned above, remove hard mask by between intermediate insulating layer and hard mask, increasing etching selectivity.As a result, can reduce excessive damage to the intermediate insulating layer in the unit area.After removing hard mask, can not be created in the difference in thickness of the intermediate insulating layer between neighboring area and the unit area.And, can reduce electrical short between storage node contact plug and the bit line and the parasitic capacitance between memory node and the bit line.
Though in this embodiment of the present invention exemplary illustration the formation of storage node contact hole, this embodiment can be applicable to use any other situations of hard mask during forming the contact hole of semiconductor device.According to an embodiment of the present invention, the difference in thickness of the intermediate insulating layer between unit area and the neighboring area is minimized.
According to this embodiment of the present invention, after storage node contact hole forms, can utilize the high etch-selectivity between intermediate insulating layer and the hard mask, the damage on the intermediate insulating layer is minimized.And, can reduce the distortion of storage node contact hole.In addition, the hard mask of selective etch before storage node contact plug forms makes the moisture of intermediate insulating layer inside easily to flee to the outside.Therefore, threshold voltage that can stable transistor.
The application comprises and the korean patent application KR 2005-0123470 theme relevant with KR 2006-0087607 that is committed to Korean Patent office on December 14th, 2005 and on September 11st, 2006 respectively, and the full content of these applications is incorporated this paper by reference into.
Though with regard to particular the present invention has been described, can under not departing from, make variations and modifications as the spirit and scope of the invention defined in the claims, this will be apparent to those skilled in the art.
Claims (19)
1. method of making the storage node contact hole of semiconductor device comprises:
On substrate, form intermediate insulating layer;
On intermediate insulating layer, form hard mask;
The etching intermediate insulating layer is to form storage node contact hole;
Form passivation layer to fill the space of the storage node contact hole that is limited by intermediate insulating layer and hard mask;
The etch-rate that utilizes hard mask removes hard mask sooner than the etch-rate of intermediate insulating layer; With
Remove passivation layer.
2. the process of claim 1 wherein during removing hard mask the hard mask that the etch-rate of hard mask and intermediate insulating layer remains 2-3 part: the ratio of 1 part intermediate insulating layer.
3. the method for claim 2, wherein removing of hard mask comprises and utilizes etch-back process.
4. the process of claim 1 wherein that passivation layer comprises photoresist layer.
5. the method for claim 4, wherein the formation of passivation layer comprises:
On intermediate insulating layer, form photoresist layer, up to filling up storage node contact hole; With
By implementing the code-pattern expose process, make photoresist layer only remain in the inside of storage node contact hole.
6. the method for claim 5, wherein removing of passivation layer comprises and uses oxygen plasma to implement stripping process.
7. the method for claim 6, wherein hard mask comprise a kind of in silicon nitride layer and the polysilicon layer.
8. the method for claim 6, wherein intermediate insulating layer comprises the oxide-base material.
9. the method for claim 6, wherein substrate is restricted to unit area and neighboring area, and storage node contact hole is formed in the unit area.
10. method of making the storage node contact hole of semiconductor device comprises:
On the substrate that is defined as unit area and neighboring area, form oxide skin(coating);
On oxide skin(coating), form the silicon-rich oxy-nitride SRON layer that comprises a large amount of silicon;
Utilize the SRON layer to come the etching oxide layer, in the unit area, to form storage node contact hole as hard mask;
Form space of filling storage node contact hole and the passivation layer that contacts with Semiconductor substrate;
The etch-rate that utilizes the SRON layer removes the SRON layer sooner than the etch-rate of oxide skin(coating); With
Remove passivation layer.
11. the method for claim 10, wherein during removing the SRON layer, the etch-rate of SRON layer and oxide skin(coating) remains the SRON layer of 2-3 part: the ratio of 1 part oxide skin(coating).
12. the method for claim 11, wherein removing of SRON layer comprises and utilizes etch-back process.
13. the method for claim 12, wherein etch-back process comprises that use reactive ion etching type plasma chamber is as etching chamber.
14. the method for claim 13, wherein etch-back process comprises that use comprises difluoromethane CH
2F
2, methane CH
4With oxygen O
2Mist and add in the described mist argon Ar gas as diluent gas.
15. the method for claim 14, wherein CH
2F
2, CH
4And O
2With 2 parts of CH
2F
2: 1 part of CH
4: 1 part of O
2Ratio mix.
16. the method for claim 14, wherein CH
2F
2, CH
4And O
2Total flow be 80sccm or littler, the flow of Ar gas is 100sccm-1000sccm.
17. the method for claim 10, wherein passivation layer comprises photoresist layer.
18. the method for claim 17, wherein the formation of passivation layer comprises:
On oxide skin(coating), form photoresist layer, up to filling up storage node contact hole; With
By implementing the code-pattern expose process, make photoresist layer only remain in the inside of storage node contact hole.
19. the method for claim 18, wherein removing of passivation layer comprises and utilizes oxygen plasma to implement stripping process.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR20050123470 | 2005-12-14 | ||
| KR1020050123470 | 2005-12-14 | ||
| KR1020060087607 | 2006-09-11 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1983553A CN1983553A (en) | 2007-06-20 |
| CN100505210C true CN100505210C (en) | 2009-06-24 |
Family
ID=38165962
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB200610152834XA Expired - Fee Related CN100505210C (en) | 2005-12-14 | 2006-10-20 | Method for fabricating storage node contact hole of semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| KR (1) | KR100772681B1 (en) |
| CN (1) | CN100505210C (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110938434A (en) * | 2019-12-05 | 2020-03-31 | 中国科学院微电子研究所 | Etching method of inner side wall, etching gas and preparation method of nanowire device |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102194677B (en) * | 2010-03-11 | 2013-07-31 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing clearance wall of semiconductor apparatus |
| CN108269804B (en) * | 2016-12-30 | 2019-08-23 | 联华电子股份有限公司 | The production method of semiconductor storage |
| CN114823539A (en) * | 2021-01-29 | 2022-07-29 | 长鑫存储技术有限公司 | Manufacturing method of semiconductor structure and semiconductor structure |
| CN114823541A (en) * | 2021-01-29 | 2022-07-29 | 长鑫存储技术有限公司 | Method for forming semiconductor structure |
| CN116705694A (en) * | 2022-02-24 | 2023-09-05 | 长鑫存储技术有限公司 | Semiconductor structure, forming method thereof and manufacturing method of dynamic random access memory |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR980005510A (en) * | 1996-06-26 | 1998-03-30 | 김광호 | How to create a storage node contact |
| KR19990075146A (en) * | 1998-03-18 | 1999-10-15 | 윤종용 | Contact hole formation method of storage electrode |
| KR20030000695A (en) * | 2001-06-26 | 2003-01-06 | 주식회사 하이닉스반도체 | Method for forming the storage node of semiconductor device |
-
2006
- 2006-09-11 KR KR1020060087607A patent/KR100772681B1/en not_active IP Right Cessation
- 2006-10-20 CN CNB200610152834XA patent/CN100505210C/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110938434A (en) * | 2019-12-05 | 2020-03-31 | 中国科学院微电子研究所 | Etching method of inner side wall, etching gas and preparation method of nanowire device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100772681B1 (en) | 2007-11-02 |
| KR20070063409A (en) | 2007-06-19 |
| CN1983553A (en) | 2007-06-20 |
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