CN102194677B - Method for manufacturing clearance wall of semiconductor apparatus - Google Patents
Method for manufacturing clearance wall of semiconductor apparatus Download PDFInfo
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- CN102194677B CN102194677B CN 201010124693 CN201010124693A CN102194677B CN 102194677 B CN102194677 B CN 102194677B CN 201010124693 CN201010124693 CN 201010124693 CN 201010124693 A CN201010124693 A CN 201010124693A CN 102194677 B CN102194677 B CN 102194677B
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- fluorocarbon
- inert gas
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Abstract
The invention provides a method for manufacturing a clearance wall of a semiconductor apparatus. The method comprises the following steps of: providing a substrate, wherein the surface of the substrate has a grid structure; forming an oxide layer on the substrate and the grid structure; forming a clearance wall material layer on the oxide layer; and etching the oxide layer and the clearance wall material layer by using etching gas containing fluorocarbon and inert gas but not containing oxygen to form the clearance wall, wherein the flow velocity ratio of the fluorocarbon to the inert gas 0.1 to 1. By the method, the problem that the thicknesses of the clearance walls in a dense area and a non-dense area are nonuniform can be effectively solved and the electrical property of the apparatus is improved, so that the apparatus operates at a uniform speed in different environments, and then the qualification rate is improved.
Description
Technical field
The present invention relates to semiconductor fabrication process, particularly a kind of method of making the semiconductor device clearance wall.
Background technology
At present, along with developing rapidly of very lagre scale integrated circuit (VLSIC), the integrated level of chip is more and more higher, and the circuit design size is more and more littler.At present, manufacturer can make the semiconductor device with 32nm even littler live width.
In the manufacture process of existing MOS (metal-oxide semiconductor (MOS)) device, utilize the technology that clearance wall is set to inject source area and the drain region of MOS to help control and definition dopant usually.Figure 1A and Figure 1B are the cutaway view of the related semiconductor device of each step in the flow process of prior art making clearance wall.Please refer to Figure 1A, substrate 100 is provided earlier, be formed with grid structure 110 on the substrate 100.Grid structure 110 for example comprises gate oxide layers 110A and grid 110B.Gate oxide layers 110A and grid 110B utilize conventional deposition, photoetching and etching technics formed.Wherein, the material of gate oxide layers 110A for example is silica, and the material of grid 110B for example is doped polycrystalline silicon.Then, form oxide skin(coating) 101 at substrate 100 and grid structure 110, wherein the formation method of oxide skin(coating) 101 is good with chemical vapor deposition method, and the thickness of oxide skin(coating) 101 is good with 75 dusts to 150 dusts then.Then, form spacer material layer 102 with methods such as LPCVD or PECVD on oxide skin(coating) 301, this layer is mainly material, for example silicon nitride (Si
xN
y), be rich in nitride, the silicon oxynitride (SiO of silicon
xN
y) and be rich in the nitrogen oxide of silicon one or more.The thickness of spacer material layer 102 is good with 300 dusts to 2000 dusts.
Please refer to Figure 1B, oxide skin(coating) 101 and spacer material layer 102 are carried out the selectivity dry etch process, form clearance wall.Etching gas can comprise fluorocarbon, inert gas and oxygen.The example of fluorocarbon comprises CF
4, CHF
3, C
2F
6Deng.
In the manufacture process of clearance wall, along with dwindling of element critical size, it is inhomogeneous that the thickness of clearance wall may become, and it is to realize the reliable electric property of device and avoid one of key of short-channel effect that the thickness difference of zones of different internal clearance wall is limited in the tolerable error scope.Yet the deposition of above-mentioned spacer material layer is used vapour deposition, for example chemical vapour deposition (CVD) or physical vapour deposition (PVD) etc. usually.In the process of thin film deposition, the film thickness in the non-dense set district that the less compact district of device pitch and device pitch are bigger in the circuit is easy to occur difference, and the compact district film thickness is less than the thickness of non-dense set district film usually.Traditional etching technics can hand on this species diversity, causes the clearance wall of compact district after the etching to be thinner than the clearance wall in non-dense set district.Clearance wall meeting in uneven thickness descends the electric property of device, and makes device speed of service under varying environment inconsistent, thereby causes yields to descend.
Therefore, be badly in need of a kind of compact district and inhomogeneous effective ways of the interval crack wall thickness of non-dense set of solving at present, to improve the electric property of device, make device speed of service under varying environment even, thereby improve yields.
Summary of the invention
Introduced the concept of a series of reduced forms in the summary of the invention part, this will further describe in the embodiment part.Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range of attempting to determine technical scheme required for protection.
The invention provides a kind of method of making the semiconductor device clearance wall, described method comprises the following steps: to provide a substrate successively, and the surface of this substrate has grid structure; Form oxide skin(coating) at described substrate and described grid structure; Form the spacer material layer at described oxide skin(coating); And use the etching gas comprise fluorocarbon and inert gas but not comprise oxygen that described oxide skin(coating) and described spacer material layer are carried out etching, to form clearance wall, wherein, the velocity ratio of described fluorocarbon and described inert gas is 0.1-1.
According to a further aspect in the invention, the method for described making semiconductor device clearance wall is characterised in that, described spacer material layer comprises silicon nitride, be rich in nitride, the silicon oxynitride of silicon and be rich in one or more materials in the nitrogen oxide of silicon.
According to a further aspect in the invention, the method for described making semiconductor device clearance wall is characterised in that described fluorocarbon is that carbon/fluorine compares the compound smaller or equal to 0.5.
According to a further aspect in the invention, the method for described making semiconductor device clearance wall is characterised in that the flow velocity of described fluorocarbon is 50-500sccm.
According to a further aspect in the invention, the method for described making semiconductor device clearance wall is characterised in that the flow velocity of described inert gas is 500-1000sccm.
According to a further aspect in the invention, the method for described making semiconductor device clearance wall is characterised in that the flow velocity of described inert gas is 700-1000sccm.
According to a further aspect in the invention, the method for described making semiconductor device clearance wall is characterised in that the velocity ratio of described fluorocarbon and described inert gas is 0.1-0.5.
The method according to this invention can effectively solve compact district and the inhomogeneous problem of the interval crack wall thickness of non-dense set, has improved the electric property of device, makes device speed of service under varying environment even, thereby improves yields.
Description of drawings
Following accompanying drawing of the present invention is used for understanding the present invention at this as a part of the present invention.Embodiments of the invention and description thereof have been shown in the accompanying drawing, have been used for explaining principle of the present invention.In the accompanying drawings,
Figure 1A and Figure 1B are the schematic cross sectional views of the related semiconductor device of each step in the flow process of prior art making clearance wall;
Fig. 2 A to Fig. 2 C is the cutaway view of making the related semiconductor device of each flow process of clearance wall according to one embodiment of present invention;
Fig. 3 is the process chart of making clearance wall according to one embodiment of present invention.
Embodiment
In the following description, a large amount of concrete details have been provided in order to more thorough understanding of the invention is provided.Yet, it will be apparent to one skilled in the art that the present invention can need not one or more these details and implemented.In other example, for fear of obscuring with the present invention, be not described for technical characterictics more well known in the art.
In order thoroughly to understand the present invention, will in following description, detailed steps be proposed, so that explanation the present invention is the etching technics that how to pass through to improve clearance wall, solve the inhomogeneous problem of etching post gap wall thickness.Obviously, execution of the present invention is not limited to the specific details that the technical staff of semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, yet except these were described in detail, the present invention can also have other execution modes.
Though hereinafter be that example is explained method of the present invention with the MOS transistor, yet the clearance wall that it will be appreciated by those skilled in the art that this method and use this method to form can be applicable to any MOS transistor and MOSEFT.Fig. 2 A to Fig. 2 C illustrates the cutaway view of the related semiconductor device of each flow process of making clearance wall according to one embodiment of present invention.
Please refer to Fig. 2 A, substrate 200 is provided earlier, be formed with grid structure 210 on the substrate 200.Grid structure 210 for example comprises gate oxide layers 210A and grid 210B.Grid structure 210 can form by traditional deposition, photoetching and plasma etching or wet etching.Substrate 200 can be including but not limited in the following material of mentioning at least a: for example silicon, silicon-on-insulator (silicon oninsulator, SOI), stacked silicon (stacked silicon on insulator on the insulator, SSOI), stacked SiGe (stacked SiGe on insulator on the insulator, S-SiGeOI), germanium on insulator silicon (SiGe on insulator, SiGeOI) and germanium on insulator (Ge on insulator, GeOI).Wherein, the material of gate oxide layers 210A for example is silica, and the material of grid 210B for example is doped polycrystalline silicon.
Grid structure comprises gate oxide layers 210A and grid 210B.Gate oxide layers 210A can be by technology commonly used, and for example thermal oxidation method, nitrogenize, sputtering sedimentation or chemical vapour deposition technique form.Gate oxide layers 210A can comprise silica (SiO
2), silicon nitride (Si
xN
y), silicon oxynitride (Si
xO
yN
z) or the dielectric material of high-k etc.Grid 210B can form by deposition, the sputtering technology that for example chemical vapour deposition (CVD), magnetron sputtering etc. are commonly used.Grid 210B can be by at least a composition the in for example polysilicon, amorphous polysilicon, doped polycrystalline silicon and the polycrystalline SiGe.
Then, please refer to Fig. 2 B, form oxide skin(coating)s 201 at substrate 200 and grid structure 210, the method that wherein forms oxide skin(coating) 201 is chemical vapor deposition method, for example plasma enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD) preferably.The thickness of preferred oxide skin(coating) 201 is the 75-150 dust.Oxide skin(coating) 201 can utilize tetramethylsilane (TEOS) and/or two (tert-butyl group amino) silane (BTBAS) and oxygen source to form, and wherein oxygen source is good with ozone or oxygen/ozone mixture, also can be the silica of other form.Also can utilize hot boiler tube or flash annealing to form oxide skin(coating) 201, wherein annealing temperature is being good between 800 ℃ to 1100 ℃.Then, form spacer material layer 202 with methods such as LPCVD or PECVD on oxide skin(coating) 201, this layer is mainly material, for example silicon nitride (Si
xN
y), be rich in nitride, the silicon oxynitride (SiO of silicon
xN
y) and be rich in the nitrogen oxide of silicon one or more.The thickness of preferred spacer material layer 202 is the 300-2000 dust.
Please refer to Fig. 2 C, according to one embodiment of present invention, oxide skin(coating) 201 and spacer material layer 202 are carried out the selectivity dry etch process, to form clearance wall.Etching technics for example uses single or the compound radio-frequency electric field carries out reactive ion etching (RIE).Etching gas can comprise the inert gas of fluorocarbon and big flow, but does not comprise oxygen.The example of fluorocarbon comprises that carbon/fluorine compares the compound smaller or equal to 0.5, for example CF
4, CHF
3, C
2F
6Deng.Fluorocarbon is main etching gas, and the material of oxide skin(coating) 201 and spacer material layer 202 is played corrasion.The flow velocity of fluorocarbon is 50-500sccm.The flow velocity of inert gas is 500-1000sccm.The inert gas that flow velocity is bigger can play the effect of the main etching gas of dilution, and then can carry out more accurate control to the etch rate of compact district and the interval crack of non-dense set wall material layer, so preferred flow velocity is 700-1000sccm.Preferred inert gas is argon gas or helium.In addition, the inventor finds, when not comprising oxygen in the etching gas, such etching gas can reduce the difference between the film thickness in the bigger non-dense set district of the less compact district of device pitch in the circuit and device pitch better.Its reason it be unclear that, but the inventor is presumed as follows: oxygen may generate passivation with silicon nitride reaction and be deposited on sidewall, especially in the non-dense set district, can make the width of non-dense set district sidewall greater than the compact district like this.According to embodiments of the invention, the velocity ratio of fluorocarbon and inert gas effect in the 0.1-1 scope is preferable in the etching gas, and effect is better in the 0.1-0.5 scope.
Utilize transmission electron microscope (TEM) that the cross-section structure of the clearance wall in the compact district that forms by the described method of one embodiment of the invention and non-dense set district is analyzed.The tem analysis result is as follows: the thickness of compact district grid two side clearance walls is respectively 20.2nm and 19.4nm, and the thickness of non-dense set district grid two side clearance walls is respectively 20.3nm and 19.9nm.Two groups of data contrast as can be seen, and the thickness of the clearance wall in non-dense set district and the clearance wall of compact district is basic identical, and the thickness of grid two side clearance walls only increases 0.1nm and 0.5nm respectively.Utilize TEM that the cross-section structure of the clearance wall in the compact district of adopting method of the prior art and forming and non-dense set district is analyzed equally, it is identical with the step that forms clearance wall according to the inventive method that method of the prior art refers to form the step of clearance wall, and difference is the inert gas and the oxygen that comprise in the etching gas that flow velocity is less.The tem analysis result is as follows: the clearance wall thickness of the inner grid left and right sides, compact district is respectively 20.4nm and 19.1nm, but the clearance wall thickness of the inner grid left and right sides, non-dense set district is respectively 23.2nm and 23.6nm, that is to say that the clearance wall of compact district is than the thin 3nm of clearance wall in non-dense set district.The contrast of above-mentioned experimental data as can be seen, the method according to this invention can be improved the interval crack of non-dense set wall thickness effectively with respect to the increase of compact district clearance wall thickness, makes after the etching clearance wall thickness of zones of different even.
In addition, respectively under the proper testing voltage and under the low test voltage, to carrying out check experiment according to method of the prior art with according to the clearance wall of the inventive method manufacturing, relatively to adopt the yields of the device that two kinds of methods obtain.Check experiment result shows, improves about 15% and 10% according to the yields of the device of the inventive method manufacturing respectively with respect to the yields according to the device of conventional method manufacturing.
The flow chart of Fig. 3 shows the technological process of making grid according to the embodiment of the invention.In step 301, substrate is provided earlier, be formed with grid structure on the substrate.Grid structure for example comprises gate oxide layer segment and grid part.In step 302, forming thickness at substrate and grid structure is the oxide skin(coating) of 75-150 dust, and the method that wherein forms oxide skin(coating) is chemical vapor deposition (CVD) technology preferably.Also can utilize hot boiler tube or flash annealing to form oxide skin(coating).Then, form the spacer material layer with methods such as CVD on oxide skin(coating), this layer is mainly material, for example silicon nitride (Si
xN
y), be rich in nitride, the silicon oxynitride (SiO of silicon
xN
y) and be rich in the nitrogen oxide of silicon one or more.The thickness of preferred spacer material layer is the 300-2000 dust.In step 303, oxide skin(coating) and spacer material layer are carried out the selectivity dry etch process, to form clearance wall.Etching gas can comprise the inert gas of fluorocarbon and big flow, but does not comprise oxygen.The example of fluorocarbon comprises that carbon/fluorine compares the compound smaller or equal to 0.5, for example CF
4, CHF
3, C
2F
6Deng.Fluorocarbon is main etching gas, and the material of oxide skin(coating) and spacer material layer is played corrasion.The flow velocity of fluorocarbon is 50-500sccm.The flow velocity of inert gas is 500-1000sccm, and preferred flow velocity is 700-1000sccm.Preferred inert gas is argon gas or helium.According to embodiments of the invention, the velocity ratio of fluorocarbon and inert gas effect in the 0.1-1 scope is preferable in the etching gas, and effect is better in the 0.1-0.5 scope.
The present invention mainly improves in the process that adopts the vapour deposition process deposit film non-dense set district with respect to the increase of compact district spacer material layer thickness by the control kind of etching gas and flow velocity.In etching process, main etching gas such as use fluorocarbon are finished the main etching of spacer material layer.In addition, used the inert gas of big flow velocity, the inert gas dilution of big flow velocity main etching gas, thereby the compact district makes the reaction speed of compact district integral body slower than non-dense set district owing to will etch away more spacer material.Therefore, be consistent substantially according to the thickness of clearance wall in compact district and non-dense set district of the inventive method manufacturing, so improved the electric property of device, make device speed of service under varying environment identical, thereby improve yields.
Have according to the semiconductor device of the clearance wall of embodiment manufacturing as mentioned above and can be applicable in the multiple integrated circuit (IC).For example be memory circuitry according to IC of the present invention, as random-access memory (ram), dynamic ram (DRAM), synchronous dram (SDRAM), static RAM (SRAM) (SRAM) or read-only memory (ROM) etc.Can also be logical device according to IC of the present invention, as programmable logic array (PLA), application-specific integrated circuit (ASIC) (ASIC), combination type DRAM logical integrated circuit (buried type DRAM) or other circuit devcies arbitrarily.IC chip according to the present invention can be used for for example consumer electronic products, in various electronic products such as personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera, digital camera, mobile phone, especially in the radio frequency products.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just is used for for example and illustrative purposes, but not is intended to the present invention is limited in the described scope of embodiments.It will be appreciated by persons skilled in the art that in addition the present invention is not limited to above-described embodiment, can also make more kinds of variants and modifications according to instruction of the present invention, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (8)
1. method of making the semiconductor device clearance wall, described method comprises the following steps: successively
One substrate is provided, and this substrate comprises compact district and the bigger non-dense set district of device pitch that device pitch is less, and the surface of described substrate has the grid structure that lays respectively at described compact district and non-dense set district;
Form oxide skin(coating) at described substrate and described grid structure;
Form the spacer material layer at described oxide skin(coating); And
Use comprises fluorocarbon and inert gas but the etching gas that do not comprise oxygen carries out etching to described oxide skin(coating) and described spacer material layer, is positioned at the uniform clearance wall of thickness in described compact district and non-dense set district with formation,
Wherein, the velocity ratio of described fluorocarbon and described inert gas is 0.1-1, and the flow velocity of described inert gas is 500-1000sccm.
2. the method for claim 1 is characterized in that, described spacer material layer comprises silicon nitride, be rich in nitride, the silicon oxynitride of silicon and be rich in one or more materials in the nitrogen oxide of silicon.
3. the method for claim 1 is characterized in that, described fluorocarbon is that carbon/fluorine compares the compound smaller or equal to 0.5.
4. method as claimed in claim 3 is characterized in that, the flow velocity of described fluorocarbon is 50-500sccm.
5. the method for claim 1 is characterized in that, the flow velocity of described inert gas is 700-1000sccm.
6. the method for claim 1 is characterized in that, the velocity ratio of described fluorocarbon and described inert gas is 0.1-0.5.
7. integrated circuit that comprises the semiconductor device clearance wall of making by the method for claim 1, wherein said integrated circuit is selected from dynamic random access memory, synchronous RAM, static RAM, read-only memory, programmable logic array and radio circuit.
8. electronic equipment that comprises the semiconductor device clearance wall of making by the method for claim 1, wherein said electronic equipment is selected from personal computer, game machine, cellular phone, personal digital assistant, video camera and digital camera.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1691295A (en) * | 2004-04-23 | 2005-11-02 | 中国科学院微电子研究所 | Self-aligning silicide method for RF lateral diffusion field-effect transistor |
| CN1983553A (en) * | 2005-12-14 | 2007-06-20 | 海力士半导体有限公司 | Method for fabricating storage node contact hole of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6794303B2 (en) * | 2002-07-18 | 2004-09-21 | Mosel Vitelic, Inc. | Two stage etching of silicon nitride to form a nitride spacer |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1691295A (en) * | 2004-04-23 | 2005-11-02 | 中国科学院微电子研究所 | Self-aligning silicide method for RF lateral diffusion field-effect transistor |
| CN1983553A (en) * | 2005-12-14 | 2007-06-20 | 海力士半导体有限公司 | Method for fabricating storage node contact hole of semiconductor device |
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