CN102024706A - Method for manufacturing semiconductor device - Google Patents
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- CN102024706A CN102024706A CN2009101962686A CN200910196268A CN102024706A CN 102024706 A CN102024706 A CN 102024706A CN 2009101962686 A CN2009101962686 A CN 2009101962686A CN 200910196268 A CN200910196268 A CN 200910196268A CN 102024706 A CN102024706 A CN 102024706A
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Abstract
The invention discloses a method for manufacturing a semiconductor device. The method comprises the following the steps of: providing a substrate; forming a gate electrode oxide layer and a gate electrode on the substrate; forming a clearance wall insulation layer on the gate electrode oxide layer and the side wall of the gate electrode, and meanwhile, forming a first insulation layer at the back side of the substrate; forming clearance wall on the side wall of the clearance wall insulation layer, and meanwhile, forming a second insulation layer at the back side of the first insulation layer; forming a source electrode and a drain electrode on the substrate; forming an etching stopping layers on the clearance wall; forming a high-stress induction layer on the etching stopping layer; and carrying out N20 treatment on the high-stress induction layer. The method disclosed in the invention can effectively prevent a photoresist poisoning problem caused by the formation of a SiN layer in the stress memory technology so as to reduce the production cost of the semiconductor device and improve the rate of good products.
Description
Technical field
The present invention relates to semiconductor fabrication process, prevent that particularly photoresist in the stress memory technology from poisoning the manufacturing process of phenomenon.
Background technology
The manufacturing of integrated circuit need form a large amount of circuit elements according to the circuit layout of appointment on given chip area.Consider service speed, power consumption and cost-efficient excellent specific property, the COMS technology is the most promising one of the method made complicated circuit that is used at present.When using the COMS technology to make complicated integrated circuit, there are millions of transistors (for example, N channel transistor and p channel transistor) to be formed on the substrate that comprises crystalline semiconductor layer.No matter what studied is N channel transistor or p channel transistor, MOS transistor all contains so-called PN junction, and PN junction is formed by following both interface: the drain/source region of high-concentration dopant and be disposed at this drain region and this source area between the counter-doping raceway groove.
Control the conductance of channel region with near the gate electrode that is formed at the channel region and separate with this channel region, for example control the current drive capability of conducting channel by thin dielectric layer.After applying suitable control voltage formation conducting channel on the gate electrode, the conductance of channel region depends on the mobility of doping content and most electric charge carriers.For the given extension of transistor width direction, the conductance of channel region depends on the distance between source area and the drain region for channel region, and this distance also is known as channel length.Therefore, the conductance of channel region is the principal element of decision MOS transistor usefulness.Therefore, the channel resistance rate that reduces channel length and reduce to be associated with channel length becomes the important design criteria that is used for improving integrated circuit operation speed.
Yet, thereby reducing channel length, lasting reduction transistor size can bring problems, for example the controllability of raceway groove reduces (this is also referred to as short-channel effect).These problems must be overcome, and progressively reduce the resulting advantage of MOS transistor channel length in order to avoid exceedingly balance out.In addition, continuing to reduce critical size (for example, transistorized grid length) also needs the technology that adapts or the more complicated technology of exploitation to be used for compensate for short channel effects, therefore can be more and more difficult from technological angle.Proposed at present to improve transistorized switching speed, promptly by increase the electronic carrier mobility of raceway groove for given channel length from another angle.The method of this raising carrier mobility can avoid or delay at least with technology that the equipment scaled size is associated in many problems of being run into.
An effective mechanism that is used for increasing charge carrier mobility is the lattice structure that changes in the raceway groove, for example pass through producing stretching or compression stress near the channel region, and stretching or compression can cause the change of electronics and hole mobility respectively so that in raceway groove, produce corresponding strain.For example, with regard to the crystal orientation of standard, in channel region, produce the mobility that uniaxial tensile strain can increase electronics, wherein, depend on the size and Orientation of elongation strain, can increase mobility and reach 50 or more percent along orientation.The increase of mobility can directly change into the raising of conductance.On the other hand, with regard to the channel region of P transistor npn npn, uniaxial compressive can increase the mobility in hole, thereby improves the conductance of P transistor npn npn.It seems at present, is extremely promising method for the next-generation technology node at introduction of stress or strain gauge technique in the integrated circuit manufacturing.Because, it is the semi-conducting material of a kind of " novel " that strained silicon can be considered, this make manufacturing speed faster semiconductor device become may and do not need the in addition expensive novel semiconductor material of exploitation, simultaneously also can compatible institute at present the general semiconductor technology manufacturing technology of use.
Generation stretching or compression stress have several modes near transistorized channel region, for example use permanent stress cover layer, wall element etc. to produce external stress, so that produce needed strain in raceway groove.Though these methods seem very effective prospect that also has very much, but for for example with contact layer, clearance wall (spacer) wait provide external stress to raceway groove when producing needed strain, apply the efficient that technology that external stress produces strain may depend on Stress Transfer mechanism.Therefore, for different transistor types, must provide different stress cover layers, this can cause increasing a plurality of extra processing steps.Particularly, if the processing step that increases is a lithography step, whole production cost is significantly increased.
Therefore, the technology in channel region generation strain of present more widespread usage is the technology of a kind of being called as " stress memory ".In the middle fabrication stage of semiconductor device, near gate electrode, form a large amount of amorphized areas, above transistor area, form stressor layers then, in the presence of this stressor layers, can make this amorphized areas recrystallization.During being used to make the annealing process of lattice recrystallization, under the stress that this stressor layers produces, strained lattice can be grown up and produce to crystal.Behind recrystallization, removable this stressor layers (therefore this stressor layers is also referred to as " sacrifice " stressor layers), and in the lattice part of recrystallization, still can keep some dependent variables.Though the mechanism that this effect produces is understanding fully as yet at present, a large amount of experiments confirm, can produce the strain of a certain degree in the polysilicon gate electrode that covers, even after the layer (being sacrificial stress layer) of initiation stress removed, this strain still can exist.Because grid structure is still being kept some dependent variable after removing this primary stress layer, corresponding strain also can be transferred to the crystal block section of growing up again, thereby also can keep certain a part of initial strain.
This stress memory technique helps combining with other " permanent " strain initiating accident sequence, for example is subjected to the contact etching stopping layer of stress, strained embedded semiconductor material or the like, so that increase the whole efficiency of strain initiating mechanism.But, this may need extra lithography step to come the extra sacrificial stress layer relevant with transistor types carried out composition, thereby whole production cost is increased.Stress memory technique can bring out the channel region of stress transfer to MOSFET, improves the element characteristics of advanced technologies (for example 65 nanometer technologies) whereby.
Traditional employing stress memory technique (SMT) is made the method for semiconductor device 100 shown in Figure 1A to 1F.Shown in Figure 1A, a substrate 101 is provided, material can be chosen as monocrystalline substrate.Deposition one deck gate oxide 102 on substrate 101 can be chosen as and utilize oxidation technology temperature in the oxygen steam ambient to form gate oxide 102 down about 800～1000 degrees centigrade.On gate oxide 102, deposit one deck doped polysilicon layer then with the chemical vapor deposition (CVD) method.Etching gate oxide 102 and polysilicon layer form gate electrode 103.Then, shown in Figure 1B, with CVD method deposition clearance wall insulating barrier 104A and 104B, this moment can be simultaneously at first insulating barrier 105 of the back side of substrate 101 growth with sample ingredient on the sidewall of grid oxic horizon 102, gate electrode 103 and above the substrate 101, and material can be chosen as SiO
2Then, shown in Fig. 1 C, form clearance wall 106A and 106B on the sidewall of clearance wall insulating barrier 104A and 104B, this moment is generation second insulating barrier 107 below first insulating barrier 105 simultaneously, and material can be chosen as SiN.Then implement ion implantation technology and form source/drain electrode 112A and 112B.Next, shown in Fig. 1 D, deposit layer of oxide layer as etching stopping layer 108 at clearance wall 106A and above the 106B with the CVD method, its thickness is 30～200 dusts.Then, with the heavily stressed induced layer 109 of CVD method deposition one deck, formation condition is on etching stopping layer 108, and the air pressure of source gas is 5torr, and power is 100w, and the source gas that is adopted is preferably SiH
4, NH
3With N
2Mist.SiH
4Flow velocity be 50sccm, NH
3Flow velocity be 3200sccm, N
2Flow velocity be 10000sccm, temperature is 480 degrees centigrade, pressure is 900MPa.Wherein, sccm is under the standard state, the flow of 1 atmospheric pressure, 25 degrees centigrade of following per minutes 1 cubic centimetre (1ml/min) just, 1torr ≈ 133.32 Pascals.Then, shown in Fig. 1 E, coating one deck has the photoresist (not shown) of pattern on semiconductor device, carries out photoetching, imposes etching step with heavily stressed induced layer 109 thinnings, becomes heavily stressed induced layer 109 '.Then, carry out cineration technics, remove the photoresist (not shown).This semiconductor device 100 is imposed rapid thermal annealing (RTA) technology, and its technological temperature scope is 1000～1100 degrees centigrade.At last, shown in Fig. 1 F, adopt wet etching method that the heavily stressed induced layer 109 ' and the etching stopping layer 108 of thinning are removed, etching solution is for example selected phosphoric acid solution, and second insulating barrier 107 and first insulating barrier 105 of substrate 101 dorsal parts also are removed simultaneously.
Traditional employing stress memory technique methods of making semiconductor devices can produce the phenomenon that photoresist is poisoned, and this is owing to adopting SiH
4, NH
3With N
2In the time of as the heavily stressed induced layer of source gas aggradation 109, following reaction takes place:
SiH
4+ N
2+ NH
3→ SiN+ accessory substance
Above-mentioned reaction can produce a kind of NH of containing
3Alkaline accessory substance, after having applied photoresist on the surface of SiN, this alkaline accessory substance can react with light in photoresist acid composition, produces a kind of macromolecular compound with viscosity, attached to the surface of photoresist in ensuing lithography step.This material is difficult to remove by the method for etching, ashing and/or chemical stripping, the follow-up pattern formation of result is no longer determined by photoresist and photoresist reprocessing may become difficulty or impossible, promptly so-called " photoresist poisoning " phenomenon.During development, the exposing patterns district of the photoresist layer that the photoresist poisoning causes has photoresist profile or the structure with non-homogeneous sidewall, when using positive photoresist, photoresist is poisoned and is usually caused forming the photoresist base, or just in the photoresist line broadening that adopts on the substrate.When using negative photoresist, may cause the photoresist pinching, this is owing to form the non-homogeneous sidewall of photoresist profile at photolithographic exposure and after developing on below the substrate, after the etching, this photoresist base or photoresist pinching problem will cause the imperfect transfer of photoresist pattern to following layer.As shown in Figure 2, originally unusual skew has taken place in the critical size that needs, and narrows down to 140nm from 180nm, and this can produce serious process deviation, will to after the performance of the semiconductor device made exert an influence, this situation does not wish to occur.
Therefore, need a kind of method, can effectively stop in stress memory technique owing to forming the photoresist poisoning problem that the SiN layer causes, so that reduction semiconductor device production cost improves yields.
Summary of the invention
Introduced the notion of a series of reduced forms in the summary of the invention part, this will further describe in the embodiment part.Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range of attempting to determine technical scheme required for protection.
In order effectively to stop the photoresist poisoning problem that in stress memory technique, causes owing to formation SiN layer, the invention provides a kind of method that is used for producing the semiconductor devices, described method comprises the following steps: to provide a substrate; On described substrate, form grid oxic horizon and gate electrode; Form the clearance wall insulating barrier on the sidewall of described grid oxic horizon and described gate electrode, the dorsal part at described substrate forms first insulating barrier simultaneously; Form clearance wall on the sidewall of described clearance wall insulating barrier, the dorsal part at described first insulating barrier forms second insulating barrier simultaneously; On described substrate, form source electrode and drain electrode; On described clearance wall, form etching stopping layer; On described etching stopping layer, form heavily stressed induced layer; Described heavily stressed induced layer is carried out N
2O handles.
The method according to this invention can effectively stop in stress memory technique owing to forming the photoresist poisoning problem that the SiN layer causes, so that reduction semiconductor device production cost improves yields.
Description of drawings
Following accompanying drawing of the present invention is used to understand the present invention at this as a part of the present invention.Embodiments of the invention and description thereof have been shown in the accompanying drawing, have been used for explaining principle of the present invention.In the accompanying drawings,
Figure 1A to Fig. 1 F is the cross-sectional view that the method for traditional employing stress memory technique forms semiconductor device;
Fig. 2 is the SEM figure that photoresist is poisoned and caused the critical size skew;
Fig. 3 A to 3G is according to the NO that adopts in stress memory technique of the present invention
2The cross-sectional view of the semiconductor device of handling;
Fig. 4 is according to the N that adopts in stress memory technique of the present invention
2The photoresist SEM figure that O handles;
Fig. 5 makes according to the N that adopts in stress memory technique of the present invention
2The semiconductor device technology flow chart that O handles.
Embodiment
In the following description, a large amount of concrete details have been provided so that more thorough understanding of the invention is provided.Yet, it will be apparent to one skilled in the art that the present invention can need not one or more these details and implemented.In other example,, be not described for technical characterictics more well known in the art for fear of obscuring with the present invention.
In order thoroughly to understand the present invention, will in following description, detailed steps be proposed, so that how explanation the present invention adopts N in stress memory technique
2O handles so that solve the problem that photoresist is poisoned.Obviously, execution of the present invention is not limited to the specific details that the technical staff had the knack of of semiconductor applications.Preferred embodiment of the present invention is described in detail as follows, yet except these were described in detail, the present invention can also have other execution modes.
In order to overcome the problem of the photoresist poisoning that causes in the stress memory technique, the present invention proposes to adopt N behind the heavily stressed induced layer of deposition
2O carries out the method for in-situ treatment.With reference to Fig. 3 A to Fig. 3 G, illustrate according to the N that in stress memory technique, adopts of the present invention
2O handles so that solve the cutaway view of each step in the semiconductor device fabrication process flow process that photoresist poisons.
As shown in Figure 3A, provide a substrate 301, material can be chosen as monocrystalline substrate, comprises doping p-well region for NMOS element area (not shown).For example, complementary metal-oxide-semiconductor (CMOS) transistor comprises that nmos pass transistor is formed on the p-well region (not shown).Deposition one deck gate oxide 302 on substrate 301 can be chosen as and utilize oxidation technology temperature in the oxygen steam ambient to form gate oxide 302 down about 800～1000 degrees centigrade.On gate oxide 302, deposit one deck doped polysilicon layer then with the chemical vapor deposition (CVD) method.Etching gate oxide 302 and polysilicon layer form gate electrode 303.
Shown in Fig. 3 B, deposit clearance wall insulating barrier 304A and 304B with the CVD method on the sidewall of grid oxic horizon 302, gate electrode 303 and above the substrate 301, this moment can be simultaneously at first insulating barrier 305 of the back side of substrate 301 growth with sample ingredient, and material can be chosen as SiO
2
Then, shown in Fig. 3 C, form clearance wall 306A and 306B on the sidewall of clearance wall insulating barrier 304A and 304B, this moment is generation second insulating barrier 307 below first insulating barrier 305 simultaneously, and material can be chosen as SiN.Then implement ion implantation technology and form source/ drain electrode 312A and 312B.
Next, shown in Fig. 3 D, deposit layer of oxide layer as etching stopping layer 308 at clearance wall 306A and above the 306B with the CVD method, its thickness is 30～200 dusts.Then, with the heavily stressed induced layer 309 of CVD method deposition one deck, formation condition is on etching stopping layer 308, and the air pressure of source gas is 5torr, and power is 100w, and the source gas that is adopted is preferably SiH
4, NH
3With N
2Mist.SiH
4Flow velocity be 50sccm, NH
3Flow velocity be 3200sccm, N
2Flow velocity be 10000sccm, temperature is 480 degrees centigrade, pressure is 900MPa.Wherein, sccm is under the standard state, the flow of 1 atmospheric pressure, 25 degrees centigrade of following per minutes 1 cubic centimetre (1ml/min) just, 1torr ≈ 133.32 Pascals.
Then, shown in Fig. 3 E, after deposition has formed heavily stressed induced layer 309, do not change under the situation of the board equipment that carries out depositing operation and reative cell, will feed N in the reative cell
2O gas carries out the N of original position to the SiN layer
2O handles.That is, on heavily stressed induced layer 309, carry out passivation reaction.The source gas that is adopted is N
2The mist of O and He, N
2The O gas flow is 1000～8000sccm, and the He gas flow is 1000～8000scc.The He here is a vector gas, helps out, and does not participate in reaction.Ionization power is 100～500w, and the crystal face of reaction is 0.2～0.5 foot apart from the distance of reactor top, can adjust this distance according to the needed time of carrying out of passivation reaction.Then reacting gas is discharged reative cell.
Then, shown in Fig. 3 F, coating one deck has the photoresist (not shown) of pattern on semiconductor device, carries out photoetching, imposes etching step with heavily stressed induced layer 309 thinnings, becomes heavily stressed induced layer 309 '.Then, carry out cineration technics, remove the photoresist (not shown).This semiconductor device 300 is imposed rapid thermal annealing (RTA) technology, and its technological temperature scope is 1000～1100 degrees centigrade, and preferred temperature is about 1030～1040 degrees centigrade.
At last, shown in Fig. 3 G, adopt wet etching method that the heavily stressed induced layer 109 ' and the etching stopping layer 108 of thinning are removed, etching solution is for example selected phosphoric acid solution, and second insulating barrier 107 and first insulating barrier 105 of substrate 101 dorsal parts also are removed simultaneously.
Fig. 4 shows according to the NO that adopts in stress memory technique of the present invention
2The photoresist SEM figure that handles.As can be seen from the figure, through N
2After O handles, eliminated the phenomenon that photoresist is poisoned, required critical size does not have any change.
The flow chart of Fig. 5 shows making and adopts N according to the embodiment of the invention in stress memory technique
2The semiconductor device technology flow chart that O handles.In step 501, a substrate is provided, material can be chosen as monocrystalline substrate, deposition one deck gate oxide on substrate, deposition one deck doped polysilicon layer on gate oxide, etching gate oxide and polysilicon layer formation gate electrode then.In step 502, deposition clearance wall insulating barrier on the sidewall of grid oxic horizon, gate electrode and above the substrate, this moment can be simultaneously at first insulating barrier of the back side of substrate growth with sample ingredient.In step 503, on the clearance wall insulating layer sidewalls, form clearance wall, this moment is generation second insulating barrier below first insulating barrier simultaneously.Then implement ion implantation technology and form source/drain electrode.In step 504, the deposition layer of oxide layer is as etching stopping layer on clearance wall.Then, the heavily stressed induced layer of deposition one deck on etching stopping layer.In step 505, after the heavily stressed induced layer of deposition, in reative cell, feed N
2O carries out original position N
2O handles, and carries out passivation reaction on heavily stressed induced layer.In step 506, coating one deck has the photoresist of pattern on semiconductor device, carries out photoetching, imposes etching step with heavily stressed induced layer thinning.Then, carry out cineration technics, remove photoresist.Semiconductor device is imposed rapid thermal annealing (RTA) technology.In step 507, adopt wet etching method that the heavily stressed induced layer and the etching stopping layer of thinning are removed, etching solution is for example selected phosphoric acid solution, and second insulating barrier and first insulating barrier of substrate dorsal part also are removed simultaneously.
In stress memory technique, adopt NO according to aforesaid embodiment manufacturing
2The semiconductor device of handling can be applicable in the multiple integrated circuit (IC).According to IC of the present invention for example is memory circuitry, as random-access memory (ram), dynamic ram (DRAM), synchronous dram (SDRAM), static RAM (SRAM) (SRAM) or read-only memory (ROM) or the like.According to IC of the present invention can also be logical device, as programmable logic array (PLA), application-specific integrated circuit (ASIC) (ASIC), combination type DRAM logical integrated circuit (buried type DRAM) or other circuit devcies arbitrarily.IC chip according to the present invention can be used for for example consumer electronic products, in various electronic products such as personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera, digital camera, mobile phone, especially in the radio frequency products.
The present invention is illustrated by the foregoing description, but should be understood that, the foregoing description just is used for for example and illustrative purposes, but not is intended to the present invention is limited in the described scope of embodiments.It will be appreciated by persons skilled in the art that in addition the present invention is not limited to the foregoing description, can also make more kinds of variants and modifications according to instruction of the present invention, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (10)
1. method that is used for producing the semiconductor devices, described method comprises the following steps:
One substrate is provided;
On described substrate, form grid oxic horizon and gate electrode;
Form the clearance wall insulating barrier on the sidewall of described grid oxic horizon and described gate electrode, the dorsal part at described substrate forms first insulating barrier simultaneously;
Form clearance wall on the sidewall of described clearance wall insulating barrier, the dorsal part at described first insulating barrier forms second insulating barrier simultaneously;
On described substrate, form source electrode and drain electrode;
On described clearance wall, form etching stopping layer;
On described etching stopping layer, form heavily stressed induced layer;
Described heavily stressed induced layer is carried out N
2O handles.
2. the method that is used for producing the semiconductor devices as claimed in claim 1 is characterized in that, described method also comprises:
The described heavily stressed induced layer of etching is so that with its thinning;
The heavily stressed induced layer of the described thinning of etching and etching stopping layer are so that remove it.
3. the method that is used for producing the semiconductor devices as claimed in claim 1 is characterized in that, the composition of described first insulating barrier is SiO
2
4. the method that is used for producing the semiconductor devices as claimed in claim 1 is characterized in that, the composition of described second insulating barrier is SiN.
5. the method that is used for producing the semiconductor devices as claimed in claim 1 is characterized in that, the composition of described heavily stressed induced layer is SiN.
6. the method that is used for producing the semiconductor devices as claimed in claim 1 is characterized in that, described heavily stressed induced layer is carried out original position N
2O handles and carries out in same reative cell in the step that forms heavily stressed induced layer on the described etching stopping layer.
7. the method that is used for producing the semiconductor devices as claimed in claim 1 is characterized in that, described heavily stressed induced layer is carried out original position N
2The gas that O handles also comprises vector gas He.
8. the method that is used for producing the semiconductor devices as claimed in claim 7 is characterized in that, described N
2The O gas flow is 1000～8000sccm, and the He gas flow is 1000～8000scc, and ionization power is 100～500w, and the crystal face of reaction is 0.2～0.5 foot apart from the distance of reactor top.
9. integrated circuit that comprises the semiconductor device that the method for claim 1 makes, described integrated circuit is selected from random access memory, dynamic random access memory, synchronous RAM, static RAM, read-only memory, programmable logic array, application-specific integrated circuit (ASIC) and buried type DRAM, radio-frequency devices.
10. electronic equipment that comprises the semiconductor device that the method for claim 1 makes, wherein said electronic equipment is selected from personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera and digital camera.
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|---|---|---|---|
| CN2009101962686A CN102024706B (en) | 2009-09-22 | 2009-09-22 | Method for manufacturing semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009101962686A CN102024706B (en) | 2009-09-22 | 2009-09-22 | Method for manufacturing semiconductor device |
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| Publication Number | Publication Date |
|---|---|
| CN102024706A true CN102024706A (en) | 2011-04-20 |
| CN102024706B CN102024706B (en) | 2012-06-20 |
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ID=43865855
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|---|---|---|---|
| CN2009101962686A Expired - Fee Related CN102024706B (en) | 2009-09-22 | 2009-09-22 | Method for manufacturing semiconductor device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102446742A (en) * | 2011-08-29 | 2012-05-09 | 上海华力微电子有限公司 | Method for preventing photoresist from losing efficacy in double-stress silicon nitride process |
| CN104217944A (en) * | 2014-09-15 | 2014-12-17 | 上海华力微电子有限公司 | Manufacture method of semiconductor device |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113725164B (en) | 2020-05-26 | 2023-07-04 | 长鑫存储技术有限公司 | Capacitor hole forming method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10326837A (en) * | 1997-03-25 | 1998-12-08 | Toshiba Corp | Semiconductor integrated circuit device and manufacture thereof, semiconductor device and manufacture thereof |
| US6680240B1 (en) * | 2002-06-25 | 2004-01-20 | Advanced Micro Devices, Inc. | Silicon-on-insulator device with strained device film and method for making the same with partial replacement of isolation oxide |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102446742A (en) * | 2011-08-29 | 2012-05-09 | 上海华力微电子有限公司 | Method for preventing photoresist from losing efficacy in double-stress silicon nitride process |
| CN104217944A (en) * | 2014-09-15 | 2014-12-17 | 上海华力微电子有限公司 | Manufacture method of semiconductor device |
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