CN100499116C - Chip package body - Google Patents
Chip package body Download PDFInfo
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- CN100499116C CN100499116C CNB200710086871XA CN200710086871A CN100499116C CN 100499116 C CN100499116 C CN 100499116C CN B200710086871X A CNB200710086871X A CN B200710086871XA CN 200710086871 A CN200710086871 A CN 200710086871A CN 100499116 C CN100499116 C CN 100499116C
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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- H01L2924/151—Die mounting substrate
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- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
- H01L2924/15155—Shape the die mounting substrate comprising a recess for hosting the device the shape of the recess being other than a cuboid
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- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H01L2924/151—Die mounting substrate
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- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
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- H01L2924/181—Encapsulation
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- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
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Abstract
This invention provides a chip package body including a loader, a silicon base plate and a first integration type passive element layer, in which, the silicon base plate includes a first surface and a second surface opposite to each other, the first conformity passive element layer is matched on the first surface and has a first pad group matched to the opposite two sides of the first integration passive element layer, in which, the density of the elements of the loader is high, and it's not necessary to add extra process devices to be integrated with the current process.
Description
Technical field
The invention relates to a kind of chip packing-body (chip package), and particularly relevant for a kind of chip packing-body with integration-type passive element layer (integrated passivedevice layer, IPD layer).
Background technology
For, high frequencyization compact in response to electronic product, modularization and multi-functional trend, electronics unit assembly is required that relatively conformability and integrated level (integration) improve.Therefore, New Times high frequency wideband material and Element Technology will be the WeiLai Technology keys.See through breakthrough, the exploitation of new technology and the integration of designing technique of new encapsulation (package) material, reached systematization module package (systeminpackage, level SIP) now.In addition, further develop high frequency chip element, integration-type passive element (integrated passive device, IPD), MEMS (micro electro mechanical system) (micro-electro-mechanical system, MEMS) and nano material technology, will be the direction that future value must be made great efforts to set up integrated building block technique and to promote high frequency wideband product usefulness.
Please refer to Fig. 1, it illustrates the schematic side view of known a kind of chip packing-body.Known chip packaging body 100 comprises a carrier 110, a plurality of chip 120 and a plurality of soldered balls 130.Carrier 110 comprises a silicon substrate 112 and an integration-type passive element layer 114.Integration-type passive element layer 114 is disposed on the silicon substrate 112, and these chips 120 are disposed on the integration-type passive element layer 114.In addition, these chips 120 are electrically connected to each other by integration-type passive element layer 114.Yet in the known chip packaging body 100, these chips 120 all are disposed on the side of integration-type passive element layer 114, so the utilization rate of the bearing space of carrier 110 is lower.In addition, owing to these chips 120 all are disposed on the side of integration-type passive element layer 114, so the height H of these soldered balls 130 can't reduce to shorten the distance of chip packing-body 100 and next level electronic installation.
Summary of the invention
The invention provides a kind of chip packing-body, the arrangements of components density of its carrier is higher.
The present invention proposes a kind of chip packing-body, and it comprises a carrier, at least one first chip and at least one second chip.Carrier comprises a silicon substrate and one first integration-type passive element layer.Silicon substrate has a first surface respect to one another and a second surface.The first integration-type passive element layer is disposed on the first surface.First chip is disposed at the relative tops, both sides (above) of the first integration-type passive element layer respectively and electrically connects the first integration-type passive element layer respectively with second chip.
The present invention proposes a kind of chip packing-body, comprising: a silicon substrate has a first surface respect to one another and a second surface; One first dielectric layer is disposed on the first surface, and wherein first dielectric layer has one the 3rd surface and one the 4th surface respect to one another, the 3rd surface contact first surface; One first connection pad group is arranged in first dielectric layer, and wherein the first connection pad flock mating places on the 3rd surface and the 4th surface; A plurality of first passive components are disposed in first dielectric layer, and wherein these first passive components electrically connect the first connection pad group; At least one first chip is electrically connected at the first connection pad group on the 3rd surface; And at least one second chip, be electrically connected at the first connection pad group on the 4th surface.Wherein first chip and second chip are disposed at the top, relative both sides of first dielectric layer respectively.
Chip packing-body of the present invention, the arrangements of components density of carrier is higher, and the process equipment that the manufacture of this chip packing-body needn't be extra and can with existing process integration.
Description of drawings
Fig. 1 illustrates the schematic side view of known a kind of chip packing-body.
Fig. 2 illustrates the schematic side view of a kind of chip packing-body of first embodiment of the invention.
Fig. 3 illustrates the schematic side view of a kind of chip packing-body of second embodiment of the invention.
Fig. 4 illustrates the schematic side view of a kind of chip packing-body of third embodiment of the invention.
Fig. 5 illustrates the schematic side view of a kind of chip packing-body of fourth embodiment of the invention.
Fig. 6 illustrates the schematic side view of a kind of chip packing-body of fifth embodiment of the invention.
Embodiment
For above-mentioned feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
Please refer to Fig. 2, it illustrates the schematic side view of a kind of chip packing-body of first embodiment of the invention.Chip packing-body 200 comprises a carrier 210 and a plurality of chips 220,230,240.Carrier 210 comprises a silicon substrate 212 and an integration-type passive element layer 214.Silicon substrate 212 has respect to one another two surperficial 212a, 212b.Integration-type passive element layer 214 is disposed on the surperficial 212a.These chips 220,230,240 are disposed at the top, relative both sides of integration-type passive element layer 214 respectively and electrically connect integration-type passive element layer 214 respectively.
Because these chips 220,230,240 are disposed at the top, relative both sides of integration-type passive element layer 214 respectively, so the bearing space of carrier 210 can fully be used.Therefore, the arrangements of components of the carrier 210 of chip packing-body 200 can have higher density.
Integration-type passive element layer 214 comprises a connection pad group 214a, a dielectric layer (dielectric layer) 214b and a plurality of passive component (passive device) 214c.Connection pad group 214a comprises at least one connection pad 214d (Fig. 2 schematically illustrates five) and at least one connection pad 214e (Fig. 2 schematically illustrates four).Dielectric layer 214b is disposed on the surperficial 212a, and dielectric layer 214b has respect to one another two surperficial 214f, 214g.The surperficial 212a of the surperficial 214f contact silicon substrate 212 of dielectric layer 214b.In addition, these connection pads 214d is disposed on the surperficial 214f.These connection pads 214e is disposed on the surperficial 214g.
In this mandatory declaration is that the material of dielectric layer 214b can be silica (siliconoxide) or polyimides (polyimide), and the material of these connection pads 214d and 214e can be metal.
In Fig. 2, carrier 210 can have at least one pothole (cavity) 216 (schematically illustrating two).These potholes 216 are arranged in the silicon substrate 212 and expose these connection pads 214d.These chips 220,230 lay respectively in these potholes 216, and are disposed on the surperficial 214f of dielectric layer 214b.And chip 240 is disposed on the surperficial 214g of dielectric layer 214b.In addition, these chips 220,230 can pass through a plurality of conductive projections (conductive bump) 222,232 and electrically connect these connection pads 214d, and chip 240 can electrically connect these weld pads 214e by a plurality of conductive projections 242.In addition, these chips 220,230 and 240 can be electrically connected to each other by integration-type passive element layer 214 according to design requirement.
But it should be noted in these potholes 216 through-silicon substrates 212 and expose these connection pads 214d.
These passive components 214c is disposed in the dielectric layer 214b and electrically connects connection pad group 214a.In detail, each passive component 214c can be electrically connected to part these connection pads 214d and part these connection pads 214e by the internal wiring 214h of integration-type passive element layer 214 or be electrically connected to part these connection pads 214d or be electrically connected to these connection pads 214e.Look closely designer's demand and decide.In addition, these passive components 214c also can be electrically connected to each other.And these passive components 214c can be resistor (resistor), capacitor (capacitor) or inductor (inductor).
Mandatory declaration be that integration-type passive element layer 214 more comprises filter (filter) or impedance transducer (balun).Filter can be low pass filter (lowpass filter) or band pass filter (band pass filter), and impedance transducer can be high-frequency converter (high-frequency transformer).
Chip packing-body 200 more comprises a plurality of soldered balls 250, and it is disposed on the surperficial 214g of integration-type passive element layer 214, and these soldered balls 250 are in order to electrically connect a printed circuit board (PCB).It must be emphasized that at this, because these chips 220,230,240 are disposed at respectively on the relative both sides of integration-type passive element layer 214 of carrier 210, so the chip 240 that the designer can be less with thickness T is disposed on the same side of integration-type passive element layer 214 with these soldered balls 250.Therefore, the height H of these soldered balls 250 ' can reduce to shorten the distance of chip packing-body 200 and printed circuit board (PCB).
The basic function mode of chip packing-body 200 is as described below.The high-frequency signal that the antenna of printed circuit board (PCB) received transfers to chip packing-body 200 via these soldered balls 250.Afterwards, a certain band signal of high-frequency signal (band signal) can be transferred to via integration-type passive element layer 214 chip 220 (for example for radio frequency chip) low noise amplifier (low noise amplifier, LNA).Afterwards, chip 220 is transferred to this band signal chip 240 (for example being the fundamental frequency chip) again and makes further signal processing.And chip 240 also a certain signal can be transferred to chip 220 power amplifier (power amplifier, PA).Then, the signal that is transmitted is after via the processing of integration-type passive element layer 214 and be transferred to the antenna of printed circuit board (PCB) by these soldered balls 250.
Please refer to Fig. 3, it illustrates the schematic side view of a kind of chip packing-body of second embodiment of the invention.The chip packing-body 300 of second embodiment is similar to the chip packing-body 200 of first embodiment.The carrier 310 of second embodiment more comprises the conductive through hole (conductive throughhole) 318 (Fig. 3 schematically illustrates three) of connection pad 317 (Fig. 3 schematically illustrates three) and at least one through-silicon substrate 312 at least one surperficial 312b that is disposed at silicon substrate 312.These connection pads 317 electrically connect the chip 350 that is disposed on the surperficial 312b.And these conductive through holes 318 electrically connect these connection pads 317 and integration-type passive element layer 314 connection pad group 314a to these connection pads of small part 314d.Therefore, the carrier 310 of second embodiment can carry more element, and in other words, the arrangements of components density of the carrier 310 of chip packing-body 300 is higher.
Please refer to Fig. 4, it illustrates the schematic side view of a kind of chip packing-body of third embodiment of the invention.The chip packing-body 400 of the 3rd embodiment is similar to the chip packing-body 300 of second embodiment.The carrier 410 of the 3rd embodiment more comprises another integration-type passive element layer 419, and it is disposed on the surperficial 412b of silicon substrate 412.In this mandatory declaration is that member, member annexation and the functional similarity of the integration-type passive element layer 414,419 of the 3rd embodiment and integration-type passive element layer 214 (see figure 2) of first embodiment are so repeat no more in this.
Among the 3rd embodiment, these chips 450,460 are disposed on the integration-type passive element layer 419 and electrically connect these connection pads 419e of connection pad group 419a.These connection pads 419d of connection pad group 419a is via these conductive through holes 418 of through-silicon substrate 412, and be electrically connected to connection pad group 414a to these connection pads of small part 414d.In other words, these chips 450,460 pass through integration-type passive element layer 419 and these conductive through holes 418, and are electrically connected to integration-type passive element layer 414.
Please refer to Fig. 5, it illustrates the schematic side view of a kind of chip packing-body of fourth embodiment of the invention.The chip packing-body 500 of the 4th embodiment is similar to the primary structure of the chip packing-body 300 of second embodiment.And these chips 520,530 are disposed on the surperficial 512b of silicon substrate 512, and see through these conductive through holes 518 to electrically connect these connection pads 517.
Please refer to Fig. 6, it illustrates the schematic side view of a kind of chip packing-body of fifth embodiment of the invention.The chip packing-body 600 of the 5th embodiment is similar to the primary structure of the chip packing-body 400 of the 3rd embodiment.And these chips 620,630 pass through integration-type passive element layer 619 and these conductive through holes 618, and are electrically connected to integration-type passive element layer 614.
In sum, chip packing-body of the present invention has following advantage at least:
One, because these chips is disposed at the top, relative both sides of the integration-type passive element layer of carrier respectively, so the bearing space of carrier can fully be used.Therefore, the arrangements of components density of carrier of the present invention is higher.
Two, since these chips be disposed at respectively on the relative both sides of integration-type passive element layer of carrier, so chip and these soldered balls that the designer can be less with thickness are disposed on the same side of integration-type passive element layer.Therefore, the height of these soldered balls can reduce to shorten the distance of chip packing-body of the present invention and next level electronic installation.
Three, the process equipment that the manufacture of chip packing-body of the present invention needn't be extra and can with existing process integration.
The above only is preferred embodiment of the present invention; so it is not in order to limit scope of the present invention; any personnel that are familiar with this technology; without departing from the spirit and scope of the present invention; can do further improvement and variation on this basis, so the scope that claims were defined that protection scope of the present invention is worked as with the application is as the criterion.
Being simply described as follows of symbol in the accompanying drawing:
100,200,300,400,500,600: chip packing-body
110,210,310,410,510,610: carrier
112,212,312,412,512: silicon substrate
114,214,314,414,419,614,619: the integration-type passive element layer
120,220,230,240,350,450,460,520,530,620,630: chip
130,250: soldered ball
212a, 212b, 214f, 214g, 312b, 412b, 512b: surface
214a, 414a, 419a: connection pad group
214b: dielectric layer
214c: passive component
214d, 214e, 314d, 317,414d, 419d, 419e, 517: connection pad
214h: internal wiring
216: pothole
222,232,242: conductive projection
318,418,518,618: conductive through hole
H, H ': highly
T: thickness.
Claims (10)
1. a chip packing-body is characterized in that, this chip packing-body comprises:
One carrier comprises:
One silicon substrate has a first surface respect to one another and a second surface; And
One first integration-type passive element layer is disposed on this first surface, and wherein this first integration-type passive element layer has one first connection pad group, and this first connection pad flock mating places on the relative both sides of this first integration-type passive element layer;
At least one first chip; And
At least one second chip, wherein this first chip is disposed at the top, relative both sides of this first integration-type passive element layer respectively and electrically connects this first integration-type passive element layer respectively with this second chip, wherein, this first chip and this second chip electrically connect this first connection pad group respectively.
2. chip packing-body according to claim 1 is characterized in that, this first connection pad group comprises:
At least one first connection pad; And
At least one second connection pad, wherein this first connection pad is disposed at respectively on the relative both sides of this first integration-type passive element layer with this second connection pad, and this first chip and this second chip electrically connect this first connection pad and this second connection pad respectively.
3. chip packing-body according to claim 1 is characterized in that, this first integration-type passive element layer comprises:
One first dielectric layer, be disposed on this first surface, wherein this first dielectric layer has one the 3rd surface and one the 4th surface respect to one another, the 3rd this first surface of surface contact, and this first connection pad flock mating places on the 3rd surface and the 4th surface, this first chip configuration is in the 3rd surface, and this second chip configuration is on the 4th surface; And
A plurality of first passive components are disposed in this first dielectric layer, and wherein said first passive component electrically connects this first connection pad group.
4. chip packing-body according to claim 1, it is characterized in that, this carrier has at least one pothole, and it is arranged in this silicon substrate and this first connection pad group of expose portion, and this first chip configuration is in this pothole and electrically connect this first connection pad group of part.
5. chip packing-body according to claim 1 is characterized in that, this carrier more comprises:
At least one the 3rd connection pad is disposed on this second surface; And
At least one conductive through hole runs through this silicon substrate and electrically connects this first connection pad group of part and the 3rd connection pad, and wherein this first chip configuration is on this second surface and electrically connect the 3rd connection pad.
6. chip packing-body according to claim 1 is characterized in that, this carrier more comprises:
One second integration-type passive element layer, be disposed on this second surface, wherein this second integration-type passive element layer has one second connection pad group, and this second connection pad flock mating places on the relative both sides of this second integration-type passive element layer, and this first chip configuration is on this second integration-type passive element layer and electrically connect this second connection pad group of part, and wherein this second integration-type passive element layer more comprises:
One second dielectric layer, be disposed on this second surface, wherein this second dielectric layer has one the 5th surface and one the 6th surface respect to one another, and the 5th this second surface of surface contact, and this second connection pad flock mating places on the 5th surface and the 6th surface, and this first chip configuration is on the 6th surface; And
A plurality of second passive components are disposed in this second dielectric layer, and wherein said second passive component electrically connects this second connection pad group; And
At least one conductive through hole runs through this silicon substrate and electrically connects this first connection pad group of part and this second connection pad group of part.
7. chip packing-body according to claim 6 is characterized in that, this second connection pad group comprises:
At least one the 3rd connection pad; And
At least one the 4th connection pad, wherein the 3rd connection pad is disposed at respectively on the relative both sides of this second integration-type passive element layer with the 4th connection pad, and this first chip electrically connects the 4th connection pad, and this conductive through hole electrically connects this first connection pad group of part and the 3rd connection pad.
8. a chip packing-body is characterized in that, this chip packing-body comprises:
One silicon substrate has a first surface respect to one another and a second surface;
One first dielectric layer is disposed on this first surface, and wherein this first dielectric layer has one the 3rd surface and one the 4th surface respect to one another, the 3rd this first surface of surface contact;
One first connection pad group is arranged in this first dielectric layer, and wherein this first connection pad flock mating places on the 3rd surface and the 4th surface;
A plurality of first passive components are disposed in this first dielectric layer, and wherein said first passive component electrically connects this first connection pad group;
At least one first chip is electrically connected at this first connection pad group on the 3rd surface; And
At least one second chip is electrically connected at this first connection pad group on the 4th surface;
Wherein this first chip and this second chip are disposed at the top, relative both sides of this first dielectric layer respectively.
9. chip packing-body according to claim 8 is characterized in that, more comprises at least one pothole, is arranged in this silicon substrate and this first connection pad group of expose portion, and this first chip configuration is in this pothole and electrically connect this first connection pad group of part.
10. chip packing-body according to claim 8 is characterized in that, more comprises;
At least one the 3rd connection pad is disposed on this second surface; And
At least one conductive through hole runs through this silicon substrate and electrically connects this first connection pad group of part and the 3rd connection pad, and wherein this first chip configuration is on this second surface and electrically connect the 3rd connection pad.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB200710086871XA CN100499116C (en) | 2007-03-21 | 2007-03-21 | Chip package body |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB200710086871XA CN100499116C (en) | 2007-03-21 | 2007-03-21 | Chip package body |
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| Publication Number | Publication Date |
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| CN101022103A CN101022103A (en) | 2007-08-22 |
| CN100499116C true CN100499116C (en) | 2009-06-10 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB200710086871XA Active CN100499116C (en) | 2007-03-21 | 2007-03-21 | Chip package body |
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| CN (1) | CN100499116C (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102064157A (en) * | 2009-11-18 | 2011-05-18 | 智邦科技股份有限公司 | System encapsulation module of wireless local area network |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1284746A (en) * | 1999-07-02 | 2001-02-21 | 国际商业机器公司 | Electronic Package for electronic element and manufacturing method thereof |
| CN1505149A (en) * | 2002-12-02 | 2004-06-16 | 华泰电子股份有限公司 | Three-dimensional packaging apparatus of multichip integrated circuit |
| CN1591885A (en) * | 2003-08-25 | 2005-03-09 | 株式会社瑞萨科技 | Manufacturing method of solid-state image sensing device |
| CN1929132A (en) * | 2006-10-11 | 2007-03-14 | 威盛电子股份有限公司 | Electronic apparatus |
-
2007
- 2007-03-21 CN CNB200710086871XA patent/CN100499116C/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1284746A (en) * | 1999-07-02 | 2001-02-21 | 国际商业机器公司 | Electronic Package for electronic element and manufacturing method thereof |
| CN1505149A (en) * | 2002-12-02 | 2004-06-16 | 华泰电子股份有限公司 | Three-dimensional packaging apparatus of multichip integrated circuit |
| CN1591885A (en) * | 2003-08-25 | 2005-03-09 | 株式会社瑞萨科技 | Manufacturing method of solid-state image sensing device |
| CN1929132A (en) * | 2006-10-11 | 2007-03-14 | 威盛电子股份有限公司 | Electronic apparatus |
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| CN101022103A (en) | 2007-08-22 |
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