CN100489631C - TFT LCD array substrate structure and its production method - Google Patents
TFT LCD array substrate structure and its production method Download PDFInfo
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- CN100489631C CN100489631C CNB2006100806418A CN200610080641A CN100489631C CN 100489631 C CN100489631 C CN 100489631C CN B2006100806418 A CNB2006100806418 A CN B2006100806418A CN 200610080641 A CN200610080641 A CN 200610080641A CN 100489631 C CN100489631 C CN 100489631C
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Abstract
The invention discloses a TFT LCD array base structure, which comprises the following parts: base, gate wire, gate electrode, gate insulating layer, semiconductor layer and datawire, wherein the insulating dielectric layer covers upper of the base, gate wire, gate electrode, gate insulating layer and semiconductor layer; the through-hole passes two sides of the insulating dielectric layer on the semiconductor layer; the Ohm contact layer is sedimented the through-hole; the pixel electrode contacts the semiconductor layer Ohm through Ohm contact layer in the hole; the source electrode and leak electrode lie on the pixel electrode. The invention also discloses a making method of TFT LCD array base structure, which simplifies the original 5Mask technique into 3Mask technique. The source and leak electrode metal layers and pixel electrode layer can be sedimented in the same or different sputtering equipments continuously, which improve the utility of sputtering equipment.
Description
Technical field
The present invention relates to a kind of Thin Film Transistor-LCD (TFT LCD) array base-plate structure and manufacture method thereof, relate in particular to TFT LCD array base-plate structure and manufacture method thereof that 3 photoetching processes of a kind of usefulness are made.
Background technology
The liquid crystal display that with TFT LCD is representative has had development at full speed as a kind of important flat pannel display mode in nearly ten years, get more and more people's extensive concerning.Because the cut-throat competition between each manufacturer and the continuous progress of TFT LCD manufacturing technology, display quality is good, and the LCD that price is more cheap is constantly introduced to the market.Therefore, adopt advanced more manufacturing technology, simplify production technology, reducing production costs becomes the important assurance that TFT LCD production firm is survived in cut-throat competition.
The manufacturing technology of TFT LCD array base palte has experienced from the evolution of 7 photoetching techniques (7Mask), 5 photoetching techniques (5Mask) up till now, and the 5Mask technology becomes the main flow that present TFT LCD array base palte is made.
Part manufacturer also begins now at 4Mask technology, the 4Mask technology is to be benchmark with the 5Mask technology, utilize gray tone photoetching (Gray Tone Mask) technology, active layer photoetching (ActiveMask) and source-drain electrode photoetching (S/D Mask) are merged into a Mask, by adjusting etching (Etch) technology, thereby finish the function of original Active Mask and S/D Mask, promptly reach the effect of twice Mask technology by Mask technology.
Gray Tone Mask technology is to use the figure that has strip (Slit) on Mask, by the interference and the diffraction effect of light, forms translucent graphics field on Mask.In exposure process, light can only partly see through translucent area.By the control exposure, shine on the photoresist after can making light by the Gray Tone zone on the Mask, photoresist can only partly be exposed, and other parts can fully be exposed.After the development, complete exposure area does not have photoresist, and fully the thickness of exposed areas photoresist will be less than complete unexposed zone, thereby forms 3-D solid structure on photoresist.By the transmitance in control Gray Tone zone, i.e. " dutycycle " of lines zone and white space can be controlled the thickness of photoresist.Thereby thisly be collectively referred to as Gray Tone Mask technology in the method for using translucent graphic on photoresist, to form the different three-D pattern of thickness on the mask blank.
The 5Mask technology comprises photoetching process 5 times, and they are respectively gate electrode photoetching (Gate Mask), active layer photoetching (Active Mask), source-drain electrode photoetching (S/D Mask), via hole photoetching (ViaHole Mask) and pixel electrode photoetching (Pixel Mask).In each Mask processing step, comprise one or many thin film deposition (Thin Film Deposition) technology and etching technics (comprising dry etching Dry Etch and wet etching Wet Etch) technology again respectively, formed the cyclic process of 5 thin film deposition → photoetching → etchings.Specific embodiment such as Fig. 2.
The typical pixel cells of the resulting TFT LCD of the 5Mask technological process array base palte that process is above as shown in Figure 1.
Although existing 5Mask or 4Mask manufacturing process technology are with respect to original 7Mask technology, in technological process, simplify greatly, plant factor and production capacity also significantly improve, but still there is the technological process complexity in it, the not high defective of production capacity and plant factor.
Summary of the invention
The present invention seeks at Developing Trend in Technology, a kind of minimizing photoetching process is provided, thereby reduce processing step, improve production capacity and reduce cost; And the raising usage ratio of equipment, reduce the process time, the TFT LCD array base-plate structure and the manufacture method thereof of enhancing productivity.
The invention provides a kind of TFT LCD array base-plate structure, comprise parts such as substrate, grid line, gate electrode, gate insulation layer, semiconductor layer and data line, the top of substrate, grid line, gate electrode, gate insulation layer and semiconductor layer is coated with insulating medium layer, there is via hole the insulating medium layer both sides that wherein are positioned at the semiconductor layer top, Ohmic contact is deposited upon in the via hole, pixel electrode is by ohmic contact layer in the via hole and semiconductor layer Ohmic contact, and source electrode and drain electrode are positioned at the top of pixel electrode.
Wherein, described ohmic contact layer is the microcrystal silicon material.Described ohmic contact layer also can be the composite bed that is made of N+a-Si layer and Mo, Cr, W or their alloying metal layer.Described data line and source electrode are structure as a whole.Described grid line and gate electrode are the monofilm of AlNd, Al, Cu, Mo, MoW or Cr, perhaps the composite membrane that is constituted for AlNd, Al, Cu, Mo, MoW and Cr combination in any.Described gate insulation layer or insulating medium layer are the monofilm of SiNx, SiOx or SiOxNy, perhaps are the composite membrane that SiNx, SiOx and SiOxNy combination in any are constituted.Described source-drain electrode or data line are the monofilm of Mo, MoW or Cr, perhaps are the composite membrane that Mo, MoW and Cr combination in any are constituted.
The present invention also provides a kind of manufacture method of TFT LCD array base-plate structure simultaneously, comprising:
Wherein, when adopting the gray tone mask plate to carry out mask in the described step 1, make the part printing opacity position that forms the corresponding mask plate of grid line and gate electrode position, form the light tight position of the corresponding mask plate in thin film transistor (TFT) position, the complete printing opacity position of the corresponding mask plate in other positions.When adopting the gray tone mask plate to carry out mask in the described step 4, make the part printing opacity position that forms the corresponding mask plate in pixel electrode position, form the light tight position of the corresponding mask plate in drain electrode, source electrode and data line position, the complete printing opacity position of the corresponding mask plate in other positions.Described step 3 is made ohmic contact layer can make PH3 carry out interfacial reaction with via hole a-Si partly under the isoionic state of H2 for feed PH3 and H2 in plasma enhanced chemical vapor deposition chamber, by the control reaction conditions, generates the uc-Si contact layer; Also can be and in the via hole mask, adopt the high temperature photoresist, when finishing, technology do not carry out photoresist lift off, directly carry out microcrystalline silicon deposition by chemical vapour deposition technique, by photoresist stripping process photoresist and the microcrystal silicon layer above the photoresist are peeled off again, thereby obtain microcrystal silicon layer in the via hole.Also can be and in the via hole mask, adopt the high temperature photoresist, when finishing, technology do not carry out photoresist lift off, by chemical vapour deposition technique deposition one deck N+a-Si, and then very thin Mo, Cr, W or their the alloying metal layer of deposition one deck, by photoresist stripping process photoresist and the N+a-Si above the photoresist and Mo, Cr, W or their alloying metal layer are peeled off again, thus obtain in the via hole N+a-Si with and Mo, Cr, W or their alloying metal layer.Adopting sputtering technology pixel deposition electrode layer and source-drain electrode metal level in the described step 4 is to carry out successive sedimentation in identical or different equipment.
The present invention and existing 5 lithographic fabrication processes relatively mainly contain following effect: 1, a kind of new the TFT LCD array base-plate structure and the manufacture method thereof that are different from existing 5Mask and 4Mask technology are provided.By being 3Mask technology, reduce the Twi-lithography process altogether, thereby reach the minimizing processing step, the purpose of enhancing productivity and reducing production costs original 5Mask work simplification; 2, by merging gate electrode photoetching and active layer photoetching, can after having deposited the grid metal level, directly carry out the deposition of gate insulation dielectric layer and semiconductor layer; By merging source-drain electrode and pixel electrode photoetching, make that source-drain electrode metal level and transparent pixels electrode layer can successive sedimentations in same sputtering equipment, thereby improve the utilization factor of sputtering equipment.So just significantly reduce the process time, improved production efficiency, thereby reach the purpose that improves production capacity and reduce production costs; 3,, adopted microcrystal silicon (uc-Si) material to realize multiple different designs (ITO is different with Mo, can not realize Ohmic contact with N+a-Si) such as Ohmic contact in order to guarantee that pixel electrode layer and semiconductor layer have good Ohmic contact.
Description of drawings
Fig. 1 is traditional TFT LCD array base palte pixel cell planar graph;
Fig. 2 is traditional 5Mask technological process;
Fig. 3 is technological process of the present invention;
The TFT LCD array base-plate structure typical pixel cells planar graph of Fig. 4 for adopting the present invention to obtain;
Fig. 5 is Fig. 4 A-A cross section figure;
Fig. 6 is Fig. 4 B-B cross section figure;
The planar graph that Fig. 7 obtains after through technologies such as first gray tone mask plate mask and etchings for the present invention;
Fig. 8 is Fig. 7 C-C cross section figure;
Fig. 9 passes through the planar graph that obtains after via hole mask and the etching for the present invention;
Figure 10 is Fig. 9 D-D cross section figure;
Figure 11 makes the cross section figure of ohmic contact layer for the present invention adopts approach (1);
Figure 12 makes the cross section figure of ohmic contact layer for the present invention adopts approach (2);
Figure 13 makes the cross section figure of ohmic contact layer for the present invention adopts approach (3).
Reference numeral:
1, substrate; 6, pixel electrode;
2, grid line and gate electrode; 7, data line;
3, gate insulation layer; 8, insulating medium layer;
4, semiconductor layer; 9, high temperature photoresist;
5, ohmic contact layer; 10, Mo (W or Cr or their alloy).
Embodiment
As shown in Figure 3, for process flow diagram of the present invention, comprise the steps:
The grid metal level that deposits in this step can be the monofilm of AlNd, Al, Cu, Mo, MoW or Cr, also can be one of AlNd, Al, Cu, Mo, MoW or Cr or composite membrane that combination in any constituted.The gate insulation dielectric layer of deposition can be the monofilm of SiNx, SiOx or SiOxNy, perhaps is one of SiNx, SiOx or SiOxNy or composite membrane that combination in any constituted
The insulating medium layer that deposits in this step can be the monofilm of SiNx, SiOx or SiOxNy, perhaps is one of SiNx, SiOx or SiOxNy or composite membrane that combination in any constituted.
In order to realize that pixel electrode is the Ohmic contact of source-drain electrode and semiconductor layer, several different approaches below main the employing:
(1) in plasma enhanced chemical vapor deposition chamber, feeds PH3 and H2, make PH3 under the isoionic state of H2, carry out interfacial reaction with via hole semiconductor layer partly, by the control reaction conditions, in via hole, generate microcrystal silicon layer, thereby be that the pixel electrode of next step deposition realizes that by microcrystal silicon layer and semiconductor layer Ohmic contact is ready.
(2) in the mask lithography of step 2, adopt the high temperature photoresist, when finishing, technology do not carry out photoresist stripping process, directly carry out microcrystalline silicon deposition by the plasma enhanced chemical vapor deposition method, by the photoresist lift off technology photoresist and the microcrystal silicon layer above the photoresist are peeled off again, thereby obtain and the identical structure of approach (1), for the pixel electrode that deposits later realizes that by microcrystal silicon layer and semiconductor layer Ohmic contact is ready.
(3) in the mask lithography of step 2, adopt the high temperature photoresist, when finishing, technology do not carry out photoresist stripping process, by plasma enhanced chemical vapor deposition method deposition one deck N+a-Si, and then very thin MO (or Cr or W or their alloys) metal level of deposition one deck, by the photoresist glass technology with N+a-Si on photoresist and the photoresist and Mo (or Cr, W or their alloys) metal level peels off, obtain and approach (1) and (2) similar structure, for the pixel electrode of back is got ready by MO (or Cr or W or their alloy) metal level and N+a-Si and semiconductor layer realization Ohmic contact.
The source-drain electrode metal level that deposits in this step can be the monofilm of Mo, MoW or Cr, perhaps is one of Mo, MoW or Cr or composite membrane that combination in any constituted.
Obtain as Fig. 4 through above-mentioned steps, Fig. 5 and TFT LCD array base-plate structure shown in Figure 6, comprise the grid line and the gate electrode 2 that are formed on the substrate 1, gate insulation layer 3 and semiconductor layer 4, its feature that is different from prior art is mainly: substrate 1, grid line and gate electrode 2, the top of gate insulation layer 3 and semiconductor layer 4 is coated with insulating medium layer 8, and there is via hole insulating medium layer 8 both sides that are positioned at semiconductor layer 4 tops, ohmic contact layer 5 is deposited in this via hole, pixel electrode 6 is by ohmic contact layer in the via hole 5 and semiconductor layer 4 Ohmic contact, source electrode and drain electrode are positioned at the top of pixel electrode 6, and data line 7 is structure as a whole with the source electrode.And ohmic contact layer 5 also can be the composite bed that is made of N+a-Si layer and Mo, Cr, W or their alloying metal layer except adopting the microcrystal silicon material.Grid line and gate electrode 2 can be the monofilm of AlNd, Al, Cu, Mo, MoW or Cr, also can be one of AlNd, Al, Cu, Mo, MoW or Cr or composite membrane that combination in any constituted.Gate insulation layer 3 or insulating medium layer 8 can be the monofilm of SiNx, SiOx or SiOxNy, also can be one of SiNx, SiOx or SiOxNy or composite membrane that combination in any constituted.Source-drain electrode or data line 7 can be the monofilm of Mo, MoW or Cr, also can be one of Mo, MoW or Cr or composite membrane that combination in any constituted.
Below, describe the preferred manufacture method of the present invention in detail with reference to accompanying drawing.
The manufacture method of TFT LCD array base-plate structure of the present invention comprises:
(1) as shown in figure 11.By PH3 under H2 Plasma condition with step 2 in the a-Si layer of the via hole that forms carry out interfacial reaction and generate uc-Si
(2) as shown in figure 12.When in step 2, carrying out the via hole mask, adopt high temperature photoresist 9, behind exposure and etching formation via hole, the high temperature photoresist of not peeling off 9, using plasma strengthens chemical vapour deposition technique, deposition one deck uc-Si
To not need part uc-Si layer and photoresist lift off to fall by photoresist lift off (Lift Off) technology again, thereby in the only remaining via hole part uc-Si layer be arranged.
(3) as shown in figure 13.When carrying out the via hole mask in step 2, adopt high temperature photoresist 9, after technologies such as exposure and etching formed via hole, the high temperature photoresist of not peeling off 9, using plasma strengthened chemical vapour deposition technique deposition one deck N+a-Si
Sputtering method deposition one deck Mo10 (Cr or W or their alloy)
, (Lift Off) technology of peeling off is with photoresist again fallen unwanted N+a-Si layer and Mo metal level (Cr or W or their alloy) and photoresist lift off, thereby in the only remaining via hole part N+a-Si layer and Mo metal level (Cr or W or their alloy) is arranged.
Adopt the manufacture method of 3Mask technology by above method, obtained complete tft array substrate structure, reducing processing step, when reducing production costs and enhancing productivity, improve Sputter efficiency of equipment and utilization factor, a kind of new manufacture method that is different from the TFT LCD array base-plate structure that has 5Mask technology and 4Mask technology now is provided simultaneously.
Present embodiment has only provided realizes a kind of embodiment of the present invention, but device architecture in this scheme and the scheme and process conditions can change, but this variation can not depart from the TFT part of Gate electrode and a-Si forms ITO pixel electrode layer and the successive sedimentation of S/D electrode layer and the spirit and the category that adopt Gray Tone technology to form under same Mask under same Mask.
Claims (14)
1. TFT LCD array base-plate structure, comprise substrate, grid line, gate electrode, gate insulation layer, semiconductor layer and data line, it is characterized in that: the top of described substrate, grid line, gate electrode, gate insulation layer and semiconductor layer is coated with insulating medium layer, there is via hole the insulating medium layer both sides that wherein are positioned at the semiconductor layer top, Ohmic contact is deposited upon in the via hole, pixel electrode is by ohmic contact layer in the via hole and semiconductor layer Ohmic contact, and source electrode and drain electrode are positioned at the top of pixel electrode.
2, array base-plate structure according to claim 1 is characterized in that: described ohmic contact layer is the microcrystal silicon material.
3, array base-plate structure according to claim 1 is characterized in that: the composite bed of described ohmic contact layer for being made of N+a-Si layer and Mo, Cr, W or their alloying metal layer.
4, according to the arbitrary described array base-plate structure of claim 1 to 3, it is characterized in that: described data line and source electrode are structure as a whole.
5, according to the arbitrary described array base-plate structure of claim 1 to 3, it is characterized in that: described grid line and gate electrode are the monofilm of AlNd, Al, Cu, Mo, MoW or Cr, perhaps the composite membrane that is constituted for AlNd, Al, Cu, Mo, MoW and Cr combination in any.
6, according to the arbitrary described array base-plate structure of claim 1 to 3, it is characterized in that: described gate insulation layer or insulating medium layer are the monofilm of SiNx, SiOx or SiOxNy, perhaps are the composite membrane that SiNx, SiOx and SiOxNy combination in any are constituted.
7, according to the arbitrary described array base-plate structure of claim 1 to 3, it is characterized in that: described source, drain electrode or data line are the monofilm of Mo, MoW or Cr, perhaps are the composite membrane that Mo, MoW and Cr combination in any are constituted.
8, a kind of manufacture method of TFT LCD array base-plate structure is characterized in that, comprising:
Step 1, adopt sputtering technology on substrate, to deposit the grid metal level, adopt chemical vapour deposition technique to deposit gate insulation dielectric layer and semiconductor layer successively then, utilize the gray tone mask plate to carry out mask and etching, form grid line, gate electrode, gate insulation layer and thin film transistor (TFT) semiconductor layer part;
Step 2 on the substrate of completing steps one, adopts chemical vapour deposition technique deposition insulating medium layer, carries out via hole mask and etching technics, forms the via hole of the insulating medium layer both sides that are positioned at the semiconductor layer top;
Step 3 is made ohmic contact layer in step 2 formation via hole;
Step 4 on the substrate of completing steps three, adopts sputtering technology pixel deposition electrode layer, the source-drain electrode metal level, utilize the gray tone mask plate to carry out mask and etching, form pixel electrode, source electrode, drain electrode and data line, wherein the drain electrode of Xing Chenging is that one links to each other with data line.
9, manufacture method according to claim 8, it is characterized in that: when adopting the gray tone mask plate to carry out mask in the described step 1, make the part printing opacity position that forms the corresponding mask plate of grid line and gate electrode position, form the light tight position of the corresponding mask plate in thin film transistor (TFT) position, the complete printing opacity position of the corresponding mask plate in other positions.
10, manufacture method according to claim 8, it is characterized in that: when adopting the gray tone mask plate to carry out mask in the described step 4, make the part printing opacity position that forms the corresponding mask plate in pixel electrode position, form the light tight position of the corresponding mask plate in drain electrode, source electrode and data line position, the complete printing opacity position of the corresponding mask plate in other positions.
11, manufacture method according to claim 8, it is characterized in that: described step 3 is made ohmic contact layer and is specially feeding PH3 and H2 in plasma enhanced chemical vapor deposition chamber, make PH3 under the isoionic state of H2, carry out interfacial reaction with via hole a-Si partly, by the control reaction conditions, generate the uc-Si contact layer.
12, manufacture method according to claim 8, it is characterized in that: described step 3 is made ohmic contact layer and is specially employing high temperature photoresist in the via hole mask, when finishing, technology do not carry out photoresist lift off, directly carry out microcrystalline silicon deposition by chemical vapour deposition technique, by photoresist stripping process photoresist and the microcrystal silicon layer above the photoresist are peeled off again, thereby obtain microcrystal silicon layer in the via hole.
13, manufacture method according to claim 8, it is characterized in that: described step 3 is made ohmic contact layer and is specially employing high temperature photoresist in the via hole mask, when finishing, technology do not carry out photoresist lift off, by chemical vapour deposition technique deposition one deck N+a-Si, and then the very thin Mo of deposition one deck, Cr, W or their alloying metal layer, again by photoresist stripping process with photoresist and N+a-Si above the photoresist and Mo, Cr, W or their alloying metal layer peel off, thus obtain in the via hole N+a-Si with and Mo, Cr, W or their alloying metal layer.
14, manufacture method according to claim 8 is characterized in that: adopting sputtering technology pixel deposition electrode layer and source-drain electrode metal level in the described step 4 is to carry out successive sedimentation in identical or different equipment.
Priority Applications (8)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100806418A CN100489631C (en) | 2006-05-23 | 2006-05-23 | TFT LCD array substrate structure and its production method |
| US11/737,954 US7952099B2 (en) | 2006-04-21 | 2007-04-20 | Thin film transistor liquid crystal display array substrate |
| KR1020070039430A KR100898694B1 (en) | 2006-04-21 | 2007-04-23 | Tft lcd array substrate and manufacturing method thereof |
| JP2007113400A JP2007294970A (en) | 2006-04-21 | 2007-04-23 | Tft-lcd array substrate and its manufacturing method |
| US13/096,380 US8354305B2 (en) | 2006-04-21 | 2011-04-28 | Thin film transistor liquid crystal display array substrate and manufacturing method thereof |
| JP2011103041A JP5564464B2 (en) | 2006-04-21 | 2011-05-02 | TFT-LCD array substrate and manufacturing method thereof |
| US13/735,166 US8642404B2 (en) | 2006-04-21 | 2013-01-07 | Thin film transistor liquid crystal display array substrate and manufacturing method thereof |
| US14/056,199 US20140038371A1 (en) | 2006-04-21 | 2013-10-17 | Thin film transistor liquid crystal display array substrate and manufacturing method thereof |
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| CNB2006100806418A CN100489631C (en) | 2006-05-23 | 2006-05-23 | TFT LCD array substrate structure and its production method |
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| CN100489631C true CN100489631C (en) | 2009-05-20 |
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Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI481029B (en) | 2007-12-03 | 2015-04-11 | 半導體能源研究所股份有限公司 | Semiconductor device |
| CN101807586B (en) | 2009-02-13 | 2013-07-31 | 北京京东方光电科技有限公司 | TFT-LCD (Thin Film Transistor Liquid Crystal Display) array substrate and manufacturing method thereof |
| CN101957526B (en) * | 2009-07-13 | 2013-04-17 | 北京京东方光电科技有限公司 | TFT-LCD (Thin Film Transistor-Liquid Crystal Display) array substrate and manufacturing method thereof |
| CN102508385A (en) * | 2011-11-17 | 2012-06-20 | 华映视讯（吴江）有限公司 | Pixel structure, array substrate and manufacturing method thereof |
| CN102810558B (en) * | 2012-08-07 | 2014-10-15 | 京东方科技集团股份有限公司 | Thin film transistor, array substrate and preparation methods of thin film transistor and array substrate, and liquid crystal display |
| US9530808B2 (en) | 2013-09-12 | 2016-12-27 | Boe Technology Group Co., Ltd. | TFT array substrate, manufacturing method thereof, and display device |
| CN103474399B (en) * | 2013-09-12 | 2015-12-02 | 北京京东方光电科技有限公司 | Tft array substrate manufacture method and tft array substrate, display device |
| CN103762218A (en) * | 2014-01-16 | 2014-04-30 | 北京京东方光电科技有限公司 | Array substrate, manufacturing method thereof and display device |
| CN105629598B (en) * | 2016-03-11 | 2018-12-11 | 深圳市华星光电技术有限公司 | The array substrate and production method of FFS mode |
| CN105974620A (en) * | 2016-06-17 | 2016-09-28 | 京东方科技集团股份有限公司 | Method for manufacturing substrate, substrate and display device |
| CN109375441B (en) * | 2018-12-21 | 2022-03-01 | 信利半导体有限公司 | Substrate routing structure and routing manufacturing method |
| TWI681530B (en) * | 2019-02-01 | 2020-01-01 | 力士科技股份有限公司 | Metal-oxide-semiconductor device |
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