CN100426511C - Baseplate structure of thin film transistor device array, and preparation method - Google Patents

Baseplate structure of thin film transistor device array, and preparation method Download PDF

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Publication number
CN100426511C
CN100426511C CNB2006100829725A CN200610082972A CN100426511C CN 100426511 C CN100426511 C CN 100426511C CN B2006100829725 A CNB2006100829725 A CN B2006100829725A CN 200610082972 A CN200610082972 A CN 200610082972A CN 100426511 C CN100426511 C CN 100426511C
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China
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film
photoresist
source
via hole
grid
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CNB2006100829725A
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Chinese (zh)
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CN101093845A (en
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龙春平
赵继刚
林承武
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北京京东方光电科技有限公司
京东方科技集团股份有限公司
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Priority to CNB2006100829725A priority Critical patent/CN100426511C/en
Priority claimed from KR1020070061491A external-priority patent/KR100846974B1/en
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Abstract

The structure of basal plate for thin film transistor (TFT) device array includes transparent insulated substrate, a set of continuous data lines, and a set of intermittent grid lines (IGL). The grid lines are disconnected at interjunction place with data lines. There are via holes to expose metal thin film (MTF) of source and drain poles at two ends of IGL. Through via holes, conductive film connects IGL. Data lines are covered by dull protective film. Via hole of exposing MTF is formed near to TFT device. Via hole of exposing MTF of source and drain poles is formed above them. Through via hole above the source pole, connection data lines etc, and the source pole is connected to data lines. Through via hole above the drain pole, the drain pole is connected to pixel poles. The invention also discloses method for manufacturing the basal plate. Features are: reducing number of mask plates and photo etching procedures, and simplifying TFT-LCD preparation to 2-Mask processes.

Description

A kind of baseplate structure of thin film transistor device array and manufacture method thereof

Technical field

The present invention relates to a kind of liquid crystal display device (LCD), relate in particular to the baseplate structure of thin film transistor device array and the manufacture method thereof of LCD.

Background technology

In liquid crystal display device, the optical anisotropy of liquid crystal molecule and polarization characteristic change by the orientation of controlling liquid crystal molecule.The oriented of liquid crystal molecule changes along with applying external electric field thereon.By changing the orientation of liquid crystal molecule, realize the refraction of light and the demonstration of image.In various liquid crystal display devices, active matrix liquid crystal display has attracted a large amount of research and development inputs owing to the superiority of its high definition and animation demonstration, and is obtaining application widely aspect consumer electronics and the computer.Thin film transistor comprises thin-film transistor (TFT) and the pixel electrode that is arranged in matrix form.

Usually LCD is made up of a upper substrate, an infrabasal plate and the liquid crystal that is sandwiched between the two.Upper substrate is so-called color membrane substrates, generally includes public electrode and colored filter.Infrabasal plate is so-called array base palte, generally includes thin-film transistor and pixel electrode.Color membrane substrates can be by the colored filter of photoetching process formation for several times.Array base palte typically uses 4 to 6 mask (Mask), a few step iterative process such as peels off through the exposure of thin film deposition, mask and corrosion, forms the thin-film transistor and the pixel electrode of arranged.The Mask that uses in the array base palte manufacture process is many more and operation is many more, and fraction defective and cost are just high more.

Fig. 1 a to 1d has illustrated a kind of 4-Mask manufacture process with array base palte of bottom grating structure, back of the body raceway groove corrosion type TFT.At first deposition one deck grid metallic film on glass substrate utilizes the grid line mask to form grid line and gate electrode 2 by photoetching process, as shown in Figure 1a.The grid metallic film is constituting by molybdenum, aluminium, aluminium nickel etc. or they usually.Secondly at other All Ranges of grid metal and substrate, deposit grid insulating film, intrinsic semiconductor film, doped semiconductor films and source continuously successively and leak metallic film, utilize second mask to form the TFT device, shown in Fig. 1 b by photoetching process.Grid insulating film constitutes the dielectric of TFT switching device as gate insulator 3.Its material generally is silica or silicon nitride or silicon oxynitride or their combination.Semiconductor layer 4 is made up of intrinsic semiconductor film and doped semiconductor films.The normally plain amorphous silicon of intrinsic semiconductor film, the conducting channel 1 of formation charge carrier.Doped semiconductor films generally is the doped n type amorphous silicon, compares with plain amorphous silicon, has lower resistivity, can form low-resistance ohmic contact with metal.Leak in the metallic film in the source, form the data wire that the control pixel voltage signal is provided, the source electrode 5 and the drain electrode 6 of TFT device.Metallic film employing and grid metal materials similar are leaked in the source, as molybdenum, aluminium nickel etc.

Metal electrode and active layer isolated island are leaked in the source of formation shown in Fig. 1 b, need to use a kind of gray tone (Gray Tone) mask that is called.Normally used Mask forms complete light transmission part and complete lightproof part above the mask, their form and the needed identical patterns of device.Its complete lightproof part generally is made up of metallic film (as chromium), and the light transmission part then is not have metallic film fully.The GrayTone mask then is the zone that has increased the part printing opacity, promptly arranges the crack of certain width and spacing in certain zone of mask in order.Because the diffraction of incident light causes the variation of light transmittance, thereby the photoresist of counterpart transmission region accepts to be different from the exposure of complete transmission region, forms so-called photoresist (Gray Tone) zone of partly exposing.Be compared to photoresist unexposed fully (Full Tone) zone, Gray Tone zone photoresist is owing to accept the part exposure, and its thickness is less than the photoresist in Full Tone zone.

Utilize the gray tone mask to form one deck photoresist pattern on metallic film is leaked in the source, wherein the photoresist in GrayTone zone covers TFT raceway groove 1, photoresist cover data line, source electrode 5 and the drain electrode 6 in Full Tone zone.At first carry out the source and leak the etching of metallic film, remove data wire, source electrode 5, drain electrode 6 and TFT raceway groove and leak metallic film in the source of all parts in addition.Remove the photoresist and the photoresist that keeps a part of Full Tone zone in the Gray Tone zone of TFT channel part then, continuous corrosion is removed the source leakage metallic film and the doped semiconductor films of TFT channel part, forms TFT raceway groove 1.

Deposition one deck dielectric on the substrate that forms gate electrode, active layer isolated island, data wire and source-drain electrode.Use common mask, on the passivation layer 7 on drain electrode top, form passivation layer via hole 8 by photoetching process, shown in Fig. 1 c.

At the conductive film of the other parts deposition layer of transparent of the drain electrode 6 at passivation layer 7, passivation layer via hole 8 places and substrate, use the mask of pixel electrode, form pixel electrode 9 by photoetching process, shown in Fig. 1 d.So far, utilize 4 mask to finish the making of array base palte.

To finish the array base palte manufacture craft with respect to 5 traditional mask simple although above-mentioned 4 mask are finished the making of array base palte, and utilization rate of equipment and installations increases, but still has complex manufacturing technology, the not high defective of production capacity and utilization rate of equipment and installations.

Summary of the invention

The objective of the invention is defective, a kind of baseplate structure of thin film transistor device array and manufacture method thereof of using 2 mask to make is provided at prior art.Wherein, providing the purpose of 2-Mask manufacturing process is to avoid aforementioned 5-Mask or relevant defective and the restriction of 4-Mask method.Further explain, the objective of the invention is to simplify the manufacturing process flow of tft array substrate, reduce the defective in the technical process, to improve the yield of product.Further again, the objective of the invention is by reducing the number of times of Mask technology, to improve usage ratio of equipment and production capacity.

To achieve these goals, the invention provides a kind of baseplate structure of thin film transistor device array, comprising:

The transparent insulation substrate;

One group of continuous data wire leaks metallic film by the source identical with the thin-film transistor source-drain electrode and constitutes;

One group of interrupted grid line disconnects with data wire intersection;

Grid line top is coated with grid insulating film, intrinsic semiconductor film and passivation protection film;

There is the via hole that exposes the grid metallic film at interrupted grid line two ends, and the conductive film that connects grid line couples together interrupted grid line by via hole;

The data wire below remains with grid metallic film, grid insulating film, intrinsic semiconductor film and doped semiconductor films, is coated with the passivation protection film on the data wire, and is forming the via hole that source of exposure leaks metallic film near the film transistor device place;

Thin-film transistor is formed at the zone of grid line top near data wire, and its source electrode and drain electrode leak metallic film by the source to be formed, and the pattern of source electrode and drain electrode is within gate electrode, intrinsic semiconductor film and the doped semiconductor films pattern fully; Source electrode, drain electrode and raceway groove top all are coated with the passivation protection film, form the via hole that source of exposure leaks metallic film above source electrode, the drain electrode, the source electrode is connected with data wire by the via hole of source electrode top, the conductive film that connects data wire and source electrode, the via hole that reaches on the data wire; Drain electrode is connected with pixel electrode by the via hole of its top.

Wherein said pixel electrode, connect grid line conductive film, and to connect data wire identical with the material of the conductive film of source electrode.

To achieve these goals, the present invention also provides a kind of manufacture method of baseplate structure of thin film transistor device array simultaneously, comprising:

On the transparent insulation substrate successively, successive sedimentation grid metallic film, grid insulating film, intrinsic semiconductor film, doped semiconductor films and source leak metallic film;

Using first gray tone mask to leak in the source to define on the metallic film forms the complete reserve area of photoresist, photoresist part reserve area and does not have the photoresist zone;

Carry out the corrosion that metallic film, doped semiconductor films, intrinsic semiconductor film, grid insulating film and grid metallic film are leaked in the source successively, continuously, form data wire;

Remove the photoresist of photoresist part reserve area, the photoresist of the complete reserve area of reserve part photoresist, carry out the corrosion that metallic film and doped semiconductor films are leaked in the source successively, form channel part and the source electrode and the drain electrode of segmented grid line and TFT device;

Deposition passivation protection film uses second gray tone mask to define on the passivation protection film and forms the complete reserve area of photoresist, photoresist part reserve area and do not have the photoresist zone;

Carry out the passivation protection film and cross pitting corrosion, form via hole, the via hole on data wire top, the via hole on electrode top, source and the via hole on drain electrode top at grid line two ends;

Remove the photoresist of photoresist part reserve area, the photoresist of the complete reserve area of reserve part photoresist, deposition layer of transparent conductive film on substrate then;

Remove residue photoresist and the conductive film on it, keep the conductive film that connects grid line, connect data wire and the conductive film of source electrode and the conductive film of pixel electrode area.

Wherein, first gray tone mask of described use is leaked in the source when definition forms the complete reserve area of photoresist, photoresist part reserve area and do not have the photoresist zone on the metallic film, makes the complete reserve area correspondence of photoresist form the data wire zone, form the source electrode zone and form the drain electrode zone; Corresponding TFT channel region and the formation grid region of forming of photoresist part reserve area; Other parts are no photoresist zone.Second gray tone mask of described use defines on the passivation protection film when forming the complete reserve area of photoresist, photoresist part reserve area and not having the photoresist zone, makes the corresponding connection of photoresist part reserve area grid line part, connects data wire and source electrode part and pixel electrode area; Via hole, the via hole on data wire top, the via hole on electrode top, source and the via hole on drain electrode top at corresponding grid line two ends, no photoresist zone; Other parts are the complete reserve area of photoresist.Described successive sedimentation grid metallic film, grid insulating film, intrinsic semiconductor film, doped semiconductor films and source leakage metallic film are realized in distinct device, wherein grid metallic film and source leakage metallic film obtains by sputtering sedimentation, and grid insulating film, intrinsic semiconductor film and doped semiconductor films obtain by chemical vapor deposition.The described corrosion of carrying out continuously leaking metallic film, doped semiconductor films, intrinsic semiconductor film, grid insulating film and grid metallic film in the source realizes in distinct device, wherein metallic film is leaked by wet etching in grid metallic film and source, and grid insulating film, intrinsic semiconductor film and doped semiconductor films are finished by dry etching.The described corrosion of carrying out continuously leaking metallic film, doped semiconductor films, intrinsic semiconductor film, grid insulating film and grid metallic film in the source can be carried out dry etching to each tunic and realize by changing etchant gas and etching condition in same equipment.The described passivation protection film that carries out is crossed pitting corrosion for to be made up of the burn into intrinsic semiconductor film and the grid insulating film continuous corrosion of passivation protection film, and the corrosion of semiconductive thin film is different with the etchant gas and the etching condition of insulation film as previously mentioned.Described carrying out carried out quarter when the passivation protection film is crossed pitting corrosion, to form via hole, the via hole on data wire top, the via hole on electrode top, source and the via hole on drain electrode top at grid line two ends simultaneously.Described removal photoresist part reserve area photoresist is removed for using plasma etching method cineration technics.Described removal residue photoresist and the conductive film on it are for adopting liftoff stripping technology, stripper only carries out chemical reaction with photoresist, do not corrode other material that comprises transparent conductive film, transparent conductive film on the photoresist is peeled off and is removed with photoresist, and stripper is the mixed liquor of acetone, isopropyl alcohol, alcohol or above-mentioned solvent, perhaps the mixing material of other organic stripper.Described first gray tone mask and second gray tone mask, its lightproof part comprises the double-layer films material, and the semi light transmitting part branch comprises thin film material layer, and the light transmission part does not have above-mentioned thin-film material fully.The thin-film material of semi-transparent part can be a chromium oxide, and the thin-film material of lightproof part can be chromium and chromium oxide.The semi-transparent zone of described first gray tone mask and second gray tone mask includes the slit and the fillet of certain orientation and spacing.

As mentioned above, utilize gray tone (Gray Tone) mask technique and photoresist lift off (Lift-off) technology, only use 2 mask and Twi-lithography technology to finish the making of the array base palte of liquid crystal display device.Manufacturing process is simplified like this, has reduced production cost.In above-mentioned array base palte, being connected of the connection of grid line, source electrode and data wire and being connected of grid line lining portion, data wire lining portion and external circuit all are to be realized by transparent conductive film in second Gray Tone mask photoetching process.

Below in conjunction with the drawings and specific embodiments, the present invention is further elaborated.

Description of drawings

Fig. 1 a is the cross-sectional view of TFT after first Mask technology of prior art 4Mask manufacturing process is finished;

Fig. 1 b is the cross-sectional view of TFT after second Mask technology of prior art 4Mask manufacturing process is finished;

Fig. 1 c is the cross-sectional view of TFT after the 3rd Mask technology of prior art 4Mask manufacturing process is finished;

Fig. 1 d is the cross-sectional view of TFT after the 4th Mask technology of prior art 4Mask manufacturing process is finished;

Fig. 2 is the single pixel vertical view of TFT-LCD array base palte of the present invention;

Fig. 3 a is the cross-sectional view of A-A direction among Fig. 2;

Fig. 3 b is the cross-sectional view of B-B direction among Fig. 2;

Fig. 4 finishes the pixel vertical view behind the photoresist pattern of first Gray Tone for the present invention;

Fig. 5 a is the cross-sectional view of C-C direction among Fig. 4;

Fig. 5 b is the cross-sectional view of D-D direction among Fig. 4;

Fig. 6 finishes the pixel vertical view after the photoetching process of first Mask for the present invention;

Fig. 7 a is the cross-sectional view of E-E direction among Fig. 6;

Fig. 7 b is the cross-sectional view of F-F direction among Fig. 6;

Fig. 8 finishes the pixel vertical view behind the photoresist pattern of second Gray Tone for the present invention;

Fig. 9 a is the cross-sectional view of G-G direction among Fig. 8;

Fig. 9 b is the cross-sectional view of H-H direction among Fig. 8;

Figure 10 a finishes after second Mask photoetching process the cross-sectional view of G-G direction among Fig. 8 for the present invention;

Figure 10 b finishes after second Mask photoetching process the cross-sectional view of H-H direction among Fig. 8 for the present invention;

Figure 11 finishes the post-depositional pixel vertical view of conductive film for the present invention;

Figure 12 a be among Figure 10 I-I to cross-sectional view;

Figure 12 b is the cross-sectional view of J-J direction among Figure 10;

Mark among the figure: 1, TFT raceway groove; 2, gate electrode; 3, gate insulator; 4, semiconductor layer; 5, source electrode; 6, drain electrode; 7, passivation layer; 8, passivation layer via hole; 9, pixel electrode; 10, the pixel electrode at via hole place; 11, grid line; 12, grid line protuberance; 13, data wire; 17, the via hole at grid line two ends; 18, the conductive film that connects grid line; 19, the via hole on data wire top; 20, the via hole on source electrode top; 21, the via hole on drain electrode top; 22, the conductive film that connects data wire and source electrode; 25, grid metallic film; 26, grid insulating film; 27, intrinsic semiconductor film; 28, doped semiconductor films; 29, ohmic contact layer; 30, form the photoresist of grid region; 31, form the photoresist in data wire zone; 32, form the photoresist of source electrode zone; 33, form the photoresist in drain electrode zone; 34, form the photoresist of TFT channel region; 35, no photoresist zone; 36, metallic film is leaked in the source; 38, the via hole on grid line top does not have the photoresist part; 39, the via hole on data wire top does not have the photoresist part; 40, the via hole on source electrode top does not have the photoresist part; 41, the via hole on drain electrode top does not have the photoresist part; 42, the photoresist that connects the grid line part; 43, the photoresist that connects data wire and source electrode part; 44, the photoresist of pixel region; 45, the photoresist of the complete reserve area of photoresist; 48, the conductive film of pixel region; 49, passivation protection film; 50, the conductive film on photoresist top.

Embodiment

Shown in Fig. 2, Fig. 3 a and Fig. 3 b, a kind of baseplate structure of thin film transistor device array of the present invention comprises grid line 11 and perpendicular data wire 13.Grid line 11 and data wire 13 be pixel region of intersection definition mutually.The thin-film transistor of each pixel is formed at the zone of grid line 11 tops near data wire 13.Thin-film transistor comprises a gate electrode 2, source electrode 5, drain electrode 6, gate insulator (grid insulating film 26), an intrinsic semiconductor film 27 and a doped semiconductor films 28.A storage capacitance is formed between grid line protuberance 12 and the pixel electrode 9.Pixel electrode 9 is connected with drain electrode 6 by the via hole 21 on drain electrode top.Each data wire 13 all is continuous on substrate, and each grid line 11 all is discontinuous, is cut off by data wire 13, and the via hole 17 by the grid line two ends is connected by the conductive film 18 that connects grid line.Source electrode 5 is positioned at the top of gate electrode, the via hole 20 by electrode top, source, connects data wire and the conductive film 22 of source electrode and the via hole 19 on data wire top and links to each other with data wire 13.

Fig. 3 a and Fig. 3 b are respectively along the cross-sectional view of A-A and B-B face among Fig. 2.

As shown in the figure, grid metallic film 25 is formed on the transparent substrates, and the grid metal is made of low resistivity material and very high reflectivity arranged.Grid insulating film 26 and intrinsic semiconductor film 27 are covered in the zone of all grid metallic films 25, have only except the grid outer lead liner part.Ohmic contact layer 29 is made up of doped semiconductor films 28, and doped semiconductor films 28 only is retained in the source and leaks metallic film 36 contacted zones.

Grid line 11 essence are the part of discontinuous grid metallic film 25, and the top of grid line 11 is coated with grid insulating film 26, intrinsic semiconductor film 27 and passivation protection film 49.The via hole 17 at grid line two ends passes passivation protection film 49, intrinsic semiconductor film 27 and grid insulating film 26, exposes grid line 11.Grid line 11 is leaked the data wire 13 of metallic film 36 formation by the source and the plural layers of bottom separate.The signal of data wire 13 is to leak metallic film 36 by the source to transmit, and data wire 13 bottoms also remain with grid metallic film 25, grid insulating film 26, intrinsic semiconductor film 27 and doped semiconductor films 28, and they are inoperative to data-signal.Be coated with passivation protection film 49 on the data wire, and at the via hole 19 that is formed with data wire top near TFT device place.Zone outside data wire 13 and grid line 11 and TFT device, passivation protection film 49 bottoms do not have metallic film to exist.The all surfaces of this array base palte is by one deck dielectric film, and promptly passivation protection film 49 covers, and only draws the part opening that connects lead at some.Transparent conductive film as conductive film that connects lead and formation pixel electrode is a same material, finishes in same Mask processing step.

The TFT difference made from traditional 4-Mask technology as seen from the figure, the source electrode of this TFT device and data wire are not directly to connect together, i.e. source leakage metallic film disconnects between source electrode and data wire.Their connection is to be finished at the via hole place by transparent conductive film.It is not continuous also having the grid line of this TFT device, and disconnects at the data wire place.Interrupted grid line is to be realized at the via hole place connecting by transparent conductive film.Above-mentioned two differences and following illustrated three-layer thin-film successive sedimentation have determined array base palte to be finished by two Mask technologies.

The process for making of the array base palte of said structure illustrates with Fig. 4 to Figure 12.

Fig. 4 is to use first gray tone mask to carry out the photoresist array base palte vertical view of the different-thickness that forms after mask and the exposure technology.Fig. 5 a and Fig. 5 b are respectively the cross-sectional view of Fig. 4 along A-A and B-B.Shown in Fig. 5 a and Fig. 5 b, continuously, in turn on transparent substrates, form grid metallic film 25, grid insulating film 26, intrinsic semiconductor film 27, doped semiconductor films 28 and source and leak metallic film 36.Grid metallic film 25 leaks metallic film 36 with the source and adopts identical or similar method preparation as magnetron sputtering, and they use similar low-resistance metal material, such as molybdenum, aluminium, alumel, chromium, copper etc.Grid insulating film 26, intrinsic semiconductor film 27 and doped semiconductor films 28 can adopt identical method to form continuously on identical equipment, as chemical vapour deposition (CVD).Grid insulating film 26 uses materials such as silica, silicon nitride, silicon oxynitride, and intrinsic semiconductor film 27 and doped semiconductor films 28 adopt materials such as amorphous silicon, microcrystal silicon, polysilicon.

Shown in Fig. 4, Fig. 5 a and Fig. 5 b, use first gray tone mask to leak the photoresist pattern that metallic film 36 surfaces form in the source, it comprises the complete reserve area of photoresist (Full Tone), photoresist part reserve area (Gray Tone) and do not have the zone of photoresist.The complete reserve area of photoresist comprises: form the photoresist 31 in data wire zone, form the photoresist 32 of source electrode zone and the photoresist 33 in formation drain electrode zone; Photoresist part reserve area comprises: form the photoresist 34 of TFT channel region and form the regional photoresist 30 of grid line (comprising the grid line protuberance); Other parts are no photoresist zone 35.Gray tone mask in this step, its lightproof part comprises the double-layer films material, and the semi light transmitting part branch comprises thin film material layer, and the light transmission part does not have above-mentioned thin-film material fully, the thin-film material of semi-transparent part can be a chromium oxide, and the thin-film material of lightproof part can be chromium and chromium oxide.In addition, the semi-transparent zone of gray tone mask also can include the slit and the fillet of certain orientation and spacing.

Shown in Fig. 6, Fig. 7 a and Fig. 7 b, the corrosion of carrying out successively continuously leaking metallic film 36 in the source of burn into grid insulating film 26 of burn into intrinsic semiconductor film 27 of burn into doped semiconductor films 28 and the corrosion of grid metallic film 25 form data wire 13, source electrode 5 and drain electrode 6.Utilize photoresist ashing technology to remove the photoresist of photoresist part reserve area then, promptly form the photoresist 34 of TFT channel region and form the regional photoresist 30 of grid line (comprising the grid line protuberance), reserve part forms the photoresist 33 in the photoresist 31 in data wire zone, the photoresist 32 that forms the source electrode zone and formation drain electrode zone, carry out the corrosion of source leakage metallic film 36 and the corrosion of doped semiconductor films 28 continuously successively, form grid line 11 (comprising the grid line protuberance) and TFT raceway groove 1.The source is leaked metallic film 36 and is formed ohmic contact at the zone and the doped semiconductor films 28 of source electrode 5, drain electrode 6, obtains ohmic contact layer 29.

In the continuous corrosion process, need to use different caustic solution, corrosive liquid and etchant gas, guarantee to realize selection ratio, the angle of gradient (Profile) and the critical size (CD) of different materials.Such as in the technology that forms data wire 13, source electrode 5 and drain electrode 6, grid insulating film 26, intrinsic semiconductor film 27 and doped semiconductor films 28 can use similar method to remove, i.e. plasma etching or reactive ion etching.Adjust etching gas and etching condition, different etchant gas combination and different gas flows are selected in the corrosion that can realize this three-layer thin-film in same equipment from gases such as sulphur hexafluoride, chlorine, oxygen, helium, can realize the corrosion of above-mentioned different films in same equipment.As sulphur hexafluoride, chlorine and helium etching semiconductor film; Sulphur hexafluoride, oxygen and helium etching insulation film; Chlorine and oxygen corroding metal film.For the optimization of reaching device architecture and the high efficiency of technology, the etching condition of different films such as plasma power, air pressure, electrode spacing etc. are distinguished to some extent.The corrosion of semiconductive thin film is generally carried out in than low pressure and more powerful plasma cavity, has the effect of stronger ion bombardment and sputtering etching; Insulation film and metallic film generally carry out in than hyperbar and lower powered slightly plasma cavity, have stronger chemical reaction ion etching effect.。As feed the sulphur hexafluoride of tens of sccm and the chlorine of thousands of sccm to equipment, with tens of millitorr air pressure, efficiently etching is removed semiconductive thin film more than thousands of watts of power; As feed the sulphur hexafluoride of hundreds of sccm and the chlorine of hundreds of sccm to equipment, with hundreds of millitorr air pressure, efficiently etching is removed insulation film below thousands of watts of power.The removal of metallic film 36 is leaked in the source, can adopt the method for chemical corrosion liquid etching, also can adopt the method for plasma etching or reactive ion etching.Hundreds of to the chlorine of thousands of sccm and the oxygen of thousands of sccm as feeding to dry etching equipment, with hundreds of millitorr air pressure, efficiently etching is removed metallic film below thousands of power.Such as when forming grid line 11 and TFT raceway groove 1, use the method and the foregoing condition of plasma etching or reactive ion etching again, can in same equipment, leak metallic film 36 and doped semiconductor layer film 28 in the continuous corrosion source.Wet etching only is used for the removal of metallic film, generally uses the mixed liquor of nitric acid, hydrochloric acid and the acetic acid of finite concentration ratio, is undertaken by immersion and spray pattern under the temperature of tens of degree.

Shown in Fig. 8 and Fig. 9 a, 9b, on the substrate of finishing first Mask technology, form one deck passivation protection film 49 and photoresist pattern.The material of passivation protection film 49 is similar to grid insulating film 26 with the preparation method.The photoresist pattern that uses second gray tone mask to form comprises the complete reserve area of photoresist, photoresist part reserve area and do not have the zone of photoresist.Photoresist part reserve area comprises: the photoresist 42, connection data wire and the photoresist 43 of source electrode part and the photoresist 44 of pixel electrode area that connect the grid line part; No photoresist zone comprises: the via hole that the via hole that the via hole that the via hole at grid line two ends does not have photoresist part 38, data wire top does not have photoresist part 39, electrode top, source does not have photoresist part 40 and drain electrode top does not have photoresist part 41; Other parts are the complete reserve area 45 of photoresist (except grid line and the data wire outside lead cushion region).Via hole 17 adjacent domains on adjacent segmented grid line 11 tops form the photoresist 42 that connects the grid line part, across data wire 13.The photoresist that forms the photoresist part reserve area that via hole 20 adjacent domains on photoresist part reserve area and electrode top, source form in the adjacent domain of the via hole 19 on data wire top links together, and becomes the photoresist 43 of continuous connection data wire and source electrode part.Via hole 21 adjacent domains on drain electrode top form the photoresist of photoresist part reserve area and the photoresist of the photoresist part reserve area that pixel region forms links together, and become the photoresist 44 of continuous pixel electrode area.Gray tone mask in this step, its lightproof part comprises the double-layer films material, and the semi light transmitting part branch comprises thin film material layer, and the light transmission part does not have above-mentioned thin-film material fully, the thin-film material of semi-transparent part can be a chromium oxide, and the thin-film material of lightproof part can be chromium and chromium oxide.In addition, the semi-transparent zone of gray tone mask also can include the slit and the fillet of certain orientation and spacing.

Carry out the corrosion of burn into intrinsic semiconductor film 27 of passivation protection film 49 and the corrosion of grid insulating film 26 continuously, at corresponding via hole 19, the via hole 20 on electrode top, source, the via hole 21 on drain electrode top and the via hole 17 at grid line two ends that forms data wire top shown in Figure 10 a and Figure 10 b in no photoresist zone.In this corrosion process, carried out carving to form each via hole simultaneously; By the selection of caustic solution and etchant gas and the control of etching condition, the source that makes is leaked metallic film 36 and is not corroded in the corrosion process of intrinsic semiconductor film 27 and grid insulating film 26.Use with first time Mask technology in the identical method of photoresist ashing technology, remove the photoresist of all photoresist part reserve areas, the photoresist of the complete reserve area of reserve part photoresist.When photoresist was carried out ashing treatment, the control process conditions made the complete reserve area 45 residual photoresists of photoresist form vertical sidewall pattern.At this moment, outside originally the metallic film of the passivation layer diaphragm 49 of photoresist part reserve area and each via bottom all is exposed to.

Use with grid metallic film and source and leak the identical preparation method of metallic film, at the layer of transparent conductive film 24 of substrate Zone Full formation shown in Figure 11, Figure 12 a and Figure 12 b.Vacuum condition and the electrode and the annex thereof of control sputtering chamber make not deposit transparent conductive film on the sidewall of photoresist of the complete reserve area 45 of photoresist.Array base palte is immersed in the chemical stripping liquid, utilizes liftoff stripping technology to remove the photoresist 45 of the complete reserve area of photoresist and the transparent conductive film 50 that forms on it.Originally the conductive film of photoresist part reserve area and formation via area (former no photoresist zone) is retained, and forms the conductive film 18 that connects grid line, connects the conductive film 22 of data wire and source electrode, the conductive film 48 of pixel electrode area.Each part mentioned above couples together on whole array by corresponding via hole.Owing to do not deposit on the sidewall of the photoresist of the complete reserve area 45 of photoresist and go up transparent conductive film, common photoresist lift off liquid such as acetone, isopropyl alcohol, alcohol or their mixed liquor, just can directly corrode photoresist, and not need to use special stripper that other materials such as transparent conductive film are corroded from the side-walls of the photoresist of the complete reserve area 45 of photoresist.For peel off fully outside pixel portion and the passivation layer via hole photoresist and on the conductive film that adheres to, when carrying out stripping technology, adopt spray, vibration is rocked or ultrasonic wave etc. method is auxiliary carries out.So far, the array base palte of a kind of LCD is finished making by 2-Mask technology.

The described TFT structure of above example is not unique structure of the present invention, and variation and storage capacitance variation for the source-drain electrode shape also can realize by the manufacturing process of above-mentioned 2-Mask.Other various modifications and variations can occur in device architecture and making step aspect, and these modifications and variations do not depart from the spirit and scope of the invention.Therefore, the present invention comprises the modifications and variations that all meet claim.

It should be noted that at last, above embodiment is only unrestricted in order to technical scheme of the present invention to be described, although the present invention is had been described in detail with reference to preferred embodiment, those of ordinary skill in the art should can use different materials and equipment to realize it as required, promptly can make amendment or be equal to replacement, and not break away from the spirit and scope of technical solution of the present invention technical scheme of the present invention.

Claims (15)

1, a kind of baseplate structure of thin film transistor device array comprises:
The transparent insulation substrate;
One group of continuous data wire leaks metallic film by the source identical with the source-drain electrode of thin-film transistor and constitutes;
One group of interrupted grid line disconnects with data wire intersection;
Grid line top is coated with grid insulating film, intrinsic semiconductor film and passivation protection film;
There is the via hole that exposes the grid metallic film at interrupted grid line two ends, and the conductive film that connects grid line couples together interrupted grid line by via hole;
The data wire below remains with grid metallic film, grid insulating film, intrinsic semiconductor film and doped semiconductor films, is coated with the passivation protection film on the data wire, and is forming the via hole that source of exposure leaks metallic film near the thin-film transistor place;
Thin-film transistor is formed at the zone of grid line top near data wire, and its source electrode and drain electrode leak metallic film by the source to be formed, and the pattern of source electrode and drain electrode is within gate electrode, intrinsic semiconductor film and the doped semiconductor films pattern fully; Source electrode, drain electrode and raceway groove top all are coated with the passivation protection film, form the via hole that source of exposure leaks metallic film above source electrode, the drain electrode, the source electrode is connected with data wire by the via hole of source electrode top, the conductive film that connects data wire and source electrode, the via hole that reaches on the data wire; Drain electrode is connected with pixel electrode by the via hole of its top.
2, array base-plate structure according to claim 1 is characterized in that: described pixel electrode, connect grid line conductive film, and to connect data wire identical with the material of the conductive film of source electrode.
3, a kind of manufacture method of baseplate structure of thin film transistor device array is characterized in that, comprising:
On the transparent insulation substrate successively, successive sedimentation grid metallic film, grid insulating film, intrinsic semiconductor film, doped semiconductor films and source leak metallic film;
Using first gray tone mask to leak in the source to define on the metallic film forms the complete reserve area of photoresist, photoresist part reserve area and does not have the photoresist zone;
Carry out the corrosion that metallic film, doped semiconductor films, intrinsic semiconductor film, grid insulating film and grid metallic film are leaked in the source successively, continuously, form data wire;
Remove the photoresist of photoresist part reserve area, the photoresist of the complete reserve area of reserve part photoresist, carry out the corrosion that metallic film and doped semiconductor films are leaked in the source successively, form channel part and the source electrode and the drain electrode of segmented grid line and TFT device;
Deposition passivation protection film uses second gray tone mask to define on the passivation protection film and forms the complete reserve area of photoresist, photoresist part reserve area and do not have the photoresist zone;
Carry out the passivation protection film and cross pitting corrosion, form via hole, the via hole on data wire top, the via hole on electrode top, source and the via hole on drain electrode top at grid line two ends;
Remove the photoresist of photoresist part reserve area, the photoresist of the complete reserve area of reserve part photoresist, deposition layer of transparent conductive film on substrate then;
Remove residue photoresist and the conductive film on it, keep the conductive film that connects grid line, connect data wire and the conductive film of source electrode and the conductive film of pixel electrode area.
4, manufacture method according to claim 3, it is characterized in that: first gray tone mask of described use is leaked in the source when definition forms the complete reserve area of photoresist, photoresist part reserve area and do not have the photoresist zone on the metallic film, makes the complete reserve area correspondence of photoresist form the data wire zone, form the source electrode zone and form the drain electrode zone; Corresponding TFT channel region and the formation grid region of forming of photoresist part reserve area; Other parts are no photoresist zone.
5, manufacture method according to claim 3, it is characterized in that: second gray tone mask of described use defines on the passivation protection film when forming the complete reserve area of photoresist, photoresist part reserve area and not having the photoresist zone, makes the corresponding connection of photoresist part reserve area grid line part, connects data wire and source electrode part and pixel electrode area; Via hole, the via hole on data wire top, the via hole on electrode top, source and the via hole on drain electrode top at corresponding grid line two ends, no photoresist zone; Other parts are the complete reserve area of photoresist.
6, according to the arbitrary described manufacture method of claim 3 to 5, it is characterized in that: described successive sedimentation grid metallic film, grid insulating film, intrinsic semiconductor film, doped semiconductor films and source leakage metallic film are realized in distinct device, wherein grid metallic film and source leakage metallic film obtains by sputtering sedimentation, and grid insulating film, intrinsic semiconductor film and doped semiconductor films obtain by chemical vapor deposition.
7, according to the arbitrary described manufacture method of claim 3 to 5, it is characterized in that: the described corrosion of carrying out continuously leaking metallic film, doped semiconductor films, intrinsic semiconductor film, grid insulating film and grid metallic film in the source realizes in distinct device, wherein metallic film is leaked by wet etching in grid metallic film and source, and grid insulating film, intrinsic semiconductor film and doped semiconductor films are finished by dry etching.
8, according to the arbitrary described manufacture method of claim 3 to 5, it is characterized in that: the described corrosion of carrying out continuously leaking metallic film, doped semiconductor films, intrinsic semiconductor film, grid insulating film and grid metallic film in the source is to pass through to change etchant gas and etching condition in same equipment, each tunic is carried out dry etching realize.
9, according to the arbitrary described manufacture method of claim 3 to 5; it is characterized in that: the described passivation protection film that carries out is crossed burn into intrinsic semiconductor film and the grid insulating film continuous corrosion that pitting corrosion is the passivation protection film, and the corrosion of semiconductive thin film is different with condition with the etchant gas of insulation film.
10, according to the arbitrary described manufacture method of claim 3 to 5; it is characterized in that: described carrying out carried out quarter when the passivation protection film is crossed pitting corrosion, with the via hole that forms the grid line two ends simultaneously, the via hole on data wire top, the via hole on electrode top, source and the via hole on drain electrode top.
11, according to the arbitrary described manufacture method of claim 3 to 5, it is characterized in that: described removal photoresist part reserve area photoresist is removed for using plasma etching method cineration technics.
12, according to the arbitrary described manufacture method of claim 3 to 5, it is characterized in that: described removal residue photoresist and the conductive film on it are for adopting liftoff stripping technology, stripper only carries out chemical reaction with photoresist, do not corrode other material that comprises transparent conductive film, the transparent conductive film on the photoresist is peeled off and is removed with photoresist.
13, manufacture method according to claim 12 is characterized in that: described stripper is the mixed liquor of acetone, isopropyl alcohol, alcohol or above-mentioned solvent.
14, according to the arbitrary described manufacture method of claim 3 to 5, it is characterized in that: described first gray tone mask and second gray tone mask, its lightproof part comprises the double-layer films material, the semi light transmitting part branch comprises thin film material layer, the light transmission part does not have above-mentioned thin-film material fully, the thin-film material of semi-transparent part is a chromium oxide, and the thin-film material of lightproof part is chromium and chromium oxide.
15, according to the arbitrary described manufacture method of claim 3 to 5, it is characterized in that: the semi-transparent zone of described first gray tone mask and second gray tone mask includes the slit and the fillet of certain orientation and spacing.
CNB2006100829725A 2006-06-23 2006-06-23 Baseplate structure of thin film transistor device array, and preparation method CN100426511C (en)

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JP2007166833A JP4728292B2 (en) 2006-06-23 2007-06-25 Array substrate structure of thin film transistor liquid crystal display and manufacturing method thereof
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