CN100485695C - PI solution method based on IC package PCB co-design - Google Patents
PI solution method based on IC package PCB co-design Download PDFInfo
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- CN100485695C CN100485695C CNB200610078217XA CN200610078217A CN100485695C CN 100485695 C CN100485695 C CN 100485695C CN B200610078217X A CNB200610078217X A CN B200610078217XA CN 200610078217 A CN200610078217 A CN 200610078217A CN 100485695 C CN100485695 C CN 100485695C
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Abstract
The invention relates to the field of very large scale integrated (VLSI) circuit technique, especially a PI solving method for IC-package-PCB cooperative design for solving power supply integrity problem in back-end design, comprising: 1) building a circuit model suitable for VLSI PI analysis; 2) analyzing and extracting parasitical parameters corresponding to the circuit mode; 3) determining design indexes in the PI design; 4) utilizing EDA tool and owned algorithm model to make accurate simulation and calculation; 5) on the premise of considering power supply integrity, according to the PI design indexes and simulated results, quickly determining a proper number of I/Os of power supply.
Description
Technical field
The present invention relates to VLSI (very large scale integrated circuit) (VLSI) technical field, particularly solve the PI solution of integrated circuit (IC)-encapsulation-printed circuit board (PCB) (PCB) collaborative design of power supply integrity issue in the back end design.
Background technology
Along with the operating rate and the integrated level of integrated circuit (IC) are more and more higher, chip functions is more and more, and chip power-consumption is increasing, and the toggle frequency of unit is more and more higher, has also brought increasing of chip input and output pin simultaneously.The noise that these may cause on power supply and the ground wire cause the ic core piece performance to descend, even capability error can not be worked, this has just brought the problem of power supply integrality, can have influence on the convergence of sequential, the success of design, the size of power consumption and chip operation stable.When process dwindled, supply voltage was also descending, and had brought very big challenge also for when reducing power consumption the power supply integrality.Can effectively avoid voltage drop (IR-drop) in design process, simultaneous switching noise and electromigration power supply integrality (PI) problems such as (EM) is assurance and the necessary condition that the high-speed digital circuit chip is successfully realized.
The physical Design of past chip is in the consideration that encapsulates in early days of design, and just after chip production goes out, the shell of corresponding form is asked at the pressure welding layout of self by contact encapsulation producer, encapsulates.Along with the development of integrated circuit technique, the showing especially of power supply integrity issue, problems such as the ghost effect of encapsulation and printed circuit board (PCB) (PCB) plate level loading condition had become the key factor of influence design success or not already.Traditional design can not satisfy big number of leads, the large chip area, and the requirement of high speed device for the consideration of packaging cost and performance, should just be carried out the analysis of application environment of pcb board level, the feasibility of encapsulation and cost analysis in chip design.For guaranteeing the successful Application of chip product in the future, initial stage in physical Design just should be passed through the power supply integrity analysis, on physical location and electrical property, optimize chip design, thereby reduce iteration and expense in IC design-package design-PCB design entire product Application and Development process.
In IC-encapsulation-PCB collaborative design, function and input-output unit (IO) number that will realize at chip, at first estimate chip area, according to alternative packing forms, every parasitic parameter of encapsulation and pcb board level applicable cases are if select back-off sealing dress other packing forms in addition for use, also need to calculate pressure welding filament length degree, after the ghost effect of consideration by its introducing, the power supply integrality is analyzed, estimated the power supply/ground number and the ideal position that can meet the demands.Consider selectable packing forms and cost, select packing forms, offer physical Design and do reference, carry out placement-and-routing, carry out time series analysis.At last, after chip wiring is finished, carry out parasitic parameter for the path of key signal and extract, the encapsulation parameter that working in coordination with encapsulation manufacturer provides carries out signal integrity (SI) analysis, finishes checking.
The collaborative design of IC-encapsulation-PCB can solve many number of pins effectively, the IC design and the encapsulation problem of high performance device.From the process of collaborative design as can be seen, as Fig. 1, its core is the solution of power supply integrality.
The principal element that influences the power supply integrality has two aspects: be because power distribution system (PDS on the one hand, Power Distribution System) pressure drop that causes of the resistance of electric power loop and the electric current by resistance, the inductance and the electric current variation that are meant the PDS electric power loop on the other hand cause simultaneous switching noise, have caused ground bullet (ground bounce) and voltage sag (voltage sag).
Output unit is the simultaneous switching noise main noise source, because it is very fast to flow through the big switching current variation of its ground wire and package parasitic inductance, package parasitic inductance is also bigger, so the noise ratio that produces is more serious.Increasing when the scale of integrated circuit, concerning the deviser, be difficult to whole design is carried out the modeling and simulation of simultaneous switching noise.Therefore at the initial stage of design output unit is carried out rationally accurate modeling and simulation, it is crucial reducing its simultaneous switching noise according to the result.
Summary of the invention
The objective of the invention is to be suitable for PI synchro switch output noise realistic model of analyzing and the method for extracting the pairing parasitic parameter of circuit model of VLSI by foundation, draw a kind of PI solution based on IC-encapsulation-PCB collaborative design, can determine the number of suitable power supply ground input block fast, choose the number of synchronous output unit, the type of encapsulation, this method is fast and convenient and the result is accurate, is applicable to the power supply integrity issue that solves in the VLSI (very large scale integrated circuit).
One aspect of the present invention provides circuit model and the simplified model thereof of analyzing the synchro switch output noise, by the emulation under different condition, sums up the different factors that influence its size, is applicable to the carrying out of instructing chip design.
Another aspect of the present invention is to determine fast suitable power supply ground number.This is that the space of Bian Huaing is not too large in other words because behind basic selected encapsulated type, most of parameter is decided often, makes the whole bag of tricks that improves noise to be restricted.Physical Design person solves synchro switch output noise efficient ways, is to add enough power supply ground input-output unit (IO) synchronized switching signal is isolated, to reduce the size of noise.Can predict, the number on power supply ground is many more, and the synchro switch output noise will be more little, but in the reality, and this is unpractical for the consideration of cost and realizability.
The number of signal IO unit is determined by the logic function of design, but the number of power supply and unit, ground is determined by the physics realization that designs.Enhancing along with chip functions, need to handle increasing information, the input and output number of signal can become very big, cause area of chip to be limited by the IO limited in number, power supply and ground number of unit can make area become big too much, and area can bring the problem of timing closure too greatly again, the selection of its type and number should be satisfied area, power consumption, the requirement of the power supply integrality aspects such as noise, current density, EM of overturning synchronously obtains optimum number after balance is handled.Encapsulating the certain number of pins of shell in addition also is the factor that restriction power supply ground number increases.In actual design, will on the basis of satisfying the requirement of power supply integrality, optimize the number on power supply ground as much as possible.Hope by the PI analysis and obtain quantized value comparatively accurately.Its technical scheme is as follows:
A kind of method based on the power supply integrity issue in the solution VLSI (very large scale integrated circuit) of IC-encapsulation-PCB collaborative design that is applicable to the design of VLSI back-end physical is characterized in that this method comprises:
1) sets up based on the circuit model of analyzing the synchro switch output noise;
2) analysis and the pairing parasitic parameter of extraction circuit model are determined output load according to the PCB applied environment;
3) determine design objective in the PI design;
4) according to the IO characteristic, determine the selection of IO, self required power supply ground working current that provides was analyzed when IO was worked, and obtained the performance index of IO; Working current to logic nuclear is analyzed; Determine the output switching activity rate of chip according to functional simulation;
5) consider under the prerequisite of power supply integrality,, determine suitable power supply ground IO number fast according to PI design objective and simulation result; Wherein, simulation result is the power supply ground working current of IO, the working current of logic nuclear and the output switching activity rate of chip.
This method is applied in the circuit model based on analysis synchro switch output noise in the PI analysis, it is the practical lumped circuit parameter model that is extracted after the collaborative driving circuit of considering IC, encapsulation and PCB three, parasitic parameter effect, the output load, the influence factor that PI is analyzed that circuit model is complete considers comprehensively, is the carrying out that object that PI analyzes instructs PI in the physical Design with this circuit model.
This method is by setting up based on the circuit model of analyzing the synchro switch output noise, determine the information of output load according to the PCB applied environment, by setting up balance simultaneous switching noise, voltage drop and current density three to the influence of PI and definite mathematical relation, the means of utilizing HSPICE simulation analysis and manual calculations to combine, thus the power supply ground IO number of determining VLSI is fast guaranteed the PI of chip.
Describe PI solution in detail based on IC-encapsulation-PCB collaborative design below by giving an example.
Description of drawings
Fig. 1 is an IC-encapsulation-PCB collaborative design process flow diagram.
Fig. 2 is a circuit model figure of analyzing the synchro switch output noise.
Fig. 3 is the circuit reduction illustraton of model.
Fig. 4 is the synoptic diagram that influences of stray inductance value.
Fig. 5 is the synoptic diagram that influences of output switching element number.
Fig. 6 is the synoptic diagram that influences of decoupling capacitor.
Fig. 7 is the synoptic diagram that influences of stationary unit number.
Fig. 8 is that driving force is the simulation waveform figure of 4,8,12,16 output units.
Fig. 9 is the oscillogram of input block 3.3v and 1.8v power supply vagabond current.
Figure 10 is the oscillogram of output unit 3.3v and 1.8v power supply vagabond current.
Embodiment
Fig. 1 is an IC-encapsulation-PCB collaborative design method, is example with 0.18 micron technology, and the method that solves the power supply integrity issue is discussed particularly.
Foundation is suitable for the circuit model of the synchro switch output noise that the PI of VLSI analyzes, and is the key factor that can the decision design success at the modeling and simulating of design initial.
Input-output unit (IO) unit mainly is that the cascade by the different impact dampers of a packet size constitutes.Output unit will drive heavy load, and afterbody need pass through very big electric current, so the relative previous stages of size is much bigger, it is high that supply voltage is also wanted accordingly.Therefore actual output unit is by two different power voltage supplies and corresponding two ground are arranged.Set up model such as Fig. 2, PO represents an output unit, and 3.3V voltage is given the afterbody power supply of PO, and 1.8V voltage is given preceding what and the chip internal power supply of PO, and corresponding also have two different ground to connect.1.8V voltage comes the power ring of the logic nuclear power supply of self-supporting chip, generally all smaller by the transistor size of its power supply, the electric current that passes through is also smaller.Therefore mainly by the parasitic parameter of 3.3V power supply branch road and corresponding ground branch road thereof, the parasitic parameter of data output branch road causes the simultaneous switching noise that is risen by high-current leading.
As shown in Figure 2, power lead on the chip and ground line model are with simple RLC network (R
V, L
V, C
V) and (R
G, C
G, L
G) constitute.Welding lead (bond wires), package lead and pin (package traces and pins) are used two RLC network (R respectively
P, L
P, C
P) and (R
b, L
b, C
b) constitute.Each parameter value of these two RLC networks is decided by the type of encapsulation.PCB VCC and PCB Gnd are the power supplys of the 3.3V on the PCB and accordingly.And node Chip VDD33 and Chip Gnd are the power supplys of the 3.3V of input on the chip and accordingly.VDD and VSS are power supply and the corresponding ground to PO unit power supply 1.8V.C wherein
b, C
pValue less, the later value of connecting is littler, and the reactance that obtains is L under the clock frequency of general design at present, R more than 10 times of equivalent reactance of connecting are so these two electric capacity can be ignored.Parasitic parameter value (the R of power lead on the chip and ground wire
V, L
V, C
V) and (R
G, C
G, L
G) also very little, can ignore equally.In addition, resistance r
VAnd r
gValue also very little comparatively speaking, also can be left in the basket.So can simplify circuit such as Fig. 3, wherein BUF is an impact damper, and PO8 is an output IO unit, R
d, L
dBe the parameter of Chip Packaging power interface, R
g, L
gBe the parameter of Chip Packaging ground interface, R
w, L
wBe the parameter of Chip Packaging signaling interface, C
LIt is load capacitance.Because the influence of the parasitic parameter of the welding lead of Chip Packaging and chip pin etc., the actual voltage value of the ground port VSSD of the 3.3V power supply port VDD33 of PO8 and correspondence will not be constant ideal value.For different packaged resistances and inductance L
d, L
w, L
g, R
d, R
w, R
gValue will be different.
According to model, can obtain influencing the factor of synchro switch output noise by emulation.Conclusion is, inductance value is big more, and noise is also just big more, as Fig. 4; When the output switching element number increased, it is big that noise also becomes simultaneously, as Fig. 5; When decoupling capacitor became big, noise was also along with weakening, as Fig. 6; The number increase of static output unit also can reduce noise, and the unit of switch is many more, and static unit is few more, and noise is also just big more, as Fig. 7.
The inductance of power supply in the reduction Chip Packaging and ground pin, the number of pins such as increasing power supply ground shortens wire length, adopts better packing forms etc.The mutual coupling inductance that increases power supply and ground also can reduce the total inductance in loop; Allow the pin on power supply and ground distribute in pairs, and close as far as possible.The module big to switching frequency on the chip increases decoupling capacitor, considers that the loop inductance of high-frequency current can be very little like this, can reduce the simultaneous switching noise of chip internal to a great extent at the inner decoupling capacitor that uses of Chip Packaging.
Following step is exactly to determine the method for power supply ground IO number.Under the deep submicron process, the IO unit that power supply ground IO is divided into to the logic nuclear (CORE) of chip and periphery powers two types.When definite power supply and ground number of unit, need to calculate respectively.This routine signal input port is 138, and output port is 104.
Determine output load according to the PCB applied environment, determine the encapsulation parasitic parameter according to packing forms.Overwhelming majority load all is a cmos device, is capacitive load.The size of load will be determined according to different plate applicable cases, generally, can be used to carry out the analysis of PI by hypothesis certain experience numerical value.By the analysis to practical application, the input load of general device is below the 10pf, and PCB layout electric capacity can be estimated according to unit-area capacitance and power supply ground level area.Determine the encapsulation parasitic parameter according to packing forms; This routine input load is 10pf, power supply ground level area 300mm
2, wiring capacitance is 0.126pF*300＜40pF, is 50pf so obtain the load maximal value.Representative value in application can be made as 35pf.
The parasitic parameter of encapsulation should directly be asked for to encapsulation producer.To the various piece of Chip Packaging (package), comprise socket (socket) and pcb board level line are estimated, obtain the parasitic parameter of entire chip outside.This example is R=4 Ω, L=10nH, and electric capacity is in 1pf.
According to passing design experiences, to set for the scope that the fluctuation of supply voltage can be tolerated, this method will have enough surpluses, to guarantee the operate as normal of circuit.Perhaps select more accurate way for use, extract the simplification circuit of electric power network, carry out emulation, determine admissible voltage fluctuation threshold value.For PI, this threshold value is an of paramount importance index.
In this example, we select 5% empirical value for use.
Step 4 according to the IO characteristic, is determined the selection of IO, and self the required power supply ground working current that provides when IO worked analyzes, and obtains the performance index of IO; Utilize eda tool and own algorithm model to carry out accurate simulation calculation; Working current to logic nuclear (CORE) is analyzed; According to functional simulation, determine the output switching activity rate of chip;
According to the ability that drives capacitive load,, carry out the selection of IO according to the IO characteristic.In general, storehouse provider can provide a variety of output unit and the comparatively single input blocks of kind with different driving ability, mainly is exactly to select the type of output unit so select the problem of IO.According to the load and the parasitic parameter of step 2, in conjunction with different output units, carry out emulation, determine suitable output unit according to the result.In the design of carrying out the sequential driving, need as far as possible little transit time (transition time), but can make ground bullet (ground bounce) become serious like this, so need the compromise of a selection here, in general, it is good selecting the output unit of medium transition time.The simulation waveform that this is routine such as Fig. 8, this waveform are respectively 4,8,12,16 output unit, the simulation result when driving the 50pf load at driving force.According to aforesaid standard, should select driving force is 8 output unit, and under the 35pf load, its transition time is 3.2ns.
Self required power supply ground working current that provides when IO is worked is analyzed.Its objective is assurance normal to all IO power supply.According to frequency of operation, under the condition of a fixed load, IO is carried out emulation, obtain the oscillogram of 3.3v and the 1.8v power supply vagabond current of IO, and then instruct the selection of 3.3V power supply ground number.Fig. 9 be input block under the 50MHz frequency, the oscillogram of 3.3v and 1.8v power supply vagabond current.Figure 10 is that driving force is 8 output unit, and in the 50MHz frequency, load is 3.3v and the 1.8v power supply vagabond current oscillogram of 35pf.Reach a conclusion after the analysis, 1.8V power supply/ground is less to the current contribution of IO, and the electric current on contrast 3.3V power supply/ground can be ignored.The maximum current that obtains input block is 4mA, and the maximum current of output unit is 30mA.
In IC-encapsulation-PCB collaborative design, the initial stage of IC design is just after the RTL code is finished, just can pass through functional simulation, collaborative eda tool is finished estimating of power consumption, obtain the roughly numerical value of CORE working current,, can draw power consumption numerical value more accurately along with the carrying out of physical Design.According to the working current of CORE, just can extrapolate the demand number of chip to 1.8V power supply ground.Here, our current value of estimation is 2600mA.
According to functional simulation, determine under the normal operative condition upset rate of chip I.After carrying out functional simulation, can obtain the assembly average of upset rate according to the working condition of IO.Here we have obtained 40% maximum upset rate score.
According to the number of input block, the IO cell power consumption value that can the reference unit storehouse provides or with reference to the lowest high-current value of input block in the step 4 required power supply ground number of input block operate as normal that is guaranteed.According to the number of output unit, (IR-drop) and current density are considered the power supply ground number that guarantees that the output unit operate as normal is required for comprehensive ground bounce, voltage drop." with reference to the lowest high-current value of step 4 " arranged in the step 5, refer to the maximum current of resulting input block, be 4mA in this example.
According to the number of output unit, comprehensive ground bounce, IR-drop and current density are considered the power supply ground number that guarantees that the output unit operate as normal is required.The number that more than inputs or outputs power supply ground all should be got the maximum among the various account form gained results.
The IO cell power consumption value that this routine reference unit storehouse provides is calculated as the method for output power supply ground number: the maximum current that single 3.3V power supply can provide is 39mA, and ground is 81mA.The input block number is 138, and the input block power consumption that library file provides is 50.54mW/MHz, and the input data frequency is 80MHz, and the number that calculates at the 3.3V power supply of input block is Number1=P
Inputall/ (3.3V*I
Single)=80*50.54*138/ (3.3*39)=4.335.Computing method with reference to step 4 lowest high-current value: the required average current of input block is 4mA, and maximum upset rate is 40%, and the number that calculates required power supply is Number2=I
Inputall* toggle/I
Single=4*138*40%/39=5.661.So selecting 6 power supplys is the input block power supply.The number that can draw ground according to the method for above-mentioned selection power supply number equally should be 3.
This example is as follows from the power supply ground number that ground bounce angle is defined as the output unit power supply: general storehouse provider can be according to different stray inductance sizes, the reference point of the needed power supply of all kinds output unit ground number is provided, and all output units that add up are calculated the sum that obtains required power supply ground.It is 12 that root obtains required power supply number accordingly, and ground is 13.
Consider that from the IRDROP angle output unit power supply ground number is as follows: after the selected noise margin, according to step 2 resistance, inductance, step 4 rise time and upset rate, obtain the Maximum Transfer Unit number that single power supply can be supplied with, can the load ratio of maximum number of output total number and single power supply is the number behind the consideration IRDROP.This example is calculated as follows:
T
10-90＝3.2ns，L＝10nH，R＝4Ω，C＝35pF
I(t)×R×No
3.3＝0.15×U
No
3.3＝4.28575
No＝(104*40％)÷No
3.3＝41.6/4.28575＝9.7
Power supply ground number is 10.
Consider as follows from the current density angle.The product of output unit average current, number and upset rate can bear maximum current divided by single power supply, can required power supply number.This example draws power supply ground number and is respectively 15.
Take all factors into consideration ground bounce, IRDROP and current density, add the required number of input, select power supply ground number to be respectively 21 and 18 at last.
In physical Design, carry out power consumption analysis, according to power consumption profile, some more at the number on the bigger part power distribution ground of power consumption.IO carries out follow-up placement-and-routing after arranging and finishing, and finishes the IC-encapsulation-PCB collaborative design of considering behind the PI.
Specific embodiment
The present invention has obtained application in the IC-encapsulation-PCB of 4,500,000 DSP of the KW0501 of Microelectronic Institute collaborative design process, what it adopted is the 0.18umCMOS of SMIC technology.The result of chip testing has shown the validity and the practicality of this PI solution.
Claims (4)
1, a kind of method based on the power supply integrity issue in the solution VLSI (very large scale integrated circuit) of integrated circuit (IC)-encapsulation-printing board PCB collaborative design that is applicable to the design of VLSI (very large scale integrated circuit) VLSI back-end physical is characterized in that this method comprises:
1) sets up based on the circuit model of analyzing the synchro switch output noise;
2) analysis and the pairing parasitic parameter of extraction circuit model are determined output load according to the PCB applied environment;
3) determine design objective in the power supply integrality PI design;
4) according to input-output unit IO characteristic, determine the selection of IO, self required power supply ground working current that provides was analyzed when IO was worked, and obtained the performance index of IO; Working current to logic nuclear is analyzed; Determine the output switching activity rate of chip according to functional simulation;
5) consider under the prerequisite of power supply integrality,, determine suitable power supply ground IO number fast according to PI design objective and simulation result; Wherein, simulation result is the power supply ground working current of IO, the working current of logic nuclear and the output switching activity rate of chip.
2, method according to claim 1, it is characterized in that: be applied in the circuit model in the PI analysis based on analysis synchro switch output noise, it is the practical lumped circuit parameter model that is extracted after the collaborative driving circuit of considering IC, encapsulation and PCB three, parasitic parameter effect, the output load, the influence factor that PI is analyzed that circuit model is complete considers comprehensively, is the carrying out that object that PI analyzes instructs PI in the physical Design with this circuit model.
3, method according to claim 1, it is characterized in that: this method is by setting up based on the circuit model of analyzing the synchro switch output noise, determine the information of output load according to the PCB applied environment, by setting up balance simultaneous switching noise, voltage drop and current density three to the influence of PI and definite mathematical relation, the means of utilizing HSPICE simulation analysis and manual calculations to combine, thus the power supply ground IO number of determining VLSI is fast guaranteed the PI of chip.
4, method according to claim 1 is characterized in that, this method specifically comprises the steps:
Step 1 is set up circuit model and the simplified model thereof of analyzing the synchro switch output noise;
Foundation is suitable for the circuit model of the synchro switch output noise that the PI of VLSI analyzes, input and output IO unit mainly is that the cascade by the different impact dampers of a packet size constitutes, output unit will drive heavy load, afterbody need pass through very big electric current, so the relative previous stages of size is much bigger, it is high that supply voltage is also wanted accordingly;
Step 2, collaborative consideration and definite IC, encapsulation and PCB three's driving circuit, parasitic parameter effect and output load;
Determine output load according to the PCB applied environment, generally, can be used to carry out the analysis of PI by hypothesis certain experience numerical value, PCB layout electric capacity can be estimated according to unit-area capacitance and power supply ground level area, determines the encapsulation parasitic parameter according to packing forms;
Step 3 according to design experiences and simulation result, is determined the design objective of PI;
According to passing design experiences, to set for the scope that the fluctuation of supply voltage can be tolerated, this method will have enough surpluses, perhaps select more accurate way for use, extract the simplification circuit of electric power network, carry out emulation, determine admissible voltage fluctuation threshold value;
Step 4 according to the IO characteristic, is carried out the selection of IO; Self required power supply ground working current that provides when IO is worked is analyzed; Utilizing eda tool and own algorithm model to carry out accurate simulation calculation analyzes the working current of logic nuclear; According to functional simulation, determine the output switching activity rate of chip, according to the load and the parasitic parameter of step 2,, carry out emulation in conjunction with different output units, determine suitable output unit according to the result;
Step 5 is determined number and the putting position of power supply ground IO;
According to the number of input block, the IO cell power consumption value that the reference unit storehouse provides or with reference to the required power supply ground number of input block operate as normal that is guaranteed of the lowest high-current value in the working current of step 4; According to the number of output unit, synthetically bullet, voltage drop and current density are considered the power supply ground number that guarantees that the output unit operate as normal is required.
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| US8949102B2 (en) | 2011-02-24 | 2015-02-03 | Cadence Design Systems, Inc. | Method and system for power delivery network analysis |
| US10289141B2 (en) | 2015-07-24 | 2019-05-14 | Industrial Technology Research Institute | Method for generating power distribution network (PDN) model, and power distribution network analysis method and device |
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