CN100479174C

CN100479174C - Telescopic-lattice chip for silicon-based tellurium-cadmium mercury device

Info

Publication number: CN100479174C
Application number: CNB2007100386647A
Authority: CN
Inventors: 胡晓宁; 李言谨; 叶振华; 何力
Original assignee: Shanghai Institute of Technical Physics of CAS
Current assignee: Shanghai Institute of Technical Physics of CAS
Priority date: 2007-03-29
Filing date: 2007-03-29
Publication date: 2009-04-15
Anticipated expiration: 2027-03-29
Also published as: CN101030591A

Abstract

The invention is concerned with the flex network structure chip of the silicon-based tellurium cadmium hydrargyrum, the chip comprising of: the Si underlay, which is set the cadmium telluride resilient coating and the tellurium cadmium hydrargyrum extending thin film on the Si underlay in turn and combines hard; forms the special network photosensitive embattle on the HgCdTe extending thin film by the device chip preparation technics, the network structure can flex automatically when the temperature changes. The advantages of the invention are: the network structure can decompose the big chip into the small chip integration with the unit of the photosensitive measure whether how is the device scale and the device size, in order that the capability of the mechanics device is foreign to the size of the scale basically, which can solve the reliability after extend the scale of the focal-plane device.

Description

The telescopic-lattice chip of silicon-based tellurium-cadmium mercury device

Technical field

The present invention relates to the chip of the basic mercury cadmium telluride of silicon (Si) (HgCdTe) infrared focal plane array device, specifically be meant the Si substrate that to alleviate chip and a kind of telescopic-lattice chip of the thermal mismatch stress between the epitaxial film HgCdTe.

Background technology

Infrared focal plane array device is not only to have had the imaging sensor that infrared information obtained but also had the advanced person of the information processing function, has important in military, civilian fields such as earth observation from space, electrooptical countermeasures, robot vision, Search/Track, medical and industrial thermal imaging and guided missile precise guidances and uses widely.

Along with improving constantly of said system demand, the development trend of infrared focal plane device is towards the development of aspects such as extensive, polychrome detection.In the development process of large area array infrared detector, it is outstanding day by day to reduce focal plane practicability technical problems such as material cost, raising device reliability.The application of Si base HgCdTe material has solved the problem of material cost well.But with respect to common material therefor CdZnTe base HgCdTe or GaAs base HgCdTe, the thermal coefficient of expansion between Si and the HgCdTe differs too big (50%), and the former about 14%.So work as material from epitaxial growth temperature (near 200 ℃) cool to room temperature (～25 ℃), again when room temperature is cooled to device working temperature (approximately-193 ℃), huge thermal mismatching between substrate Si and the HgCdTe epitaxial film makes material have very big internal stress, after temperature cycles repeatedly, can cause fault in material propagation, influence material property, cause component failure.Theory analysis shows that along with the continuous increase of device size, the internal stress that is caused by the two layers of material thermal mismatching causes that the problem of component failure is more apparent outstanding.

Summary of the invention

Based on the problem that exists on the above-mentioned existing chip structure, the objective of the invention is in order to alleviate large scale Si base proposes a kind of Telescopic-lattice with epitaxial film HgCdTe thermal mismatch stress chip.

Technical scheme of the present invention is: by not influencing under the prerequisite that each photosensitive first electrical signal of focus plane device chip draws, with between the photosensitive unit and photosensitive unit be connected by network configuration with electricity between the public electrode and realize, wear and the HgCdTe material of disconnected part and buffering layer material carved fully, the base that makes the photosensitive unit of focus plane device chip no longer is the continuously large stretch of of entire chip size level, but each little base of photosensitive unit is realized connecting by Telescopic-lattice.Can stretch more freely to alleviate the mismatch stress in the material in high low temperature circulation time network configuration like this, be about to low temperature down because the strain of the continuous large-area thin-film material that greatest differences brought of the thermal coefficient of expansion of Si and HgCdTe is converted to the strain of the tiny area of Telescopic-lattice, suppressed the dislocation multiplication in the material, make the photosensitive first performance in the entire chip scope not cause losing efficacy, thereby improve chip reliability because of thermal mismatch stress.

Device chip of the present invention comprises: the Si substrate, on the Si substrate, be equipped with the cadmium telluride buffer layer, the tellurium cadmium mercury epitaxial film that are combined with it solidly successively, the photosensitive first array and the public electrode that on the HgCdTe epitaxial film, form, it is characterized in that: between photosensitive unit and the photosensitive unit, be to form a network by photoetching and dry etching to be connected between photosensitive unit and the public electrode, the removal that is etched of the HgCdTe material of non-network connecting part, be that each photosensitive first zone has an island of one's own, between island and the island and with public electrode between be connected by network.Isolation groove width between island and the island is 2-3 μ m, and the network live width is 8-10 μ m.Structure of the present invention is suitable for photosensitive unit several 320 * 240 and above Si base HgCdTe infrared focal plane array device chip.

The advantage of the highly significant that the present invention brings is exactly, no matter the device scale has much, device size has much, the little chip that it is unit that network configuration all resolves into large chip photosensitive first yardstick equivalently integrated, the performance of device is irrelevant with scale basically on mechanics like this, thereby is hopeful to solve the integrity problem after the focal plane device scale enlarges at all.

Description of drawings

Fig. 1 is the planar structure schematic diagram of device chip of the present invention;

Fig. 2 is the A-A ' cross-sectional view of Fig. 1;

Fig. 3 is the B-B ' cross-sectional view of Fig. 1;

Fig. 4 is the C-C ' cross-sectional view of Fig. 1.

Embodiment

Below in conjunction with accompanying drawing, be that example elaborates to embodiments of the present invention with several 320 * 240 chips of photosensitive unit:

Si base HgCdTe infrared focal plane array chip of the present invention, comprise Si substrate 1, adopt the epitaxy method cadmium telluride buffer layer 2 of on the Si substrate, growing successively, HgCdTe epitaxial film 3, then by photoetching, ion injects, conventional device chip preparation technology such as surface dielectric growth forms photosensitive unit 4 arrays and public electrode 5 on the tellurium cadmium mercury epitaxial film, utilize the appointed condition on the semiconductor device technology line again, make the network configuration figure by lithography, utilization plasma dry lithographic technique is worn the HgCdTe material and the cadmium telluride buffer layer etching of non-network structure coupling part 8, be that each photosensitive first zone has an island of one's own, between island and the island and with public electrode between be connected by network, carry out the surface passivation of device chip at last.Isolation channel 6 between island and the island is wide to be 2 μ m, and grid line 7 is wide to be 9 μ m.

Lattice chip of the present invention must guarantee the electricity output of focal plane device, and promptly each photosensitive unit all becomes the tie point of network.In addition, network configuration also will satisfy two conditions: 1. injury-free, the electric property of isolation channel material around does not have modification; 2. network configuration is not too big to photosensitive first useful signal collection area effect, does not influence reading of signal.First condition relies on advanced plasma dry not damaged lithographic technique (ICP or ECR) to realize.As for second condition, the analysis showed that fully and can satisfy, the reasons are as follows: with photosensitive first number is that 320 * 240 focal plane device is an example, and its photosensitive first centre-to-centre spacing is generally 30 μ m, the PN junction district 401 of photosensitive unit is of a size of 22 μ m * 22 μ m, and the PN junction interval of photosensitive unit is divided into 8 μ m.The size of each photosensitive first response signal of infrared focal plane device is directly proportional with effective photosensitive elemental area, and effective photosensitive elemental area Aeft=(a+Lp) ²(for the photosensitive unit of square), wherein a is the photosensitive first length of side of square, Lp is a minority diffusion length.Concerning the HgCdTe material of 1-3 μ m, 3-5 μ m, three response wave band of 8-12 μ m, minority diffusion length is generally all greater than 10 μ m, so concerning photosensitive first number is 320 * 240 silica-based infrared focal plane devices, effective photosensitive elemental area reality just equal photosensitive first centre-to-centre spacing square, i.e. 30 μ m * 30 μ m.Isolation groove width between island and the island is 2 μ m, and then isolating the effective photosensitive elemental area in back is 28 * 28 μ m ²Add the grid line join domain area between the island, total effective photosensitive elemental area is about original 90%, so can think little to effect of signals, do not influence and read, 10% the loss of signal can be compensated by the time of integration of adjusting reading circuit fully, thereby does not influence the performance of focal plane device.

Claims

1. the telescopic-lattice chip of a silicon-based tellurium-cadmium mercury device, comprise: Si substrate (1), on the Si substrate, be equipped with the cadmium telluride buffer layer (2), the tellurium cadmium mercury epitaxial film (3) that are combined with it solidly successively, array and the public electrode (5) be made up of a plurality of photosensitive units (4) in that described tellurium cadmium mercury epitaxial film (3) go up to form is characterized in that:

In described photosensitive first array between each photosensitive unit (4) and the photosensitive unit (4) and form network by photoetching and dry etching between photosensitive unit (4) and the public electrode (5) and be connected, the removal that is etched of the described cadmium telluride buffer layer (2) of non-network connecting part (8), described tellurium cadmium mercury epitaxial film (3), be that each photosensitive unit (4) has an island of one's own, be connected by network between island and the island and between island and the public electrode (5); Isolation channel between island and the island (6) is wide to be 2-3 μ m, and grid line (7) is wide to be 8-10 μ m.