CN100478271C

CN100478271C - Prepn process of beam structure in nanometer width

Info

Publication number: CN100478271C
Application number: CNB200610011781XA
Authority: CN
Inventors: 范炜; 张大成; 李婷; 罗葵; 田大宇; 李静; 王颖
Original assignee: Peking University
Current assignee: Peking University
Priority date: 2006-04-25
Filing date: 2006-04-25
Publication date: 2009-04-15
Anticipated expiration: 2026-04-25
Also published as: CN1847140A

Abstract

The present invention provides the preparation process of beam structure in nanometer width, and belongs to the field of nanometer electromechanical system (NEMS) preparing technology. The technological process includes etching steps, forming side wall in nanometer width, forming beam structure in nanometer width and releasing beam structure in nanometer width. The present invention can prepare regularly shaped beam structure in nanometer width capable of being controlled accurately, and has simple technological process, no wet etching release, high preparation efficiency, high product quality and high repeatability.

Description

The preparation method of beam structure in nanometer width

Technical field

The invention belongs to naiio-electro-meclianical systems (NEMS) processing technology field, relate in particular to a kind of processing method of beam structure in nanometer width.

Background technology

Naiio-electro-meclianical systems (NEMS) is meant the system of a class microminiature electromechanical that has the nanometer technology characteristics on characteristic size and the effect.The NEMS device has many excellent characteristic, as ultra-high frequency, extra small size and quality, and ultra low power, high sensitivity and to strong control ability of surperficial adsorptivity etc.The potential great economic benefit of NEMS technology will progressively be penetrated into the every field of national economy, comprise medical technology, life science, manufacturing industry and information communication etc.NEMS is in the starting stage at present, and scientific and technical personnel all over the world just actively are devoted to the research in this field.The nanoscale girder construction is as NEMS device the most basic core texture and functional unit, plays decisive role for the development of NEMS system, as biochip and radio-frequency devices etc., all used the nanoscale girder construction in a large number.Therefore, the processing method of nanoscale girder construction is one of the primary study problem in NEMS field.People such as Hispanic Jaume Verd have used electron beam lithography to realize the lines of nano-width (Jaume Verdet al when making beam structure in nanometer width, Design, Fabrication, and Characterization of aSubmicroelectromechanical Resonator With Monolithically IntegratedCMOS Readout Circuit, Journal of Microelectromechanical System, Vol.14, No.3,2005, pp508-519), the production efficiency of this method is low, the equipment complexity, poor repeatability, yield rate is low, the cost height is not suitable for mass production.Therefore, NEMS research and application have strong demand to the processing method of the nanoscale girder construction of high rate/low cost production.

Summary of the invention

At the problems referred to above, the invention provides a kind of method that on silicon chip, prepares beam structure in nanometer width.

A kind of preparation method of beam structure in nanometer width, its step comprises:

(1) step etching: at the upper surface of silicon chip, utilize photoetching and inductively coupled plasma etching (ICP-RIE) fabrication techniques step, this step is vertical with silicon chip surface, and guarantees that its sidewall is smooth;

(2) the nano-width side wall forms: on the silicon chip surface that forms step, utilize the non-silicon materials film of chemical vapor deposition (CVD) or physical vapor deposition (PVD) growth one deck nano thickness, require the method for deposit to have the conformal spreadability, on the sidewall of step, also adhered to film after promptly deposit is finished.

The thin-film material of growth has sufficiently high selection ratio to silicon substrate under reactive ion etching (RIE) isotropic condition, as silica (SiO ₂) and aluminium (Al) etc.Because adopted the deposition process of conformal spreadability, the film of grown on the sidewall of step nano-width (10nm to 500nm) is referred to as side wall.

(3) beam structure in nanometer width forms: utilize photoetching and anisotropic reactive ion etching (RIE) technology to remove the film of local surfaces.Anisotropic reactive ion etching can only be removed the film of silicon chip upper surface and step upper surface, and has kept the nano-width film on the step sidewall, and promptly side wall is retained.The side wall that keeps is nano-width (10nm to 500nm), and this side wall is the girder construction of nano-width.

(4) beam structure in nanometer width discharges: after side wall forms, utilize isotropic reactive ion etching (as the fluorine-based plasma etching) to remove the silicon that not blocked by film.Anisotropic reactive ion etching can be removed the silicon of all directions on the silicon chip, then prop up the silicon that the position is connected admittedly and will be removed with beam structure in nanometer width is non-, and the material of beam structure in nanometer width is not a silicon, be retained in etching process and become suspension structure, this process is called the release of beam structure in nanometer width.

Shoulder height can be 2 μ m to 4 μ m in the step 1.

The material of described beam structure in nanometer width has multiple choices, as long as it has sufficiently high selection ratio to silicon substrate under reactive ion etching (RIE) isotropic condition.

Advantage of the present invention and technique effect

The present invention can process the girder construction of nano-width, accurately controls the nanoscale width of girder construction, and the girder construction regular shape, and technological process is simple, and cost is low, yield rate height, good reproducibility, efficient height.With existing semiconductor integrated circuit technique compatibility,, be fit to the production in enormous quantities of beam structure in nanometer width according to experimental results demonstrate.

Description of drawings

The reticle schematic diagram that Fig. 1 uses for process, wherein, Fig. 1 .1 is No. 1 reticle schematic diagram, and Fig. 1 .2 is No. 2 reticle schematic diagrames, and Fig. 1 .3 is the aligned relationship schematic diagram of two reticle;

Fig. 2 is the structural representation of finishing after the step etching, and wherein, Fig. 2 .1 is a vertical view, and Fig. 2 .2 is the profile along A-A ', and Fig. 2 .3 is the profile along B-B ', and Fig. 2 .4 is the profile along C-C ';

Fig. 3 for the preparation beam structure in nanometer width film growth after structural representation, wherein, Fig. 3 .1 is a vertical view, Fig. 3 .2 is the profile along A-A ', Fig. 3 .3 is the profile along B-B ', Fig. 3 .4 is the profile along C-C ';

Fig. 4 forms the back structural representation for beam structure in nanometer width, and wherein, Fig. 4 .1 is a vertical view, and Fig. 4 .2 is the profile along A-A ', and Fig. 4 .3 is the profile along B-B ', and Fig. 4 .4 is the profile along C-C ';

Fig. 5 discharges the back structural representation for beam structure in nanometer width, and wherein, Fig. 5 .1 is a vertical view, and Fig. 5 .2 is the profile along A-A ', and Fig. 5 .3 is the profile along B-B ', and Fig. 5 .4 is the profile along C-C '.

The specific embodiment

The present invention adopts the silicon chip of single-sided polishing or twin polishing to do substrate, and technological process comprises: step etching, nano-width side wall form, beam structure in nanometer width forms and beam structure in nanometer width discharges four main technique steps.With processing silica nanometer width girder construction is example, and concrete processing step is:

(1) step etching

Upper surface at silicon chip, utilizing photoetching and inductively coupled plasma etching (ICP-RIE) fabrication techniques height is the step of 2 μ m to 4 μ m, photoetching and inductively coupled plasma etching (ICP-RIE) are technology [Nadim Maluf and Kirk Williams commonly used in the micromachined, An Introductionto Microelectromechanical System Engineering, 2 ^NdEdition, ISBN:1-58053-590-9, Artech House, 2004], used No. 1 reticle shown in Fig. 1 .1 in the photoetching this time, wherein dash area is represented lighttight figure on the reticle.The vertical view of the structure of making is shown in Fig. 2 .1.The structure of making along the profile of A-A ', B-B ' and C-C ' respectively shown in Fig. 2 .2, Fig. 2 .3 and Fig. 2 .4.The 1a district is the part that is not etched, and forms the step that has an even surface.The 2a district is the part that is etched, and forms groove.

(2) the nano-width side wall forms

On the silicon chip surface that forms step, utilize the silica (SiO of low-pressure chemical vapor phase deposition (LPCVD) growth one deck nano thickness (10nm to 500nm) of conformal spreadability ₂) film.As being 720 ℃ in temperature, air pressure is 250mtorr, and deposition time is under the condition of 2min, but growth thickness is the SiO of 20nm ₂Film.LPCVD is technology [Nadim Maluf andKirk Williams, An Introduction to Microelectromechanical SystemEngineering, 2 commonly used in the micromachined ^NdEdition, ISBN:1-58053-590-9, Artech House, 2004].The vertical view of the structure of making is shown in Fig. 3 .1, and respectively shown in Fig. 3 .2, Fig. 3 .3 and Fig. 3 .4, gray area represents to have covered SiO to the structure of making among the figure along the profile of A-A ', B-B ' and C-C ' ₂Film.The 1a district is the step of silicon chip surface, and 1b is the SiO that is deposited on ledge surface ₂Film.The 2a district is the groove of silicon chip surface, and 2b is the SiO that is deposited on bottom portion of groove ₂Film.Because the conformal spreadability of LPCVD has formed special sidewall structure 3 around step.The width w of side wall 3 can be by the LPCVD technology controlling and process at nanometer scale (10nm to 500nm).

(3) beam structure in nanometer width forms

On the basis of the above, utilize photoetching and anisotropic reactive ion etching (RIE) technology to remove local SiO ₂Film.RIE is technology [Nadim Maluf and KirkWilliams, An Introduction to Microelectromechanical SystemEngineering, 2 commonly used in the micromachined ^NdEdition, ISBN:1-58053-590-9, Artech House, 2004].Used No. 2 reticle shown in Fig. 1 .2 in the photoetching this time, wherein dash area is represented lighttight figure on the reticle.Photoetching this time concerns shown in Fig. 1 .3 with the alignment of last time photoetching.The vertical view of the structure of making is shown in Fig. 4 .1, and respectively shown in Fig. 4 .2, Fig. 4 .3 and Fig. 4 .4, gray area represents to have covered SiO to the structure of making among the figure along the profile of A-A ', B-B ' and C-C ' ₂Film.The 1a district is the step of silicon chip surface, and 1b is the SiO that ledge surface does not have removal ₂Film.The 2a district is the groove of silicon chip surface, and 2b is the SiO that bottom portion of groove does not have removal ₂Film.Because this step has been used anisotropy RIE, only,, but highly diminish so not shielded side wall 3 width w in etching process does not change after the photoetching along direction etching perpendicular to silicon chip surface, form beam structure in nanometer width 3b.3b is attached to the side of step, and its two ends all are connected with 2b with 1b.3b will be released in follow-up technology, so the width w of 3b is the width of beam structure in nanometer width.

(4) beam structure in nanometer width discharges

After side wall forms, utilize the isotropism condition removal of RIE not to be subjected to SiO ₂The silicon that film blocks.Under the isotropism condition of fluorine-based plasma etching, during etch silicon silica there is high selection ratio, so this three parts earth silicon material of 1b, 2b and 3b can be etched hardly, be not subjected to SiO ₂The silicon that film blocks is formed deep-slotted

chip breaker

1c and 2c by very fast etching.The vertical view of the structure of making is shown in Fig. 5 .1, and respectively shown in Fig. 5 .2, Fig. 5 .3 and Fig. 5 .4, gray area represents to have covered SiO to the structure of making among the figure along the profile of A-A ', B-B ' and C-C ' ₂Film.Because the horizontal undercutting of isotropic etching, make the silicon of 3b side and bottom be etched and form deep-slotted chip breaker 1c, so 3b is suspended on the 1c, become the beam structure in nanometer width of release.The two ends of 3b all are connected with 2b with 1b, and 1b and 2b are attached on the silicon, so prop up admittedly for beam structure in nanometer width 3b provides both-end.The width of beam structure in nanometer width 3b is w.

Described beam structure in nanometer width two ends are fixed on the silicon substrate, and the middle part is suspended on the shallow slot of surface of silicon.

Described beam structure in nanometer width is a movable structure, and is different with width according to material, the mechanical characteristic difference of performance.When big or material stress was big when beam width, it showed as bistable state, does not promptly have under the condition of dynamic excitation, can only keep two kinds of stationary curved states, had been subjected under the condition of dynamic excitation, can conversion between two kinds of case of bendings; Less or material stress hour can free vibration on its width when the width of beam.

In sum, the invention discloses a kind of beam structure in nanometer width preparation method.Above-described application scenarios and embodiment are not to be used to limit the present invention, and any those skilled in the art without departing from the spirit and scope of the present invention, can do various changes and retouching, so protection scope of the present invention is looked the claim scope and defined.

Claims

1, a kind of preparation method of beam structure in nanometer width, its step comprises:

(1) step etching: at the upper surface of silicon chip, utilize photoetching and inductively coupled plasma etching fabrication techniques step, this step is vertical with silicon chip surface, and guarantees that its sidewall is smooth;

(2) the nano-width side wall forms: on the silicon chip surface that forms step, utilize the film of chemical vapor deposition or physical vapor deposition growth one deck nano thickness, the material of this film is silica, silicon nitride, carborundum or metal, the material that above-mentioned film adopts has sufficiently high selection ratio to silicon under isotropic reactive ion etching condition, the method of above-mentioned deposit has the conformal spreadability, on the sidewall of step, cover film after deposit is finished, forming side wall;

(3) beam structure in nanometer width forms: utilize photoetching and anisotropic reactive ion etching technology to remove the film of local surfaces, keep the side wall of nano-width on the step sidewall, form the girder construction of nano-width;

(4) beam structure in nanometer width discharges: after the girder construction of nano-width forms, utilize isotropic reactive ion etching to remove that beam structure in nanometer width is non-to prop up the silicon that the position is connected admittedly, the girder construction of nano-width keeps in etching process, and beam structure in nanometer width discharges and forms suspension structure.

2, the preparation method of beam structure in nanometer width as claimed in claim 1, it is characterized in that: step 1 further comprises: shoulder height is 2 μ m to 4 μ m.

3, the preparation method of beam structure in nanometer width as claimed in claim 1 or 2 is characterized in that:

Step 2 further comprises: the film thickness of generation is 10nm to 500nm.