CN100474619C - High voltage operating field effect transistor, bias circuit therefor and high voltage circuit thereof - Google Patents

Abstract

A high voltage operating field effect transistor is formed in an IC or LSI by utilizing a constituent portion of a transistor or a process technique for a standard power supply voltage of the IC or LSI. In order to increase an operating voltage of a field effect transistor, measures are taken in which a gate is divided into division gates, and electric potentials which are closer to a drain electric potential and which change according to increase or decrease in the drain electric potential are supplied to the division gates nearer a drain, respectively.

Description

The high-pressure work field-effect transistor, be used for this transistorized biasing circuit and high-tension circuit

The background technology of invention

1. TECHNICAL FIELD OF THE INVENTION

The present invention relates to a kind of high-pressure work field-effect transistor, be used for their biasing circuit and their high-tension circuit.The high-pressure work field-effect transistor is meant a kind of like this transistor, and this transistor is worked under than the big voltage of the transistorized withstand voltage absolute value that designs for the reference power supply voltage among IC or the LST at an absolute value.

2. the description of prior art

In the high voltage field effect transistor of routine, as shown in Figure 1, high withstand voltage drain region 380 is arranged on high withstand voltage dielectric film 480 belows, and is arranged on the high withstand voltage dielectric film 480 withstand voltage in order to improve drain electrode at the field plate 580 of high potential biasing.As shown in Figure 2, when the grid length [thereby and conformance to standard] of the field-effect transistor that in MOSIC or MOSLSI, uses when becoming the small size that is equal to or less than sub-micron, by providing the lightly doped drain zone or the drain extension 340 that are called as lightly doped drain (LDD) to design this field effect transistor, to stand reference power supply voltage.But, the impurity concentration that high withstand voltage drain region need be lower than lightly mixed drain area, or all than two of the big length of lightly mixed drain area and the degree of depth or they.For this reason, in JP2002-314044A, form high withstand voltage zones by three zones that differ from one another in conjunction with impurity concentration and the tie point degree of depth.Notice, in Fig. 1 and Fig. 2, reference marker 100 expression Semiconductor substrate, reference marker 200 expression source areas, reference marker 300 expression drain regions, reference marker 400 expression gate insulating films, and reference marker 500 expression conductive grids.

In this case, when the withstand voltage field-effect transistor of height is integrated among IC or the LSI, the manufacture process that is starved of shadow mask and is used to form high withstand voltage dielectric film and high withstand voltage drain region, this has caused expensive.In addition, although the high withstand voltage transistor that can be used to have this structure that increases, the minimizing of drive current becomes a problem.And, can be increased to improve withstand voltagely though be used for channel length normal voltage, that have the field-effect transistor of drain electrode extended structure or LDD structure, improved degree is low, and drive current almost with the channel length minimizing that is inversely proportional to.When using the gate insulating film of this field-effect transistor that is used for normal voltage, the withstand voltage withstand voltage restriction that is subjected to this dielectric film of field-effect transistor.In addition, under the transistorized situation that forms in the semiconductive thin film on the dielectric substrate of for example silicon-on-insulator (SOI), high electric field is focused in the film of drain electrode end of raceway groove.Therefore, withstand voltage and keep big output current by using prior art to increase drain electrode, many than the transistorized situation difficulty that in Semiconductor substrate, forms.

The summary of invention

Consider aforementioned factor, an object of the present invention is, by utilizing the transistor arrangement part, perhaps be used for the treatment technology of the regular transistor of under reference power supply voltage, working at IC or LSI, in IC or LSI, form the high-pressure work field-effect transistor.

In order to obtain above-mentioned purpose, in the present invention, in order to increase the field-effect transistor operating voltage of (being called " high-pressure work field-effect transistor " in the present invention), grid between source electrode and drain electrode is divided into the place of branch grid and measures, and current potential is provided for the branch grid of more close drain electrode respectively, and wherein above-mentioned each current potential more is close to drain potential and each current potential according to the increase of drain potential or reduce to change.

Being constructed as follows of first solving device.

Just, a kind of high-pressure work field-effect transistor comprises at least:

Substrate;

Mutual separated source region and drain region on the surface of substrate;

The lip-deep semiconductor channel shaped region of the substrate between source region and drain region;

Be positioned at a plurality of minutes grids of raceway groove shaped region top, this a plurality of minutes grids obtain by cutting apart in source/drain extreme direction; And

A plurality of gate insulating films between raceway groove shaped region and a plurality of minutes grids,

Wherein signal potential is provided in a plurality of minutes grids the branch grid of close source region, and bias potential is offered such branch grid respectively, promptly than the branch grid of the more close drain region of branch grid of close source region, wherein each bias potential has the absolute value of the specific potential of being equal to, or greater than, each bias potential is according to the increase of drain potential or reduce to change, and the closer to the drain region, the absolute value that is provided to each above-mentioned each bias potential that divides grid is just big more.

And then first kind of distortion described below can be used to improve frequency characteristic.

Just, in high-pressure work field-effect transistor according to first kind of solving device, divide the quantity of grid to be equal to or greater than three, first constant potential is provided for respect to the branch grid of close source region and is positioned at branch grid on the side of drain region, and bias potential is provided for the branch grid of more close drain region respectively, wherein each bias potential changes according to the increase or the minimizing of drain potential, and its absolute value is big more towards the drain region more.

In this structure, normal signal current potential Vg is provided for the branch grid G 1 of close source region.Current potential up to bias potential Vd1 offers branch grid G 2, G3....Gk respectively, wherein each current potential equals or is higher than the signal potential Vg or the first constant potential Vs1, each current potential is than the more close drain potential Vd of source potential Vs, and each current potential is according to the increase of drain potential or reduce to change, and wherein above-mentioned minute grid is with respect to the branch grid of the most close source region and be positioned on the source side.Divide the current potential absolute value of grid to be provided for these minutes grid respectively, wherein the absolute value of this current potential becomes big towards the drain region.

The first constant potential Vs1 is equal to or less than the power supply potential that is used for IC or LST.In the present invention, the signal potential Vg and the first constant potential Vs1 are called as specific potential jointly.

When the absolute value of drain potential Vd becomes when being equal to or less than the absolute value of specific potential, each current potential that offers branch grid G 2, G3....Gk can be retained as and equal or be higher than specific potential, preventing the minimizing of the driving current value in low drain potential, wherein above-mentioned minute grid is positioned on the drain side with respect to the branch grid G 1 of close source region.

In the present invention, the current potential that offers branch grid G 2, G3....Gk that each is such is called as " absolute value be equal to or higher than the absolute value of specific potential and according to the increase of drain potential or the bias potential that reduces to change ".This current potential that offers branch grid G k is represented as Vd1.

Offer the current potential Vd1 of the branch grid G k of close drain region and be current potential near drain potential Vd.Then, even when current potential Vd1 is equal to or less than Vd, perhaps even when current potential Vd1 is equal to or higher than Vd, can both obtain this effect, unless current potential Vd1 is different fully with Vd.Owing to towards the source region time, reduce to below the Vd1 in the channel potential below minute grid, wherein divide grid to be positioned on the source side with respect to the branch grid G k of close drain region, operating voltage is compared with the situation of single door standard crystal tubular construction and is improved more.

In order to adopt gate insulating film to be used for regular transistor in IC or the LSI, in transistor of the present invention, be permitted for difference between Vd and the Vd1 by the degree that increases the value that design margin obtains to supply voltage, wherein regular transistor is worked under this supply voltage.Usually, prepare two kinds of regular transistor in many cases, just, be used for the regular transistor and the regular transistor that is used for external interface of internal logic.Therefore, when high-pressure work is more preferential than current capacity, can use thick gate insulating film and voltage to be used for external interface.

The high-pressure work transistor of second kind of solving device has following structure, and wherein the source region of first kind of solving device is used as the place that signal is provided.

Just, the high-pressure work field-effect transistor comprises at least:

Substrate;

In mutual separated source region of substrate surface and drain region;

Semiconductor channel shaped region in substrate surface is to be maintained between source region and the drain region;

A plurality of branch grids above the raceway groove shaped region, this a plurality of minutes grids obtain by cutting apart in source/drain extreme direction; And

A plurality of gate insulating films between raceway groove shaped region and a plurality of minutes grids,

Wherein at least one in signal potential and the signal code is provided for the source region, first constant potential is provided in a plurality of minutes grids the branch grid of close source region, and bias potential is offered such branch grid respectively, promptly than the branch grid of the more close drain region of branch grid of close source region, wherein each bias potential has the absolute value that is equal to, or greater than first constant potential, each bias potential is according to the increase of drain potential or reduce to change, and the absolute value of each bias potential is just big more towards the drain region more.

High-pressure work field-effect transistor according to first kind of distortion of second solving device has following structure.

Just, the high-pressure work field-effect transistor comprises at least:

Substrate;

In mutual separated source region of substrate surface and drain region;

Semiconductor channel shaped region in substrate surface is to be maintained between source region and the drain region;

Grid above the raceway groove shaped region; And

Gate insulating film between raceway groove shaped region and grid,

Wherein at least one in signal potential and the signal code is provided for the source region, and bias potential is provided for this grid, and wherein bias potential has the absolute value that is equal to, or greater than first constant potential and according to the increase of drain potential or reduce to change.

In first kind of solving device, first kind of distortion and second kind of solving device, when the distance between adjacent minute grid was big, in some cases, electric current can be reduced or work meeting instability.For fear of this state, take following structure.Just, in according to any high-pressure work field-effect transistor in first solving device, first distortion and second solving device, be provided at respectively in a plurality of minutes raceway groove shaped regions between the grid with mesozone that channel carrier has an identical conduction type.

But, when impurity is applied in the raceway groove shaped region the raceway groove shaped region being converted to when exhausting raceway groove, and when the result be current capacity when no problem, can omit the mesozone.

When in the distance between adjacent minute grid during no better than or less than the length of grid, the mesozone can form by LDD or the drain electrode of using in regular transistor extension process, and the process that therefore is used to form the high impurity concentration drain region is unnecessary for the mesozone.

Do not need for the mesozone provide a kind of by conductive film form interconnected, therefore and do not need to provide a kind of this interconnected contact that is used for yet.When current capacity is up to specification,, do not need to increase the mesozone that impurity is given the impurity concentration identical with the high impurity concentration zone in order only to reduce contact resistance.

For this reason, even the mesozone is provided, compare with the standard crystal tubular construction of a plurality of mutual series connection, the high-pressure work field-effect transistor has simple structure and little occupied area.

The bias potential that offers second kind of grid in the solving device is also identical with first kind of solving device, and except offering the grid potential of first kind of grid in the solving device, specific potential is set to first constant potential.Be used to produce the biasing circuit (below abbreviate " biasing circuit " as) of the branch grid that is provided for first and second kinds of solving devices or grid potential, will in " description of preferred embodiment " part, be described.But, the biasing circuit and the high-pressure work circuit element that are described can not only be applied to top disclosed high-pressure work field-effect transistor, and can be applied to have drain electrode usually, the high-pressure work field-effect transistor of source electrode and a plurality of minutes grids, wherein between drain electrode and source electrode, obtain this a plurality of minutes grids by cutting apart in source/drain extreme direction.

Can cut apart or the mode of similar Fig. 3 example produces the current potential biasing that offers each minute grid by resistance.But, because the influence that employed resistance with interconnected or analog and parasitic capacitance produce can not guarantee that the value that the current potential identical with steady state value setovered can produce during transient response.For this reason, (300) are connected to the end 60-k that is connected in series to capacitive element with the capacitance that overcomes effect of parasitic capacitance from the source region, wherein current potential Vd1 is provided for this end that is connected in series, thereby can guarantee also that during transient response the branch grid G k necessary potential of close drain region changes.

This structure is suitable with a kind of situation, this situation is, capacitive element by from be connected in series the end 60-k to the interconnected of minute grid G k or, pass through this another element when another element of for example resistance is connected to when being connected in series between end 60-k and the branchs grid G k, and be connected the drain region and between the branch grid of close drain region.In the present invention, complicated is that the capacitive element of the measurement of the transient response that is useful on is described in different types of biasing circuit.Therefore, as long as the capacitive element topology directly or indirectly is connected to high-pressure work transistor drain of the present invention zone and between the branch grid of close drain region, just be described as word " capacitive element be connected to the drain region and between the branch grid of close drain region ".

In the high-pressure work transistor of a grid of first kind of distortion with second kind of solving device, directly or the suitable connection of topology be described to word " capacitive element is connected between drain region and this grid ".

The assurance of transient response also be other minute grid required.For obtaining this, the capacitive element topology directly or with the form that is included in the biasing circuit is divided between the grid in drain region and at least one.In the present invention, with aforementioned similar, for fear of complexity, this state is described to word " capacitive element is connected to the drain region and at least one divides between the grid ".But, when signal potential is provided for the branch grid of the most close source region, do not have capacitive element to be connected to the branch grid of close source region.

When this minute grid and the distance of drain region farther, the capacitive element with relatively little capacity is selected for this minute grid.

Similarly, in order to guarantee transient response, the capacitive element topology directly or with the form that is included in the biasing circuit is comprising between a plurality of minutes grids of the branch grid of close drain region.In the present invention, this state is described as word " capacitive element be connected in the branch grid at least one pair of divide between grid " fully.But, when signal potential is provided for the branch grid of the most close source region, do not have capacitive element to be connected to the branch grid of close source region at all.On the other hand, in the situation of second kind of solving device, because signal is not directly inputted to any one grid, so capacitive element can be connected to any grid.

When capacitive element is directly connected between the branch grid by twos, be configured to the ratio of the capacitance between the capacitive element of many situations no better than at the inverse ratio of the steady state current potential between the branch grid that is used for connecting.When biasing circuit is cut apart when bias potential is provided by resistance, in order to obtain the coupling between the time constant, the ratio of the anti-number between sub-resistance is set to the ratio of the capacitance between the capacitive element in many situations.

When capacitive element is connected between drain region and grid or the branch grid, when perhaps being connected between the branch grid by this way, in many cases, divide the absolute value of the current potential of grid or grid instantaneously to become littler than the first constant potential Vs1.For fear of this situation, an end of rectifying device is connected to branch grid or grid, and second constant potential can be provided for other terminal of rectifying device.In many cases, the absolute value of second constant potential is set to be added to by the forward voltage with rectifying device the value that absolute value obtained of first constant potential.

MOS structure capacitive device or PN junction capacitor can be used to this capacitive element.The PN junction capacitor can be used as rectifying device with field-effect transistor or analog with interconnective drain and gate.

Semiconductor substrate can be used as substrate, forms high-pressure work field-effect transistor of the present invention in this substrate.

Equally, being positioned at the lip-deep substrate of support substrates with the semiconductive thin film of support substrates insulation can be as high-pressure work field-effect transistor formation of the present invention substrate wherein.

In order to make suitable in a high-pressure work circuit biasing circuit that can be used to high-pressure work field-effect transistor of the present invention, the first following high-pressure work circuit element is preferred, and high-pressure work field effect transistor wherein of the present invention is applied as above-mentioned each high-pressure work circuit.Just, the high-pressure work circuit element comprises at least:

First insulated gate FET;

Second field-effect transistor with the first insulated gate FET complementation;

One end is connected to first resistance of the drain electrode of first insulated gate FET; And

One end is connected to second resistance of the source electrode of first insulated gate FET,

Wherein: first current potential is provided for the other end of first resistance, and second current potential is provided for the other end of second resistance; Second field-effect transistor is a high-pressure work field-effect transistor of the present invention, and comprises at least two branch grids; The source electrode of second field-effect transistor is connected to the drain electrode of first insulated gate FET; The branch grid of the source region of the most close second field-effect transistor is connected to the source electrode of first insulated gate FET; Second current potential is provided for the branch grid of the drain region of the most close second field-effect transistor; The grid of first insulated gate FET is set to an input; And output obtains in a position of selecting from the source electrode of first insulated gate FET and drain electrode.

In order to make suitable in a high-pressure work circuit biasing circuit that can be used to high-pressure work field-effect transistor of the present invention, below the second high-pressure work circuit element be preferred, high-pressure work field effect transistor wherein of the present invention is applied as above-mentioned each high-pressure work circuit.Just, a kind of high-pressure work circuit element comprises at least:

First insulated gate FET;

Second field-effect transistor with the first insulated gate FET complementation;

One end is connected to first resistance of the drain electrode of first insulated gate FET; And

Second group of a plurality of resistance that is connected in series, it has an end of the source series link part that is connected to first insulated gate FET,

Wherein: second field-effect transistor is a high-pressure work field-effect transistor of the present invention, and comprises at least three branch grids; The source electrode of second field-effect transistor is connected to the drain electrode of first insulated gate FET; Divide grid be connected respectively to from second group of a plurality of resistance that are connected in series an end of the end parts that is connected in series and node the position selected; The other end of first resistance is connected to first current potential; Second current potential is provided for the other end of the end parts that is connected in series of second group of a plurality of resistance that are connected in series; The grid of first insulated gate FET is set to input; And output obtains in a position of selecting from the node of the source electrode of first insulated gate FET and drain electrode and second group of a plurality of resistance that are connected in series.

In order to guarantee the transient response characteristic of the above-mentioned first and second high-pressure work circuit elements, capacitive element can be connected between the grid and source electrode of first insulated gate FET.

In order to guarantee the transient response characteristic of the above-mentioned first and second high-pressure work circuit elements, capacitive element can be connected to the source electrode of input, first insulated gate FET and output between one of them.

In order to guarantee the transient response characteristic of the above-mentioned first and second high-pressure work circuit elements, capacitive element can be connected between 2 that select from the be connected in series end and the node of second group of a plurality of resistance that are connected in series.In this case, when capacitive element is connected between the branch grid of second field-effect transistor, can expect same effect.

Effect of the present invention is as follows:

1. by being adopted as the transistorized cross-sectional structure that normal voltage is developed, and increase manufacture process seldom and in transistor, do not form the high pressure-resistance structure (change of plane graph is necessary) with certain cross section structure, can realize the high-pressure work field-effect transistor.

Notice that if can be in conjunction with the high withstand voltage cross-sectional structure of tradition, the high-pressure work field-effect transistor can be worked so under higher voltage.

2. be lengthened out with channel length and compare to improve withstand voltage transistor, high-pressure work and drive current all can be modified.

3. when the needs biasing circuit, can realize the high-pressure work field-effect transistor by the manufacture process that is equipped with for normal voltage IC.Even distortion is arranged, also can realize high-pressure work by the distortion that increases seldom.

4. if be useful on the output transistor (having the voltage higher than interior voltage usually) of normal voltage IC or LSI, the dielectric film that is equipped with for output transistor can be transferred to gate insulating film.

5. therefore, can export the IC of high pressure can be by the manufacturing of common IC production line.

6. field-effect transistor can under high pressure be operated, wherein this field-effect transistor is formed in the semiconductive thin film, and by the TFT representative in the SOI substrate, on glass substrate or the organic substrate, and this field-effect transistor is difficult to carry out the high-pressure work that guarantees current capacity traditionally.

7. by introducing second kind of solving device of the present invention, normal voltage signal area and high-pressure work zone can be separated from each other in IC or LSI chip.Therefore, can avoid in low voltage operated zone forming the interconnected danger of high pressure, and can suppress signal delay to the high-pressure work zone of short arc by transmission standard voltage signal upwards.

Brief description of the drawings

In the accompanying drawings:

Fig. 1 shows the schematic cross section of the structure of traditional high withstand voltage mos transistor;

Fig. 2 shows the schematic cross section of the structure of the MOS transistor with small size grid length;

Fig. 3 shows the schematic cross section of the example of the example of the field-effect transistor that is used to explain first kind of solving device with mesozone and biasing circuit and biasing means of the present invention;

Fig. 4 shows the schematic circuit of the embodiment 1 of biasing circuit of the present invention;

Fig. 5 shows the schematic circuit of the embodiment 2 of biasing circuit of the present invention;

Fig. 6 shows the schematic circuit of the embodiment 3 of biasing circuit of the present invention;

Fig. 7 shows the schematic circuit of the embodiment 4 of biasing circuit of the present invention;

Fig. 8 shows the schematic circuit of the embodiment 5 of biasing circuit of the present invention;

Fig. 9 shows the schematic circuit of the embodiment 6 of biasing circuit of the present invention;

Figure 10 is a schematic circuit of explaining the connection of high-pressure work circuit element of the present invention;

Figure 11 shows the schematic circuit of the embodiment 7 of biasing circuit of the present invention;

Figure 12 shows the schematic circuit of the embodiment 8 of biasing circuit of the present invention;

Figure 13 is the plane graph of example 1 of the present invention;

Figure 14 is the sample diagram of measurement result of output characteristic of the experiment of the MOS transistor of the n channel high-voltage yard effect transistor of Comparative Examples 1 and the long raceway groove of tradition;

Figure 15 is the sample diagram of measurement result of output characteristic of the experiment of the MOS transistor of the p channel high-voltage yard effect transistor of Comparative Examples 1 and the long raceway groove of tradition;

Figure 16 is the plane graph of example 2 of the present invention;

Figure 17 shows the diagram of voltage transfer characteristic of the biasing circuit of example 2;

Figure 18 shows the diagram of measurement result of experiment sampling output characteristic of the n channel high-voltage yard effect transistor of example 2;

Figure 19 shows the diagram of measurement result of experimental sampling output characteristic of the p channel high-voltage yard effect transistor of example 2.

The description of preferred embodiment

Description for the preferred embodiments of the present invention will relate generally to a kind of situation hereinafter, in this this situation, mainly suppose a kind of n channel high-voltage yard effect transistor.If the symbol of voltage relationship is changed between positive and negative, then absolute value is applicable to amplitude relation, and n type conductibility is converted into p type conductibility, and this can also be applied to the p slot field-effect transistor.

In embodiments of the invention 1, as described in Figure 3, by a plurality of branches conduction grids 500-1,500-2...., the 500-k (corresponding to above-mentioned G1, G2...., Gk) (k is equal to or greater than 2 integer) of cutting apart acquisition in source/drain extreme direction be positioned at semiconductor channel shaped region 130 (130-1,130-2, the top of 130-3....130-k),, the semiconductor channel shaped region is held in place between the source region 200 and drain region 300 on the surface of substrate 100.Gate insulating film 400-1,400-2...., 400-k be arranged on raceway groove shaped region 300 and divide grid 500 (500-1, between 500-2...., 500-k).

Signal potential is provided for the branch grid 500-1 of the most close source region 200 in a plurality of minutes grids.Equally, bias potential is provided for each minute grid than branch grid 500-1 more close drain region 300 of the most close source region 200 respectively, wherein each bias potential is according to the increase of drain potential or reduce to change, and the absolute value of bias potential 300 becomes big more towards the drain region more.

If the distance between adjacent minute grid is big, then in some cases, divide the channel resistance between the grid to become big, and work become unstable.Therefore, in many cases, each all have the conduction type identical with channel carrier mesozone 230-1 ...., in 230-(k-1) the raceway groove shaped regions that are provided at respectively between the branch grid.Mesozone 230-1 ...., 230-(k-1) provide with raceway groove shaped region 130 be divided into raceway groove shaped region 130-1,130-2 ... .130-k.

When each source region 200 and drain region 300 are all made by semiconductor, can be by forming these mesozones with the identical process that forms source region 200 and drain region 300.When the MOSIC manufacture process with a plurality of operations comprised drain electrode extension or LDD process, this also can be applied to this.

In the structure of minute grid, normal signal current potential Vg is provided for the branch grid 500-1 (G1) of the most close source region 200.Each current potential be equal to or be higher than signal potential Vg or the first constant potential Vs1, but the current potential that is equal to or less than bias potential Vd1 be provided for respectively branch grid 500-2 (G2) ... .500-k (Gk), wherein divide grid 500-2 (G2) ... .500-k (Gk) is than branch grid 500-1 more close drain side of the most close source region 200.The current potential that 300 absolute values become big more towards the drain region is provided for the branch grid than branch grid 500-1 more close drain region 300 of the most close source region 200 respectively more.

But, offer branch grid 500-2 (G2) ... each absolute value of the current potential of .500-k (Gk) is controlled as and is equal to or higher than specific potential (the signal potential Vg or the first constant potential Vs1), thereby prevent to reduce at the drive current of low drain potential, wherein divide grid 500-2 (G2) ... .500-k (Gk) is than branch grid 500-1 more close drain side of the most close source region 200.

The current potential Vd1 that offers the branch grid 500-k (Gk) of the most close drain region 300 is more near the current potential of Vd.Therefore, even current potential Vd1 is equal to or less than or when being higher than Vd, also can obtain this effect, unless current potential Vd1 is different from Vd fully.

Because it is lower than Vd that the absolute value of the channel potential below minute grid becomes towards source region 200 time, wherein above-mentioned minute grid is the branch grid than the more close source side of branch grid 500-k (Gk) of the most close drain region 300, so, compare with the situation of standard crystal tubular construction, operating voltage is improved more.

Be permitted for difference between Vd and the Vd1 by the value that design margin and supply voltage addition are obtained, wherein regular transistor is operated under supply voltage.In many cases, two kinds of transistors for example, are used for the transistor and the transistor that is used for external interface of internal logic, for regular transistor is equipped with.Therefore, in this case, the thickness that is used for the transistorized gate insulating film of external interface is applied to the gate insulating film of high-pressure work field-effect transistor of the present invention, and by design margin being added to the value that obtains on the supply voltage that is equipped with for the transistor that is used for external interface, be applied as the allowable voltage difference between Vd and the Vd1, thereby can expand operating voltage range of the present invention.

Be used to provide the example of structure of these current potentials shown in Fig. 3 to each minute grid.Resistance 50-1,50-2 ... .50-(k-1) is connected in series mutually, and current potential V2 ...., Vk from node 60-2 ... 60-k be provided for respectively branch grid 500-2 (G2) ... .500-k (Gk).

Vg is provided for node 60-1, and Vd1 is provided for node 60-k.

In the present invention, resistance does not need to have linear current-voltage characteristic.In addition, not only can cut apart, and can produce bias potential by the transistorized active element among the IC for example by the current potential that uses resistance.

In order to increase the input impedance of high-pressure work field-effect transistor of the present invention, current potential V2, V3 ... .Vk (K 〉=2), just, voltage between the first constant potential Vs1 and bias potential Vd1, can be provided for respectively branch grid 500-2 (G2) ... .500-k (Gk), wherein the first constant potential Vs1 is equal to or less than the supply voltage that uses among IC or the LSI.Equally in this time, with aforementioned similar, current potential is provided for the branch grid respectively, and wherein the absolute value of current potential 300 becomes big more towards the drain region more, and wherein above-mentioned minute grid is the branch grid than branch grid 500-1 more close drain region 300 of the most close source region 200.When the absolute value of Vd1 is lower than Vs1, Vs1 be provided for each divide grid 500-2 (G2) ... .500-k (Gk).In this case, Vs1 replaces Vg and is provided for node 60-1, and when the absolute value of Vd1 is bigger than Vs1, Vg be provided for 500-1 and Vd1 be provided for node 60-k.In the present invention, be connected in series the part terminal (end or the other end) also can be called as " node " in many cases.

In order further to increase high frequency input impedance, as according to the distortion 1 of embodiments of the invention 1, the current potential V2 that offers branch grid 500-2 (G2) can be fixed to the first constant potential Vs1, wherein divide grid 500-2 (G2) to be positioned on the side of drain region, and divide grid 500-1 (G1) near there and the most close source region 200 with respect to a minute grid 500-1 (G1).Under this situation, obtain to improve withstand voltage effect equally.In Fig. 3, in this case, the first constant potential Vs1 is applied to branch grid 500-2 (G2) and node 60-2, so resistance 50-1 and node 60-1 become unnecessary.In distortion 1, divide the quantity of grid to be equal to or greater than three.

For the further high frequency characteristics of improving, and capacitive element (element with capacitive element, for example, PN junction or MIS capacitor) can be connected between branch grid 500-2 (G2) and the AC earth point.

For the transient response of the biasing that improves the branch grid 500-k that is applied to the most close drain region 300, capacitive element can be connected between drain region 300 and the node 60-k.

In order to improve the transient response that is applied to the biasing on each minute grid, capacitive element can be connected to drain region 300 and node 60k, 60-(k-1) ...., between in 60-3 at least one.Capacitive element preferably be connected to drain region 300 and all node 60k, 60-(k-1) ...., between 60-3.In this case, when the parasitic capacitance value of observing from each node is almost equal each other, capacitance descends according to the successively decreasing order of reference marker of node, make that the capacitance between drain region 300 and node 60-(k-1) is littler than the capacitance between drain region 300 and node 60-k, and the rest may be inferred.

In order to improve the transient response of the biasing that is applied to each minute grid, capacitive element can be connected to 60k, 60-(k-1) ...., between 60-2 at least two nodes or neighbouring node.Preferably, capacitive element is connected between drain region 300 and the node 60-k, and, capacitive element be connected to by twos node 60k, 60-(k-1) ...., between 60-2 neighborhood of nodes that are connected to.The ratio of the capacitance of the capacitive element that between neighborhood of nodes, connects by twos be selected as no better than resistance 50 .. (k-1) ..., the inverse ratio of 50-2 resistance value.

In these situations, the current potential absolute value of node becomes lower than first constant potential in some cases.For fear of this state, an end of rectifying device can be connected to this node, and second constant potential can be provided for the other end of rectifying device.In many cases, the absolute value of second constant potential is set to be added to the value that is obtained on the absolute value of first constant potential by the forward voltage with rectifying device.

Capacitive element becomes topology to the connection mode of biasing circuit and equals:

Word " capacitive element be connected to the drain region and between the branch grid of close drain region ",

Word " capacitive element is connected to the drain region and at least one divides between the grid ",

Word " capacitive element is connected between at least one pair of branch grid of branch grid ", and

Word " end of rectifying device is connected to this minute grid, and second constant potential is provided for the other end of rectifying device ".

Embodiments of the invention 2 can provide following structure.Just, the high-pressure work field-effect transistor comprises at least:

Substrate;

Mutual separated source region and drain region on the surface of substrate;

Semiconductor channel shaped region on the surface of substrate is to remain between source region and the drain region;

A plurality of minutes grids above the raceway groove shaped region, this a plurality of minutes grids obtain by cutting apart in source/drain extreme direction; And

A plurality of gate insulating films between raceway groove shaped region and a plurality of minutes grids,

Wherein at least one of signal potential and signal code is provided for the source region, first constant potential is provided in a plurality of minutes grids the branch grid of close source region, and each bias potential is provided for such branch grid respectively, promptly than the branch grid of the more close drain region of branch grid of close source region, wherein each bias potential all has the absolute value that is equal to or greater than first constant potential, each bias potential is according to the increase of drain potential or reduce to change, and the absolute value of each bias potential becomes big more more towards the drain region.

Comprising at least according to the high-pressure work field-effect transistor in the distortion 1 of embodiments of the invention 2:

Substrate;

Mutual separated source region and drain region on substrate surface;

At the semiconductor channel shaped region of substrate surface, to remain between source region and the drain region;

Grid above the raceway groove shaped region; And

Gate insulating film between raceway groove shaped region and grid,

Wherein at least one of signal potential and signal code is provided for the source region, and bias potential has the absolute value that is equal to, or greater than first constant potential, and according to the increase of drain potential or reduce to change.

The source electrode of the high-pressure work field-effect transistor of distortion 1 of the present invention and embodiment 2 is by the interconnected drain electrode that is connected to the regular transistor of IC or LSI inside of conductivity, thereby the normal voltage signal can be converted into the high-pressure work signal.

And normal voltage signal area and high-pressure work zone can be separated mutually.Therefore, because the normal voltage signal can upwards be transferred to the high-pressure work zone with low amplitude value, can avoid the interconnected danger that is formed in the low voltage operated zone of high pressure, and can suppress signal delay.

In order to obtain this purpose, first constant potential is selected as the specific potential in the gate bias current potential of high-pressure work field-effect transistor of embodiment 2.

In second kind of solving device, in some cases, when the distance between the adjacent sub grid was big, it is unstable that the channel resistance between the adjacent sub grid becomes big and operation becomes equally.Therefore, in the raceway groove shaped region between minute grid, wherein each mesozone all has the conduction type identical with channel carrier by twos in the mesozone.The raceway groove shaped region is divided into those mesozones.

The process that is used for manufacturer's standard IC or LSI is identical with first kind of solving device, shaped region in the middle of wherein IC standard or LSI can be applied to.

Offer the branch grid of embodiment 2 and be out of shape the bias potential of 1 grid that also all the branch grid potential with the branch grid that offers first kind of solving device is identical.

The improvement of the transient response characteristic of the bias potential that obtains owing to the connection of capacitive element is also identical with situation among the embodiment 1, and wherein bias potential offers the branch grid of embodiment 2 and is out of shape 1 grid.In the situation of the distortion 1 of embodiment 2, wording " the branch grid of close drain region " is substituted by " grid ".

Bias potential Vd1 is according to the increase of Vd or reduce to increase or reduce.But Vd1 and Vd do not need to have linear relationship.

Notice that when having a plurality of supply voltage, driving current value and the withstand voltage voltage that is utilized during the best that becomes adopt Vs1.At this moment, use gate insulating film to bear this voltage, wherein the thickness of gate insulating film is prepared in the manufacture process of IC or LSI.

The present invention also can be applied to have the transistor of LDD or drain electrode extended structure.

The present invention is applied in the high-pressure work field-effect transistor that forms in the Semiconductor substrate, the high-pressure work field-effect transistor that in having so-called semiconducting insulation (SOI:semiconductor-on-insulator) substrate of semiconductive thin film, forms, wherein semiconductive thin film is formed on support substrate, glass substrate, on the insulating surface of organic thin slice or analog, and the high-pressure work field-effect transistor that in semiconductor-naked body (SON:semiconductor-on-nothing), forms with semiconductive thin film, wherein semiconductive thin film and support substrate insulation, this support substrate keeps at a cavity from right-hand man's side.

Have the bias potential that many kinds are used for high-pressure work field-effect transistor of the present invention and produce circuit (hereafter is " biasing circuit ").The embodiment of biasing circuit hereinafter will be disclosed.Because being used for the connection and being connected of rectifying device of the improved capacitive element of transient response is described at embodiment 1 and embodiment 2, wherein embodiment 1 and embodiment 2 have resistance division shown in Figure 3, so the following description that does not repeat about this independent circuit.

At first, will provide description below, wherein divide grid 500-k the most close drain region 300 about the circuit of the bias potential (Vd1) of the grid of the distortion 1 that is used for produce dividing grid 500-k or embodiment 2.Dividing the bias potential that obtains by the current potential of the current potential between bias potential Vd1 and the specific potential can be used as the bias potential that is used for other minute grid and provides.

The embodiment 1 of biasing circuit comprises that at least one has the adder of at least two inputs and an output, the current potential that wherein increases according to drain potential or reduce to change is provided for one of two inputs, and specific potential Vslg is provided for two inputs another; And the current potential of the output of adder is provided for the grid of the distortion 1 of the branch grid of the most close drain region or embodiment 2 as bias potential.

As shown in Figure 4, adder 44 is analog operation circuit current potential and that export to output 70-3 that are used for will being applied to respectively input 70-1 and 70-2.Therefore, when current potential Vd2 and Vg are provided for a terminal 70-1 and another terminal 70-2 respectively, adder 44 output potential Vg+Vd2 (=Vd1) give output 70-3, wherein current potential Vd2 is according to the increase of drain potential or reduce to change.Therefore, this bias potential Vd1 offers the branch grid of close drain region by output 70-3.

In the above embodiments 1, even when the first constant potential Vs1 replaces Vg to be provided for another input 70-2 of adder 44, bias potential can be provided for the grid of the distortion 1 of the branch grid of drain region of the most close high-pressure work field-effect transistor of the present invention or embodiment 2.In this case, relational expression Vd1=Vs1+Vd2 sets up.

In many cases, the high voltage source of high-pressure work field-effect transistor of the present invention is converted into the power supply of adder 44.Technology of the present invention also is applied to forming the transistor of this analog operation circuit 44, thereby allows high pressure to be output.

A kind of biasing circuit of embodiment 2 has been shown among Fig. 5, the component construction of this biasing circuit is simpler than the biasing circuit of embodiment 1, is used to provide the branch grid of current potential to the drain region of the most close high-pressure work field-effect transistor of the present invention or the grid of the distortion 1 of embodiment 2.From Fig. 5, can know and find out, the biasing circuit of embodiment 2 comprises at least two resistance that are connected in series 51 and 52, wherein current potential is provided for two resistance 51 being connected in series and a terminal 70-2 of 52 from high voltage source, and their another terminal is connected to the drain region; And bias potential is provided for the grid of the distortion 1 of the branch grid of the most close drain region or embodiment 2 from the node 70-3 between two resistance 51 and 52 that is connected in series.

Notice among Fig. 5, reference marker VH represents the high voltage source current potential, and becomes the resistance value of two resistance that the value of the first constant potential Vs1 is selected as being connected in series usually when VHx (resistance value of the resistance on the drain side)/(resistance values of two resistance that are connected in series).

In the embodiment 2 of biasing circuit, electric current flows to drain electrode from the high pressure source electrode.The resistance value that depends on resistance, this state become problem in many cases.The embodiment 3 of biasing circuit is illustrated as an example in Fig. 6, wherein this biasing circuit does not flow into the electric current of drain electrode, and this biasing circuit is used to provide the branch grid of current potential to the drain region of the most close high-pressure work field-effect transistor of the present invention or the grid of the distortion 1 of embodiment 2.Can know from Fig. 6 and find out that the embodiment 3 of biasing circuit comprises at least one rectifying device 43 and the resistance 52 that is connected in series mutually, wherein the end 70-1 that is connected in series in the rectifying device side is connected to the drain region; Specific potential is provided for the end 70-2 that is connected in series of resistance side; And bias potential is provided for the branch grid of close drain region from the node 70-3 between rectifying device 43 and the resistance 52.When bias potential was provided for the grid of distortion 1 of embodiment 2, specific potential was set to first constant potential.

In embodiment 3, in order to specify, the equivalent rectifying device that rectifying device 43 forms with PN junction diode, Schottky diode, by the drain and gate that connects insulated gate FET or the form of analog realize.It is when reducing near earthing potential when drain potential that rectifying device 43 is provided, and the absolute value that the current potential that provides is provided is reduced to and is equal to or less than | Vg| or | the level of Vs|.

When omit increasing specific potential (Vg or Vs1) for simplicity when offering the current potential of the end 70-1 that is connected in series, as relational expression Vd in this case " during the Vg establishment, fully demonstrate high withstand voltage effect.Under the situation that the increase in specific potential is omitted, becoming at end 70-1 the current potential that is connected in series is equal to or less than specific potential when adding Vf, and the current potential of node 70-3 is fixed and is approximately specific potential.

Here, reference marker Vf represents the forward voltage of rectifying device.When rectifying device was realized with the form of field-effect transistor with interconnective grid and drain electrode, forward voltage Vf became the threshold voltage of the grid Vth43+ Δ V of insulated gate FET.Δ V be to corresponding to the electric current that flows through resistance 52, grid is to the recruitment of source voltage.

When the current potential of drain region in embodiment 3 when VH changes into Vs1, if this changes the change height than the resistance value of parasitic capacitance that depends on node 70-3 based on time constant and resistance 52, therefore rectifying device 43 instantaneous dissengaged positionss that become so postpone to be forced to the change of the bias potential that reason node 70-3 provides and produce.This situation is not expected.In order to improve the state that this is not expected, capacitive element can be connected to being connected in series between end 70-1 and the node 70-3 on the rectifying device side.

This situation is equivalent to a kind of situation topologically, and in this case, capacitive element is connected between the branch grid of drain region of end 70-1 drain region that is connected and the most close node 70-3 connections that are connected in series.

Fig. 7 shows the embodiment 4 of biasing circuit, and this biasing circuit is used to cut apart the output of biasing circuit of embodiment 1 so that the current potential that the obtains branch grid to high-pressure work field-effect transistor of the present invention to be provided respectively.A plurality of resistors that are connected in series 51-1,51-2 ... .51-first group a end of (k-1) is connected to the output 70-3 of the biasing circuit of embodiment 1, and specific potential Vs1g is provided for its other end.

Bias potential respectively by from series connection node 61-2,61-3 ..., 61-(k-1) and the end 61-k (70-3) that is connected in series in the appropriate position of selecting obtain, to be provided for the branch grid.

Be provided for the branch grid that is positioned at drain side with respect to branch grid contiguous with it and the most close source region as the first constant potential Vs1, if divide the quantity of grid to be designated as k, the resistance number of connection that belongs to first group of a plurality of resistance that are connected in series becomes (k-2), and the first constant potential Vs1 is provided for its other end.

Fig. 8 shows the embodiment 5 of biasing circuit, and this biasing circuit is used to cut apart the output of embodiment 2 of biasing circuit so that the current potential that the obtains branch grid to high-pressure work field-effect transistor of the present invention to be provided respectively.First group of a plurality of resistance 51-1,51-2 that are connected in series ... the end of .51-(k-1) is connected to the output 70-3 of the biasing circuit of embodiment 2, and specific potential Vs1g is provided for its other end.

Bias potential respectively by from series connection node 61-2,61-3 ..., 61-(k-1) and the end 61-k (70-3) that is connected in series in the appropriate position of selecting obtain, to be provided for the branch grid.

Be provided for the branch grid that is positioned at drain side with respect to branch grid contiguous with it and the most close source region as the first constant potential Vs1, if divide the quantity of grid to be designated as k, the resistance number of connection that belongs to first group of a plurality of resistance that are connected in series becomes (k-2), and the first constant potential Vs1 is provided for its other end.

Fig. 9 shows the embodiment 6 of biasing circuit, and this biasing circuit is used to cut apart the output of embodiment 3 of biasing circuit so that the current potential that the obtains branch grid to high-pressure work field-effect transistor of the present invention to be provided respectively.One end of rectifying device 43 be connected to second group of a plurality of resistance 52-1,52-2 that are connected in series ... the end of .52-(k-1), and specific potential Vs1g is provided for its other end.The other end of rectifying device 43 is connected to the drain electrode of high-pressure work field-effect transistor of the present invention.

Bias potential respectively by from series connection node 62-2,62-3 ..., 62-(k-1) and the end 62-k (70-3) that is connected in series in the appropriate position of selecting obtain, to be provided for the branch grid.

Be provided for the branch grid that is positioned at drain side with respect to branch grid contiguous with it and the most close source region as the first constant potential Vs1, if divide the quantity of grid to be designated as k, the resistance number of connection that belongs to first group of a plurality of resistance that are connected in series becomes (k-2), and the first constant potential Vs1 is provided for its other end.

Following circuit structure can be suitable for an element into the high-pressure work circuit, and high-pressure work field-effect transistor wherein of the present invention is applied to this high-pressure work circuit.Just, a kind of high-pressure work circuit element comprises at least:

First insulated gate FET;

Second field-effect transistor with the first insulated gate FET complementation;

One end is connected to first resistor of the drain region of first insulated gate FET; And

One end is connected to second resistor of the source region of first insulated gate FET,

Wherein first current potential is provided for the other end of first resistor, and second current potential is provided for the other end of second resistor; Second field-effect transistor is a high-pressure work field-effect transistor of the present invention, and comprises at least two branch grids; The source electrode of second field-effect transistor is connected to the drain electrode of first insulated gate FET; The branch grid of the source region of the most close second field-effect transistor is connected to the source electrode of first insulated gate FET; Second current potential is provided for the branch grid of the drain region of the most close second field-effect transistor; The grid of first insulated gate FET is set to input; And a position of selecting from the source electrode of first insulated gate FET and drain electrode obtains output.

Following circuit structure can be suitable for another element into the high-pressure work circuit, and high-pressure work field-effect transistor wherein of the present invention is applied to this high-pressure work circuit.Just, a kind of high-pressure work circuit element comprises at least:

First insulated gate FET;

Second field-effect transistor with the first insulated gate FET complementation;

One end is connected to first resistor of the drain electrode of first insulated gate FET; And

One end of the end parts that is connected in series is connected to second group of a plurality of resistor that is connected in series of the source electrode of first insulated gate FET,

Wherein: second field-effect transistor is a high-pressure work field-effect transistor of the present invention, and comprises at least three branch grids; The source electrode of second field-effect transistor is connected to the drain electrode of first insulated gate FET; The branch grid is connected respectively to from the position of the node of the end parts that is connected in series of second group of a plurality of resistor that are connected in series and end selection; The other end of first resistor is connected to first current potential; Second current potential is provided for the other end of the end parts that is connected in series of second group of a plurality of resistor that are connected in series; The grid of first insulated gate FET is set to input; And a position of selecting from the node of the source electrode of first insulated gate FET and drain electrode and second group of a plurality of resistor that are connected in series obtains output.

Figure 10 shows the circuit diagram of the connection of explaining high-pressure work circuit element of the present invention.In Figure 10, reference marker 51 expressions first resistor, reference marker 52-1 ..., 52-(k-1) expression second group of a plurality of resistor that is connected in series, reference marker 45 expressions first insulated gate FET, and reference marker 45-200,45-300 and 45-500 is represented source electrode, drain electrode and the grid of first insulated gate FET respectively.Reference marker 46 expressions second field-effect transistor, reference marker 46-200 and 46-300 is represented the source electrode and the drain electrode of second field-effect transistor (high-pressure work field-effect transistor) respectively, and reference marker 46-500-1,46-500-2 ...., 46-500-k represent respectively the most close source region the branch grid, with respect to contiguous it and the branch grid 46-500-1 of close source region be positioned at branch grid on the side of drain region .... and the branch grid of close drain region.

The branch grid 46-500-1 of the source region of the most close second field-effect transistor 46 is connected to the source electrode 45-200 of first insulated gate FET 45, and the source electrode 46-200 of second field-effect transistor 46 is connected to the drain electrode 45-300 of first insulated gate FET 45.This source electrode that connects control first insulated gate FET 45 is (Vth46+ Δ V) (its definition will be described below) to the voltage that drains, so that first insulated gate FET 45 is avoided high withstand voltage operation.

One end of first resistor 51 is connected to the drain electrode 45-300 of first insulated gate FET 45, and the node between first resistor 51 and first insulated gate FET 45 becomes an output 70-3.One end of second group of a plurality of resistor that are connected in series is connected to the source electrode 45-200 of first insulated gate FET 45, and becomes an output 70-4.The first current potential V1 is provided for the other end 70-1 of first resistor 51, and the second current potential V2 is provided for the other end 62-1 of second group of a plurality of resistor that are connected in series.The second current potential V2 also is provided for branch grid 46-500-k of the drain region of the most close second field-effect transistor 46.The current potential that the appropriate position of selecting obtains from the node of second group of a plurality of resistor that are connected in series and one end is provided for other minute grid respectively.

When second field-effect transistor had two branch grids, second group of a plurality of resistor that are connected in series can replace with second a single resistor.

An example as the distortion of above-mentioned high-pressure work circuit element provides:

A kind of high-pressure work circuit element, wherein first and second resistors at least one form by a plurality of resistors that are connected in series, and the node between them is used as output;

A kind of high-pressure work circuit element, wherein first resistor is made up of a plurality of resistors that are connected in series, and the source electrode of second field-effect transistor is connected to the node between them;

A kind of high-pressure work circuit element, wherein second resistor is made up of a plurality of resistors that are connected in series, and the drain electrode of second field-effect transistor is connected to the node between them;

A kind of high-pressure work circuit element, wherein the drain electrode of second field-effect transistor is connected to second current potential;

A kind of high-pressure work circuit element, wherein the drain electrode of second field-effect transistor is connected to second current potential by the 3rd resistor;

A kind of high-pressure work circuit element, wherein the drain electrode of second field-effect transistor is connected to the 3rd current potential;

A kind of high-pressure work circuit element, wherein the drain electrode of second field-effect transistor is connected to the 3rd current potential by the 3rd resistor; And

A kind of high-pressure work circuit element, wherein one of first and second resistors are made by constant flow element.

In addition, those skilled in the art increases or changes an element and is included in the scope of claim of the present invention to wherein circuit element in ordinary skill.

Threshold voltage of the grid Vth46 adds that the deviation of the Δ V of first insulated gate FET produces between input of first insulated gate FET of high-pressure work circuit element and source electrode output.In order to reduce this deviation, first insulated gate FET can be made by depletion mode fet.Here, Δ V is the pressure drop of passing additional necessity of the grid of first insulated gate FET and drain electrode, and it is corresponding to the electric current that flows through second resistor.

In the high-pressure work circuit element, when the absolute value of the threshold voltage of the grid of the threshold voltage of the grid of first insulated gate FET and second field-effect transistor almost was equal to each other, the deviation that produces between the input of first insulated gate FET and drain electrode output was almost compensated.

In the embodiment 2 of biasing circuit, make the electric current of auto bias circuit to flow into the drain electrode of high-pressure work field-effect transistor of the present invention.In addition, in [biasing circuit] of the embodiment 3 of biasing circuit, increase the resistor of the biasing circuit in parallel with the drain electrode output resistor of high-pressure work field-effect transistor of the present invention.When these materials in performance with produce when going wrong aspect the image, a kind of insulated gate FET is introduced into this biasing circuit, and drain voltage is imported into its grid, thereby has solved this problem.In biasing circuit, can utilize this high-pressure work circuit element.

Will be described below the embodiment 7 of the biasing circuit that utilizes this high-pressure work circuit element.Just, example as shown in figure 11, in high-pressure work circuit element shown in Figure 10, first current potential is high voltage source current potential VH, second current potential is an earthing potential, and earthing potential is provided for the drain electrode of second field-effect transistor by the 3rd resistor 53.

The grid 45-500 of first insulated gate FET 45 is connected to the drain electrode of high-pressure work field-effect transistor of the present invention, and bias potential is from the grid of the distortion 1 of the branch grid of the drain region that the drain electrode 45-300 and the node 70-3 between first resistor 51 of first insulated gate FET 45 offers the most close high-pressure work field-effect transistor of the present invention or embodiment 2.

If the resistance value of the 3rd resistor 53 is represented as (resistance value of first resistor) * (Vs1)/(VH-Vs1), when drain potential became electronegative potential, the current potential of grid that offers the distortion 1 of the branch grid of the most close drain region or embodiment 2 did not change to earthing potential from Vs1.

Be connected to the node between the drain electrode of the 3rd resistor and second field-effect transistor when the other end 62-1 of second group of a plurality of resistor that are connected in series, and the resistance value of the 3rd resistor is set to (resistance value of first resistor) * (Vs1-Vth46-Δ V)/(during VH-Vs1), can obtain same effect.Here, (Vth46+ Δ V) is when by (grid that the electric current of the expression of VH-Vs1)/(resistance value of first resistor) obtains when flowing through second field-effect transistor is to the voltage of source electrode.

When current potential (Vs1-Vth46-Δ V) is provided for the other end 62-1 of second group of a plurality of resistor that are connected in series, can obtain identical effect.

For the output of the embodiment 7 by utilizing biasing circuit provides the branch grid of bias potential to a plurality of high-pressure work field-effect transistors of the present invention, for example, as in the embodiment 5 of biasing circuit, one end of first group of a plurality of resistor that are connected in series is connected to output 70-3, this output 70-3 extends since the drain electrode 45-300 of first insulated gate FET 45, specific potential is provided for its other end, and obtain current potential in the appropriate position of selecting from the node of first group of a plurality of resistor that are connected in series and end portion thereof respectively, to be provided for the branch grid.

When first constant potential is provided for when being positioned at the branch grid of drain region side with respect to branch grid contiguous and the most close source region, the number of connection of first group of a plurality of resistor that are connected in series becomes k-2, and first constant potential is provided for its other end part.

And, the biasing circuit of the embodiment 8[of biasing circuit as shown in figure 12] shown in, bias potential can be respectively from second group of a plurality of resistor 52-1 that are connected in series ...., 52-(k-1) node 62-2 ..., 62-(k-1) and end portion 62-1 and 62-k in the position selected obtain, thereby be provided for the branch grid of high-pressure work field-effect transistor of the present invention.At this moment, specific potential be provided for second group of a plurality of resistor 52-1 that are connected in series ... another end portion of .52-(k-1).

When first constant potential is provided for the branch grid that is positioned at the drain region side with respect to branch grid contiguous and the most close source region, first constant potential is provided for other end part.

Notice, when the grid of the high-pressure work field-effect transistor of the present invention of the power supply that needs bias potential only is of the most close drain region, perhaps only there is a grid to be provided as the distortion 1 of embodiment 2, and the quantity of the branch grid of second field-effect transistor is 2 o'clock, second group of a plurality of resistor that are connected in series is made up of single second resistor, and bias potential offers this grid by the source electrode of first field-effect transistor and the node between single second resistor.

In the embodiment 8 of the biasing circuit that utilizes the high-pressure work circuit element, the resistive element of the biasing circuit that increases in parallel with the drain electrode of high-pressure work field-effect transistor of the present invention is removed from the biasing circuit of embodiment 6 fully.

Notice in the biasing circuit of embodiment 8, in some above-mentioned distortion, can omit the 3rd resistor 53.

Realize the resistor of the biasing circuit of each embodiment 1 to 8 of the present invention in order not increase the distortion of any special manufacture process or minority once again, can use the polyresistor that in simulation MOSIC, uses, the impurity layer that on substrate surface, forms by the ion implantation technique of reverse LDD of being used for or drain electrode extension, or analog.Having almost, the resistor of linear characteristic preferably is used as this resistor.Yet, use for the low energy consumption of the high sheet resistor device of needs, can use field effect transistor channel impedance, be formed on such as the semiconductive thin film on the dielectric substrate of SOI substrate or glass substrate or biochip or analog.In this case, resistor is unnecessary has a linear resistance property.

The present invention includes a transistor, its structure or bias potential change in known range.And the combined Darlington wherein of structure of the present invention is also included within the scope of the present invention.In addition, except the element of describing in the biasing circuit of the present invention, be increased that for example resistor, capacitive element or transistor are also included within the scope of the present invention with the biasing circuit in the scope that drops on the ordinary skill power supply.

Figure 13 shows the plane graph of the device of example 1 of the present invention.Because Figure 13 is not a sectional view,, in Figure 13, draw by the pattern or the analog of parallax indication in order to increase the identification directly perceived of each parts.In the figure, reference marker 100 expression SOI substrates, the source electrode of reference marker 200 expression high-pressure work field-effect transistors, the drain electrode of reference marker 300 expression high-pressure work field-effect transistors, and branch grid G 1, G2, G3, G4 and the G5 of reference marker 500-1,500-2,500-3,500-4 and 500-5 expression high-pressure work field-effect transistors, these minutes grid below, gate insulating film 400-1,400-2,400-3,400-4 and 400-5 (not shown) are formed on raceway groove shaped region 130 (not shown).Raceway groove shaped region 130 is divided into branch raceway groove 130-1,130-2,130-3,130-4 and 130-5 (not shown) by mesozone 230-1,230-2,230-3 and 230-4, these minutes raceway groove each all have width W 1 and length L c1.Branch channel length Lc1 is a value that obtains by the lateral overlap length that deducts mesozone below minute grid or regions and source from minute grid length Lg1.

Notice that the square 30 that draws in the drawings shows a contact hole.

Raceway groove shaped region 130 (not shown), source region 200, drain region 300 and mesozone 230 (230-1,230-2,230-3 and 230-4) are formed in the semiconductive thin film in the surface of SOI substrate 100.Each source region 200, drain region 300 and mesozone 230 all are the high impurity concentration zones that attaches the elongated area of the impurity concentration with reduction.Phosphorus or arsenic are as the impurity of n channel high-voltage yard effect transistor, and boron is as the impurity of p channel high-voltage yard effect transistor.

Reference marker 50-2,50-3 and 50-4 expressions are used for the resistor of branch current potential.The width that semiconductive thin film in SOI substrate 100 is processed in left rear side is the shape that LR and length are approximately 2WR, and the periphery of resistor is an oxide, thereby obtains to be used for the resistor 50-2,50-3 and 50-4 of branch current potential.And resistor 50-2,50-3 and 50-4 is realized by increasing impurity identical in the situation with extension alloy or channel dopants.In order to form node 60-2,60-3 and 60-4, the high concentration impurities that is used for the source/drain shaping is added to the part that forms node.The preferably opposite conduction type of conduction type that is used for the impurity that is added to resistor of branch current potential with the impurity of the regions and source that is increased to high-pressure work field-effect transistor of the present invention.

In the drawings, reference marker 30 expression contact holes, reference marker 60-25 expressions provide current potential and extend to the interconnected of branch grid 500-2 from node 60-2, reference marker 60-35 is represented from node 60-3 to dividing the interconnected of grid 500-3, reference marker 60-45 is represented from node 60-4 to dividing the interconnected of grid 500-4, reference marker 60-55 expression provides the interconnected of current potential from node 60-5 to minute grid 500-5, reference marker 205 expression source electrode guiding electrodes, reference marker 305 expression drain conductors electrodes, and reference marker 500-15 expressions are from the guiding electrode of minute grid 500-1.

High-pressure work field-effect transistor with example 1 of said structure is combined in the SOI substrate by experimental group.

The high-pressure work field-effect transistor that experiment is made has five branch grids, and wherein each divides grid to have the grid length of Lg1=0.8 μ m and the grid width of W1=80 μ m, and has the SiO that thickness is 11nm ₂Film is as gate insulating film.It is length/width=80 μ m/2.4 μ m that each resistor 50-1,50-2 and 50-3 all forms dimension scale.The SOI substrate is by the silicon thin film of 100nm thickness, the SiO of 100nm thickness ₂Film and silicon substrate are formed.

Be provided for branch grid 500-2 (G2) when Vg offers branch grid 500-1 (G1), Vs1=1V, Vs1=1V is provided for node 60-2, and when Vd+Vs1=Vd+1V was provided for node 60-5, output characteristic was illustrated in Figure 14 by the curve of black circles or black triangle.

For the output characteristic with high voltage field effect transistor of the present invention compares, be formed on the output characteristic of the conventional criteria MOS transistor on the identical substrate, be illustrated in the drawings by the black triangle curve, wherein this identical substrate has the grid length of 4 μ m and the grid width of 80 μ m.The reason of selecting the grid length of 4 μ m to be used for the conventional criteria MOS transistor is total grid length of five branch grids of this grid length high-pressure work field-effect transistor according to the invention.Because the channel length as the conventional criteria MOS transistor of a comparative example is longer than the summation of the value of the length of five branch raceway grooves of high-pressure work field-effect transistor of the present invention, so this comparative example of conventional type is seen and will be had superiority from the viewpoint of average electric field.

Figure 14 shows the output characteristic of the n channel high-voltage yard effect transistor of experiment manufacturing.

Under the situation of the conventional MOS transistor of property example as a comparison, electric current I ds begins to be increased to suddenly the Vds slightly littler than 2V.But, under the situation of high-pressure work field-effect transistor of the present invention, even when Vds=10V, do not observe the unexpected increase of electric current I ds yet.In addition, the current value of high-pressure work field-effect transistor Vgs=0.6V of the present invention approximately is 7 times of MOS transistor big of property example as a comparison.

Figure 14 shows, and simply increases by channel length, compares with the improvement that MOS transistor is withstand voltage, and withstand voltage quilt improves significantly, and has kept high current drive capability.

Figure 15 shows the output characteristic of the p channel high-voltage yard effect transistor of experiment manufacturing.

Under the situation of the conventional MOS transistor of property example as a comparison, electric current I ds begins to be increased to suddenly Vds=-3V.But, under the situation of high-pressure work field-effect transistor of the present invention, though when Vds=-7V, observe the increase of electric current I ds, the withstand voltage 10V that is equal to or greater than of the Vds during Vgs=0V.In addition, the current value the during Vgs=-0.6V of high-pressure work field-effect transistor of the present invention approximately is that 9 times of the conventional MOS transistor of property example as a comparison are big.

Figure 15 shows, and simply increases by channel length, compares with the improvement that MOS transistor is withstand voltage, and withstand voltage quilt improves significantly, and has kept high current drive capability.

Figure 16 shows the plane graph of the device of example 2 of the present invention.Because Figure 16 is not a sectional view, so, in order to increase the identification directly perceived of each parts, the pattern and the analog that in Figure 16, draw and represent by parallax.

In example 2, use biasing circuit corresponding to the embodiment 6 of biasing circuit.MOS transistor 43 is used as rectifying device, and wherein the grid 540 of this MOS transistor and drain electrode 340 are interconnected by interconnected 545.The source electrode 240 of MOS transistor 43 is connected in series with resistor 50-4 by interconnected 60-55.The drain electrode 340 of MOS transistor 43 is by interconnected 545 drain electrodes that are connected to high-pressure work field-effect transistor of the present invention.Other element be connected with those elements of example 1 be connected identical.

When the first constant potential Vs1 was 1V, the relation between the drain potential Vd of node 60-5 and the current potential V5 showed the characteristic shown in Figure 17.When Vd becomes when being equal to or less than Vs1, be maintained at current potential a little more than Vs1=1V at the current potential V5 of node 60-5.Because MOS transistor 43 is as the function of rectifying device, so the current potential on each node 60-2,60-3,60-4 and 60-5 does not become the first constant potential Vs1 that is equal to or less than node 60-2.Therefore, each V2, V3, V4 and V5 do not become and are equal to or less than current potential Vs1.For this reason, even in the low zone of Vd, high-pressure work field-effect transistor output current of the present invention is also kept.

Figure 18 shows the output characteristic of the n channel high-voltage yard effect transistor of an experiment manufacturing.Under the situation of p channel high-voltage yard effect transistor of the present invention,, do not observe the unexpected increase of electric current I ds because Vds rises to 10V at least.Because biasing circuit is directly connected to the influence of drain electrode, the drain current during Vg=0V increases about 150nA.Because this is not the leakage current that causes owing to the degradation that installs, so just do not need to worry reliability.In addition, in V-I characteristic " impact " occur Vds ≈ 1V near.But the appearance of impact is that promptly branch gate bias Be Controlled is fixed in the scope of Vd＜≈ 1V owing to a fact, so it is not because withstand voltage degradation.

Be equal to or less than in the area of low pressure of 1V at Vds, the current driving ability of n channel high-voltage yard effect transistor of the present invention approximately is that 3 times of MOS transistor of property example as a comparison are big.When Vds becomes high pressure, obtain the magnification ratio identical with example 1.

Figure 19 shows the output characteristic of the p channel high-voltage yard effect transistor of an experiment manufacturing.In p channel high-voltage yard effect transistor of the present invention, though when | Vds| equals or is higher than 8V, observe the increase of electric current I ds, the withstand voltage absolute value of the Vds during Vgs=0V equals or is higher than 10V.Because biasing circuit is directly connected to drain electrode, so approximately the drain electrode output resistance of 4M Ω is connected in parallel.But, because this is not because the leakage current that the degradation of device causes does not just need to worry reliability.In addition, in V-I characteristic " little impact " occur Vds ≈-1V near.But the appearance of impact is that promptly branch gate bias Be Controlled is fixed on owing to a fact | in the scope of Vd|＜≈ 1V, so it is not because withstand voltage degradation.When | when Vds| becomes high pressure, obtain with the identical magnification ratio of example 1.

| Vds| is equal to or less than in the area of low pressure of 1V, and when Vgs=-0.6V, the current driving ability of p channel high-voltage yard effect transistor of the present invention is about 5 times of MOS transistor of property example as a comparison.

Though above-mentioned example 1 and example 2 are formed in the example of the field-effect transistor in the SOI substrate, for this transistor, increase the withstand voltage difficulty that is considered to, even but also can obtain same effect in the field-effect transistor that in SON or Semiconductor substrate, forms.

The present invention includes a kind of transistor, as can be seen, this transistorized structure or bias potential can be changed in ordinary skill from foregoing description of the present invention, and, be also included within the scope of the present invention in conjunction with the transistor of structure of the present invention.In addition, except the element of describing in the biasing circuit of the present invention, for example be increased resistor or capacitive element and be also included within the scope of the present invention with the biasing circuit that drops in the ordinary skill.

Claims (49)

1, a kind of high-pressure work field-effect transistor comprises:

Substrate;

Mutual separated source region and drain region on the surface of substrate;

The lip-deep semiconductor channel shaped region of the substrate between source region and drain region;

Be positioned at a plurality of minutes grids of raceway groove shaped region top, this a plurality of minutes grids obtain by cutting apart in source/drain extreme direction; And

A plurality of gate insulating films between raceway groove shaped region and a plurality of minutes grids,

Wherein signal potential is provided in a plurality of minutes grids the branch grid of close source region, and bias potential is offered respectively than the branch grid of the more close drain region of branch grid of close source region, wherein each bias potential has the absolute value of the specific potential of being equal to, or greater than, each bias potential is according to the increase of drain potential or reduce to change, and just big more the closer to the absolute value of described each bias potential in drain region.

2, according to the high-pressure work field-effect transistor of claim 1, wherein divide the quantity of grid to be equal to or greater than three, first constant potential is provided for the branch grid that is positioned at the drain region side with respect to the branch grid of close source region, and bias potential is offered the branch grid of more close drain region respectively, wherein each bias potential changes according to the increase or the minimizing of drain potential, and its absolute value is big more towards the drain region more.

3,, wherein lay respectively in a plurality of minutes raceway groove shaped regions between the grid with mesozone that channel carrier has an identical conduction type according to the high-pressure work field-effect transistor of claim 1.

4,, wherein lay respectively in a plurality of minutes raceway groove shaped regions between the grid with mesozone that channel carrier has an identical conduction type according to the high-pressure work field-effect transistor of claim 2.

5, according to the high-pressure work field-effect transistor of one of claim 1 and 3, wherein capacitive element is connected to the drain region and except the branch grid of the most close source region at least one divided between grid.

6, according to the high-pressure work field-effect transistor of one of claim 2 and 4, wherein capacitive element is connected to the drain region and except the branch grid of the most close source region at least one divided between grid.

7, according to the high-pressure work field-effect transistor of one of claim 1 and 3, wherein capacitive element be connected to except the branch grid of the most close source region at least one pair of divide between grid.

8, according to the high-pressure work field-effect transistor of one of claim 2 and 4, wherein capacitive element be connected to except the branch grid of the most close source region at least one pair of divide between grid.

9, according to the high-pressure work field-effect transistor of one of claim 1 and 3, wherein an end of rectifying device be connected to except the branch grid of the most close source region at least one divide grid, and second constant potential is provided for the other end of rectifying device.

10, according to the high-pressure work field-effect transistor of one of claim 2 and 4, wherein an end of rectifying device be connected to except the branch grid of the most close source region at least one divide grid, and second constant potential is provided for the other end of rectifying device.

11, according to claim 1,2, one of 3 and 4 described high-pressure work field-effect transistors, wherein substrate is a Semiconductor substrate.

12, according to claim 1,2, one of 3 and 4 described high-pressure work field-effect transistors, wherein substrate is such substrate, in this substrate, is positioned on the surface of support substrates with the semiconductive thin film of support substrates insulation.

13, a kind of high-pressure work field-effect transistor comprises:

Substrate;

Mutual separated source region and drain region on the surface of substrate;

The lip-deep semiconductor channel shaped region of the substrate between source region and drain region;

A plurality of minutes grids above the raceway groove shaped region, this a plurality of minutes grids obtain by cutting apart in source/drain extreme direction; And

A plurality of gate insulating films between raceway groove shaped region and a plurality of minutes grids,

Wherein at least one in signal potential and the signal code is provided for the source region, first constant potential is provided in a plurality of minutes grids the branch grid of close source region, and bias potential is offered respectively than the branch grid of the more close drain region of branch grid of close source region, wherein each bias potential has the absolute value that is equal to, or greater than first constant potential, each bias potential is according to the increase of drain potential or reduce to change, and the absolute value of each bias potential becomes big more more towards the drain region.

14,, wherein lay respectively in a plurality of minutes raceway groove shaped regions between the grid with mesozone that channel carrier has an identical conduction type according to the high-pressure work field-effect transistor of claim 13.

15, according to the high-pressure work field-effect transistor of one of claim 13 and 14, wherein capacitive element is connected to the drain region and except the branch grid of the most close source region at least one divided between grid.

16, according to the high-pressure work field-effect transistor of one of claim 13 and 14, wherein capacitive element be connected to except the branch grid of the most close source region at least one pair of divide between grid.

17, according to the high-pressure work field-effect transistor of one of claim 13 and 14, wherein an end of rectifying device be connected to except the branch grid of the most close source region at least one divide grid, and second constant potential is provided for the other end of rectifying device.

18, according to the described high-pressure work field-effect transistor in one of claim 13 and 14, wherein substrate is a Semiconductor substrate.

19, according to the described high-pressure work field-effect transistor in one of claim 13 and 14, wherein substrate is such substrate, and in this substrate, the semiconductive thin film that insulate with support substrates is positioned on the surface of support substrates.

20, a kind of biasing circuit that is used for as claim 1,3,5, one of 7 and 9 described high-pressure work field-effect transistors comprises the adder with at least two inputs and an output,

Wherein: increase or the current potential that reduces to change is provided for one of two inputs according to drain potential, and specific potential is provided for another input in two inputs; And the current potential of the output of adder is provided for the branch grid of close drain region as bias potential.

21, a kind of biasing circuit that is used for as claim 2,4,6,8, one of 10 and 13 described high-pressure work field-effect transistors comprises the adder with at least two inputs and an output,

Wherein: increase or the current potential that reduces to change is provided for one of two inputs according to drain potential, and first constant potential is provided for another input in two inputs; And the current potential of the output of adder is provided for the branch grid of close drain region as bias potential.

22, a kind of biasing circuit that is used for as claim 1,3,5, one of 7 and 9 described high-pressure work field-effect transistors comprises:

Adder with at least two inputs and an output; And

First group of a plurality of resistor that is connected in series;

Wherein: an end of the end parts that is connected in series of first group of a plurality of resistor that are connected in series is connected to the output of adder, and specific potential is provided for the other end of the end parts that is connected in series; Be provided in two inputs one according to the increase of drain potential or the current potential that reduces to change, specific potential is provided for another in two inputs; And the position that bias potential is selected from the described end of the end parts that is connected in series of first group of a plurality of resistor that are connected in series and series connection node respectively is provided for the branch grid.

23, be used for biasing circuit as claim 2,4,6,8, one of 10 and 13 described high-pressure work field-effect transistors according to claim 22 a kind of, wherein: first constant potential is provided for another input in two inputs; And first constant potential is provided for the other end of the end parts that is connected in series of first group of a plurality of resistor that are connected in series.

24, a kind of being used for as claim 1 to 2, the biasing circuit of one of 3 to 10 and 13 described high-pressure work field-effect transistors comprises two resistors that are connected in series,

Wherein: the current potential of high voltage source is provided for an end of the end parts that is connected in series of two resistors that are connected in series, and the other end of the end parts that is connected in series is connected to the drain region; And bias potential is provided for the branch grid of close drain region from the node between two resistors that are connected in series.

25, be used for biasing circuit according to claim 24 a kind of as claim 1,3,5, one of 7 and 9 described high-pressure work field-effect transistors, wherein: an end of first group of a plurality of resistor that are connected in series is connected to two nodes between the resistor that is connected in series, and specific potential is provided for the other end of first group of a plurality of resistor that are connected in series; And the position of selecting from the series connection node of first group of a plurality of resistor that are connected in series and the end parts that is connected in series obtains bias potential, so that described bias potential is offered the branch grid respectively.

26, be used for biasing circuit according to claim 24 a kind of as claim 2,4,6,8, one of 10 and 13 described high-pressure work field-effect transistors, wherein: an end of first group of a plurality of resistor that are connected in series is connected to two nodes between the resistor that is connected in series, and first constant potential is provided for the other end of first group of a plurality of resistor that are connected in series; And the position of selecting from the series connection node of first group of a plurality of resistor that are connected in series and the end parts that is connected in series obtains bias potential, so that described bias potential is offered the branch grid respectively.

27, a kind of biasing circuit that is used for as claim 1,3,5, one of 7 and 9 described high-pressure work field-effect transistors comprises the rectifying device and the resistor that are connected in series,

Wherein: the end that is connected in series of rectifying device side is connected to drain electrode; Specific potential is provided for the end that is connected in series of resistor side; And bias potential is provided for the branch grid of close drain region from the node between rectifying device and the resistor.

28, a kind of biasing circuit that is used for as claim 2,4,6,8, one of 10 and 13 described high-pressure work field-effect transistors comprises the rectifying device and the resistor that are connected in series,

Wherein: the end that is connected in series of rectifying device side is connected to drain electrode; First constant potential is provided for the end that is connected in series of resistor side; And bias potential is provided for the branch grid of close drain region from the node between rectifying device and the resistor.

29, a kind of biasing circuit that is used for as claim 1,3,5, one of 7 and 9 described high-pressure work field-effect transistors comprises:

Rectifying device; And

Second group of a plurality of resistor that is connected in series,

Wherein: an end of rectifying device is connected to an end of second group of a plurality of resistor that are connected in series; The other end of rectifying device is connected to drain electrode; Specific potential is provided for the other end of second group of a plurality of resistor that are connected in series; And the position that current potential is selected from the be connected in series end and the series connection node of second group of a plurality of resistor that are connected in series by second group of a plurality of resistor that are connected in series is provided for the branch grid respectively.

30, a kind of biasing circuit that is used for as claim 2,4,6,8, one of 10 and 13 described high-pressure work field-effect transistors comprises:

Rectifying device; And

Second group of a plurality of resistor that is connected in series,

Wherein: an end of rectifying device is connected to an end of second group of a plurality of resistor that are connected in series; The other end of rectifying device is connected to drain electrode; First constant potential is provided for the other end of second group of a plurality of resistor that are connected in series; And the position that current potential is selected from the be connected in series end and the series connection node of second group of a plurality of resistor that are connected in series by second group of a plurality of resistor that are connected in series is provided for the branch grid respectively.

31, a kind of high-pressure work circuit element comprises:

First insulated gate FET;

Second field-effect transistor with the first insulated gate FET complementation;

One end is connected to first resistor of the drain region of first insulated gate FET; And

One end is connected to second resistor of the source region of first insulated gate FET,

Wherein: first current potential is provided for the other end of first resistor; And second current potential is provided for the other end of second resistor; Second field-effect transistor is as claim 1,3,5,7 and 9 described high-pressure work field-effect transistors, and comprises at least two branch grids, and the source electrode of second field-effect transistor is connected to the drain electrode of first insulated gate FET; The branch grid of the source region of the most close second field-effect transistor is connected to the source electrode of first insulated gate FET; Second current potential is provided for the branch grid of the drain region of the most close second field-effect transistor; The grid of first insulated gate FET is set to an input; And output obtains from a position of being selected by the source electrode and the drain electrode of first insulated gate FET.

32, a kind of high-pressure work circuit element comprises:

First insulated gate FET;

Second field-effect transistor with the first insulated gate FET complementation;

One end is connected to first resistor of the drain region of first insulated gate FET; And

One end of the end parts that is connected in series is connected to second group of a plurality of resistor that is connected in series of the source electrode of first insulated gate FET,

Wherein: second field-effect transistor is as claim 1,3,5,7 and 9 described high-pressure work field-effect transistors, and comprises at least three branch grids; The source electrode of second field-effect transistor is connected to the drain electrode of first insulated gate FET; The branch grid is connected respectively to by the node of the end parts that is connected in series of second group of a plurality of resistor that are connected in series and the position that an end is selected; The other end of first resistor is connected to first current potential; Second current potential is provided for the other end of the end parts that is connected in series of second group of a plurality of resistor that are connected in series; The grid of first insulated gate FET is set to an input; And the position that output is selected from the node by the source electrode of first insulated gate FET and drain electrode and second group of a plurality of resistor that are connected in series obtains.

33, according to the high-pressure work circuit element of claim 31, wherein capacitive element is connected between one of the source electrode of the input and first insulated gate FET and drain electrode.

34, according to the high-pressure work circuit element of claim 32, wherein capacitive element is connected between one of the source electrode of the input and first insulated gate FET and drain electrode.

35. according to the high-pressure work circuit element of one of claim 31 and 32, wherein first insulated gate FET is a depletion mode transistor.

36, according to the high-pressure work circuit element of one of claim 31 to 34, wherein at least one in first resistor and second resistor is made up of a plurality of resistors that are connected in series, and the node between a plurality of resistors that are connected in series is set to an output.

37, according to the high-pressure work circuit element of one of claim 31 to 34, wherein first resistor is made up of a plurality of resistors that are connected in series, and the source electrode of second field-effect transistor is connected to the node between a plurality of resistors that are connected in series.

38, according to the high-pressure work circuit element of one of claim 31 to 34, wherein second resistor is made up of a plurality of resistors that are connected in series, and the drain electrode of second field-effect transistor is connected to the node between a plurality of resistors that are connected in series.

39, according to the high-pressure work circuit element of one of claim 31 to 34, wherein the drain electrode of second field-effect transistor is connected to second current potential.

40, according to the high-pressure work circuit element of one of claim 31 to 34, wherein the drain electrode of second field-effect transistor is connected to second current potential by the 3rd resistor.

41, according to the high-pressure work circuit element of one of claim 31 to 34, wherein the drain electrode of second field-effect transistor is connected to the 3rd current potential.

42, according to the high-pressure work circuit element of one of claim 31 to 34, wherein the drain electrode of second field-effect transistor is connected to the 3rd current potential by the 3rd resistor.

43, according to the high-pressure work circuit element of one of claim 31 to 34, wherein one of first resistor and second resistor are made by constant flow element.

44, a kind of biasing circuit that comprises as the described high-pressure work circuit element of one of claim 31 to 34, wherein: first current potential forms the high voltage source current potential; Second current potential forms earthing potential, and earthing potential is provided for the drain electrode of second field-effect transistor by the 3rd resistor; The grid of first insulated gate FET is connected to the drain electrode as claim 1 to 2, one of 3 to 10 and 13 described high-pressure work field-effect transistors; And bias potential is provided for the branch grid of the most close drain region as claim 1 to 2, one of 3 to 10 and 13 described high-pressure work field-effect transistors from the drain electrode of first insulated gate FET and the node between first resistor.

45, a kind ofly comprise as the described high-pressure work circuit element of one of claim 36 to 38 and be used for biasing circuit as claim 1,3,5, one of 7 and 9 described high-pressure work field-effect transistors, wherein first current potential forms the high voltage source current potential, specific potential replaces the other end that second current potential is provided for second group of a plurality of resistor that are connected in series, and current potential is from being provided for the branch grid respectively by the position of selecting the node of second group of a plurality of resistor that are connected in series and the end portion.

46, a kind ofly comprise as the described high-pressure work circuit element of one of claim 36 to 38 and be used for biasing circuit as claim 2,4,6, one of 10 and 13 described high-pressure work field-effect transistors, wherein first current potential forms the high voltage source current potential, first constant potential replaces the other end that second current potential is provided for second group of a plurality of resistor that are connected in series, and current potential is from being provided for the branch grid respectively by the position of selecting the node of second group of a plurality of resistor that are connected in series and the end portion.

47, be used for biasing circuit according to a kind of in the claim 44 as claim 1,3,5, one of 7 and 9 described high-pressure work field-effect transistors, wherein an end of first group of a plurality of resistor that are connected in series is connected to the drain electrode of first insulated gate FET and the node between first resistor, specific potential is provided for the other end of first group of a plurality of resistor that are connected in series, and current potential is from offering the branch grid respectively by the position of selecting the node of first group of a plurality of resistor that are connected in series and the end portion.

48, be used for biasing circuit according to a kind of in the claim 44 as claim 2,4,6,8, one of 10 and 13 described high-pressure work field-effect transistors, wherein an end of first group of a plurality of resistor that are connected in series is connected to the drain electrode of first insulated gate FET and the node between first resistor, first constant potential is provided for the other end of first group of a plurality of resistor that are connected in series, and current potential is from offering the branch grid respectively by the position of selecting the node of first group of a plurality of resistor that are connected in series and the end portion.

49, a kind ofly comprise as the described high-pressure work circuit element in one of claim 32 or 34 and be used for biasing circuit as claim 1 to 2, one of 3 to 10 and 13 described high-pressure work field-effect transistors, wherein first current potential forms the high voltage source current potential, and earthing potential replaces the other end that second current potential is provided for second resistor, to provide current potential to the branch grid of close drain region.

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