CN100474588C - Semiconductor device - Google Patents
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- CN100474588C CN100474588C CNB2006100042086A CN200610004208A CN100474588C CN 100474588 C CN100474588 C CN 100474588C CN B2006100042086 A CNB2006100042086 A CN B2006100042086A CN 200610004208 A CN200610004208 A CN 200610004208A CN 100474588 C CN100474588 C CN 100474588C
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Abstract
A semiconductor device is provided. In a conventional semiconductor device, there has been a problem that, in a region where a wiring layer to which a high electric potential is applied traverses a top surface of an isolation region, the withstand voltage is deteriorated. In a semiconductor device of the present invention, an epitaxial layer is deposited on a substrate, and an LDMOSFET is formed in one region divided by an isolation region. In a region where a wiring layer connected to a drain electrode traverses a top surface of the isolation region, a conductive plate having a ground electric potential and another conductive plate in a floating state are formed under the wiring layer. With this structure, electric field is reduced in the vicinity of the isolation region under the wiring layer, whereby a withstand voltage of the LDMOSFET is increased.
Description
Technical field
Near the electric field that the present invention relates to seek separated region relaxes, and the semiconductor device that voltage endurance is improved.
Background technology
As one of existing power semiconductor arrangement, horizontal type bilateral diffusion field-effect tranisistor (below be called LDMOSFET (Lateral Double Diffused Metal Oxide Semiconductor Field EffectTransister)) is well-known.For example LDMOSFET and other signal processing circuit are integrated on the same semiconductor chip, use as drive circuit.And on the zone on separated region, the drain electrode that the drain region of LDMOSFET is applied high potential is striden separated region and is drawn out to the outside.At the separated region that is positioned at the drain electrode downside, the diffusion zone lower than the concentration in Disengagement zone territory extends to the drain region side from separated region.By this structure, near the electric field the end of the separated region that drain electrode is striden is concentrated and is relaxed, and improves withstand voltage between drain electrode-source electrode.This technology is known (for example with reference to patent documentation 1).
Existing height is withstand voltage to be integrated on the same semiconductor chip with LDMOSFET and other signal processing circuit (for example control circuit or logical circuit), forms high-withstand-voltage integrated circuit.As this structure, on the epitaxial loayer on the Semiconductor substrate, be formed with the separated region that arrives substrate from epi-layer surface in lamination.The zone that forms LDMOSFET utilizes separated region to be electrically insulated with other element-forming region to separate.And on the zone on separated region, the drain electrode that applies high potential in the drain region to LDMOSFET is striden separated region and is drawn.At the separated region that is positioned at below the drain electrode, form the conductive layer that is electrically connected with separated region, it covers above engaging zones with separated region and epitaxial loayer.By this structure, near the electric field the end of the separated region that drain electrode is striden is concentrated and is relaxed, and improves withstand voltage between drain electrode-source electrode.This technology is well-known (for example with reference to patent documentation 2).
Patent documentation 1: the spy opens flat 10-242452 communique (6-8 page or leaf, 1-3 figure)
Patent documentation 2: the spy opens flat 9-260503 communique (4-6 page or leaf, 1-5 figure)
As mentioned above, in existing LDMOSFET, relax, extend to the drain region side from separated region than the diffusion zone of territory, Disengagement zone low concentration because near the electric field the end of the separated region that drain electrode is striden is concentrated.And, extending to form to the drain region side by making with the idiostatic diffusion zone of separated region, the drain region is formed on the zone further from separated region.By this structure, below above-mentioned diffusion zone, form the inactive area that does not dispose LDMOSFET.Therefore, existence can not be efficiently the problem of chip size configuration element-forming region relatively.
In addition, in existing LDMOSFET, concentrate near the electric field the end of the separated region that will be positioned at drain electrode below and to relax, and form the conductive layer that above separated region, extends to the drain region side.And conductive layer and separated region are idiostatic.By this structure, the relative drain electrode of conductive layer has screen effect.Its on the other hand, conductive layer has the field plate effect that the Potential distribution that is formed at epitaxial loayer is exerted an influence.That is,, the distance of separation of conductive layer and epitaxial loayer need be increased, will reduce from the influence of conductive layer in the drain region side.For realizing this structure, the dielectric film above the epitaxial loayer need be thickened, and the problem that exists manufacturing cost to raise.
In addition, in existing LDMOSFET, near the electric field that is positioned at for mitigation the end of separated region of drain electrode below is concentrated, and forms the conductive layer that extends above separated region to the drain region side.Conductive layer forms step-like, and it is along with big more near the distance of separation of drain region and epitaxial loayer.And conductive layer for example is made of metals such as aluminium or low-resistance polysilicon etc.By this structure, need between separated region and drain region, carry out microfabrication in narrow zone, cause the complicated problem of manufacturing process and exist.In addition, the thickness of the dielectric film of conductive layer below is also different, also needs to be used to form the special-purpose operation of conductive layer, and the problem that exists manufacturing cost to raise.
Summary of the invention
The present invention the invention provides a kind of semiconductor device in view of above-mentioned various situations constitute, and it has, separated region, and it is distinguished into a plurality of element-forming region with semiconductor layer; Insulating barrier, it is formed on above the described semiconductor layer; Wiring layer, it strides across described separated region, and on described insulating barrier from a described element-forming region to another described component forming region domain wiring, on the described insulating barrier of described wiring layer downside, have: the first conduction anode, it covers on the engaging zones of described separated region and described semiconductor layer and disposes, and is electrically connected with described separated region; The second conduction anode, it is configured between described first conduction anode and the described wiring layer with floating state, and its at least a portion zone intersects to form respectively with described first conduction anode and described wiring layer.Therefore, in the present invention, apply the current potential identical with separated region at the first conduction anode.The second conduction anode is according to the intermediate potential of the current potential of the current potential of electric capacity composition of proportions wiring layer and the first conduction anode.By this structure, can relax near the electric field of separated region and concentrate, can improve voltage endurance.
In addition, in semiconductor device of the present invention, described second conduction anode side direction under described wiring layer is extended from the direction that described separated region leaves, and described second the conduction one end anode, that be positioned at a described element-forming region and described first the conduction anode, be positioned at identity element form the zone an end compare, further from described separated region.Therefore, in the present invention, the second conduction anode has screen effect with respect to wiring layer.On the other hand, second conducting screen has the field screen effect that the Potential distribution that is formed on the semiconductor layer is exerted an influence.
In addition, in semiconductor device of the present invention, the current potential of the described second conduction anode is 0.3～0.6 times the current potential that is applied to the current potential on the described wiring layer.Therefore, in the present invention, the second conduction anode carries out electric capacity respectively with the first conduction anode and wiring layer and engages.By this structure, the second conduction anode is applied to 0.4～0.6 times current potential of the current potential on the wiring layer according to its electric capacity composition of proportions, can relax the electric field of the extreme portion of first conducting screen and concentrate.
In semiconductor device of the present invention, the described first conduction anode is made of polysilicon film.Therefore, in the present invention, the first conduction anode is made of polysilicon film.By this structure, when element-forming region forms MOSFET,, can form the first conduction anode by the operation shared with gate electrode.
In semiconductor device of the present invention, the described wiring layer downside that applies the current potential higher than described separated region be formed with described first and described second the conduction anode.Therefore, in the present invention, below applying the wiring layer of high potential, dispose first and second conduction anode.By this structure, particularly can relax the electric field of the wiring layer downside that is applied with high potential and concentrate, can improve voltage endurance.
In semiconductor device of the present invention, this semiconductor device has: separated region, and it is distinguished into a plurality of element-forming region with semiconductor layer; Insulating barrier, it is formed at above the described semiconductor layer; Wiring layer, it intersects on described separated region, on described insulating barrier from a described element-forming region to another described component forming region domain wiring, on the described insulating barrier of described wiring layer downside, have: the first conduction anode, it disposes with floating state, covers above the engaging zones of described separated region and described semiconductor layer; The second conduction anode, it is configured between described first conduction anode and the described wiring layer with floating state, and its at least a portion zone intersects to form respectively with described first conduction anode and described wiring layer.Therefore, in the present invention, can according to the electric capacity ratio first the conduction anode current potential and second the conduction anode current potential between set different current potentials respectively.By this structure, can relax near the electric field in separated region end that is positioned at the wiring layer below that is applied with high potential and concentrate, can improve voltage endurance.
In semiconductor device of the present invention, the current potential of the described first conduction anode is the current potential height than described separated region, than the low current potential of current potential of the described second conduction anode.Therefore, in the present invention, relative second conducting screen of the first conduction anode has screen effect.On the other hand, first conducting screen has the field screen effect that the Potential distribution that is formed on the semiconductor layer is exerted an influence.
In semiconductor device of the present invention, this semiconductor device has: separated region, and it is formed on the semiconductor layer; A plurality of semiconductor elements, it is surrounded by described separated region and is formed on the described semiconductor layer; Wiring layer, its insulation processing and forming on described semiconductor layer is extended to another described semiconductor element by described separated region from a described semiconductor element, is fixed as desirable current potential; The first conduction anode, its be insulated handle and overlay configuration in described wiring layer lower floor, be electrically connected with described separated region; The second conduction anode, its and described first conduction anode and the described wiring layer between insulation processing, and at least a portion and the described first conduction anode and described wiring layer be overlay configuration respectively, by change at least described wiring layer and described second the conduction anode overlapping area or described second the conduction anode and described first the conduction anode overlapping area, adjust described second the conduction anode current potential.Therefore, in the present invention, dispose first and second conduction anode that lower floor is insulated processing on the wiring layer that is electrically connected between with semiconductor element.According to this structure, the overlapping area by adjusting the first conduction anode and the second conduction anode and the overlapping area of second conduction anode and wiring layer can be adjusted the current potential of the second conduction anode, can improve the voltage endurance of semiconductor element.
In the present invention, the area configurations of intersecting on separated region at the wiring layer that is applied with high potential has and the conduction anode of separated region same potential and the conduction anode of floating state.According to this structure, can relax near the electric field in separated region end that is disposed at the wiring layer downside and concentrate, can improve the voltage endurance of semiconductor element.
In the present invention, dispose the conduction anode of floating state at the wiring layer downside that is applied with high potential.This conduction anode is according to the desirable current potential of electric capacity composition of proportions.By this structure and manufacture method, the relative wiring layer of this conduction anode has screen effect.On the other hand, according to the field screen effect of this conduction anode, can improve the voltage endurance of semiconductor element.
In the present invention, be applied with the wiring layer downside of high potential, and covering above the engaging zones of conduction anode with separated region and semiconductor layer of separated region same potential.According to this structure, can obtain the screen effect of this conduction anode, can relax near the electric field in separated region end and concentrate.
In the present invention, dispose two conduction anodes of floating state at the wiring layer downside that is applied with high potential.The high current potential of current potential near the conduction anode constituent ratio separated region above the separated region.According to this structure, near the conduction anode above the separated region, mainly has effect as screen effect.On the other hand, this conduction anode also has an effect of screen effect, can improve the voltage endurance of semiconductor element.
Description of drawings
Fig. 1 is the profile that is used to illustrate the N channel-type LDMOSFET of the embodiment of the invention;
Fig. 2 (A) is used to illustrate that the separated region upper electric field of the embodiment of the invention relaxes the profile of structure, (B), (C) be the figure that is used to illustrate the capacity coupled state above the top separated region;
Fig. 3 is the figure that is used to illustrate the withstand voltage relation of the ratio of the wiring layer current potential of the embodiment of the invention and conducting screen electrode potential and LDMOSFET;
Fig. 4 (A) is the figure of Potential distribution of the LDMOSFET of the explanation embodiment of the invention, (B) is that the ionization by collision of explanation LDMOSFET produces the figure in zone;
Fig. 5 is the profile that is used to illustrate the N channel-type LDMOSFET of the embodiment of the invention;
Fig. 6 (A) is the plane graph that is used to illustrate the N channel-type LDMOSFET of the embodiment of the invention, (B) is its plane graph.
Symbol description
1 N channel-type LDMOSFET
3 N type epitaxial loayers
4 separated regions
6 n type diffused layers
16 drain electrodes
18 wiring layers
24 conduction anodes
25 conduction anodes
31 N channel-type LDMOSFET
32 wiring layers
33 conduction anodes
34 conduction anodes
35 silicon oxide films
Embodiment
Below, describe the semiconductor device of one embodiment of the invention in detail with reference to Fig. 1～Fig. 4.Fig. 1 is the profile that is used to illustrate the N channel-type LDMOSFET of present embodiment.Fig. 2 (A) is used to illustrate that the separated region upper electric field of present embodiment relaxes the profile of structure.Fig. 2 (B) is the figure of the capacity coupled state on separated region of explanation present embodiment.Fig. 2 (C) is the figure of the capacity coupled state on separated region of explanation present embodiment.Fig. 3 is the wiring layer current potential that is used to illustrate present embodiment and the figure of the withstand voltage relation of the ratio of conducting screen electrode potential and LDMOSFET.Fig. 4 (A) is the figure of Potential distribution of the LDMOSFET of explanation present embodiment.Fig. 4 (B) is that the ionization by collision of the LDMOSFET of explanation present embodiment produces the figure in zone.
As shown in Figure 1, N channel-type LDMOSFET1 mainly by p type single crystal silicon substrate 2, N type epitaxial loayer 3, P type separated region 4, N type imbed diffusion layer 5, the n type diffused layer 6,7 that uses as the drain region, the p type diffused layer 8,9 that uses as the reverse grid zone, n type diffused layer 10, locos oxide film 11, grid oxidation film 12, gate electrode 13, insulating barrier 14,15, drain electrode 16, source electrode 17, the wiring layer 18 that uses as the source region constitute.
N type epitaxial loayer 3 is piled up in above the p type single crystal silicon substrate 2.In addition, the epitaxial loayer in the present embodiment 3 corresponding " semiconductor layer " of the present invention.And, in the present embodiment, the situation that is formed with one deck epitaxial loayer 3 on substrate 2 is described, but is not limited thereto.For example, as " semiconductor layer " of the present invention, also can be the situation that lamination has the multilayer epitaxial layer on substrate.In addition, " semiconductor layer " of the present invention can only be the situation of substrate also, and substrate also can be n type single crystal silicon substrate, compound semiconductor substrate.
P type separated region 4 is formed on substrate 2 and the epitaxial loayer 3.Separated region 4 connects from the P type of substrate 2 diffusion into the surfaces to be imbedded diffusion layer and forms from the p type diffused layer of epitaxial loayer 3 diffusion into the surfaces.And separated region 4 is idiostatic with substrate 2, for example, is applied with earthing potential (GND).By this structure, epitaxial loayer 3 is distinguished into a plurality of element-forming region by the PN junction zone of separated region 4 and epitaxial loayer 3 and the PN junction zone of substrate 2 and epitaxial loayer 3.
The N type is imbedded diffusion layer 5 and is formed on substrate 2 and 3 two zones of epitaxial loayer.The N type is imbedded diffusion layer 5 and is for example made antimony (Sb) diffusion and formation.As shown in the figure, the N type is imbedded the below, formation zone that diffusion layer 5 is formed on LDMOSFET1.
N type diffused layer 6,7 is formed on the epitaxial loayer 3.N type diffused layer 6 is used as the drain region and uses, and n type diffused layer 7 is used as the drain electrode export area and uses.N type diffused layer 6,7 surrounds p type diffused layer 8 and forms a ring-type.
P type diffused layer 8,9 is formed on the epitaxial loayer 3.P type diffused layer 8 is used as the reverse grid zone and uses, and p type diffused layer 9 is used as the reverse grid export area and uses.
N type diffused layer 10 is formed on the p type diffused layer 8.N type diffused layer 10 is used as the source region and uses.N type diffused layer 10 surrounds p type diffused layer 9 and forms a ring-type.P type diffused layer 8 between n type diffused layer 6 and n type diffused layer 10 is used as channel region and uses.
LOCOS (Local Oxidation of Silicon) oxide-film 11 is formed on the desirable zone of epitaxial loayer 3.Locos oxide film 11 is formed on above the separated region 4, realizes that element separates.In addition, locos oxide film 11 so long as thick oxide-film get final product.For example, also can be on separated region 4, burying the situation of the structure of utilizing the groove that STI (shallow-trench isolation Shallow Trench Isolation) method forms underground by dielectric film.
At last, not shown among the figure, but on insulating barrier 15 optionally lamination form bpsg film, sog film, TEOS film, silicon nitride film etc.And the silicon nitride film that is formed at the superiors is used as diaphragm and uses, and can suppress the intrusion of moisture.
Shown in Fig. 2 (A),, below wiring layer 18, be formed with conduction anode 24,25 above separated region 4 in the zone that the wiring layer 18 that is connected with drain electrode 16 intersects.In addition, the conduction anode 24 " the first conduction anode " corresponding of the present invention in the present embodiment, conduction anode 25 corresponding " second anode " of the present invention.
Shown in Fig. 2 (B), the conduction anode 25 of floating state is a dielectric material with insulating barrier 14, with conduction anode 24 capacitive coupling as earthing potential.And, the electric capacity of conduction anode 24 and conduction anode 25 is made as C1.On the other hand, conduction anode 25 is a dielectric material with insulating barrier 15, with wiring layer 18 capacitive coupling of drain potential.And, the electric capacity of conduction anode 25 and wiring layer 18 is made as C2.In addition, M1 is the conduction anode 24 of X-direction and the subtend width of conduction anode 25, and M2 is the conduction anode 25 of Y direction and the subtend width of wiring layer 18.
At this moment, shown in Fig. 2 (C), capacitor C 1, C2 can carry out any design alteration according to the pattern arrangement of conduction anode 25.Solid line is conduction anode 24, and dotted line is conduction anode 25, and chain-dotted line is a wiring layer 18.The zone of conduction anode 24 and conduction anode 25 subtends is by the shadow representation of oblique line, and the zone of conduction anode 25 and wiring layer 18 subtends is by the shadow representation of point.For example, in Y direction, than conducting electricity the narrow of anode 24, under the wide situation than wiring layer 18, N1 diminishes at the width that designs conduction anode 25, and conduction anode 24 diminishes with the zone of conduction anode 25 subtends.Consequently capacitor C 1 reduces.In addition, in X-direction, extend under the situation of contact hole 23 sides than conduction anode 24 at conduction anode 25, it is big that M2 becomes, and it is big that the zone of conduction anode 25 and wiring layer 18 subtends becomes.Consequently capacitor C 2 increases.In addition, N1 is the conduction anode 24 of Y direction and the width of conduction anode 25 subtends, and N2 is the conduction anode 25 of Y direction and the subtend width of wiring layer 18.
And, conduction anode 25 respectively with the capacitor C 1, C2 of wiring layer 18 and conduction anode 24 according to above-mentioned condition displacement.That is, dispose in fixed area under the situation of conduction anode 24 and wiring layer 18, can consider that the quantity of electric charge that conducts electricity between anode 24 and the wiring layer 18 is certain.At this moment, capacitor C 1, C2 can be according to the current potentials of its electric capacity distribution ratio adjustment conduction anode 25 according to the configuring area displacement of conduction anode 25.In the present embodiment, can be according to the current potential of design condition adjustment such as area, the allocation position conduction anode 25 of conduction anode 25.In addition, under the situation of the pattern arrangement of design alteration conduction anode 24 and wiring layer 18, equally also can adjust capacitor C 1, C2, adjust the current potential of conduction anode 25.
Specifically, with the conduction anode 25 current potential be V1, be V2 with the current potential that puts on the wiring layer 18.In addition, as mentioned above, on conduction anode 24, be applied with earthing potential.At this moment, V1 utilizes following numerical expression to represent with the relation of itself and V2.
V1＝{C2/(C1+C2)}×V2
In addition, as mentioned above, conduction anode 25 is configured between conduction anode 24 and the wiring layer 18.By this structure, forming the intermediate potential that puts on the current potential on the conduction anode 24 and put on the current potential on the wiring layer 18 on the conduction anode 25.
As shown in Figure 3, in the structure shown in Fig. 2 (A), solid line represents that distance of separation L1 is the situation of 36 (μ m), and chain-dotted line represents that distance of separation L1 is the situation of 45 (μ m).
Shown in solid line, satisfy following numerical expression, under the situation that has disposed conduction anode 25, the withstand voltage of LDMOSFET is more than 320 (V).
0.3<C2/(C1+C2)<0.6
On the other hand, shown in chain-dotted line, satisfy following numerical expression, under the situation that has disposed conduction anode 25, the withstand voltage of LDMOSFET is more than 320 (V).
0<C2/(C1+C2)<0.6
That is, in the structure shown in Fig. 2 (A), though owing to the size of distance of separation L1 there are differences, configuration conduction anode 25 between conduction anode 24 and wiring layer 18, the current potential V1 that makes conduction anode 25 are 0.3～0.6 times of current potential V2 of wiring layer 18.By this structure, conduction anode 25 relative wiring layers 18 have screen effect.And the wiring layer 18 that is applied with high potential will give the influence mitigation of the Potential distribution of epitaxial loayer 3.On the other hand, the Potential distribution of conduction anode 25 relative epitaxial loayers 3 has a screen effect.And, equipotential line is reduced in an end 28 intensive situations of conduction anode 24, make concentrated mitigation of electric field to an end 28 of conduction anode 24.
Specifically, shown in Fig. 4 (A), be under 0.6 times the situation of current potential V2 of wiring layer 18 at the current potential V1 of conduction anode 25, the zone that equipotential line is intensive is dispersed in an end 27 of conduction anode 25 and an end 28 of conduction anode 24.Final shown in the shadow region of Fig. 4 (B), the epitaxial loayer 3 below an end 28 of conduction anode 24 produces ionization by collision.But, by conducting electricity the pattern arrangement of anode 25, on conduction anode 25, setting desirable current potential, can relax concentrating to the electric field of an end 28 of the conducting screen utmost point 24, improve the voltage endurance of LDMOSFET.
Secondly, describe the semiconductor device of another embodiment of the present invention in detail with reference to Fig. 5.Fig. 5 is the profile that is used to illustrate the N channel-type LDMOSFET of present embodiment.
In addition, as shown in Figure 5, another embodiment of the present invention is two conduction anodes of configuration floating state on separated region, and the structure of seeking the electric field mitigation of separated region.And the structure of N channel-type LDMOSFET31 that is formed at element-forming region is identical with the structure of N channel-type LDMOSFET1 shown in Figure 1.Therefore, the explanation of N channel-type LDMOSFET31 is with reference to the explanation of Fig. 1, and the structural element identical with each inscape shown in Figure 1 uses identical symbol.In addition, when the explanation of the semiconductor device that carries out another embodiment of the present invention, suitably describe with reference to Fig. 2 and Fig. 3.
In the present embodiment, in the zone that the wiring layer 32 that is connected with drain electrode 16 intersects, below wiring layer 32, be formed with conduction anode 33,34 on separated region 4.In addition, the conduction anode 33 " the first conduction anode " corresponding of the present invention in the present embodiment, conduction anode 34 " the second conduction anode " corresponding of the present invention.
As mentioned above, in the present embodiment, also by insulating barrier 14,15,35 with separated region 4 and conduction anode 33 capacitive coupling, will conduct electricity the anode 33 and anode 34 capacitive coupling of conducting electricity, will conduct electricity anode 34 and wiring layer 32 capacitive coupling.In the present embodiment, conduction anode 33 forms near end 38 electric fields that utilize its screen effect to seek separated region 4 relax.And by the pattern arrangement of conduction anode 33, the current potential of conduction anode 33 preferably is made as 10 (V) below the degree than the current potential height in Disengagement zone territory 4.At this, the silicon oxide films 35 below the conduction anode 33 utilize the condition formation identical with grid oxidation film 12.And, silicon oxide film 35 can be punctured etc. from the electric field of conduction anode 33, need guarantee the reliability of silicon oxide film 35.Therefore, the current potential upper limit preferred 10 (V) degree of conduction anode 33.In addition, stride configuration conduction anodes 33 above the separated region 4, make the electric capacity of the capacity ratio conduction anode 33 of separated region 4 and conduction anode 33 and wiring layer 32 big.By this structure, the current potential of conduction anode 33 can be made as it 10 (V) below the degree than the current potential height in Disengagement zone territory 4.
In the present embodiment, according to the electric capacity distribution ratio, the current potential of conduction anode 33 is set to below 10 (V) than the current potential height in Disengagement zone territory 4.Thus, as mentioned above, conduction anode 33 has screen effect, on the other hand, also has a screen effect.According to this structure, near the electric field the end 38 of separated region 4 can be concentrated and relax, can improve the voltage endurance of LDMOSFET31.
On the other hand, be the screen effect of must showing up, conduction anode 34 mainly is configured in desirable zone.At this, be C3 with the electric capacity of conduction anode 33 and conduction anode 34, be C4 with the electric capacity of conduction anode 34 and wiring layer 32.The current potential of conduction anode 33 is that 10 (V) are below the degree.Therefore, as shown in Figure 3, by configuration conduction anode 34, the value that makes C4/ (C3+C4) is concentrated the electric field of an end 37 of conduction anode 33 and is relaxed for example in the scope of 0.3～0.6 degree.And, can improve the voltage endurance of LDMOSFET31.
Secondly, with reference to the Fig. 6 (A) and (B) plane pattern of key diagram 1 and semiconductor device shown in Figure 5.The plane graph of the LDMOSFET that Fig. 6 (A) expression is shown in Figure 1, the plane graph of the LDMOSFET that Fig. 6 (B) expression is shown in Figure 5.In addition, when the inscape of explanation LDMOSFET, with Fig. 1, Fig. 2 and the identical identical symbol of inscape use of each inscape shown in Figure 5.
Shown in Fig. 6 (A), from most peripheral, expression P type separated region 4 between the solid line 41 and 42, expression N type epitaxial loayer 3 between the solid line 42 and 43, expression n type diffused layer 6 between the solid line 43 and 44, expression n type diffused layer 7 between the solid line 45 and 46, expression p type diffused layer 8 between the solid line 44 and 47, expression n type diffused layer 10 between the solid line 47 and 48, the frame table of solid line 48 shows p type diffused layer 9.In addition, gate electrode 13 and the wiring layer that is connected with gate electrode are omitted.
As mentioned above, wiring layer 18 is connected with drain electrode 16 (with reference to Fig. 1) above n type diffused layer 7, applies power supply potential (Vcc) by 18 pairs of drain electrodes 16 of wiring layer.And wiring layer 18 intersects on separated region 4, is drawn out to other element-forming region.In the zone that wiring layer 18 intersects, below wiring layer 18, be formed with conduction anode 24,25 above separated region 14.
Shown in Fig. 6 (B), from most peripheral, expression P type separated region 4 between the solid line 51 and 52, expression N type epitaxial loayer 3 between the solid line 52 and 53, expression n type diffused layer 6 between the solid line 53 and 54, expression n type diffused layer 7 between the solid line 55 and 56, expression p type diffused layer 8 between the solid line 54 and 57, expression n type diffused layer 10 between the solid line 57 and 58, the frame table of solid line 58 shows p type diffused layer 9.In addition, gate electrode 13 and the wiring layer that is connected with gate electrode are omitted.
As mentioned above, wiring layer 32 is connected with drain electrode 16 (with reference to Fig. 5) above n type diffused layer 7, applies power supply potential (Vcc) by 32 pairs of drain electrodes 16 of wiring layer.And wiring layer 32 intersects on separated region 4, is drawn out to other element-forming region.In the zone that wiring layer 32 intersects, below wiring layer 32, be formed with conduction anode 33,34 above separated region 4.
And, be made as 10 (V) below the degree by conducting electricity the current potential of anode 33, utilize the screen effect of conduction anode 24 that near the electric fields the end 38 of separated region 4 are concentrated and relax, improved withstand voltage between drain electrode-source electrode.Therefore, conduction anode 33 is striden separated region 4 and is disposed, and the two elements that is configured in by separated region 4 adjacency forms on the zone.
In addition, in the present embodiment, the situation that the drain electrode of N channel-type LDMOSFET or the wiring layer that is electrically connected with drain electrode are intersected on separated region is illustrated, but is not limited to this situation.For example, in P channel-type LDMOSFET, under the situation that source electrode or the wiring layer that is electrically connected with source electrode intersect, also can obtain identical effect on separated region.In addition, in the situation of npn type bipolar transistor, under the situation that collector electrode or the wiring layer that is electrically connected with collector electrode intersect, also can obtain identical effect on separated region.In addition, in the situation of positive-negative-positive bipolar transistor, under the situation that emitter electrode or the wiring layer that is electrically connected with emitter electrode intersect, also can obtain identical effect on separated region.In addition, in the situation of diode, under the situation that anode electrode or the wiring layer that is electrically connected with anode electrode intersect, also can obtain identical effect on separated region.In addition, as the light receiver of optical semiconductor etc., in diode being applied the situation that reverse biased uses, under the situation that cathode electrode or the wiring layer that is electrically connected with anode electrode intersect, also can obtain identical effect on separated region.That is, the wiring layer higher than Disengagement zone territory at current potential intersects on separated region, and gives can utilize the structure with above-mentioned conduction anode to obtain same effect under the situation of the Potential distribution influence below the wiring layer.In addition, in the scope that does not break away from purport of the present invention, can carry out various changes.
Claims (8)
1, a kind of semiconductor device is characterized in that, has: separated region, and it is distinguished into a plurality of element-forming region with semiconductor layer; Insulating barrier, it is formed on above the described semiconductor layer; Wiring layer, it intersects on described separated region, and on described insulating barrier from a described element-forming region to another described component forming region domain wiring, on the described insulating barrier of described wiring layer downside, have: the first conduction anode, it covers on the engaging zones of described separated region and described semiconductor layer and disposes, and is electrically connected with described separated region; The second conduction anode, it is configured between described first conduction anode and the described wiring layer with floating state, and its at least a portion zone and the described first conduction anode and described wiring layer subtend respectively form.
2, semiconductor device as claimed in claim 1, it is characterized in that, described second conduction anode side direction under described wiring layer is extended from the direction that described separated region leaves, and described second the conduction one end anode, that be positioned at a described element-forming region and described first the conduction anode, be positioned at identity element form the zone an end compare, further from described separated region.
3, semiconductor device as claimed in claim 1 or 2 is characterized in that, the current potential of the described second conduction anode is 0.3～0.6 times the current potential that puts on the current potential on the described wiring layer.
4, semiconductor device as claimed in claim 1 or 2 is characterized in that, the described first conduction anode is made of polysilicon film.
5, semiconductor device as claimed in claim 1 or 2 is characterized in that, the described wiring layer downside that applies the current potential higher than described separated region be formed with described first and described second the conduction anode.
6, a kind of semiconductor device is characterized in that, has: separated region, and it is distinguished into a plurality of element-forming region with semiconductor layer; Insulating barrier, it is formed at above the described semiconductor layer; Wiring layer, it intersects on described separated region, on described insulating barrier from a described element-forming region to another described component forming region domain wiring, on the described insulating barrier of described wiring layer downside, have: the first conduction anode, it disposes with floating state, covers the engaging zones upside of described separated region and described semiconductor layer; The second conduction anode, it is configured between described first conduction anode and the described wiring layer with floating state, and its at least a portion zone intersects to form respectively with described first conduction anode and described wiring layer.
7, semiconductor device as claimed in claim 6 is characterized in that, the current potential of the described first conduction anode is the current potential height than described separated region, than the low current potential of current potential of the described second conduction anode.
8, a kind of semiconductor device is characterized in that, has: separated region, and it is formed on the semiconductor layer; A plurality of semiconductor elements, it is surrounded by described separated region and is formed on the described semiconductor layer; Wiring layer, its insulation processing and forming on described semiconductor layer is extended to another described semiconductor element by described separated region from a described semiconductor element, is fixed as desirable current potential; The first conduction anode, its be insulated handle and overlay configuration in described wiring layer lower floor, be electrically connected with described separated region; The second conduction anode, its and described first conduction anode and the described wiring layer between insulation processing, and at least a portion and the described first conduction anode and described wiring layer be overlay configuration respectively, by change at least described wiring layer and described second the conduction anode overlapping area or described second the conduction anode and described first the conduction anode overlapping area, adjust described second the conduction anode current potential.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005098966 | 2005-03-30 | ||
| JP098966/05 | 2005-03-30 | ||
| JP191023/05 | 2005-06-30 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1841741A CN1841741A (en) | 2006-10-04 |
| CN100474588C true CN100474588C (en) | 2009-04-01 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006100042086A Expired - Fee Related CN100474588C (en) | 2005-03-30 | 2006-01-28 | Semiconductor device |
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| Country | Link |
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| CN (1) | CN100474588C (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100840667B1 (en) * | 2007-06-26 | 2008-06-24 | 주식회사 동부하이텍 | Lateral dmos device and fabrication method therefor |
| US7781834B2 (en) | 2007-07-03 | 2010-08-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Robust ESD LDMOS device |
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| CN1841741A (en) | 2006-10-04 |
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