CN100468567C - 用于在低电源电压操作中产生参考电压的浮动栅极模拟电压电平移位电路和方法 - Google Patents
用于在低电源电压操作中产生参考电压的浮动栅极模拟电压电平移位电路和方法 Download PDFInfo
- Publication number
- CN100468567C CN100468567C CNB2005100922429A CN200510092242A CN100468567C CN 100468567 C CN100468567 C CN 100468567C CN B2005100922429 A CNB2005100922429 A CN B2005100922429A CN 200510092242 A CN200510092242 A CN 200510092242A CN 100468567 C CN100468567 C CN 100468567C
- Authority
- CN
- China
- Prior art keywords
- voltage
- floating grid
- coupled
- grid
- capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/062—Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/067—Single-ended amplifiers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/14—Dummy cell management; Sense reference voltage generators
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/08—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
- H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
- H03K5/2481—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors with at least one differential stage
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/22—Control and timing of internal memory operations
- G11C2207/2254—Calibration
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Read Only Memory (AREA)
- Non-Volatile Memory (AREA)
- Control Of Electrical Variables (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
参数 | SET模式 | READ模式 |
Vcc | 8V | 1V |
Vfg1 | 2.7V | 0.7V |
Vshift | 8V | 0V |
Claims (14)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/884,234 US7113017B2 (en) | 2004-07-01 | 2004-07-01 | Floating gate analog voltage level shift circuit and method for producing a voltage reference that operates on a low supply voltage |
US10/884,234 | 2004-07-01 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1755833A CN1755833A (zh) | 2006-04-05 |
CN100468567C true CN100468567C (zh) | 2009-03-11 |
Family
ID=35513238
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2005100922429A Expired - Fee Related CN100468567C (zh) | 2004-07-01 | 2005-07-01 | 用于在低电源电压操作中产生参考电压的浮动栅极模拟电压电平移位电路和方法 |
Country Status (3)
Country | Link |
---|---|
US (4) | US7113017B2 (zh) |
CN (1) | CN100468567C (zh) |
TW (1) | TWI389117B (zh) |
Families Citing this family (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7113017B2 (en) * | 2004-07-01 | 2006-09-26 | Intersil Americas Inc. | Floating gate analog voltage level shift circuit and method for producing a voltage reference that operates on a low supply voltage |
US7429888B2 (en) * | 2004-01-05 | 2008-09-30 | Intersil Americas, Inc. | Temperature compensation for floating gate circuits |
JP4241466B2 (ja) * | 2004-03-29 | 2009-03-18 | 日本電気株式会社 | 差動増幅器とデジタル・アナログ変換器並びに表示装置 |
US7728713B2 (en) * | 2005-05-06 | 2010-06-01 | Intelleflex Corporation | Accurate persistent nodes |
DE102005043201A1 (de) * | 2005-09-09 | 2007-03-15 | Degussa Ag | Fällungskieselsäuren mit einer besonderen Porengrößenverteilung |
US7352228B2 (en) * | 2006-05-03 | 2008-04-01 | Texas Instruments Incorporated | Method and apparatus of a level shifter circuit with duty-cycle correction |
US7576609B1 (en) * | 2008-02-21 | 2009-08-18 | Himax Technologies Limited | Preamplifier for receiver and method thereof |
US7750717B2 (en) * | 2008-07-25 | 2010-07-06 | Texas Instruments Incorporated | Single supply level shifter circuit for multi-voltage designs, capable of up/down shifting |
US8791418B2 (en) * | 2008-12-08 | 2014-07-29 | Micron Technology, Inc. | Increasing the spatial resolution of dosimetry sensors |
CA2745475C (en) * | 2008-12-17 | 2014-02-25 | Fpinnovations | A method to control the dispersibility and barrier properties of dried nanocrystalline cellulose in solutions of different ph and ionic strength |
JP2010226703A (ja) * | 2009-02-27 | 2010-10-07 | Renesas Electronics Corp | レベルシフト回路及びこれを備えたスイッチ回路 |
US8446188B2 (en) * | 2009-05-15 | 2013-05-21 | Qualcomm, Incorporated | Systems and methods for producing a predetermined output in a sequential circuit during power on |
JPWO2012157031A1 (ja) * | 2011-05-13 | 2014-07-31 | パナソニック株式会社 | 信号電位変換回路 |
US8818005B2 (en) | 2011-05-17 | 2014-08-26 | Fairchild Semiconductor Corporation | Capacitor controlled switch system |
CN102403902B (zh) * | 2011-11-16 | 2014-02-05 | 无锡华润上华科技有限公司 | 一种应用于功率因数校正器中的高压大电流驱动电路 |
TWI481194B (zh) * | 2012-02-10 | 2015-04-11 | Richtek Technology Corp | 浮接閘驅動器電路以及在浮接閘驅動器電路中為單端準位平移器改善抗雜訊能力的電路與方法 |
US9391600B2 (en) * | 2012-04-16 | 2016-07-12 | Intel Corporation | Voltage level shift with charge pump assist |
US9165644B2 (en) | 2012-05-11 | 2015-10-20 | Axon Technologies Corporation | Method of operating a resistive memory device with a ramp-up/ramp-down program/erase pulse |
US8953362B2 (en) | 2012-05-11 | 2015-02-10 | Adesto Technologies Corporation | Resistive devices and methods of operation thereof |
US9001553B1 (en) | 2012-11-06 | 2015-04-07 | Adesto Technologies Corporation | Resistive devices and methods of operation thereof |
FR3042876B1 (fr) * | 2015-10-27 | 2017-12-15 | STMicroelectronics (Alps) SAS | Detection de perturbations d'une alimentation |
KR102367787B1 (ko) * | 2016-06-30 | 2022-02-24 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 장치 및 반도체 장치의 동작 방법 |
CN109308090B (zh) * | 2017-07-26 | 2020-10-16 | 中芯国际集成电路制造(上海)有限公司 | 稳压电路和方法 |
US10782420B2 (en) | 2017-12-18 | 2020-09-22 | Thermo Eberline Llc | Range-extended dosimeter |
US10692570B2 (en) * | 2018-07-11 | 2020-06-23 | Sandisk Technologies Llc | Neural network matrix multiplication in memory cells |
US11959937B2 (en) * | 2019-12-06 | 2024-04-16 | Keithley Instruments, Llc | Triaxial power and control systems and methods |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3750115A (en) * | 1972-04-28 | 1973-07-31 | Gen Electric | Read mostly associative memory cell for universal logic |
US4752912A (en) | 1985-05-14 | 1988-06-21 | Xicor, Inc. | Nonvolatile electrically alterable memory and method |
US4935702A (en) | 1988-12-09 | 1990-06-19 | Synaptics, Inc. | Subthreshold CMOS amplifier with offset adaptation |
US5059920A (en) | 1988-12-09 | 1991-10-22 | Synaptics, Incorporated | CMOS amplifier with offset adaptation |
US4980859A (en) | 1989-04-07 | 1990-12-25 | Xicor, Inc. | NOVRAM cell using two differential decouplable nonvolatile memory elements |
US4953928A (en) | 1989-06-09 | 1990-09-04 | Synaptics Inc. | MOS device for long-term learning |
US5095284A (en) | 1990-09-10 | 1992-03-10 | Synaptics, Incorporated | Subthreshold CMOS amplifier with wide input voltage range |
US5166562A (en) | 1991-05-09 | 1992-11-24 | Synaptics, Incorporated | Writable analog reference voltage storage device |
US5875126A (en) | 1995-09-29 | 1999-02-23 | California Institute Of Technology | Autozeroing floating gate amplifier |
US5721702A (en) * | 1995-08-01 | 1998-02-24 | Micron Quantum Devices, Inc. | Reference voltage generator using flash memory cells |
US5903487A (en) | 1997-11-25 | 1999-05-11 | Windbond Electronics Corporation | Memory device and method of operation |
US6297689B1 (en) | 1999-02-03 | 2001-10-02 | National Semiconductor Corporation | Low temperature coefficient low power programmable CMOS voltage reference |
EP1058270B1 (en) | 1999-06-04 | 2007-03-21 | STMicroelectronics S.r.l. | Biasing stage for biasing the drain terminal of a nonvolatile memory cell during the read phase |
JP3933817B2 (ja) * | 1999-06-24 | 2007-06-20 | 富士通株式会社 | 不揮発性メモリ回路 |
US6515903B1 (en) | 2002-01-16 | 2003-02-04 | Advanced Micro Devices, Inc. | Negative pump regulator using MOS capacitor |
US6898123B2 (en) * | 2003-01-07 | 2005-05-24 | Intersil Americas Inc. | Differential dual floating gate circuit and method for programming |
US7113017B2 (en) * | 2004-07-01 | 2006-09-26 | Intersil Americas Inc. | Floating gate analog voltage level shift circuit and method for producing a voltage reference that operates on a low supply voltage |
US6847551B2 (en) * | 2003-01-28 | 2005-01-25 | Xicor, Inc. | Apparatus for feedback using a tunnel device |
US6914812B2 (en) * | 2003-01-28 | 2005-07-05 | Intersil America Inc. | Tunnel device level shift circuit |
-
2004
- 2004-07-01 US US10/884,234 patent/US7113017B2/en not_active Expired - Fee Related
-
2005
- 2005-06-30 TW TW094122154A patent/TWI389117B/zh not_active IP Right Cessation
- 2005-07-01 CN CNB2005100922429A patent/CN100468567C/zh not_active Expired - Fee Related
-
2006
- 2006-09-22 US US11/525,791 patent/US7432744B2/en not_active Expired - Fee Related
- 2006-09-22 US US11/525,792 patent/US7345523B2/en not_active Expired - Fee Related
- 2006-09-22 US US11/525,739 patent/US7345522B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US20060001470A1 (en) | 2006-01-05 |
US7113017B2 (en) | 2006-09-26 |
TW200615952A (en) | 2006-05-16 |
US20070013415A1 (en) | 2007-01-18 |
CN1755833A (zh) | 2006-04-05 |
TWI389117B (zh) | 2013-03-11 |
US20070013430A1 (en) | 2007-01-18 |
US20070013431A1 (en) | 2007-01-18 |
US7345523B2 (en) | 2008-03-18 |
US7432744B2 (en) | 2008-10-07 |
US7345522B2 (en) | 2008-03-18 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
ASS | Succession or assignment of patent right |
Owner name: INTERSIL AMERICA CO., LTD. Free format text: FORMER OWNER: XICOR INC. Effective date: 20140103 |
|
C41 | Transfer of patent application or patent right or utility model | ||
TR01 | Transfer of patent right |
Effective date of registration: 20140103 Address after: American California Patentee after: Intersil Americas LLC Address before: American California Patentee before: Xicor Inc. |
|
CF01 | Termination of patent right due to non-payment of annual fee | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090311 Termination date: 20160701 |